Product Folder Sample & Buy Support & Community Tools & Software Technical Documents ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 ADS127L01 24-Bit, High-Speed, Wide-Bandwidth Analog-to-Digital Converter 1 Features 3 Description • • The ADS127L01 is a 24-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) with data rates up to 512 kSPS. This device offers a unique combination of excellent dc accuracy and outstanding ac performance. The high-order, chopper-stabilized modulator achieves very low drift with low in-band noise. The on chip decimation filter suppresses modulator out-of-band noise. In addition to a lowlatency filter, the ADS127L01 provides multiple wideband filters with less than ±0.00004 dB of ripple, and an option for –116-dB stop-band attenuation at the Nyquist rate. 1 • • • • • • • Data Rates: Up to 512 kSPS AC Performance: – Passband: Up to 230 kHz – SNR: Up to 115.5 dB (at OSR 256) – THD: –126 dB (LP and VLP modes) DC Accuracy: – Offset Drift: 1.5 μV/°C – Gain Drift: 0.2 ppm/°C Operating Modes: – HR: 111 dB SNR (128 kSPS at 26 mW) – LP: 108 dB SNR (128 kSPS at 15 mW) – VLP: 105 dB SNR (128 kSPS at 9 mW) Digital Filter Options: – Low-latency Filter: Sinc Frequency Response – Wideband 1 Filter: (0.45 to 0.55) × fDATA Transition Band – Wideband 2 Filter: (0.40 to 0.50) × fDATA Transition Band SPI™ or Frame-Sync Serial Interface – Daisy-Chain Compatible Analog Supply: 2.7 V to 3.6 V Digital Supply: 1.7 V to 3.6 V Operating Temperature: –40°C to +125°C 2 Applications • • • • Traditionally, industrial delta-sigma ADCs that offer good drift performance use digital filters with large passband droop. As a result, industrial delta-sigma ADCs have limited signal bandwidth and are mostly suited for dc measurements. High-resolution ADCs in audio applications offer larger usable bandwidths, but the offset and drift specifications are significantly weaker than industrial counterparts. The ADS127L01 combines these converters, providing high-precision industrial measurement with excellent dc and ac specifications over an extended industrial temperature range of –40°C to +125°C. A variety of operating modes allow for optimization of speed, resolution, and power. A programmable serial interface with one of three options (SPI, frame-sync slave, or frame-sync master) provides convenient interfacing across isolation barriers to microcontrollers or digital signal processors (DSPs). Device Information(1) Vibration and Modal Analysis Data Acquisition Systems Acoustics and Dynamic Strain Gauges Power Quality Analysis PART NUMBER ADS127L01 REFN LVDD AVDD ADC Frequency Spectrum 0 DVDD LDO -20 INTLDO SCLK AINP û ADC Modulator AINN SPI and Frame-Sync Interface Wideband 1 Filter DOUT DRDY/FSYNC DAISYIN Wideband 2 Filter FSMODE FORMAT Control Logic -40 CS DIN RESET/PWDN OSR [1:0] Amplitude (dB) Low-Latency Filter BODY SIZE (NOM) 5.00 mm × 5.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. ADS127L01 Block Diagram REFP PACKAGE TQFP (32) -60 -80 -100 -120 FILTER [1:0] CLK ADS127L01 AGND DGND Copyright © 2016, Texas Instruments Incorporated -140 -160 -180 0 20 40 60 80 Frequency (kHz) 100 120 D001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics.......................................... 7 Timing Requirements: Serial Interface................... 10 Switching Characteristics: Serial Interface.............. 10 Timing Requirements: Frame-Sync Master Mode . 12 Switching Characteristics: Frame-Sync Master Mode ........................................................................ 12 6.10 Timing Requirements: Frame-Sync Slave Mode .. 13 6.11 Switching Characteristics: Frame-Sync Slave Mode ........................................................................ 13 6.12 Typical Characteristics .......................................... 15 7 Parameter Measurement information ................ 23 7.1 Noise Performance ................................................. 23 8 Detailed Description ............................................ 25 8.2 8.3 8.4 8.5 8.6 9 Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming .......................................................... Register Maps ......................................................... 25 26 37 45 51 Application and Implementation ........................ 56 9.1 9.2 9.3 9.4 Application Information............................................ Typical Application ................................................. Do's and Don'ts ...................................................... Initialization Setup .................................................. 56 70 73 74 10 Power Supply Recommendations ..................... 76 10.1 Power-Supply Sequencing.................................... 76 10.2 Power-Supply Decoupling .................................... 76 11 Layout................................................................... 77 11.1 Layout Guidelines ................................................. 77 11.2 Layout Example .................................................... 77 12 Device and Documentation Support ................. 79 12.1 12.2 12.3 12.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 79 79 79 79 13 Mechanical, Packaging, and Orderable Information ........................................................... 79 8.1 Overview ................................................................. 25 4 Revision History Changes from Original (April 2016) to Revision A • 2 Page Changed from product preview to production data ................................................................................................................ 1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 5 Pin Configuration and Functions AVDD AGND FORMAT HR RESET/PWDN DVDD DGND CAP3 32 31 30 29 28 27 26 25 PBS package 32-Pin TQFP Top View AINN 3 22 SCLK AINP 4 21 DIN AGND 5 20 DOUT AVDD 6 19 DRDY/FSYNC REXT 7 18 DAISYIN INTLDO 8 17 START Not to scale OSR0 OSR1 FILTER0 FSMODE CAP2 FILTER1 REFN REFP 16 CS 15 23 14 2 13 CAP1 12 CLK 11 24 10 1 9 LVDD Pin Functions PIN DESCRIPTION (1) I/O NO. NAME 1 LVDD Supply 2 CAP1 Analog output Modulator common-mode voltage. Connect a 1-µF capacitor to AGND 3 AINN Analog input Negative analog input. 4 AINP Analog input Positive analog input. 5 AGND Supply Analog ground. 6 AVDD Supply Analog supply connection. Connect a 1-μF capacitor to AGND. 7 REXT Analog input Analog power-scaling bias resistor pin. Recommended external resistor values: REXT = 60.4 kΩ to AGND for high-resolution (HR) and low-power (LP) modes REXT = 120 kΩ to AGND for very-low-power (VLP) mode 8 INTLDO Digital input LVDD voltage selection pin (pull high to AVDD or low to AGND through 10-kΩ resistor). 0: Internal analog low-dropout regulator (LDO) for LVDD voltage supply. 1: External LVDD voltage supply. 9 REFP Analog input Positive analog reference input. Connect a minimum 10-μF capacitor to REFN 10 REFN Analog input Negative analog reference input. 11 CAP2 Analog output Reference for common-mode voltage. Connect a 1-µF capacitor to AGND. (1) LVDD analog supply. INTLDO = 0: LVDD is an analog-supply output pin. Connect a 1-µF capacitor to AGND. INTLDO = 1: LVDD is an analog-supply input pin. Connect to a 1.8-V supply. See the Unused Inputs and Outputs section for unused pin connections. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 3 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Pin Functions (continued) PIN NO. NAME DESCRIPTION (1) I/O 12 FILTER1 Digital input 13 FILTER0 Digital input Digital filter select pin (2). 00: Wideband 1 filter (WB1) 01: Wideband 2 filter (WB2) 10 : Low-latency filter (LL) 11: Reserved 14 FSMODE Digital input Frame-sync mode pin (2). 0: Slave mode 1: Master mode. Frame-sync mode only. 15 OSR1 Digital input Oversampling ratio (OSR) pin for the decimation filters (2). 16 Wideband filters, FILTER[1:0] = 00 or 01: 00: 32x oversampling (OSR 32) 01: 64x oversampling (OSR 64) 10: 128x oversampling (OSR 128) 11: 256x oversampling (OSR 256) OSR0 Digital input 17 START Digital input Synchronization signal to start or restart a conversion. 18 DAISYIN Digital input Daisy-chain input. 19 DRDY/FSYNC Digital input/output 20 DOUT Digital output 21 DIN Digital input 22 SCLK 23 CS Digital input Chip select. Tie directly to DGND when using the frame-sync interface. 24 CLK Digital input Master clock input. 25 CAP3 Supply output Internally-generated digital operating voltage. Connect a 1-µF capacitor to DGND. 26 DGND Digital ground Digital ground. 27 DVDD Supply input Digital supply. Decouple DVDD to DGND with a 1-μF capacitor (3) 28 RESET/PWDN Digital input Reset or power-down pin, active low (3). 29 HR Digital input ADC operating mode (2). 1: High-resolution (HR) 0: Low-power (LP) or very-low-power (VLP) (4) Interface select (2). 0: SPI 1: Frame-Sync FORMAT Digital input 31 AGND Analog ground 32 AVDD Supply input 4 SPI protocol: Data ready, active low (3). Frame-sync protocol: Frame-sync input signal (3) Serial data output Serial data input. Tie directly to DGND when using the frame-sync interface. Digital input/output Serial clock input (3). 30 (2) (3) (4) Low-latency filter, FILTER[1:0] = 10: 00: 32x oversampling (OSR 32) 01: 128x oversampling (OSR 128) 10: 512x oversampling (OSR 512) 11: 2048x oversampling (OSR 2048) Analog ground. Analog supply. Decouple AVDD to AGND with a 1-μF capacitor. Pull the hardware mode pins high to DVDD or low to DGND through 100-kΩ resistors. See the Reset and Power-Down Pins (RESET/PWDN) section for specific hardware design details if using power-down mode. Entering LP mode or VLP mode is set by REXT resistor value. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 6 Specifications 6.1 Absolute Maximum Ratings (1) Voltage MIN MAX AVDD to AGND –0.3 4.0 DVDD to DGND –0.3 4.0 LVDD to AGND –0.3 2.0 AGND to DGND –0.3 0.3 REFP to AGND –0.3 AVDD + 0.3 REFN to AGND –0.3 AVDD + 0.3 Analog input AGND – 0.3 AVDD + 0.3 Digital input DGND – 0.3 DVDD + 0.3 (2) –10 10 Operating ambient, TA –40 125 Input, continuous, any pin except power supply pins Current Temperature Junction, TJ (2) V mA 150 Storage, Tstg (1) UNIT –60 °C 150 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Input pins are diode-clamped to the power-supply rails. Limit the input current to 10 mA or less if the analog input voltage exceeds VAVDD + 0.3 V or is less than VAGND – 0.3 V, or if the digital input voltage exceeds VDVDD + 0.3 V or is less than VDGND – 0.3 V. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 5 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com 6.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN NOM MAX UNIT 2.7 3.0 3.6 V 1.7 1.8 1.9 V 1.7 1.8 3.6 V POWER SUPPLY AVDD Analog power supply LVDD Low voltage analog supply DVDD Digital supply INTLDO = 1 ANALOG INPUTS VIN Differential input voltage VIN = (VAINP – VAINN) –VREF VREF V VAINP, VAINN Absolute input voltage AINP or AINN to AGND AGND AVDD V VCM Common-mode input voltage VCM = (VAINP + VAINN) / 2 (AVDD + AGND) / 2 V VOLTAGE REFERENCE INPUTS VREFN Negative reference input VREFP Positive reference input VREF Reference input voltage AGND – 0.1 AGND AGND + 1.0 V VREFN + 0.5 2.5 AVDD V VREF = VREFP – VREFN 0.5 2.5 3.0 V HR mode 0.1 16.384 17.6 LP mode 0.1 8.192 8.8 VLP mode 0.1 4.096 4.4 EXTERNAL CLOCK SOURCE Master clock rate (1) fCLK MHz DIGITAL INPUTS Input voltage DGND DVDD V –40 125 °C TEMPERATURE RANGE TA (1) Operating ambient temperature To meet maximum speed conditions, fCLK duty cycle must be 49% < duty cycle < 51%. 6.4 Thermal Information ADS127L01 THERMAL METRIC (1) PBS (TQFP) UNIT 32 PINS RθJA Junction-to-ambient thermal resistance 73.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 15.9 °C/W RθJB Junction-to-board thermal resistance 26.7 °C/W ψJT Junction-to-top characterization parameter 0.4 °C/W ψJB Junction-to-board characterization parameter 26.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com 6.5 SBAS607A – APRIL 2016 – REVISED MAY 2016 Electrical Characteristics Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications at TA = 25°C. All specifications at AVDD = 3 V, LVDD = 1.8 V (external), DVDD = 1.8 V, VREF = 2.5 V, INTLDO = 1, FILTER[1:0] = 01 (WB2), and fCLK = 16.384 MHz for HR mode, 8.192 MHz for LP mode, or 4.096 MHz for VLP mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS HR mode, fCLK = 16.384 MHz Differential input impedance 5 LP mode, fCLK = 8.192 MHz 11 VLP mode, fCLK = 4.096 MHz 23 kΩ DC PERFORMANCE Resolution No missing codes HR mode fDATA Data rate LP mode VLP mode Integral nonlinearity (1) INL 24 Wideband filters Bits 512, 256, 128, 64 Low-latency filter 512, 128, 32, 8 Wideband filters 256, 128, 64, 32 Low-latency filter 256, 64, 16, 4 Wideband filters 128, 64, 32, 16 Low-latency filter 128, 32, 8, 2 HR mode VCM = AVDD / 2 2.5 10 LP mode VCM = AVDD / 2 1 5 VLP mode VCM = AVDD / 2 1 5 Offset error ±0.1 Offset drift 1.5 Gain error Gain drift CMRR PSRR (1) (2) (2) Power-supply rejection mV μV/°C %FSR 0.003% HR mode 0.8 3 LP mode 0.4 2.5 VLP mode 0.2 2 HR mode Common-mode rejection ppm 3.0 0.2 Gain calibration accuracy Noise kSPS WB2, OSR 32 10.6 WB2, OSR 64 7.3 10.1 WB2, OSR 128 5.1 7.2 WB2, OSR 256 3.6 5.2 fCM = 60 Hz 95 AVDD fPS = 60 Hz 90 DVDD fPS = 60 Hz 85 LVDD fPS = 60 Hz 80 ppm/°C μVRMS dB dB Best fit method. For all wideband filter configurations, see Table 1. For all low-latency filter configurations, see Table 2. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 7 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Electrical Characteristics (continued) Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications at TA = 25°C. All specifications at AVDD = 3 V, LVDD = 1.8 V (external), DVDD = 1.8 V, VREF = 2.5 V, INTLDO = 1, FILTER[1:0] = 01 (WB2), and fCLK = 16.384 MHz for HR mode, 8.192 MHz for LP mode, or 4.096 MHz for VLP mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE WB2, OSR 32 Signal-to-noise ratio (2) (3) SNR Total harmonic distortion (4) THD SFDR Spurious-free dynamic range 104.4 WB2, OSR 64 104.9 107.8 WB2, OSR 128 107.9 110.9 WB2, OSR 256 110.6 113.9 WB2, OSR 256, VREF = 3.0 V 115.5 HR mode, fIN = 4 kHz, VIN = –0.5 dBFS –113 LP mode, fIN = 4 kHz, VIN = –0.5 dBFS –126 VLP mode, fIN = 4 kHz, VIN = –0.5 dBFS –129 HR mode –115 LP mode –130 VLP mode –130 dB dB dB DIGITAL FILTER RESPONSE: WIDEBAND Bandwidth See Table 1 Passband ripple ±0.000032 FILTER = 00 (WB1) (0.45 to 0.55) × fDATA FILTER = 01 (WB2) (0.40 to 0.50) × fDATA Transition band Stopband attenuation Hz 116 Group delay Settling time dB Complete settling dB 42 / fDATA s 84 / fDATA s DIGITAL FILTER RESPONSE: LOW LATENCY Bandwidth See Table 2 Group delay See Low-Latency Filter Mode section Settling time See Low-Latency Filter Mode section VOLTAGE REFERENCE INPUTS Reference input impedance HR mode 2.2 LP mode 3.2 VLP mode kΩ 4 SYSTEM MONITORS Input over-range detect accuracy ±100 mV DIGITAL INPUT/OUTPUT (DVDD = 1.7 V to 3.6 V) VIH High-level input voltage 0.7 DVDD DVDD V VIL Low-level input voltage DGND 0.3 DVDD V VOH High-level output voltage IOH = 2 mA 0.8 DVDD DVDD V VOL Low-level output voltage IOL = 2 mA DGND 0.2 DVDD V IH Input leakage, high IH = 3.6 V –10 10 μA IL Input leakage, low IL = DGND –10 10 μA (3) (4) 8 Minimum SNR is ensured by the limit of the dc noise specification. THD includes the first nine harmonics of the input signal. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 Electrical Characteristics (continued) Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications at TA = 25°C. All specifications at AVDD = 3 V, LVDD = 1.8 V (external), DVDD = 1.8 V, VREF = 2.5 V, INTLDO = 1, FILTER[1:0] = 01 (WB2), and fCLK = 16.384 MHz for HR mode, 8.192 MHz for LP mode, or 4.096 MHz for VLP mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY INTLDO = 0 AVDD Power-down current IAVDD ILVDD IDVDD PD (5) (6) AVDD current LVDD current (5) (6) DVDD current (2) Power dissipation INTLDO = 1 8 2 μA DVDD 0.6 LVDD, INTLDO = 1 0.6 HR mode 1.3 1.6 LP mode 0.8 1.0 VLP mode 0.4 0.6 HR mode 9.3 11 LP mode 4.6 5.5 VLP mode 2.3 2.8 HR mode OSR 128 2.8 3.4 LP mode OSR 128 1.5 1.8 VLP mode OSR 128 0.8 1.1 HR mode, OSR 128, AVDD = 3.0 V, DVDD = 1.8 V INTLDO = 1, LVDD = 1.8 V, 25.7 30.8 INTLDO = 0 36.8 44.2 LP mode, OSR 128, AVDD = 3.0 V, DVDD = 1.8 V INTLDO = 1, LVDD = 1.8 V, 13.4 16.1 INTLDO = 0 18.9 22.7 VLP mode, OSR 128, AVDD = 3.0 V, DVDD = 1.8 V INTLDO = 1, LVDD = 1.8 V, 6.8 8.2 INTLDO = 0 9.5 11.4 mA mA mA mW LVDD current sourced from AVDD when the internal LDO is used (INTLDO = 0). ILVDD current scales with fCLK; see Figure 49. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 9 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 6.6 www.ti.com Timing Requirements: Serial Interface over operating ambient temperature range (unless otherwise noted) tc(CLK) Master clock period Master clock high and low pulse duration tw(CP) 2.8 V < DVDD ≤ 3.6 V 1.7 V ≤ DVDD ≤ 2.8 V MIN MAX MIN HR mode 57 10,000 57 10,000 LP mode 114 10,000 114 10,000 VLP mode 227 10,000 227 10,000 HR mode 28 5,000 28 5,000 LP mode 56 5,000 56 5,000 112 5,000 112 5,000 VLP mode TYP TYP MAX UNIT ns ns td(CSSC) Delay time, CS falling edge to first SCLK rising edge (1) tc(SC) SCLK period 40 tw(SCHL) Pulse duration, SCLK high or low 20 25 ns tsu(DI) Setup time, DIN valid before SCLK falling edge 6 9 ns th(DI) Hold time, DIN valid after SCLK falling edge 8 9 ns tw(CSH) Pulse duration, CS high 6 6 tCLK td(SCCS) Delay time, final SCLK falling edge to CS rising edge 2 2 tCLK td(DECODE) Delay time, command decode time 4 SPI timeout (2) 12 6250 ns 50 6250 4 ns tCLK 16 16 TOUT_DEL = 0 2 2 tCLK TOUT_DEL = 1 214 214 tCLK tsu(DCI) Setup time, DAISYIN valid before SCLK falling edge th(DCI) Hold time, DAISYIN valid after SCLK falling edge (1) (2) 8 5 8 ns 20 25 ns CS can be tied low permanently in case the serial bus is not shared with any other device. See the SPI Timeout section for more information. 6.7 Switching Characteristics: Serial Interface over operating free-air temperature range (unless otherwise noted) 2.8 V < DVDD ≤ 3.6 V 1.7 V ≤ DVDD ≤ 2.8 V MIN MIN TYP MAX TYP MAX UNIT tp(CSDO) Propagation delay time CS falling edge to DOUT driven 12 18 ns tp(SCDO) Propagation delay time SCLK rising edge to valid new DOUT 15 21 ns tv(DO) Valid time, SCLK falling edge to DOUT invalid tp(CSDOZ) Propagation delay time CS rising edge to DOUT high impedance 10 18 tSCLK / 2 Submit Documentation Feedback 20 20 tSCLK / 2 ns 20 ns Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 tw(CP) tc(CLK) CLK tw(CSH) td(DECODE) § § CS tc(SC) td(CSSC) tw(SCHL) td(SCCS) § 1 2 3 8 1 2 3 8 § SCLK th(DI) tsu(DI) tv(DO) DIN § § § tp(SCDO) tp(CSDOZ) tp(CSDO) § § § § DOUT NOTE: SPI settings are CPOL = 0 and CPHA = 1. Figure 1. SPI Format Timing § § MSBD1 DAISYIN LSBD1 tsu(DCI) th(DCI) § SCLK th(DO) MSBD0 § § DOUT LSBD0 MSBD1 Figure 2. SPI Daisy-Chain Interface Timing Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 11 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 6.8 www.ti.com Timing Requirements: Frame-Sync Master Mode over operating ambient temperature range and DVDD = 1.7 V to 3.6 V (unless otherwise noted) 1.7 V ≤ DVDD ≤ 3.6 V MIN tc(CLK) Master clock period tw(CP) Master clock high and low pulse duration TYP MAX HR mode 57 10,000 LP mode 114 10,000 VLP mode 227 10,000 HR mode 28 5,000 LP mode 56 5,000 112 5,000 VLP mode UNIT ns ns 6.9 Switching Characteristics: Frame-Sync Master Mode over operating free-air temperature range (unless otherwise noted) 2.8 V < DVDD ≤ 3.6 V 1.7 V ≤ DVDD ≤ 2.8 V MIN MIN TYP MAX TYP MAX UNIT td(CSC) Delay time, rising edge of CLK to falling edge of SCLK tc(FRAME) Frame period tw(FP) Pulse duration, FSYNC positive or negative td(FSSC) Delay time, rising edge of FSYNC to falling edge of SCLK tc(SC) SCLK period 1 / (32fDATA) 1 / (32fDATA) s tw(SCHL) Pulse duration, SCLK high or low 1 / (64fDATA) 1 / (64fDATA) s tv(DO) Valid time, SCLK rising edge DOUT invalid tp(SCDO) Propagation delay time SCLK falling edge to DOUT driven 15 17 ns tp(FSDO) Propagation delay time FSYNC rising edge to DOUT MSB valid 12 15 ns 15 15 ns 1 / fDATA 1 / fDATA s 1 / (2fDATA) 1 / (2fDATA) s 6 8 25 25 ns ns tw(CP) tc(CLK) CLK tc(FRAME) tw(FP) § td(CSC) § FSYNC tc(SC) td(FSSC) tw(SCHL) § § SCLK tp(FSDO) tv(DO) tp(SCDO) Bit 30 Bit 15 Bit 14 § § Bit 31 § § DOUT Bit 0 Figure 3. Frame-Sync Format Timing Master Mode 12 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 6.10 Timing Requirements: Frame-Sync Slave Mode over operating ambient temperature range and DVDD = 1.7 V to 3.6 V (unless otherwise noted) tc(CLK) tw(CP) Master clock period Master clock high and low pulse duration 2.8 V < DVDD ≤ 3.6 V 1.7 V ≤ DVDD ≤ 2.8 V MIN MAX MIN HR mode 57 10,000 57 10,000 LP mode 114 10,000 114 10,000 VLP mode 227 10,000 227 10,000 HR mode 28 5,000 28 5,000 LP mode 56 5,000 56 5,000 112 5,000 112 5,000 VLP mode TYP TYP MAX UNIT ns ns td(CSC) Delay time, rising edge of CLK to falling edge of SCLK tc(FRAME) Frame period tw(FP) Pulse durration, FSYNC positive or negative td(FSSC) Delay time, rising edge of FSYNC to falling edge of SCLK 6 6 ns td(SCFS) Delay time, falling edge of SCLK to rising edge of FSYNC 2 2 ns tc(SC) SCLK period 40 56 ns tw(SCHL) Pulse duration, SCLK high or low 20 28 ns 8 8 ns 25 31 ns 2 2 ns 1 / fDATA 1 / fDATA 2 s 2 tSCLK DAISY-CHAIN TIMING tsu(DCI) Setup time, DAISYIN valid before SCLK rising edge th(DCI) Hold time, DAISYIN valid after SCLK rising edge 6.11 Switching Characteristics: Frame-Sync Slave Mode over operating free-air temperature range (unless otherwise noted) tv(DO) Hold time, SCLK rising edge to invalid DOUT tp(SCDO) Propagation delay time SCLK falling edge to new DOUT tp(FSDO) Propagation delay time FSYNC rising edge to DOUT MSB valid 2.8 V < DVDD ≤ 3.6 V 1.7 V ≤ DVDD ≤ 2.8 V MIN MIN TYP MAX 17 TYP MAX 25 ns 22 15 UNIT 22 25 22 ns 32 ns tw(CP) tc(CLK) CLK td(CSC) tc(FRAME) § tw(FP) § FSYNC tc(SC) td(FSSC) td(SCFS) tw(SCHL) § § SCLK tp(FSDO) tv(DO) tp(SCDO) Bit 30 Bit 15 Bit 14 § § Bit 31 § § DOUT Bit 0 Figure 4. Frame-Sync Format Timing Slave Mode Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 13 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com § § MSBD1 DAISYIN LSBD1 tsu(DCI) § th(DCI) SCLK MSBD0 § § DOUT LSBD0 MSBD1 Figure 5. Frame-Sync Slave Daisy-Chain Timing 14 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 6.12 Typical Characteristics 0 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications at TA = 25°C. All specifications at AVDD = 3 V, LVDD = 1.8 V (external), DVDD = 1.8 V, VREF = 2.5 V, INTLDO = 1, FILTER[1:0] = 01 (WB2), OSR[1:0] = 10 (OSR 128), and fCLK = 16.384 MHz for HR mode, 8.192 MHz for LP mode, or 4.096 MHz for VLP mode (unless otherwise noted) -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 40 80 120 160 Frequency (kHz) 200 240 0 40 fIN = 4 kHz, VIN = –0.5 dBFS, HR mode, WB2, 512 kSPS, 32768 samples 200 240 D027 Figure 7. Output Spectrum 0 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) 120 160 Frequency (kHz) fIN = 4 kHz, VIN = –20 dBFS, HR mode, WB2, 512 kSPS, 32768 samples Figure 6. Output Spectrum -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 40 80 120 160 Frequency (kHz) 200 240 0 40 80 D028 fIN = 4 kHz, VIN = –0.5 dBFS, HR mode, WB1, 512 kSPS, 32768 samples 120 160 Frequency (kHz) 200 240 D029 fIN = 4 kHz, VIN = –20 dBFS, HR mode, WB1, 512 kSPS, 32768 samples Figure 8. Output Spectrum Figure 9. Output Spectrum 0 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) 80 D026 -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 20 40 60 80 Frequency (kHz) 100 120 130 0 D030 fIN = 4 kHz, VIN = –0.5 dBFS, LP mode, WB2, 256 kSPS, 32768 samples 20 40 60 80 Frequency (kHz) 100 120 130 D031 fIN = 4 kHz, VIN = –20 dBFS, LP mode, WB2, 256 kSPS, 32768 samples Figure 10. Output Spectrum Figure 11. Output Spectrum Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 15 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Typical Characteristics (continued) Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications at TA = 25°C. 0 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) All specifications at AVDD = 3 V, LVDD = 1.8 V (external), DVDD = 1.8 V, VREF = 2.5 V, INTLDO = 1, FILTER[1:0] = 01 (WB2), OSR[1:0] = 10 (OSR 128), and fCLK = 16.384 MHz for HR mode, 8.192 MHz for LP mode, or 4.096 MHz for VLP mode (unless otherwise noted) -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 10 20 30 40 Frequency (kHz) 50 60 65 0 5 D032 fIN = 4 kHz, VIN = –0.5 dBFS, VLP mode, WB2, 128 kSPS, 32768 samples 10 15 20 25 30 35 40 45 50 55 60 65 Frequency (kHz) D033 fIN = 4 kHz, VIN = –20 dBFS, VLP mode, WB2, 128 kSPS, 32768 samples Figure 13. Output Spectrum 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) Figure 12. Output Spectrum 0 -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 30 60 90 120 150 180 Frequency (kHz) 210 0 240 20 D034 Input shorted, HR mode, WB2, 512 kSPS, 32768 samples 40 60 80 Frequency (kHz) 100 120 D035 Input shorted, LP mode, WB2, 256 kSPS, 32768 samples Figure 14. Output Spectrum Figure 15. Output Spectrum 0 30 25 -20 20 Output Voltage (PV) Amplitude (dB) -40 -60 -80 -100 -120 15 10 5 0 -5 -10 -15 -140 -20 -160 -25 -30 -180 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Frequency (kHz) D036 Input shorted, VLP mode, WB2, 128 kSPS, 32768 samples Time D039 HR mode, 0.5 seconds data collection Figure 17. ADC Conversion Noise Figure 16. Output Spectrum 16 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 Typical Characteristics (continued) Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications at TA = 25°C. 12 Voltage (PV) 10 8 6 4 2 0 -2 -4 -6 -8 -10 Noise (PVRMS) 4200 3900 3600 3300 3000 2700 2400 2100 1800 1500 1200 900 600 300 0 -12 Number of Occurrences All specifications at AVDD = 3 V, LVDD = 1.8 V (external), DVDD = 1.8 V, VREF = 2.5 V, INTLDO = 1, FILTER[1:0] = 01 (WB2), OSR[1:0] = 10 (OSR 128), and fCLK = 16.384 MHz for HR mode, 8.192 MHz for LP mode, or 4.096 MHz for VLP mode (unless otherwise noted) 5.2 5.18 5.16 5.14 5.12 5.1 5.08 5.06 5.04 5.02 5 4.98 4.96 4.94 4.92 4.9 0.5 0.75 1 1.25 D040 2.25 2.5 2.75 3 D053 Figure 19. Noise vs VREF Figure 18. Noise Histogram 9 5.15 8 5.125 Noise (PVRMS) 7 Noise (PVrms) 1.75 2 VREF (V) Inputs shorted HR mode, 65536 points 6 5 4 5.1 5.075 5.05 5.025 3 2 -40 5 -20 0 20 40 60 Temperature (qC) 80 100 120 0 2 D048 Inputs shorted 4 6 8 10 fCLK (MHz) 12 14 16 18 D055 HR mode Figure 20. Noise vs Temperature Figure 21. Noise vs fCLK 0 HR Mode LP Mode VLP Mode -30 -45 -60 -75 -90 -105 Total Harmonic Distortion (dB) 0 -15 Total Harmonic Distortion (dB) 1.5 HR Mode LP Mode VLP Mode -20 -40 -60 -80 -100 -120 -140 -120 -135 0.5 0.7 1 2 3 4 5 6 7 8 10 20 30 4050 70 100 Input Frequency (kHz) D037 -160 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 Input Amplitude (dBFS) WB2, OSR 32 -5 0 D038 WB2, OSR 32 Figure 22. Total Harmonic Distortion vs fIN Figure 23. Total Harmonic Distortion vs VIN Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 17 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Typical Characteristics (continued) Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications at TA = 25°C. All specifications at AVDD = 3 V, LVDD = 1.8 V (external), DVDD = 1.8 V, VREF = 2.5 V, INTLDO = 1, FILTER[1:0] = 01 (WB2), OSR[1:0] = 10 (OSR 128), and fCLK = 16.384 MHz for HR mode, 8.192 MHz for LP mode, or 4.096 MHz for VLP mode (unless otherwise noted) -100 -105 Total Harmonic Distortion (dB) -110 -115 -120 -125 -105 -110 -115 -120 -125 -130 -135 -140 2.5 3 VREF (V) 0 2 4 HR mode, fIN = 4 kHz, VIN = 0.5 dBFS Figure 24. Total Harmonic Distortion vs VREF 5 2.5 -1 29 .8 04 .6 -1 08 .4 -1 -1 -1 16 .1 12 .3 0 20 16 18 D054 D074 HR mode, fIN = 4 kHz, VIN = 0.5 dBFS Total Harmonic Distortion (dB) .8 7.5 -1 28 10 -1 14 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 .2 Number of Occurrences Number of Occurrences 12 Figure 25. Total Harmonic Distortion vs fCLK 12.5 Total Harmonic Distortion (dB) 8 10 fCLK (MHz) fIN = 4 kHz, HR mode 15 D072 LP mode, fIN = 4 kHz, VIN = 0.5 dBFS Figure 26. Total Harmonic Distortion Histogram Figure 27. Total Harmonic Distortion Histogram 10 8 9 7 8 HR Mode LP Mode VLP Mode 6 7 Linearity (ppm) Number of Occurrences 6 D052 -1 21 2 .4 1.5 -1 23 1 25 -130 0.5 -1 Total Harmonic Distortion (dB) -100 6 5 4 3 5 4 3 2 2 1 1 0 -40 Total Harmonic Distortion (dB) 22 .3 -1 24 .1 -1 -1 26 27 .9 -1 29 .7 -1 31 .6 -1 33 .5 -1 -1 35 .4 0 -20 D073 0 20 40 60 Temperature (qC) 80 100 120 D050 VLP mode, fIN = 4 kHz, VIN = 0.5 dBFS Figure 28. Total Harmonic Distortion Histogram 18 Submit Documentation Feedback Figure 29. INL vs Temperature Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 Typical Characteristics (continued) Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications at TA = 25°C. All specifications at AVDD = 3 V, LVDD = 1.8 V (external), DVDD = 1.8 V, VREF = 2.5 V, INTLDO = 1, FILTER[1:0] = 01 (WB2), OSR[1:0] = 10 (OSR 128), and fCLK = 16.384 MHz for HR mode, 8.192 MHz for LP mode, or 4.096 MHz for VLP mode (unless otherwise noted) 3 2 1200 1.5 Number of Occurrences 1 0.5 0 -0.5 -1 -1.5 -2 1000 800 600 400 200 -2.5 D051 1 16 1 12 81 41 1 9 9 0 2.5 -3 2 -7 1.5 19 1 59 0 0.5 VIN (V) -1 -0.5 -1 -1 99 -1.5 31 -2 -2 -3 -2.5 -1 Linearity Error (ppm) 1400 25qC -40qC 125qC 2.5 Offset Error (PV) D042 Inputs shorted Figure 30. INL vs VIN Figure 31. Offset Error Histogram 200 1400 150 100 1000 Offset Error (PV) Number of Occurrences 1200 800 600 400 50 0 -50 -100 -150 -200 200 -250 -300 -40 53 -20 0 1. 1. 2 87 0. 55 1 22 0. 0. .1 3 -0 .4 6 -0 9 .7 .0 -0 1 -1 .4 -1 -1 .6 8 0 Gain Error (%FSR) D041 20 40 60 Temperature (qC) 80 100 120 D047 Inputs shorted Figure 33. Offset Error vs Temperature Figure 32. Gain Error Histogram -0.24 10 9 Number of Occurrences Gain Error (%FSR) -0.21 -0.18 -0.15 -0.12 8 7 6 5 4 3 2 1 9 1. 79 68 1. 57 1. 47 1. 36 1. 1. 14 03 1. 1. D049 92 0 120 0. 100 81 80 0. 20 40 60 Temperature (qC) 71 0 0. -20 0. 6 -0.09 -40 Offset Drift (PV/qC) D043 Inputs shorted, 30 devices Figure 34. Gain Error vs Temperature Figure 35. Offset Drift Histogram Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 19 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Typical Characteristics (continued) Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications at TA = 25°C. 10 20 9 17.5 8 Number of Occurrences Number of Occurrences All specifications at AVDD = 3 V, LVDD = 1.8 V (external), DVDD = 1.8 V, VREF = 2.5 V, INTLDO = 1, FILTER[1:0] = 01 (WB2), OSR[1:0] = 10 (OSR 128), and fCLK = 16.384 MHz for HR mode, 8.192 MHz for LP mode, or 4.096 MHz for VLP mode (unless otherwise noted) 7 6 5 4 3 15 12.5 10 7.5 5 D045 LP mode, 30 Devices Figure 36. Gain Drift Histogram Figure 37. Gain Drift Histogram 0.22 20 TA = 25qC TA = -40qC TA = 125qC 0.21 18 16 Gain Error (%FSR) 0.19 14 12 10 8 6 0.18 0.17 0.16 0.15 0.14 0.13 4 0.12 2 0.11 0 0.1 0 -0 .4 -0 .1 4 0. 11 0. 36 0. 61 0. 87 1. 12 1. 37 1. 63 1. 88 2. 13 -0 .6 5 Number of Occurrences 0.2 Gain Error (ppm/qC) 1 2 3 4 5 6 D046 Figure 39. Gain Error vs fCLK Figure 38. Gain Drift Histogram 250 5.29 TA = 25qC TA = -40qC TA = 125qC 200 5.27 Input Impedance (k:) 150 100 50 0 -50 -100 -150 5.25 5.23 5.21 5.19 5.17 5.15 -200 5.13 -250 5.11 -300 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 fCLK (MHz) D061 HR mode VLP mode, 30 Devices Offset Error (PV) 53 Gain Drift (ppm/qC) D044 HR mode, 30 Devices 7 8 9 10 11 12 13 14 15 16 17 fCLK (MHz) D062 5.09 -40 -20 0 20 40 60 80 Temperature (qC) 100 120 140 D075 HR mode, fCLK = 16.384 MHz Inputs shorted, HR mode Figure 40. Offset Voltage vs fCLK 20 1. 1. 25 97 0. 69 0. 0. 13 5 .1 -0 Gain Drift (ppm/qC) -0 .4 3 74 2. 09 42 2. 44 76 2. 1. 1. 79 11 1. 0. 0. 0. -0 . -0 . 46 0 14 0 19 2.5 51 1 0. 41 2 Figure 41. Differential Input Impedance vs Temperature Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 Typical Characteristics (continued) Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications at TA = 25°C. All specifications at AVDD = 3 V, LVDD = 1.8 V (external), DVDD = 1.8 V, VREF = 2.5 V, INTLDO = 1, FILTER[1:0] = 01 (WB2), OSR[1:0] = 10 (OSR 128), and fCLK = 16.384 MHz for HR mode, 8.192 MHz for LP mode, or 4.096 MHz for VLP mode (unless otherwise noted) 180 180 AVDD LVDD DVDD 170 160 150 150 140 140 PSRR (dB) PSRR (dB) 160 AVDD DVDD 170 130 120 110 130 120 110 100 100 90 90 80 80 70 70 60 60 0 50 100 150 200 250 300 fIN (kHz) 350 400 450 500 0 50 100 D076 HR mode, INTLDO = 1 Figure 42. PSRR vs Power-Supply Frequency HR Mode LP Mode VLP Mode 400 450 500 D077 HR Mode LP Mode VLP Mode 8 ILVDD (mA) IAVDD (mA) 350 Figure 43. PSRR vs Power-Supply Frequency 1.2 0.8 0.4 6 4 2 -20 0 20 40 60 Temperature (qC) 80 100 0 -40 120 -20 0 D056 Figure 44. IAVDD vs Temperature 20 40 60 Temperature (qC) 80 100 120 D057 Figure 45. ILVDD vs Temperature 30 3 Power Dissipation (mW) HR Mode LP Mode VLP Mode 2.4 IDVDD (mA) 250 300 fIN (kHz) 10 1.6 1.8 1.2 25 HR Mode LP Mode VLP Mode 20 15 10 0.6 0 -40 200 HR mode, INTLDO = 0 2 0 -40 150 -20 0 20 40 60 Temperature (qC) 80 100 5 -40 120 -20 D058 0 20 40 60 Temperature (qC) 80 100 120 D059 INTLDO = 1, LVDD = 1.8 V Figure 46. IDVDD vs Temperature Figure 47. Power Dissipation vs Temperature Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 21 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Typical Characteristics (continued) Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications at TA = 25°C. All specifications at AVDD = 3 V, LVDD = 1.8 V (external), DVDD = 1.8 V, VREF = 2.5 V, INTLDO = 1, FILTER[1:0] = 01 (WB2), OSR[1:0] = 10 (OSR 128), and fCLK = 16.384 MHz for HR mode, 8.192 MHz for LP mode, or 4.096 MHz for VLP mode (unless otherwise noted) 40 10 8 7 ILVDD (mA) Power Dissipation (mW) 9 HR Mode LP Mode VLP Mode 32 24 16 6 5 4 8 3 0 -40 1 HR Mode LP Mode VLP Mode 2 -20 0 20 40 60 Temperature (qC) 80 100 120 0 1 2 3 4 5 D060 6 7 8 9 10 11 12 13 14 15 16 17 fCLK (MHz) D063 INTLDO = 0 Figure 49. ILVDD vs fCLK 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) Figure 48. Power Dissipation vs Temperature 0 -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 40 80 120 160 Frequency (kHz) 200 240 0 5 D064 Inputs shorted, HR mode, LL, 512 kSPS, 32768 samples Inputs shorted, HR mode, LL, 128 kSPS, 32768 samples Figure 51. Output Spectrum 0 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) Figure 50. Output Spectrum -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Frequency (kHz) D065 Inputs shorted, HR mode, LL, 32 kSPS, 32768 samples 0 0.4 0.8 1.2 1.6 2 2.4 Frequency (kHz) 2.8 3.2 3.6 4 D067 Inputs shorted, HR mode, LL, 8 kSPS, 32768 samples Figure 52. Output Spectrum 22 10 15 20 25 30 35 40 45 50 55 60 65 Frequency (kHz) D065 Figure 53. Output Spectrum Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 Typical Characteristics (continued) Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications at TA = 25°C. 5000 Number of Occurrences 4500 4000 3500 3000 2500 2000 1500 1000 500 Voltage (PV) 5 .2 8. 10 4 2 6. 1 4. 2. 0 .1 -2 .2 4. 1 3. 1 2 1 0 -1 Voltage (PV) D070 Inputs shorted, HR mode, LL, 32 kSPS, 32768 samples -2 -3 -3 .1 6500 6000 5500 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 .9 6 Number of Occurrences Noise (PV) 7. 6 4 2 0 -2 -4 -6 4 Figure 55. Noise Histogram 7000 6500 6000 5500 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 .6 D069 Inputs shorted, HR mode, LL, 128 kSPS, 32768 samples Figure 54. Noise Histogram -7 -4 Voltage (PV) D068 Inputs shorted, HR mode, LL, 512 kSPS, 32768 samples Number of Occurrences -6 . 2 .5 0. -8 -1 .2 .5 20 16 4 .8 10 5. 0 4 -5 . 8 0. -1 2 0 6. -2 0. 5 7000 6500 6000 5500 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 -1 Number of Occurrences All specifications at AVDD = 3 V, LVDD = 1.8 V (external), DVDD = 1.8 V, VREF = 2.5 V, INTLDO = 1, FILTER[1:0] = 01 (WB2), OSR[1:0] = 10 (OSR 128), and fCLK = 16.384 MHz for HR mode, 8.192 MHz for LP mode, or 4.096 MHz for VLP mode (unless otherwise noted) D071 Inputs shorted, HR mode, LL, 8 kSPS, 32768 samples Figure 56. Noise Histogram Figure 57. Noise Histogram 7 Parameter Measurement information 7.1 Noise Performance Adjust the oversampling ratio (OSR) to control the data rate and change the digital filter in order to optimize the noise performance of the ADS127L01. Hardware control pins create four oversampling options and three selectable digital filter options to configure the ADC for a specific bandwidth of interest. When averaging is increased by reducing the data rate (increasing the OSR), the in-band noise drops as more samples from the modulator are averaged to yield one conversion result. Table 1 and Table 2 summarize the device noise performance across the various oversampling options and digital filter options. Wideband 1 filter has a filter transition band of (0.45 × 0.55) fDATA, and wideband 2 filter has a filter transition band of (0.40 × 0.50) fDATA. Data are representative of typical noise performance at TA = 25°C with an external 2.5-V reference. Data shown are the result of one standard deviation of the readings with the inputs shorted together and biased to midsupply. A minimum of 1,000 consecutive readings are used to calculate the VRMS_noise voltage noise for each reading. Equation 1 is used to convert the noise in VRMS_noise to SNR, and Equation 2 is used to convert the noise in VRMS_noise to ENOB. The peak-to-peak noise for the low-latency filter is defined as VPP_noise. SNR = 20 × log (VREF × 0.7071 / VRMS_noise) ENOB = log2 (VREF × 0.7071 / VRMS_noise) (1) (2) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 23 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Noise Performance (continued) Table 1. Wideband Filters Performance Summary at AVDD = 3.0 V, DVDD = 1.8 V, and 2.5-V Reference MODE DATA RATE (SPS) OSR 512,000 32 256,000 64 128,000 128 64,000 256 256,000 32 128,000 64 64,000 128 32,000 256 128,000 32 64,000 64 32,000 128 16,000 256 High-resolution (HR) Low-power (LP) Very-low-power (VLP) TRANSITION BAND PASSBAND (kHz) SNR (dB) VRMS_noise (μVRMS) ENOB Wideband 1 filter 230.4 103.7 11.61 17.22 Wideband 2 filter 204.8 104.1 10.64 17.34 Wideband 1 filter 115.2 107.3 7.61 17.83 Wideband 2 filter 102.4 107.7 7.25 17.90 Wideband 1 filter 57.6 110.4 5.35 18.33 Wideband 2 filter 51.2 110.9 5.06 18.41 Wideband 1 filter 28.8 113.4 3.79 18.83 Wideband 2 filter 25.6 113.9 3.58 18.91 Wideband 1 filter 115.2 103.9 11.27 17.26 Wideband 2 filter 102.4 104.7 10.31 17.39 Wideband 1 filter 57.6 107.6 7.38 17.87 Wideband 2 filter 51.2 108.1 6.96 17.95 Wideband 1 filter 28.8 110.7 5.18 18.38 Wideband 2 filter 25.6 111.1 4.95 18.45 Wideband 1 filter 14.4 113.7 3.67 18.88 Wideband 2 filter 12.8 114.1 3.47 18.96 Wideband 1 filter 57.6 104.1 11.01 17.29 Wideband 2 filter 51.2 104.9 10.11 17.42 Wideband 1 filter 28.8 107.8 7.20 17.91 Wideband 2 filter 25.6 108.3 6.80 17.99 Wideband 1 filter 14.4 110.9 5.07 18.41 Wideband 2 filter 12.8 111.3 4.81 18.49 Wideband 1 filter 7.2 113.9 3.59 18.91 Wideband 2 filter 6.9 114.3 3.41 18.98 IDVDD (mA) 7.50 4.35 2.80 2.00 3.80 2.25 1.50 1.10 1.95 1.20 0.80 0.60 Table 2. Low-Latency Filter Performance Summary at AVDD = 3.0 V, DVDD = 1.8 V, and 2.5-V Reference MODE High-resolution (HR) Low-power (LP) Very-low-power (VLP) 24 OSR -3-dB BANDWIDTH (kHz) SNR (dB) VRMS_noise (μVRMS) ENOB VPP_noise (μVPP) IDVDD (mA) 512,000 32 101.8 107.6 7.40 17.87 64.67 1.60 128,000 128 50.6 110.8 5.12 18.40 44.11 1.39 32,000 512 13.7 116.2 2.74 19.30 24.14 1.33 8,000 2048 3.5 122.0 1.41 20.26 11.32 1.32 256,000 32 50.9 107.8 7.22 17.90 61.99 0.85 64,000 128 25.3 111.0 4.97 18.44 46.79 0.75 16,000 512 6.9 116.5 2.65 19.35 22.05 0.73 4,000 2048 1.7 122.2 1.37 20.30 10.73 0.72 128,000 32 25.5 108.1 6.97 17.95 65.57 0.50 32,000 128 12.7 111.3 4.80 18.49 39.64 0.44 8,000 512 3.4 116.7 2.57 19.39 20.27 0.41 2,000 2048 0.9 122.4 1.34 20.33 10.73 0.40 DATA RATE (SPS) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 8 Detailed Description 8.1 Overview The ADS127L01 is a 24-bit delta-sigma (ΔΣ) ADC that offers a combination of excellent dc accuracy and ac performance. The flexible digital-filter options make it suitable for both dc and ac applications. The device is hardware programmable, making it easy to configure into a variety of applications without the need to write to registers. The Functional Block Diagram shows the main internal features of the ADS127L01. The converter is comprised of an advanced, third-order, chopper-stabilized, delta-sigma modulator, that measures the differential input signal, VIN = (VAINP – VAINN), against the differential reference, VREF = (VREFP – VREFN). The converter core consists of a differential, switched-capacitor, delta-sigma modulator followed by a selectable digital filter. The digital-filter, low-latency path uses a cascaded combination of a fifth-order sinc and a first-order sinc filter, ideal for applications requiring fast response or systems using a multiplexed input. Two wide-bandwidth paths (wideband 1 and wideband 2) are also available, providing outstanding frequency response with very low passband ripple, a steep-transition band, and large stop-band attenuation. The ADS127L01 provides two selectable options for transition-band frequency. The wideband-filter paths are suited for applications that require high-resolution measurements of high-frequency, ac-signal content. To allow tradeoffs among speed, resolution, and power, three operating modes are supported: high-resolution (HR), low-power (LP), and very-low-power (VLP). In HR mode, SNR = 104.4 dB (VREF = 2.5 V) at a maximum data rate of 512 kSPS. At this data rate, the power dissipation is only 35 mW, and scales with master clock frequency. In LP mode, the maximum data rate is 256 kSPS, while consuming only 19 mW of power. In VLP mode, the maximum data rate is 128 kSPS, while consuming only 9 mW of power. Configure the ADS127L01 by setting the appropriate hardware I/O pins. Registers are available to control gain and offset calibrations that help with data calibration adjustments. Three interface communication modes are available, providing flexibility for convenient interfacing to microcontrollers, DSPs, or FPGAs. SPI, frame-sync slave, or frame-sync master communication modes are hardware selectable on the device. The ADS127L01 has a daisy-chain output available, and can synchronize externally to another device or system using the START signal. The daisy-chain configuration allows the device to be used conveniently in systems that require multiple channels. 8.2 Functional Block Diagram REFP REFN LVDD AVDD DVDD LDO INTLDO SCLK SPI and Frame-Sync Interface Low-Latency Filter AINP û ADC Modulator AINN Wideband 1 Filter CS DIN DOUT DRDY/FSYNC DAISYIN Wideband 2 Filter FSMODE FORMAT Control Logic RESET/PWDN OSR [1:0] FILTER [1:0] CLK ADS127L01 DGND AGND Copyright © 2016, Texas Instruments Incorporated Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 25 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com 8.3 Feature Description This section discusses the details of the ADS127L01 internal functional elements. Throughout this document, fCLK denotes the frequency of the signal at the CLK pin, tCLK denotes the period of the signal at the CLK pin, fDATA denotes the output data rate, and tDATA denotes the time period of the output data. 8.3.1 Analog Inputs (AINP, AINN) The ADS127L01 measures the differential input signal VIN = (VAINP – VAINN) against the differential reference VREF = (VREFP – VREFN). The most positive measurable differential input is +VREF and the most negative measurable differential input is –VREF. For optimum performance, drive the ADS127L01 inputs differentially, centered around a common-mode voltage of VAVDD / 2. Alternatively, if the signal is of pseudo-differential nature, the negative input can be held at a constant voltage other than 0 V (typically VAVDD / 2), and the voltage on the positive input can change. Figure 58 and Figure 59 show examples of both fully-differential and pseudo-differential signals, respectively. AINP AINP VCM VCM 1.5 V 1.5 V AINN AINN 0V 0V Figure 59. Pseudo-Differential Input Signal Figure 58. Fully-Differential Input Signal Electrostatic discharge (ESD) diodes to AVDD and GND protect the inputs. To prevent the ESD diodes from turning on, the absolute voltage on any input must stay within the range provided by Equation 3: GND – 0.3 V < VAINx < AVDD + 0.3 V (3) The analog input pins, AINP and AINN, at the front end of the converter are connected directly to the switchedcapacitor sampling network to measure the input voltage. Figure 60 shows a conceptual diagram of the modulator circuit charging and discharging the sampling capacitor through switches, although the actual implementation is slightly different. The sampling time (tCLK) is equivalent to the master clock period, and is the inverse of modulator sampling frequency. AVDD AGND tCLK = 1/fCLK AINP S1 S1 ON OFF S2 8pF S2 AINN S1 ON OFF AVDD AGND Figure 60. Equivalent Analog Input Circuitry 26 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 Feature Description (continued) The average load presented by the switched-capacitor input can be modeled with an effective differential impedance, as shown in Figure 61. The effective impedance is a function of the modulator clock, and is equal to the master clock, fCLK. The ADS127L01 samples the input at very high speeds, and does not include an integrated buffer; a suitable driver must be used. See the Application and Implementation section for recommended driver circuit designs. AINP Zeff = 5 k x (16.384MHz/fCLK) AINN Figure 61. Effective Input Impedance The ADC sampling network is connected to a delta-sigma modulator used to convert the analog input voltage into a data bit stream. The modulator is third-order, with a multibit quantizer that runs at the modulator clock frequency, fMOD, equal to the master clock frequency, fCLK. 8.3.2 Digital Filter The ADS127L01 offers three selectable digital filters to perform both filtering and oversampling of the digital data stream coming from the modulator. The oversampling ratio (OSR) and digital-filter selection sets the overall frequency response for the data converter. The available filter options for the ADS127L01 are: • A low-latency sinc filter (LL) • A wideband finite impulse response (FIR) filter with a transition band of (0.45 to 0.55) × fDATA (WB1) • a wideband finite impulse response (FIR) filter with a transition band of (0.40 to 0.50) × fDATA (WB2) The filter is selected using the hardware FILTER[1:0] pins shown in Table 11. Each filter has four OSR options (the ratio of the modulator sampling to the output data rate, or fMOD / fDATA), shown in Table 12, that are selectable through hardware the OSR[1:0] mode pins. The low-latency sinc filter is a cascaded sinc5 and sinc1 filter, and provides OSR options to achieve data rates ranging from 8 kSPS to 512 kSPS when operating from a 16.384-MHz master clock. The two wideband filters use a multistage FIR topology to provide linear phase with very low passband ripple and high stop-band attenuation. Wideband filters 1 and 2 provide four OSRs to achieve data rates ranging from 64 kSPS to 512 kSPS when operating from a 16.384-MHz master clock. Select the filter and data rate when START is low, or when the START or RESET/PWDN pin is taken low and back high after a filter-path or data-rate change. If software commands are used to control conversions, use the stop and start commands after a change to the filter path selection or the data rate. If a conversion is in process during a filter-path or data-rate change, the output data are not valid and must be discarded. 8.3.2.1 Low-Latency Filter Mode The low-latency sinc filter design consists of two stages: a fixed-decimation, fixed-order, sinc5 filter, followed by a variable-decimation, fixed-order, sinc1 filter. The first-stage, sinc5 digital filter decimates by a fixed value of 32. When using OSR 32, the first-stage digital filter bypasses the second filter stage, and has a sinc5 frequency response profile. The second digital-filter stage provides an additional oversampling of 4, 16, or 64 to create an overall oversampling of 128, 512, and 2048 options, respectively. Together, the two stages create four selectable, low-latency, filter data rates when operated from a 16.384-MHz clock: 512 kSPS, 128 kSPS, 32 kSPS, and 4 kSPS. 8.3.2.1.1 Low-Latency Filter Frequency Response The low-pass filtering effect of the sinc filter sets the overall frequency response of the ADC when in low-latency filter mode. The frequency response of OSR 32 is from only the sinc5 filter stage. The frequency response of OSR 128, 512, or 2048 is the product of the sinc5 first-stage and sinc1 second-stage frequency responses. The overall filter response is given in Equation 4: Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 27 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Feature Description (continued) 5 Hsinc 5 (f ) u Hsinc1 (f ) H(f ) ª 32Sf º ª 32NSf º sin « sin « » » fCLK ¼ ¬ fCLK ¼ ¬ u ª Sf º ª 32Sf º 32 u sin « N u sin « » » ¬ fCLK ¼ ¬ fCLK ¼ where • • • f = signal frequency fCLK = ADC master clock frequency = ADC modulator clock frequency N = Second-stage oversampling = 1 (OSR 32), 4 (OSR 128), 16 (OSR 512), or 64 (OSR 2048) (4) The inherent nature of the sinc filter response begins to attenuate frequencies as the signal moves away from dc. Expect pass-band droop for inband ac signals to the Nyquist rate, making the low-latency filter less than ideal for ac signals. As shown in Figure 62 and Figure 63, when OSR is set to 32, the digital filter frequency response follows a sinc5 transfer function with nulls occurring at fDATA and at data-rate multiples. At the null frequencies, the filter has zero gain. Convert the x-axis from the data rate, fDATA, to terms of the master clock, fCLK, by using Equation 5: fDATA = fCLK / OSR (5) 0 0 -20 -25 -40 -50 -75 Amplitude (dB) Amplitude (dB) -60 -80 -100 -120 -100 -125 -150 -140 -175 -160 -200 -180 -225 -250 -200 0 0.5 1 1.5 2 2.5 3 3.5 4 Normalized Input Frequency (fIN/fDATA) 4.5 5 0 2 D001 Figure 62. Low-Latency Filter Frequency Response (OSR 32) 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Normalized Input Frequency (fIN/fDATA) D002 Figure 63. Low-Latency Filter Frequency Response (OSR 32) to fCLK Adjust the digital-filter response by changing the OSR or the master clock, fCLK. Noise tradeoffs are made with signal bandwidth and filter latency. Selecting an OSR other than 32 superimposes new nulls from the second-stage sinc1 filter over the nulls produced by the sinc5 stage. The end result is a combined frequency response from a sinc5 function at OSR 32 with nulls created from the sinc1 second stage and at data-rate multiples. Figure 64 and Figure 65 illustrate the normalized frequency response of the low-latency filters across all four OSR settings. OSR 32 follows a sinc5 frequency response, as highlighted in Figure 62. OSR 128, OSR 512, and OSR 2048 show a combined sinc5 and sinc1 response. Figure 66, Figure 67, and Figure 68 illustrate the frequency response of OSR 128, OSR 512, and OSR 2048, respectively. The low-latency filter uses a multiple-stage, linear-phase, digital filter. Linear-phase filters exhibit constant delay time versus input frequency (also known as constant group delay). This feature of linear phase filters means that the time delay from any instant of the input signal to the corresponding same instant of the output data is constant and independent of the input-signal frequency. This behavior results in essentially zero phase error when measuring multitone signals. 28 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 0 0 -20 -2 -40 -4 -60 -6 Amplitude (dB) Amplitude (dB) Feature Description (continued) -80 -100 -120 -140 -180 -10 -12 -14 OSR 32 OSR 128 OSR 512 OSR 2048 -160 -8 OSR 32 OSR 128 OSR 512 OSR 2048 -16 -18 -200 -20 0 0.5 1 1.5 2 2.5 3 3.5 4 Normalized Input Frequency (fIN/fDATA) 4.5 5 0 D003 Figure 64. Low-Latency Filter Frequency Response (All OSRs) 0.5 D003 Figure 65. Low-Latency Filter Frequency Response (All OSRs) to 0.5 × fIN / fDATA 0 0 -25 -25 -50 -50 -75 Amplitude (dB) -75 Amplitude (dB) 0.1 0.2 0.3 0.4 Normalized Input Frequency (fIN/fDATA) -100 -125 -150 -100 -125 -150 -175 -175 -200 -200 -225 -225 -250 -250 0 20 40 60 80 100 Normalized Input Frequency (fIN/fDATA) 120 0 D004 Figure 66. Low-Latency Filter Frequency Response (OSR 128) 80 160 240 320 400 Normalized Input Frequency (fIN/fDATA) 480 D005 Figure 67. Low-Latency Filter Frequency Response (OSR 512) 0 -25 -50 Amplitude (dB) -75 -100 -125 -150 -175 -200 -225 -250 0 300 600 900 1200 1500 1800 Normalized Input Frequency (fIN/fDATA) 2100 D006 Figure 68. Low-Latency Filter Frequency Response (OSR 2048) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 29 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Feature Description (continued) 8.3.2.1.2 Low-Latency Filter Settling Time The low-latency filter takes several conversion cycles to provide fully-settled data following a START pin low-tohigh transition or a start command. The OSR setting determines the exact number of conversion cycles for first new available data, as shown in Table 3. In SPI mode, the DRDY signal remains high until settled data are available. After settled data are available, a high-to-low transition on DRDY takes place. In frame-sync mode, DOUT shifts zeroes until settled data are available. Figure 69 shows the relationship between START to the first settled available data for SPI and frame-sync interface mode. See the Start Pin (START) section for exact timing for the START pin to first available data. START Command START or START Pin DRDY Settled Data FSYNC Figure 69. START to First Available Data When applying an asynchronous step input to a converting ADS127L01, the output shift register does not gate data during digital-filter settling. The step-input-setting timing diagram shown in Figure 70 illustrates the converter step response with an asynchronous step input. The time that the analog input must be stable varies depending on the OSR. Table 3 summarizes the settling time of the low-latency filter when a step input is applied to the input. Step Input DRDY FSYNC 1 2 1 2 Figure 70. Asynchronous Step-Input Settling Time Table 3. Low-Latency Filter Settling Time 30 OSR SETTLING TIME FROM START (tCLK Periods) INPUT SETTLING (DRDY or FSYNC Pulses) 32 160 5 128 288 3 512 672 2 2048 2208 2 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 8.3.2.2 Wideband Filter Mode The two wideband filters use a multistage FIR topology to provide linear phase with minimal passband ripple and high stop-band attenuation. The filters are well suited for measuring high-frequency ac signals while still maintaining excellent dc accuracy. Both wideband filter options offer the same four OSR options; 32, 64, 128, and 256. The difference is in the transition band. When these four OSRs are paired with a 16.384-MHz clock, four selectable wideband filter data rates are created: 512 kSPS, 256 kSPS, 128 kSPS, and 64 kSPS. 8.3.2.2.1 Wideband Filters Frequency Response 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 Amplitude (dB) Amplitude (dB) Figure 71 shows the frequency response of the wideband 1 filter with a transition band of (0.45 to 0.55) × fDATA normalized to the output data rate, fDATA. Figure 72 shows the frequency response of the wideband 2 filter with a transition band of (0.40 to 0.50) × fDATA normalized to the output data rate, fDATA. These plots are valid for all of the data rates available on the ADS127L01. Substitute the selected data rate (calculated using Equation 5) to express the x-axis in absolute frequency. Figure 73 overlaps the transition band of the wideband 1 and wideband 2 filters, showing the difference in frequency response. The wideband 2 filter frequency response is designed to attenuate out-of-band signals more than –116 dB by the Nyquist frequency (0.5 × fDATA) to reduce the effects of aliasing near the transition band. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Normalized Input Frequency (fIN/fDATA) 0.9 1 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Normalized Input Frequency (fIN/fDATA) D007 FILTER[1:0] = 00 Amplitude (dB) 1 D008 FILTER[1:0] = 01 Figure 71. Wideband 1 Filter Frequency Response 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0.35 0.9 Figure 72. Wideband 2 Filter Frequency Response WB1 Filter WB2 Filter 0.4 0.45 0.5 0.55 Normalized Input Frequency (fIN/fDATA) 0.6 D001 Figure 73. Wideband Filters Transition Band Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 31 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com 0.00010 0.00010 0.00008 0.00008 0.00006 0.00006 0.00004 0.00004 Amplitude (dB) Amplitude (dB) The passband ripple for the two digital filters are shown in Figure 74 and Figure 75. 0.00002 0.00000 -0.00002 0.00002 0.00000 -0.00002 -0.00004 -0.00004 -0.00006 -0.00006 -0.00008 -0.00008 -0.00010 -0.00010 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 Normalized Input Frequency (fIN/fDATA) D010 0 FILTER[1:0] = 00 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 Normalized Input Frequency (fIN/fDATA) D011 FILTER[1:0] = 01 Figure 74. Pass-Band Ripple for Wideband 1 Filter Figure 75. Pass-Band Ripple for Wideband 2 Filter Amplitude (dB) The overall frequency response repeats at the modulator sampling rate, which is the same as the input clock frequency, fCLK. Figure 76 shows the response with the fastest data rate selected (512 kSPS when fCLK = 16.384 MHz). 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Normalized Input Frequency (fIN/fDATA) D013 Figure 76. Extended Frequency Response of Wideband 1 Filter (OSR 32) The wideband filters use a multiple-stage, linear-phase, digital-filter architecture. Linear-phase filters exhibit constant delay time versus input frequency (also known as constant group delay). This feature of linear phase filters means that the time delay from any instant of the input signal to the corresponding same instant of the output data is constant and independent of the input-signal frequency. This behavior results in essentially zero phase error when measuring multitone signals. 32 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 8.3.2.2.2 Wideband Filters Settling Time The wideband filters fully settle before outputting data for retrieval after the START pin low-to-high transition or a start command is issued. The settling time of the wideband filters is 84 conversion cycles; the DRDY signal idles high and does not assert until new settled data are available in SPI mode. In frame-sync mode, the output shift register outputs zeroes in place of the conversion data for 84 conversion cycles until the first settled data are available. A step input on the analog input requires multiple conversions to settle if START is not pulsed, or if the start command is not issued. Figure 77 shows the settling response with the x-axis normalized to conversions or DRDY/FSYNC cycles. 150 Fully Settled Data at 84 Conversions 130 110 Settling (%) 90 70 50 30 10 -10 -30 -50 0 10 20 30 40 50 60 70 Conversions (1/fDATA) 80 90 100 D012 Figure 77. Step Response For Wideband Filters 60 120 65 115 70 110 75 105 80 100 Settling (%) Settling (%) Figure 78 and Figure 79 plot the undershoot and overshoot from the wideband digital filter during an input step function. 85 90 95 95 90 85 100 80 105 75 110 70 115 65 120 40 42 44 46 48 50 52 54 Conversions (1/fDATA) 56 58 60 60 40 42 D001 Figure 78. Wideband Filters Step-Response Undershoot 44 46 48 50 52 54 Conversions (1/fDATA) 56 58 60 D020 D001 Figure 79. Wideband Filters Step-Response Overshoot Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 33 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com 8.3.3 Voltage Reference Inputs (REFP, REFN) The ADC requires the connection of an external reference voltage for operation. The voltage reference for the device is the differential voltage between REFP and REFN: VREF = (VREFP – VREFN). The reference inputs are not buffered and use a sampling structure similar to that of the analog inputs, with the equivalent circuitry on the reference inputs shown in Figure 80. The load across REFP and REFN is presented by the switched-capacitor in parallel with a 6.4-kΩ resistor, and is modeled with an effective impedance proportional to the master clock, fCLK, as shown in Figure 81. REFP REFN AVDD AVDD AGND AGND Figure 80. Equivalent Reference Input Circuitry REFP Zeff = (3.4 k REFN × 16.384 MHz / fCLK) || 6.4 k Figure 81. Effective Reference Impedance ESD diodes protect the reference inputs. To keep these diodes from turning on, make sure the voltages on the reference pins do not go below AGND by more than 0.3 V, and do not exceed AVDD by 0.3 V. Use external Schottky clamp diodes or series resistors to limit the input current to safe values if the reference input may exceed the absolute maximum ratings (see the Absolute Maximum Ratings table). A high-quality reference voltage with the appropriate drive strength is required for achieving the best performance from the ADS127L01. Noise and drift on the reference degrade overall system performance. Use a minimum parallel combination of 10-µF and 0.1-µF ceramic bypass capacitors directly across the reference inputs, REFP and REFN. Place these capacitors as close as possible to the device on the layout. See the Application Information section for example reference circuits. 34 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 8.3.4 Clock Input (CLK) The ADS127L01 requires an external clock input for operation. This clock signal is used for the sampling network of the modulator without any prescalers or dividers, and for the timing for the digital filter. Drive the ADC with an external clock by applying the clock input to the CLK pin. At the maximum data rate, the clock input is 16.384 MHz for HR mode, 8.192 MHz for LP mode, and 4.096 MHz for VLP mode. A high-quality, low-jitter clock is essential for optimum performance measuring the high-frequency input signal, fIN. Any uncertainty during sampling of the input from clock jitter limits the maximum achievable SNR. For example, target a external clock with better than 10 psrms jitter for a 200-kHz fIN. For a lower fIN, the target jitter requirement can be relaxed by –20 dB per decade. At fIN = 20 kHz, use a clock with better than 100-psrms jitter. The selection of the external clock frequency (fCLK) does not affect the resolution of the ADS127L01. The output data rates scale with fCLK frequency down to a minimum clock frequency of fCLK = 100 kHz. Use a slower fCLK to reduce the ADC power consumption and relax the requirements of an external ADC drive circuit on the analog input and reference input. Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock input. A source-terminating resistor placed at the external clock buffer often helps to reduce overshoot. 8.3.5 Out-of-Range-Detect System Monitor An out-of-range-detect, system-monitor bit (INP) is available in the status word (see the Status Word section). The out-of-range detect bit flags (INP = 1) when the input exceeds the positive or negative full-scale range, set by VREF, with each conversion result. The input is monitored using an analog comparator. The alert is enabled when the range is exceeded without waiting for the conversions to propagate through the digital filter. The INP bit is used for narrow out-of-range input glitches that may or may not be removed by the ADC digital filter. 8.3.6 System Calibration The ADC incorporates optional offset- and gain-calibration registers to system-calibrate the ADC and signal chain when in SPI mode. Enable the offset calibration register by setting FSC (bit 5 in the Configuration register) to 1, and enable the gain calibration register by setting OFC (bit 4 in the Configuration register) to 1. The programmable offset calibration value is 24 bits wide, and the gain calibration value is 16 bits wide. Use calibration to correct internal ADC errors or overall system errors. Calibration is only supported through direct user calibration, requiring the user to calculate and write the correction values to the calibration registers. Perform a system offset calibration before full-scale calibration. After power-up, but before calibrating, wait for the power supplies and reference voltage to fully settle. As shown in Figure 82, the value of the offset calibration register is subtracted from the filter output, and then multiplied by the full-scale register value. The data are then clipped to a 24-bit value to provide the final output. VAINP VAINN Digital Filter ADC + Output Data Clipped to 24 Bits Final Output OFC[2:0] registers (register addresses = 02h, 03h, 04h) > 000000h: negative offset 000000h: no offset < 000000h: positive offset FSC[1:0] registers (register addresses = 05h, 06h) < 8000h: gain > 1 8000h: gain = 1 > 8000h: gain < 1 Figure 82. ADC Calibration Block Diagram Equation 6 shows the internal calibration on the data result. ADC Final Output Data = (Filter Output – OFC[2:0]) × FSC[1:0] / 8000h (6) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 35 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com The ADC offset calibration word is 24 bits, consisting of three 8-bit registers, as shown in Table 4. The offset value is twos complement format with a maximum positive value equal to 7FFFFFh (for negative offset), and a maximum negative value equal to 800000h (for positive offset). A register value equal to 000000h has no offset correction. For offset calibration, short the ADC inputs or system inputs, and average the conversions; averaging reduces noise for a more accurate calibration. Write the average value to the offset calibration registers. The ADC subtracts the value from the conversion result. Table 4. Offset Calibration Registers REGISTER BYTE ORDER ADDRESS OFC0 LSB 02h OFC_B7 OFC_B6 OFC_B5 OFC_B4 OFC_B3 OFC_B2 OFC_B1 OFC_B0 (LSB) OFC1 MID 03h OFC_B15 OFC_B14 OFC_B13 OFC_B12 OFC_B11 OFC_B10 OFC_B9 OFC_B8 OFC2 MSB 04h OFC_B23 (MSB) OFC_B22 OFC_B21 OFC_B20 OFC_B19 OFC_B18 OFC_B17 OFC_B16 BIT ORDER The ADC gain calibration word is 16 bits consisting of two 8-bit registers, as shown in Table 5. The full-scale calibration value is twos compliment, with a unity-gain correction factor at a register value equal to 8000h. Table 6 shows register values for selected gain factors. Table 5. Gain Calibration Registers REGISTER BYTE ORDER ADDRESS FSC0 LSB 05h FSC_B7 FSC_B6 FSC_B5 FSC_B4 FSC_B3 FSC_B2 FSC_B1 FSC_B0 (LSB) FSC1 MSB 06h FSC_B15 (MSB) FSC_B14 FSC_B13 FSC_B12 FSC_B11 FSC_B10 FSC_B9 FSC_B8 BIT ORDER Table 6. Gain Calibration Register Values FSCAL[2:0] REGISTER VALUE GAIN FACTOR 7FFFh 2.00 8000h 1.00 0000h 0.00 For gain calibration, apply a dc calibration voltage that is less than positive full-scale voltage in order to avoid clipped codes (VIN < +FSR), and average the conversions to reduce noise for a more accurate calibration. Gain calibration is computed as shown in Equation 7, after offset error is removed. Full-Scale Calibration = Expected Code Value / Actual Code Value (7) If the actual code is higher than the expected value, then the calculated calibration value is less than 8000h, and the ADC gain is subsequently reduced. Write the calibration value to the gain calibration registers. 36 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 8.4 Device Functional Modes 8.4.1 Mode Selection The ADS127L01 offers three operational modes: high-resolution (HR), low-power (LP), and very-low-power (VLP). These modes optimize power consumption by restricting the maximum master-clock frequency (fCLK) controlling the data rate. The status of the HR pin determines if the device is in HR mode or LP mode. Enter VLP mode by setting the ADS127L01 in LP mode, and increasing the value of the external REXT power scaling resistor from 60.4 kΩ to 120 kΩ. The tolerance on the REXT power-scaling resistor must be 1% or better. The analog current consumed by AVDD and LVDD decreases when in LP mode, and decreases further in VLP mode, with a tighter restriction on maximum master-clock frequency. Table 7 details the modes, settings, and master clock limitations in the ADS127L01. Table 7. Mode Selection MODE MODE SELECTION PIN (HR) REXT VALUE MAXIMUM fCLK High-Resolution (HR) 1 60.4 kΩ 17.6 MHz Low-Power (LP) 0 60.4 kΩ 8.8 MHz Very-Low-Power (VLP) 0 120 kΩ 4.4 MHz 8.4.2 Hardware Configuration Pins The ADS127L01 uses two-state hardware mode pins for ADC configuration. The operating mode, interface selection, digital filter selection, and oversampling ratio (OSR) options are all controlled through hardware control pins. These pins are constantly monitored, and set by either pulling them high to DVDD, or low to DGND. Use pull-up or pull-down 100-kΩ resistors, or directly tie the pins to microcontroller or DSP I/O lines to set the state of the pins. When a change is sensed on the hardware mode pins after power-up, the ADC automatically issues a reset. To ensure synchronization, issue a software reset command, or pulse the RESET/PWDN pin following the mode change delay, td(MD). When using the SPI protocol, DRDY is held high after a mode change occurs until settled data are ready; see Figure 83 and Table 8. MODE pin td(MD) ADS127L01 Mode New Mode Old Mode td(FILT) CLK td(NDR) DRDY Figure 83. Mode Change Timing (SPI) Table 8. SPI Protocol New Data After Mode Change SYMBOL DESCRIPTION MIN td(MD) Delay time: MODE pin rising edge to mode change td(FILT) Delay time: mode change to first modulator sample td(NDR) Delay time for new data to be ready TYP 3.5 MAX UNIT 3 tCLK 4.5 tCLK Wideband filters 84 tDATA Low-latency filter See Table 3 tDATA Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 37 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com In Frame-sync protocol, the DOUT pins are held low after a mode change occurs until settled data are ready; see Figure 84 and Table 9. Data can be read from the device to detect when DOUT changes, indicating that data are valid. MODE pin td(MD) ADS127L01 Mode New Mode Old Mode CLK tsu(FILT) FSYNC td(NDR) DOUT New Data Figure 84. Mode Change Timing (Frame-Sync Interface) Table 9. Frame-Sync Protocol New Data After Mode Change SYMBOL td(MD) tsu(FILT) td(NDR) DESCRIPTION MIN TYP Delay time: MODE pin rising edge to mode change Setup time: mode change to FSYNC rising edge Delay time for new data to be ready MAX UNIT 3 tCLK Frame-sync slave 5 tCLK Frame-sync master 1 tCLK Wideband filters 84 tDATA Low-latency filter See Table 3 tDATA 8.4.2.1 Interface Selection Pins (FORMAT, FSMODE) Data are read from the ADS127L01 using one of two selectable interface protocols, SPI or frame-sync. Use the FORMAT input pin to select among the two interface options. If the frame-sync interface is selected, the ADS127L01 offers either a master or slave option, selectable using the FSMODE pin. Table 10 lists the available options. Table 10. Data Output Options 38 FORMAT FSMODE INTERFACE PROTOCOL 0 0 SPI 0 1 SPI 1 0 Frame-sync slave mode 1 1 Frame-sync master mode Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 8.4.2.2 Filter Selection Pins (FILTER) Three digital filter options are available in the ADS127L01: two wideband filter options, and a low-latency filter. See the Digital Filter section for detailed information on the digital filters and the frequency responses. The FILTER[1:0] hardware mode pins set the filter path selection for the modulator data, as shown in Table 11. Select the filter when START is low, or when the START or RESET/PWDN pin is taken low and back high after a filter path change. If software commands are used to control conversions, use the stop and start commands after a change to the filter path selection. If a conversion is in the process during a filter path change, the output data are not valid and must be discarded. Table 11. Digital-Filter Path Selection FILTER1 FILTER0 SELECTED FILTER PATH FILTER TRANSITION BAND 0 0 Wideband 1 filter 0.45 × fDATA to 0.55 × fDATA 0 1 Wideband 2 filter 0.40 × fDATA to 0.50 × fDATA 1 0 Low-latency filter 1 1 SINC5 / SINC Reserved: do not use 8.4.2.3 Oversampling Ratio Selection Pins (OSR) The ADS127L01 has two hardware oversampling ratio (OSR) pins used to configure the converter data rate. The rate at which the modulator bit stream data is decimated differs depending on whether the wideband or the lowlatency digital filter is used (set using the Filter Selection Pins (FILTER) pins). The OSR options and corresponding maximum data rate at fCLK = 16.384 MHz is shown in Table 12 for both the wideband and the lowlatency filters. Change the OSR when START is low, or when the START or RESET/PWDN pin is taken low and back high after changing the OSR. If software commands are used to control conversions, use the stop and start commands after changing the OSR. Table 12. OSR Selection FILTER OSR1 OSR0 OSR DATA RATE (kSPS) AT fCLK = 16.384 MHz 0 0 32 512 0 1 64 256 1 0 128 128 1 1 256 64 0 0 32 512 0 1 128 128 1 0 512 32 1 1 2048 8 Wideband filters Low-latency filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 39 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com 8.4.3 Start Pin (START) The START pin controls the start and stop of ADC conversions used for converter synchronization. Take the START pin low to stop conversions and reset the internal counters used for the digital filter. Pull START high to restart the conversions. Synchronization allows the conversion to be aligned with an external event, such as the changing of an external multiplexer on the analog inputs. The START pin is also used to synchronize multiple devices to within the same CLK cycle. Figure 85 and Figure 86 illustrate the timing requirement of START and CLK in SPI and frame-sync formats. After synchronization, indication of valid data depends on whether SPI or frame-sync format is used. In the SPI format, DRDY goes high as soon as START is taken low, as shown in Figure 85. After START is returned high, DRDY stays high while the digital filter completes reset and settles. After valid data are ready for retrieval, DRDY goes low. START tw(STH) tsu(ST) td(FILT) CLK td(NDR) DRDY Figure 85. Synchronization Timing (SPI Protocol) Table 13. SPI Protocol Start SYMBOL 40 DESCRIPTION MIN tw(STH) START pulse duration 4 tsu(ST) Setup time, START rising edge to CLK rising edge 10 td(FILT) Delay time, START rising edge to first modulator sample 4 td(NDR) Delay time for new data to be ready TYP MAX UNIT tCLK ns 5 tCLK Wideband filters 84 tDATA Low-latency filter See Table 3 tDATA Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 In the frame-sync format, DOUT goes low as soon as START is taken low, as shown in Figure 86. After START is returned high, the following FSYNC rising edge releases the digital filter from reset to begin conversions. DOUT stays low while the digital filter is settling. Data are ready for retrieval on DOUT after the digital filter settles. For proper synchronization, FSYNC, SCLK, and CLK must be established before taking START high, and must then remain running. If either CLK, FSYNC or SCLK are interrupted or reset, reassert the START pin. For consistent performance, reassert START after device power-on when data first appear, or after any hardware MODE pin change. tw(STH) START tsu(ST) FSYNC CLK td(NDR) Settled Data DOUT Figure 86. Synchronization Timing (Frame-Sync Protocol) Table 14. Frame-Sync Protocol Start SYMBOL tw(STH) tsu(ST) td(NDR) DESCRIPTION MIN START pulse duration Setup time, START rising edge to FSYNC rising edge Delay time for new data to be ready TYP MAX UNIT 4 tCLK Frame-sync slave 6 tCLK Frame-sync master 5 tCLK Wideband filters 84 tDATA Low-latency filter See Table 3 tDATA In addition to the START pin, start and stop commands are also available to control the start and stop of conversions, but only when using the SPI protocol. Using the commands requires that the hardware START pin is tied low the entire time. The start command is also used to synchronize multiple ADS127L01s sharing the same SPI interface. See the SPI Commands section for information on using the start and stop commands to control ADC conversions. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 41 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com 8.4.4 Reset and Power-Down Pins (RESET/PWDN) The RESET/PWDN pin has two functions, depending on the amount of time the pin is held in a low state. If RESET/PWDN is low for < 215 – 1 CLK periods, the ADS127L01 performs a reset that settles both the digital filter contents and register contents to default settings. The low-to-high transition of the RESET/PWDN pin brings the ADS127L01 out of reset by completing the digital filter reset, as shown in Figure 87 and Figure 88. tw(RSL) RESET/PWDN tsu(RS) td(FILT) CLK td(NDR) DRDY Figure 87. Reset Timing (SPI Protocol) Table 15. SPI Protocol Reset Timing SYMBOL DESCRIPTION MIN tw(RSL) RESET/PWDN pulse duration 4 TYP MAX UNIT 215 – 1 tCLK tsu(RS) Setup time, RESET/PWDN rising edge to CLK rising edge 10 ns td(FILT) Delay time, RESET/PWDN rising edge to first modulator sample 37 tCLK td(NDR) Delay time for new data to be ready Wideband filters 84 tDATA Low-latency filter See Table 3 tDATA tw(RSL) RESET/PWDN tsu(RSS) FSYNC tsu(RSM) td(RSM) CLK td(NDR) Settled Data DOUT Figure 88. Reset Timing (Frame-Sync Protocol) Table 16. Frame-Sync Protocol Reset Timing SYMBOL 42 DESCRIPTION MIN tw(RSL) RESET/PWDN pulse duration 4 tsu(RSS) Frame-Sync Slave: Setup time, RESET/PWDN rising edge to first FSYNC 7 tsu(RSM) Frame-Sync Master: Setup time, RESET/PWDN rising edge to CLK rising edge 10 td(RSM) Frame-Sync Master: Delay time, CLK rising edge to FSYNC rising edge 4 td(NDR) Delay time for new data to be ready TYP MAX UNIT 215 – 1 tCLK tCLK ns tCLK Wideband filters 84 tDATA Low-latency filter See Table 3 tDATA Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 If RESET/PWDN is low for > 215 – 1 CLK periods, the ADS127L01 enters power-down mode where both the analog and digital circuitry is completely deactivated. The digital inputs are internally disabled so there is no harm driving the pins. Use individual 1-MΩ pull-down resistors placed on CAP3 to DGND, SCLK to DGND, and DRDY/FSYNC to DGND if power-down mode is planned to be used. These resistors help discharge current when the device is placed in power-down mode. Shut down the CLK and SCLK in power-down mode to avoid additional power consumption. Return the RESET/PWDN pin high to leave power-down mode. As shown in Figure 89 and Figure 90, a minimum of 215 + 37 master clock periods must elapse before the device leaves power-down mode and begins sampling. When using SPI format, DRDY stays high after exiting power-down mode while the digital filter settles. tw(PWDN) RESET/PWDN tsu(PWDN) td(POR) CLK td(NDR) DRDY Figure 89. Power-Down Timing (SPI Protocol) Table 17. SPI Protocol Power-Down Timing SYMBOL DESCRIPTION MIN TYP MAX UNIT tw(PWDN) RESET/PWDN pulse duration to enter power-down mode 215 tsu(PWDN) Setup time, RESET/PWDN rising edge to CLK rising edge 10 ns 215 + 37 tCLK td(POR) Delay time, power-on-reset complete following RESET/PWDN rising edge td(NDR) Delay time for new data to be ready tCLK Wideband filters 84 tDATA Low-latency filter See Table 3 tDATA Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 43 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com A minimum of 215 + 7 master clock periods must elapse before the device leaves Power-down mode to begin sampling, when in Frame-Sync mode, as shown in Figure 90 and Table 18. When using Frame-Sync mode, DOUT will read back low while the digital filter settles. § tw(PWDN) § RESET/PWDN td(PORS) § § FSYNC tsu(PORM) td(PORM) CLK § td(NDR) Settled Data DOUT § § Figure 90. Power-Down Timing (Frame-Sync Protocol) Table 18. Frame-Sync Protocol Power-Down Timing SYMBOL MIN tw(PWDN) RESET/PWDN pulse duration to enter power-down mode td(PORS) Frame-sync slave: Setup time, RESET/PWDN rising edge to FSYNC rising edge tsu(PORM) Frame-sync master: Setup time, RESET/PWDN rising edge to CLK rising edge td(PORM) Frame-sync master: Delay time, CLK rising edge to FSYNC rising edge td(NDR) 44 DESCRIPTION Delay time for new data to be ready TYP 15 2 MAX UNIT tCLK 215 + 7 tCLK 10 ns 215 + 7 tCLK Wideband filters 84 tDATA Low-latency filter See Table 3 tDATA Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 8.5 Programming Data are retrieved from the ADS127L01 using a serial interface. To provide easy connection to either microcontrollers or DSPs, three communication formats are available: SPI, frame-sync master, and frame-sync slave. The FORMAT and FSMODE hardware pins select the interface. The same communication pins are used for all three interfaces: SCLK, DRDY/FSYNC, DIN, DAISYIN, and DOUT; however, functionality depends on the interface selected. When FORMAT = 0, SPI protocol is selected, and the DRDY/FSYNC pin becomes a data ready, (DRDY), output. In SPI mode, opcode commands and internal registers are available for further device configuration. Tie the FSMODE pin setting to DGND when using SPI communication format. When FORMAT = 1, frame-sync protocol is selected, and the DRDY/FSYNC pin becomes an FSYNC input or output. Frame-sync offers two different modes controlled by the FSMODE pin. When FSMODE = 0, the interface uses frame-sync slave mode, requiring that the SCLK and FSYNC signals are driven by the processor to the ADS127L01. When FSMODE = 1, the interface is set to frame-sync master mode, and the SCLK and FSYNC signals are generated from the ADC derived from the master clock. 8.5.1 Serial Peripheral Interface (SPI) Programming The SPI-compatible serial interface of the device is used to read conversion data, read and write the device configuration registers, and control device operation. Only SPI mode 1 (CPOL = 0, CPHA = 1) is supported. The interface consists of five control lines (CS, SCLK, DIN, DOUT, and DRDY/FSYNC), but the interface is operational with only four control lines. If the serial bus is not shared with any other device, CS can be tied low permanently so that only signals SCLK, DIN, DOUT and DRDY/FSYNC are required to communicate with the device. 8.5.1.1 Chip Select Pin (CS) Chip select (CS) is an active-low input that selects the device for SPI communication. CS must remain low for the entire duration of the serial communication to complete a command or data readback. When CS is taken high, the serial interface is reset, SCLK is ignored, and DOUT enters a high-impedance state. If the serial bus is not shared with another peripheral, CS can be tied low. 8.5.1.2 Serial Clock Pin (SCLK) The serial clock (SCLK) features a Schmitt-triggered input, and is used to clock data into and out of the device on DIN and DOUT, respectively. SCLKs can be sent to the ADC continuously or in byte increments. Even though the input has hysteresis, keep the SCLK signal as clean as possible to prevent glitches from accidentally shifting data. When the serial interface is idle, hold SCLK low. 8.5.1.3 Data Ready Pin (DRDY/FSYNC) In SPI mode, DRDY/FSYNC is an active-low, new-data-ready indicator for when a new conversion result is ready for retrieval. When DRDY/FSYNC transitions low, new conversion data are ready. TheDRDY/FSYNC signal transitions from low to high with the first SCLK rising edge. When no data are read during continuous conversion mode, DRDY/FSYNC remains low but pulses high for a duration of 2 · tCLK prior to the next DRDY/FSYNC falling edge. The DRDY/FSYNC pin is always actively driven, even when CS is high. 8.5.1.4 Data Input Pin (DIN) The data input pin (DIN) is used with SCLK to send data (commands and register data) to the device. The device latches data on DIN on the SCLK falling edge. The device never drives the DIN pin. 8.5.1.5 Data Output Pin (DOUT) DOUT is used with SCLK to read conversion and register data from the device. Data on DOUT are shifted out on the SCLK rising edge, to be read from the host on the SCLK falling edge. DOUT goes to a high-impedance state when CS is high. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 45 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Programming (continued) 8.5.1.6 Daisy-Chain Input Pin (DAISYIN) DAISYIN is an optional pin used with SCLK to shift data in from a secondary ADS127L01 device when in a daisy-chain configuration. Data are shifted out from DOUT of a secondary device into the DAISYIN pin of the first device. The individual data bits are latched into DAISYIN on the SCLK falling edge. See the Multiple Device Configuration section for more information on using daisy-chain mode. If not used, tie the DAISYIN pin to DGND. 8.5.1.7 SPI Timeout The ADS127L01 offers an SPI timeout feature that is used to recover communication when a serial interface transmission is interrupted. This feature is especially useful in applications where CS is permanently tied low and is not used to frame a communication sequence. The timeout feature is disabled by default, but can be enabled in the CONFIG register. The time for the timeout to issue is also configurable using the CONFIG register. When enabled, and whenever a complete command is not sent within 214 · tCLK or 216 · tCLK (configurable by the TOUT_DEL bit in the CONFIG register), the serial interface resets and the next SCLK pulse starts a new communication cycle. For the rreg and wreg commands, a complete command includes the command byte plus the register bytes that are read or written. 8.5.1.8 SPI Commands The ADS127L01 provides flexible configuration, including commands and configurable registers, only when using the SPI communication protocol. The opcode commands, summarized in Table 19, are stand-alone and configure the operation of the ADS127L01. Each command is a single byte, except for the register read and write operations that require two or more bytes. CS must remain low for the entire command operation (especially for multibyte commands). Take CS high during an opcode to abort the command. Table 19. Opcode Command Definitions COMMAND DESCRIPTION FIRST BYTE SECOND BYTE System Commands Reset Reset the device to power on values 0000 011x Start Start or restart (synchronize) conversions 0000 100x Stop Stop conversion 0000 101x Data Read Commands Rdata Read data by command 0001 0010 Register Commands Rreg Read (nnnn + 1) registers starting at address rrrr 0010 rrrr 0000 nnnn Wreg Write (nnnn + 1) registers starting at address rrrr 0100 rrrr 0000 nnnn 8.5.1.8.1 Reset (0000 011x) The reset command halts conversions and resets the ADC to power-on-reset values. During this time, the digital filter resets, requiring an additional power-up time for conversions to begin. The reset command is decoded by the ADS127L01 on the seventh falling edge of SCLK. For more information, refer to the Reset and Power-Down Pins (RESET/PWDN) section. 8.5.1.8.2 Start (0000 100x) The start command starts conversions and resynchronize the device. When conversions are stopped, either at power-up or following a stop command, issue a start command to begin ADC conversions. After the ADC is running, issuing a start command restarts the conversions by resetting the digital filters. During the reset period, DRDY/FSYNC does not toggle. The start command is decoded by the ADS127L01 on the seventh falling edge of SCLK. For more information, refer to the Start Pin (START) section. 8.5.1.8.3 Stop (0000 101x) The stop command stops conversions and places the ADC in an idle state. The stop command is decoded by the ADS127L01 on the seventh falling edge of SCLK. 46 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 8.5.1.8.4 Rdata (0001 0010) The rdata command reloads the output shift register to the MSB of the most recent data. The rdata command is decoded on the eighth SCLK falling edge, and begins shifting out the MSB of the data word on DOUT on the ninth SCLK. 8.5.1.8.5 Rreg (0010 rrrr 0000 nnnn) The rreg command reads the number of bytes specified by nnnn (number of registers to be read – 1) from the device configuration register, starting at register address rrrr. The command is completed after nnnn + 1 bytes are clocked out after the rreg command byte. For example, the command to read three registers (nnnn = 0010) starting at register address 00h (rrrr = 0000) is 0010 0000 0000 0100. The communication length must be extended by the proper number of SCLKs to shift register contents out. 8.5.1.8.6 Wreg (0100 rrrr 0000 nnnn) The wreg command writes the number of bytes specified by nnnn (number of registers to be written – 1) to the device configuration register, starting at register address rrrr. The command is completed after nnnn + 1 bytes are clocked in after the wreg command byte. For example, the command to write two registers (nnnn = 0001) starting at register address 01h (rrrr = 0001) is 0100 0001 0000 0001. Two bytes follow the command to write the contents to the registers. The frame must extend by the proper number of SCLKs to write data to the registers. 8.5.2 Frame-Sync Programming Frame-sync protocol is similar to the interface often used on audio ADCs. The ADS127L01 offers both framesync master and frame-sync slave modes that are selectable using the FSMODE pin. In frame-sync format, opcode commands and register assignments are not available. Tie DIN low to GND. 8.5.2.1 Frame-Sync Master Mode When operating in frame-sync master mode, the ADC acts as the system master, and provides the FSYNC, SCLK, and DOUT signals. The FSYNC and SCLK signals are derived as a function of the master clock input, fCLK. The data are output MSB first on the rising edge of FSYNC. 8.5.2.1.1 Chip Select Pin (CS) in Frame-Sync Master Mode CS is not used in frame-sync programming. Tie the CS pin to DGND. 8.5.2.1.2 Serial Clock Pin (SCLK) in Frame-Sync Master Mode When operating in frame-sync master mode, the serial clock (SCLK) is derived from the master clock and provided from the ADC to the microprocessor. Every frame period, tc(FRAME), includes 32 SCLKs to shift all of the data out before new data are ready. This SCLK speed is proportional to frame size, tc(FRAME) / 32 in frame-sync master mode. The frame size is determined by the data rate setting using the hardware FILTER pin settings, OSR pin settings, and speed of the master clock, fCLK. The data on DOUT are clocked out on the falling edge of SCLK to be latched on the rising edge of SCLK. 8.5.2.1.3 Frame-Sync Pin (DRDY/FSYNC) in Frame-Sync Master Mode In frame-sync master mode, the FSYNC pin is an output whose period is proportional to the ADC programmed data rate. Within each FSYNC period are 32 SCLKs to shift out the data on DOUT. The FSYNC duty cycle is designed to be 50-50, where an FSYNC low-to-high transition takes place before the MSB of new data, and highto-low transition takes place before bit 15 on the falling edge of SCLK. For more information on FSYNC mastermode timing, see Frame-Sync Master Mode Timing Requirements. 8.5.2.1.4 Data Input Pin (DIN) in Frame-Sync Master Mode DIN is not available in frame-sync master mode. Tie DIN to DGND. 8.5.2.1.5 Data Output Pin (DOUT) in Frame-Sync Master Mode The conversion data are clocked out on the falling edge of SCLK to be latched by the host processor on the rising edge of SCLK. The MSB data become valid on DOUT after FSYNC goes high. The subsequent bits are shifted out with each falling edge of SCLK. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 47 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com 8.5.2.1.6 Daisy-Chain Input Pin (DAISYIN) in Frame-Sync Master Mode DAISYIN and daisy-chain operation are not supported in frame-sync master mode. Tie DAISYIN to DGND. 8.5.2.2 Frame-Sync Slave Mode When operating in frame-sync slave mode, the user must supply framing signal FSYNC (similar to the left/right clock on stereo audio ADCs) and the serial clock SCLK (similar to the bit clock on audio ADCs). The data are output MSB first or left-justified on the rising edge of FSYNC. The FSYNC and SCLK inputs must be continuously running with the relationships shown in the Frame-Sync Timing Requirements. 8.5.2.2.1 Chip Select Pin (CS) in Frame-Sync Slave Mode CS is not used in frame-sync programming. Tie CS to DGND. 8.5.2.2.2 Serial Clock Pin (SCLK) in Frame-Sync Slave Mode In frame-sync slave mode, use SCLK to clock data out on DOUT. SCLK must run continuously; if SCLK is shut down, the data read back is corrupted. The number of SCLKs within a frame period (tc(FRAME)) can be any powerof-two ratio of CLK cycles (1, 1/2, 1/4, and so on), as long as the number of cycles is sufficient to shift the data output from all channels within one frame. Use SCLK to also shift data into DAISYIN when multiple devices are configured for daisy-chain operation. Even though SCLK has hysteresis, keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. 8.5.2.2.3 Frame-Sync Pin (DRDY/FSYNC) in Frame-Sync Slave Mode In frame-sync slave mode, the FSYNC pin is an input that transitions low to high at the data-rate frequency. The required number of fCLK cycles to each FSYNC period depends on the configuration of the FILTER[1:0] and OSR[1:0] pins. If the FSYNC period is not the proper value, data read back is corrupted. For more information on frame-sync slave-mode timing, see Frame-Sync Slave Mode Timing Requirements. 8.5.2.2.4 Data Input Pin (DIN) in Frame-Sync Slave Mode DIN is not used in frame-sync slave mode. Tie the DIN pin to DGND. 8.5.2.2.5 Data Output Pin (DOUT) in Frame-Sync Slave Mode The conversion data are clocked out on the falling edge of SCLK to be latched by the host processor on the rising edge of SCLK. The MSB data become valid on DOUT after FSYNC goes high. The subsequent bits are shifted out with each falling edge of SCLK. 8.5.2.2.6 Daisy-Chain Input Pin (DAISYIN) in Frame-Sync Slave Mode DAISYIN is an optional pin used along with SCLK to shift data from a secondary ADS127L01 device. Data are shifted out from DOUT of a secondary device into the DAISYIN pin of the first device. The data out DOUT is latched into DAISYIN on the SCLK falling edge. See the Multiple Device Configuration section for more information on using daisy-chain mode. Tie the DAISYIN pin to DGND if not used. 48 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 8.5.3 Data Format The ADS127L01 provides a 32-bit output word, 24 bits of which are data in binary twos complement format with the eight LSBs containing status word information. The size of one code (LSB) is calculated using Equation 8: 1 LSB = (2 · Vref ) / 224 = +FS / 223 (8) A positive full-scale input [VIN ≥ (+FS – 1 LSB) = (Vref – 1 LSB)] produces an output code of 7FFFFFh, and a negative full-scale input (VIN ≤ –FS = –Vref ) produces an output code of 800000h. The output clips at these codes for signals that exceed full-scale. Table 20 summarizes the ideal output codes for different input signals. Table 20. Ideal Output Code Versus Input Signal INPUT SIGNAL, VIN (VAINP – VAINN) ≥ +FS (2 23 IDEAL OUTPUT CODE (1) 23 – 1) / 2 7FFFFFh +FS / 223 (1) 000001h 0 0 –FS / 223 FFFFFFh ≤ –FS 800000h Excludes the effects of noise, INL, offset, and gain errors. 8.5.4 Status Word Trailing the 24 bits of data is an optional 8-bit status word. The status word provides a real-time update of internal system monitors and data integrity. By default, the contents are a mixture of 4-bit CRC data integrity and system monitors. Alternatively, the status word can be set to output an 8-bit CRC without the system monitors. The CRCB bit in the CONFIG regsiter controls the status word contents. Set the CRCB bit to 0 for the status word to contain 4-bit CRC [bits 7:4], one bit [bit 3] to monitor out of range input (INP), and three bits [bits 2:0] to read back as 0. Set the CRCB bit to 1 for all eight bits [bits 7:0] of the status word to contain 8-bit CRC. See Figure 91 for a visual representation of the two modes. By default, the optional 8-bit status word is enabled, but can be disabled when operating in SPI protocol and setting the CS_ENB bit to 1 in the CONFIG register. SCLK DOUT DATA CRC - 4 INP 0 0 0 CRCB = 0 DOUT DATA CRC - 8 CRCB = 1 Figure 91. Status Word Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 49 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com 8.5.5 Cyclic Redundancy Check (CRC) The ADS127L01 implements two standard CRC algorithms: CRC-4-ITU to provide a 4-bit CRC, and CRC-8CCITT for an 8-bit CRC. By default, the CRC-4-ITU option is enabled. Set the CRCB bit to 1 in the CONFIG register to change the format to CRC-8-CCITT and remove the system monitor bits from the status word. The CRC is always placed after the ADC data. The CRC is calculated using only the ADC output. When the 4-bit CRC is enabled, the ADS127L01 outputs a 4-bit status block after the CRC that is not used as part of the CRC check. 8.5.5.1 Computing the CRC To calculate the CRC, divide the data bytes by the CRC polynomial using an XOR operation. In 4-bit CRC mode, the CRC value is the 4-bit remainder of the division of the data bytes by a CRC polynomial of P(x) = x4 + x + 1. In 8-bit CRC mode, the CRC value is the 8-bit remainder of the division of the ADC data bytes by a CRC polynomial of P(x) = x8 + x2 + x + 1. Then compare the calculated CRC values to the provided CRC value in the ADC output. If the values do not match, a data-transmission error has occurred. In the event of a data-transmission error, read the data again. The CRC provides a higher level of detection of multiple-bit errors. The following list shows a general procedure to compute the CRC value. Assume the shift register is 16 bits wide: 1. Set the polynomial value to 0x03 for an 4-bit CRC, or 0x07 for an 8-bit CRC (1). 2. Set the shift register to all zeros. 3. Begin with the MSB in the data stream. For every n bits: (a) Align the MSB of the data stream with the MSB of the shift register. XOR the data byte with the shift register, and the result is automatically placed in the shift register. (b) Test the MSB of the shift register n times, and do one of the following each time: (a) If the most significant bit of the shift register is set, shift the register left by one bit, XOR the result with the polynomial, and place the result into the shift register. (b) If the most significant bit of the shift register is not set, shift the register left by one bit. 4. The result in the shift register is the CRC check value. (1) 50 The CRC algorithm used here employs an assumed set high bit. This bit is divided out by left-shifting the bit out of the register prior to XORing with the polynomial shift register. This process allows for calculation of the CRC with 8-bit hardware. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 8.6 Register Maps Table 21 describes the various ADS127L01 registers. Access to the registers is available in SPI programming mode. Register access is not available in frame-sync master or slave programming modes. Table 21. ADS127L01 Register Assignments ADDRESS REGISTER RESET VALUE (Hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 x3 (1) REV_ID4 REV_ID3 REV_ID2 REV_ID1 REV_ID0 DEV_ID2 DEV_ID1 DEV_ID0 Device ID (Read-Only Registers) 00h ID Configuration Settings 01h CONFIG 00h 0 0 FSC OFC TOUT_DEL SPI_TOUT CS_ENB CRCB 02h OFC0 00h OFC_B7 OFC_B6 OFC_B5 OFC_B4 OFC_B3 OFC_B2 OFC_B1 OFC_B0 03h OFC1 00h OFC_B15 OFC_B14 OFC_B13 OFC_B12 OFC_B11 OFC_B10 OFC_B9 OFC_B8 04h OFC2 00h OFC_B23 OFC_B22 OFC_B21 OFC_B20 OFC_B19 OFC_B18 OFC_B17 OFC_B16 05h FSC0 00h FSC_B7 FSC_B6 FSC_B5 FSC_B4 FSC_B3 FSC_B2 FSC_B1 FSC_B0 06h FSC1 80h FSC_B15 FSC_B14 FSC_B13 FSC_B12 FSC_B11 FSC_B10 FSC_B9 FSC_B8 0 HR OSR1 OSR0 FILTER1 FILTER0 FORMAT FSMODE Device Settings (Read-Only Registers) 07h (1) MODE xx (1) x is undefined. 8.6.1 ID: ID Control Register (address = 00h) [reset = x3h] This register is programmed during device manufacture to indicate device characteristics. Figure 92. ID Register 7 REV_ID4 6 REV_ID3 5 REV_ID2 R-Undefined (1) 4 REV_ID1 3 REV_ID0 2 DEV_ID2 1 DEV_ID1 R-3h 0 DEV_ID0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset (1) Reset values are device dependent. Table 22. ID Register Field Descriptions (1) Bit Field Type 7-3 REV_ID[4:0] R 2-0 DEV_ID[2:0] R Reset Description Undefined ( 1) Revision ID. These bits indicate the revision of the device and are subject to change without notice. 3h Device Family Identification. 011 = ADS127L01 Reset values are device dependent. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 51 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com 8.6.2 CONFIG: ADC Configuration Register (address = 01h) [reset = 00h] This register contains the software controlled device options. Figure 93. CONFIG Register 7 0 R-0h 6 0 R-0h 5 FSC R/W-0h 4 OFC R/W-0h 3 TOUT_DEL R/W-0h 2 SPI_TOUT R/W-0h 1 CS_ENB R/W-0h 0 CRCB R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23. CONFIG Register Field Descriptions Bit Field Type Reset Description 7-6 Reserved R 0h Reserved Always reads 0 0h System Gain Correction This bit enables system gain correction using the register contents from FSC0 and FSC1 registers. 0 = Disable system gain correction 1 = Enable system gain correction 0h Offset Correction This bit enables Offset Correction using the register contents from OFC0, OFC1, and OFC2 registers. 0 = Disable offset correction 1 = Enable offset correction 0h SPI Timeout This bit sets the time limit to hold SCLK in an idle position for the SPI reset. 0 = SPI timeout delay set to 216 tCLK. 1 = SPI timeout delay set to 214 tCLK. 0h SPI Timeout Enable This bit enables or disables the SPI timeout function. 0 = Disable SPI timeout 1 = Enable SPI timeout 5 4 3 2 52 FSC OFC TOUT_DEL SPI_TOUT R/W R/W R/W R/W 1 CS_ENB R/W 0h Status Word Enable This bit enables or disables the status word that is present following the 24-bit data output. 0 = Enable status word 1 = Disable status word 0 CRCB R/W 0h Status Word Contents This bit sets the contents used in the status word. 0 = CRC-4 and 4 bits of ADC diagnostics 1 = CRC-8 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 8.6.3 OFC0: System Offset Calibration Register 0 (address = 02h) [reset = 00h] This register contains the least significant byte for the system offset calibration. The system offset calibration is a total of three bytes or 24 bits. Figure 94. OFC0 Register 7 OFC_B7 R/W-0h 6 OFC_B6 R/W-0h 5 OFC_B5 R/W-0h 4 OFC_B4 R/W-0h 3 OFC_B3 R/W-0h 2 OFC_B2 R/W-0h 1 OFC_B1 R/W-0h 0 OFC_B0 R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 24. OFC0 Register Field Descriptions Bit Field Type Reset Description 7-0 OFC_B[7:0] R/W 00h Offset Correction Bits These bits set the system offset error correction. 8.6.4 OFC1: System Offset Calibration Register 1 (address = 03h) [reset = 00h] This register contains the middle byte for the system offset calibration. The system offset calibration is a total of three bytes or 24 bits. Figure 95. OFC1 Register 7 OFC_B15 R/W-0h 6 OFC_B14 R/W-0h 5 OFC_B13 R/W-0h 4 OFC_B12 R/W-0h 3 OFC_B11 R/W-0h 2 OFC_B10 R/W-0h 1 OFC_B9 R/W-0h 0 OFC_B8 R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 25. OFC1 Register Field Descriptions Bit Field Type Reset Description 7-0 OFC_B[15:8] R/W 00h Offset Correction Bits These bits set the system offset error correction. 8.6.5 OFC2: System Offset Calibration Register 2 (address = 04h) [reset = 00h] This register contains the most significant byte for the system offset calibration. The system offset calibration is a total of three bytes or 24 bits. Figure 96. OFC2 Register 7 OFC_B23 R/W-0h 6 OFC_B22 R/W-0h 5 OFC_B21 R/W-0h 4 OFC_B20 R/W-0h 3 OFC_B19 R/W-0h 2 OFC_B18 R/W-0h 1 OFC_B17 R/W-0h 0 OFC_B16 R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 26. OFC2 Register Field Descriptions Bit Field Type Reset Description 7-0 OFC_B[23:16] R/W 00h Offset Correction Bits These bits set the system offset error correction. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 53 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com 8.6.6 FSC0: System Gain Calibration Register 0 (address = 05h) [reset = 00h] This register contains the least significant byte for the system gain calibration. The system gain calibration is a total of two bytes or 16 bits. Figure 97. FSC0 Register 7 FSC_B7 R/W-0h 6 FSC_B6 R/W-0h 5 FSC_B5 R/W-0h 4 FSC_B4 R/W-0h 3 FSC_B3 R/W-0h 2 FSC_B2 R/W-0h 1 FSC_B1 R/W-0h 0 FSC_B0 R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 27. FSC0 Register Field Descriptions Bit Field Type Reset Description 7-0 FSC_B[7:0] R/W 00h Gain Correction Bits These bits set the system gain calibration value. 8.6.7 FSC1: System Gain Calibration Register 1 (address = 06h) [reset = 80h] This register contains the most significant byte for the system gain calibration. The system gain calibration is a total of two bytes or 16 bits. Figure 98. FSC1 Register 7 FSC_B15 R/W-1h 6 FSC_B14 R/W-0h 5 FSC_B13 R/W-0h 4 FSC_B12 R/W-0h 3 FSC_B11 R/W-0h 2 FSC_B10 R/W-0h 1 FSC_B9 R/W-0h 0 FSC_B8 R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28. FSC1 Register Field Descriptions 54 Bit Field Type Reset Description 7-0 FSC_B[15:8] R/W 80h Gain Correction Bits These bits set the system gain calibration value. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 8.6.8 MODE: Mode Settings (address = 07h) [reset = xxh] This register displays the hardware bit settings. Figure 99. MODE Register 7 0 R-0h 6 HR R-0h 5 OSR1 R-0h 4 OSR0 R-0h 3 FILTER1 R-0h 2 FILTER0 R-0h 1 FORMAT R-0h 0 FSMODE R-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 29. MODE Register Field Descriptions Bit Field Type Reset Description 7 Reserved R 0h Reserved Always reads 0 6 HR R xh High-Resolution Setting This bit shows the readback status of HR (pin 29) 0 = Low: LP Mode 1 = High: HR mode xh OSR Setting This bit shows the readback status of OSR1 (pin 15) and OSR2 (pin 16) If FILTER[1:0] = 00 or 01 (Wideband filters): 00 = 32 01 = 64 10 = 128 11 = 256 If FILTER[1:0] = 10 (Low-latency filter): 00 = 32 01 = 128 10 = 512 11 = 2048 5-4 OSR[1:0] R FILTER[1:0] R xh Filter Option Setting This bit shows the readback status of FILTER1 (pin 12) and FILTER0 (pin 13) Digital-filter mode select: 00: Wideband 1 filter 01: Wideband 2 filter 10 : Low-latency filter (SINC5 and SINC) 11: Reserved 1 FORMAT R xh Interface Format Setting This bit shows the readback status of FORMAT (pin 30) 0 = Low: SPI Mode 1 = High: Frame-sync mode 0 FSMODE R xh Frame-Sync mode setting This bit shows the readback status of FSMODE (pin 14) 0 = Low: Frame-sync slave mode 1 = High: Frame-sync master mode 3 -2 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 55 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Unused Inputs and Outputs Do not float unused digital inputs because excessive power-supply leakage current might result. The DIN and CS pins are only used in SPI interface. Tie DIN (pin 21) and CS (pin 23) directly to DGND when in frame-sync master mode or frame-sync slave mode. If not daisy-chaining devices, tie DAISYIN directly to DGND. In SPI programming mode, leave the unused DRDY/FSYNC pin floating, or tie the unused pin to DVDD through high impedance resistors. 9.1.2 Multiple Device Configuration The ADS127L01 provides configuration flexibility when multiple devices are connected in a system: • SPI programming mode supports two methods to synchronize multiple devices: cascaded or daisy-chain. • Frame-sync slave programming mode also supports the same two methods to synchronize multiple devices: cascaded or daisy-chain. • Frame-sync master programming mode only supports the cascaded method to synchronize multiple devices. Daisy-chain configuration is not available in frame-sync master mode. 9.1.2.1 Cascaded Configuration Two or more ADS127L01 devices can be cascaded together when using either SPI mode or Frame-Sync mode. Cascading devices allows multiple devices to share the same interface bus and reduces pin connections to the host processor. 56 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 Application Information (continued) 9.1.2.1.1 SPI Mode In SPI mode, CLK, SCLK, DIN, and DOUT from each device are shared with independent CS signals. Monitor the DRDY signal from only one device. Leave the remaining DRDY pins floating. Figure 100 shows the required connections for cascading multiple devices in SPI Mode. CLK CS START ADS127L01 (Device 0) GPIO1 SCLK SCLK DIN MOSI DOUT MISO DRDY/FSYNC GPIO2 DAISYIN CLK HOST PROCESSOR INT CS START SCLK ADS127L01 (Device 1) DIN DOUT DRDY/FSYNC DAISYIN Copyright © 2016, Texas Instruments Incorporated Figure 100. Cascaded Devices in SPI Mode The host processor must use a separate GPIO to control the CS pins on each ADS127L01 device. When CS is driven to a logic 1, the DOUT of that device is high-impedance. This structure allows another device to take control of the DOUT bus. The SCLK frequency must be high enough to read all of the data from each device before the next DRDY pulse arrives. Alternatively, tie the DOUT pin from each device to a separate pin on the host processor to collect data from multiple devices in parallel. Equation 9 calculates the maximum number of devices that can share the same bus in a cascaded configuration in terms of data rate, SCLK frequency, and total number of bits per device. Number of Devices ≤ (tDATA – tCSDO – tCSDOZ) / (n × tSCLK) where • n = 24 or 32 bits (9) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 57 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Application Information (continued) 9.1.2.1.2 Frame-Sync Mode In frame-sync mode, the CS pin is unused and must be tied to DGND. CLK, SCLK, DIN, and FSYNC from each device are shared with independent DOUT signals. Connect the DOUT pin from each device to a separate input pin on the host processor to read the data from multiple devices in parallel. Figure 101 shows the required connections for cascading multiple devices in frame-sync mode. CLK CS START ADS127L01 (Device 0) SCLK SCLK DIN MOSI DOUT MISO1 DRDY/FSYNC INT MISO2 DAISYIN CLK HOST PROCESSOR CS START SCLK ADS127L01 (Device 1) DIN DOUT DRDY/FSYNC DAISYIN Copyright © 2016, Texas Instruments Incorporated Figure 101. Cascaded Devices in Frame-Sync Mode Only one device can be configured in frame-sync master mode; remaining devices must be configured in framesync slave mode. Otherwise, configure all devices in frame-sync slave mode. Equation 10 calculates the maximum number of devices that can be daisy-chained for both SPI and frame-sync slave mode in terms of data rate, SCLK frequency, and total number of bits to read from each device. Number of Devices ≤ (tDATA) / (n × tSCLK) where • n = 24 or 32 bits (10) 9.1.2.2 Daisy-Chain Configuration Two or more ADS127L01 devices can be daisy-chained together in either SPI mode or frame-sync slave mode. Frame-sync master mode does not support daisy-chain configurations. For both SPI and frame-sync slave mode, connect the DOUT pin of the first device in the chain to an input pin on the host processor. Connect the DOUT pin of the remaining devices to the DAISYIN pin of the next device. Connect the DAISYIN pin on the last device to DGND. Equation 11 calculates the maximum number of devices that can share the same bus in a cascaded configuration in terms of data rate, SCLK frequency, and total number of bits per device. Number of Devices ≤ (tDATA) / (n × tSCLK) where • 58 n = 32 bits (11) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 Application Information (continued) 9.1.2.2.1 Daisy-Chain Operation Using SPI Mode In SPI mode, CLK, SCLK, DIN and CS are shared. Monitor only the DRDY signal from one device. Leave the remaining DRDY pins floating. The SCLK frequency must be high enough to read all the data from each device before the next DRDY pulse arrives. Figure 102 shows the required connections for daisy-chaining multiple devices in SPI mode. CLK START ADS127L01 (Device 0) CS GPIO SCLK SCLK DIN MOSI DOUT MISO DRDY/FSYNC HOST PROCESSOR INT DAISYIN CLK CS START SCLK ADS127L01 (Device 1) DIN DOUT DRDY/FSYNC DAISYIN Copyright © 2016, Texas Instruments Incorporated Figure 102. Daisy-Chained Devices in SPI Mode All data from Device 0 is shifted into Device 1 on the DAISYIN pin. The MSB from the Device 0 data immediately follows the LSB from Device 1 on the DOUT pin of Device 0. Figure 103 illustrates the timing relationship for daisy-chaining devices in SPI mode. DAISYIN Device 1 MSB Device 1 LSB Device 0 MSB Device 0 LSB SCLK MISO Device 1 MSB Device 1 LSB Figure 103. Daisy-Chain Timing in SPI Mode Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 59 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Application Information (continued) 9.1.2.2.2 Daisy-Chain Operation Using Frame-Sync Mode In frame-sync slave mode, CLK, SCLK, DIN and FSYNC are shared. The CS pin is unused and must be tied to DGND. The SCLK frequency must be high enough to read all the data from each device before the next frame begins. Figure 104 shows the required connections for daisy-chaining multiple devices in frame-sync slave mode. CLK CS START ADS127L01 (Device 0) SCLK SCLK DIN MOSI DOUT MISO DRDY/FSYNC INT HOST PROCESSOR DAISYIN CLK CS START SCLK ADS127L01 (Device 1) DIN DOUT DRDY/FSYNC DAISYIN Copyright © 2016, Texas Instruments Incorporated Figure 104. Daisy-Chained Devices in Frame-Sync Slave Mode All data from Device 1 are shifted into Device 0 on the DAISYIN pin. The MSB from the Device 1 data immediately follows the LSB from Device 0 on the DOUT pin of Device 1. Figure 105 illustrates the timing relationship for daisy-chaining devices in frame-sync slave mode. DAISYIN Device 1 MSB Device 1 LSB Device 0 MSB Device 0 LSB SCLK MISO Device 1 MSB Device 1 LSB Figure 105. Daisy-Chain Timing in Frame-Sync Slave Mode 60 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 Application Information (continued) 9.1.2.3 Synchronizing Devices Use the START pin or the RESET/PWDN pin to synchronize multiple devices. The START pin does not reset the device registers to the default settings. The RESET/PWDN pin resets the device to the factory default settings, and resets the interface when in frame-sync master mode. The delay from the START signal high to the first data ready is fixed for a given data rate (see the Start Pin (START) section for more details on the delay times). An alternate way to synchronize multiple devices is using the RESET/PWDN pin. The RESET/PWDN pin resets the digital interface in addition to the digital filters and registers, making it the recommended synchronization method for frame-sync master mode. The delay from the RESET/PWDN pin high to the first data ready is fixed for a given data rate (see the Reset and Power-Down Pins (RESET/PWDN) section for more details on the delay times). The RESET/PWDN pin is also used to synchronize multiple devices in SPI mode or frame-sync slave mode. 9.1.3 ADC Input Driver The input driver circuit for a high-precision delta-sigma ADC consists of two parts: a driving amplifier and a lowpass, antialiasing filter. The amplifier is used to condition the input signal voltage and provide a low outputimpedance buffer between the signal source and the switched-capacitor inputs of the ADC. The low-pass antialiasing filter, comprised of small series resistors and a differential capacitor, helps to attenuate the voltage transients created by the ADC switched-capacitor input stage, and also serves to band-limit the wideband noise contributed by the front-end circuit. Careful design of the input driver circuit is critical to take advantage of the linearity and noise performance of the ADS127L01. 9.1.3.1 Antialiasing Filter Signal aliasing in data-acquisition systems occurs when continuous-time signals are discretely sampled at a constant rate. To properly represent an analog signal in the digital domain, the system must sample the input at a sampling rate greater than twice the maximum frequency content, known as the Nyquist rate. Frequencies that are greater than one-half the sampling rate (known as the Nyquist frequency) are not represented properly in the digital domain and appear as aliases of the original input instead. Delta-sigma ADCs exhibit two Nyquist frequencies, as shown in Figure 106. The first Nyquist frequency occurs in the analog domain at one-half the modulator sampling rate (fMOD / 2). The second Nyquist frequency occurs in the digital domain at one-half the decimated output data rate (fDATA / 2). Frequency content repeats at multiples of fMOD and fDATA. Both Nyquist frequencies allow for out-of-band signals to alias into the ADC pass band, including noise from the front-end driver circuit. This aliasing increases the in-band noise level of the system and degrades overall performance if not adequately filtered. ADC INPUT û MODULATOR H(z) DIGITAL FILTER DECIMATION + Analog Domain Aliasing Digital Domain Aliasing Copyright © 2016, Texas Instruments Incorporated Figure 106. Delta-Sigma ADC Internal Signal Chain Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 61 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Application Information (continued) Magnitude (dB) Magnitude (dB) Figure 107 and Figure 108 illustrate the two aliasing domains in delta-sigma ADCs. Figure 107 shows a higherfrequency, out-of-band signal aliasing around the modulator Nyquist frequency (fMOD / 2) into the pass band. Figure 108 shows a lower-frequency, out-of-band signal aliasing around the data rate Nyquist frequency (fDATA / 2) into the pass band after being attenuated by the digital filter. Analog Domain Aliasing DC fMOD / 2 fMOD Digital Domain Aliasing DC fDATA / 2 fDATA fMOD / 2 fMOD Frequency (Hz) Frequency (Hz) Figure 107. Analog Domain Aliasing Around fMOD / 2 Figure 108. Digital Domain Aliasing Around fDATA / 2 To prevent signals from aliasing, use a low-pass antialiasing filter to attenuate the out-of-band signals. The simplest antialiasing filter is a discrete first-order, low-pass, RC filter. To achieve a higher level of attenuation at the data rate Nyquist frequency requires a higher-order filter response, usually before the last amplifier stage. The digital filter in delta-sigma ADCs reduces the attenuation requirement of the antialiasing filter by providing a high stop band attenuation between fDATA / 2 and fMOD. At multiples of fMOD, the digital filter response returns to 0 dB and repeats. This portion of the digital filter response is the sensitive frequency band where an antialiasing filter is needed. Figure 109 overlays a digital filter response with first-, second-, and third-order antialiasing filters, attenuating both out-of-band signals. Magnitude (dB) 1st-order AAF 2nd-order AAF 3rd-order AAF Digital Filter DC fDATA/2 fDATA fMOD/2 fMOD Frequency (Hz) Figure 109. Antialiasing and Digital Filters 62 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 Application Information (continued) The antialiasing RC filter also helps to attenuate the voltage transients from the sampling network at the ADC inputs. Figure 110 shows a simplified switch-capacitor circuit at the inputs of an ADC modulator. The sampling network, described in Figure 60, places a transient load on the external drive circuit. The differential capacitor in the RC filter, CDIFF, acts as a charge reservoir and transfers charge to the internal sampling capacitor, CSAMPLE, while S1 is closed. When S1 opens, S2 closes, discharging the CSAMPLE capacitor. The input driver circuit must restore the charge at the input nodes (AINP and AINN) so that the voltage settles before the S1 switch opens for the next sample acquisition. The faster the modulator sampling rate, the less time the input voltage has to settle. An amplifier with a gain-bandwidth product (GBP) that is too low fails to provide adequate settling time for the desired signal level because of the higher output impedance over frequency, and results in increased distortion. S1 RFLT ± + AINP CSAMPLE CDIFF S2 + ± AINN RFLT S1 Copyright © 2016, Texas Instruments Incorporated Figure 110. Delta-Sigma Sampling Network In the ADS127L01, the sampling capacitors have an equivalent capacitance of 8 pF. Scale CDIFF to be at least 100 times larger than CSAMPLE. Connect CDIFF directly across the ADC input pins to help provide adequate charge with each ADC sample. CDIFF must be C0G or NP0 dielectric type because these components have a high-Q, low-temperature coefficient, and stable electrical characteristics to withstand varying voltages and frequencies. Common-mode capacitors, CCM, can also be added at each input to ground to attenuate common-mode noise and sampling glitches. Size the common-mode capacitors to be one order of magnitude smaller than CDIFF in order to maintain system common-mode rejection (CMR). Figure 111 shows an example of the voltage transient created by the ADC sampling event at the inputs of an unbuffered delta-sigma ADC. The larger transients mark the moment when S1 closes to connect CSAMPLE to the external front-end circuitry. The smaller transient occurs when the S1 switch opens passing the charge through the modulator. The sequence repeats at 1 / fMOD. The data were recorded using a passive 10x probe on the AINP pin only. The same transient is observed on AINN as well. The differential transient voltage is more than an order of magnitude smaller. 160 9 AINP (mV) CLK (V) 140 120 7.5 6 4.5 80 3 60 1.5 40 0 20 -1.5 0 -3 -20 -4.5 -40 -6 -60 -7.5 -80 CLK Voltage (V) AINP Voltage (mV) 100 -9 Time D001 Figure 111. ADC Input During Sampling Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 63 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Application Information (continued) When S1 opens, the sample is latched and converted by the modulator. Increasing CDIFF provides a larger charge reservoir to the ADC, and reduces the initial voltage droop. For ADCs with a faster sampling frequency, there is less time for this voltage transient to fully settle before the next sample. The ADC input relies on a driver amplifier with sufficient bandwidth and low output impedance at high frequencies to provide recovery charge and fully settle the voltage transient before S1 opens. 9.1.3.2 Input Driver Selection Selection criteria for the input amplifiers are highly dependent on the input signal type, as well as the performance goals of the data-acquisition system. Consider the following amplifier specifications when selecting the appropriate driver amplifier for the application: • Noise. The output noise density of the front-end amplifiers must be kept as low as possible to prevent any degradation in system SNR performance. The total noise from the input stage is determined by the –3-dB bandwidth of the ADS127L01 digital filter. Make sure that the total output noise is less than 20% of the inputreferred noise of the ADC, as explained in Equation 12: eo _ RMS u f 3dB d 1 VREF u u 10 5 2 § SNR(dB) · ¨ ¸ 20 © ¹ where • • • eo_RMS = Broadband output noise of the input driver stage in nV/√Hz f-3dB = –3-dB bandwidth of the ADS127L01 digital filter in Hz (12) Distortion. Keep the distortion from the front-end drivers as low as possible, especially in the presence of a switching load. Harmonics produced by the amplifier are also compounded by harmonics produced by the ADC. Select an amplifier with at least –10 dB better distortion than the ADC distortion in order to prevent any degradation to system THD performance, as explained by Equation 13. THDAMP d THDADC 10(dB) where • • • THDAMP = Total harmonic distortion from input driver THDADC = Total harmonic distortion specification of the ADC (13) Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible, after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance of the amplifier, thus allowing the amplifier to more easily drive a larger capacitive load with a smaller series resistor. For a given low-pass filter cutoff, keep the series resistor as small as possible and increase the differential capacitor to minimize gain error and distortion (see the Antialiasing Filter section). Higher bandwidth also minimizes harmonic distortion caused by faster settling of the input transients from the ADC sampling. The required amplifier bandwidth depends on the size of the sampling capacitor, the sampling frequency, and the size of the external differential capacitor. TINA-TI simulations help model the small-signal settling behavior and the stability of the input driver circuit for a given load. The THS45xx family of fully-differential amplifiers offers the low noise and distortion specifications needed in high-performance data-acquisition systems. Table 30 shows the power versus performance tradeoff offered between the THS4531A, THS4551, and the highest performing THS4541. Table 30. Input Driver Selection DRIVER 64 GAIN BANDWIDTH PRODUCT (MHz) NOISE DENSITY (nV/√Hz) QUIESCENT CURRENT Iq (mA) NOMINAL RF AND RG (Ω) THS4531A 36 10 0.23 2k THS4551 130 3.4 1.31 1.2 k THS4541 850 2.2 9.7 402 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 Figure 112 and Figure 113 compare the distortion and noise performance of the THS4531A, THS4541, and THS4551 as they drive the inputs of the ADS127L01. Each input driver circuit was configured for a gain of one using the nominal feedback resistor values in Table 30. An AP2700 function generator provided a full-scale, sine wave input at frequencies of 2 kHz and below, such that at least five harmonics were present in the fast Fourier transform (FFT) calculated from 8,192 samples. An Agilent 33522A provided the clock input for the ADS127L01 (CLK) to set the modulator clock frequency between 100 kHz and 16.384 MHz. To quantify the distortion performance of each input driver circuit, the spurious-free dynamic range (SFDR) is calculated at each modulator clock frequency. A third-order polynomial, best-fit curve is applied to the raw data to show the overall trend for each amplifier. Figure 112 illustrates that at slower modulator clock frequencies, a lower power amplifier with less bandwidth can be used to achieve similar SFDR performance as higher power amplifiers with more bandwidth. However, faster modulator clock frequencies require the use of a wide-bandwidth amplifier to get the best performance out of the ADC. -80 Amplifier THS4541 THS4551 THS4531a -90 SFDR (dB) -100 -110 -120 -130 -140 0 2 4 6 8 10 fMOD (MHz) 12 14 16 18 D015 Figure 112. SFDR vs fMOD In contrast to SFDR, the signal-to-noise ratio (SNR) of a data-acquisition signal chain is more dependent on the input amplifier noise density, as well as the ADC output data rate. Figure 113 displays the SNR performance of the ADS127L01 measured while driving the inputs with the THS4531A, THS4541, and THS4551. The digital filter in the ADS127L01 is configured to use the wideband 2 transition band and an OSR of 256 throughout the SNR measurements. An AP2700 provided a small-signal 1 kHz input sine wave of 100 mVpp. An Agilent 33522A provided the clock input (CLK) for the ADS127L01 to set the modulator clock frequency between 100 kHz and 16.384 MHz. The measured SNR is normalized to full-scale. 120 Amplifier THS4541 THS4551 THS4531a SNR (dB) 115 110 105 0 2 4 6 8 10 fMOD (MHz) 12 14 16 18 D014 Figure 113. SNR vs fMOD Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 65 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com The SNR performance is expected to remain relatively constant for all three amplifiers across modulator frequencies. However, the improvement in SNR at slower modulator frequencies is because of the reduced bandwidth of the digital filter as it scales down with modulator clock, limiting the input source broadband noise. At higher frequencies, noise from the input source dominates as the digital-filter bandwidth increases. The difference in amplifier noise density, listed in Table 30, has the largest effect on the system noise performance. 9.1.3.3 Amplifier Stability Driving a capacitive load can degrade the phase margin of the input amplifier, and can make the amplifier unstable. To prevent the amplifier from becoming unstable, a series isolation resistor (RFLT) is used at the amplifier output, as shown in Figure 110. A higher resistance value increases phase margin and makes the amplifier more stable, but also increases distortion caused by the interaction with the nonlinear input impedance of the ADC modulator. Distortion increases with source output impedance, input-signal frequency, and inputsignal amplitude. The selection of RFLT requires a balance between distortion and the stability of the input driver design. The use of 1% components is allowed because the CDIFF mitigates the degradation of CMR caused by input imbalances. The input amplifier must be selected with a bandwidth higher than the cutoff frequency, fC, of the antialiasing filter at the ADC inputs. Use a TINA-TI simulation to confirm that the amplifier has more than 30° of phase margin when driving the selected filter to verify stability. Simulation is critical because some amplifiers require more bandwidth than others to drive the same filter. If the input amplifier circuit has less than 20° of phase margin, consider adding a capacitor at the amplifier inputs to increase phase margin. 66 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 9.1.4 ADC Reference Driver Design the reference driver to provide a precision, low-drift reference voltage to the ADC for best performance. Similar to the input of the ADC, a switched-capacitor circuit samples the reference voltage between REFP and REFN. The switched capacitor imposes a transient load on the external reference driver circuit at the modulator frequency. A reference buffer is required to restore the charge across the differential capacitor at the reference input pins so that the voltage settles before the next acquisition. The integrated broadband reference noise must remain significantly less than the ADC integrated noise to minimize SNR degradation. Choose a reference driver with relatively low noise density. Reference noise can be heavily filtered with a low-pass filter. Below are two options for driving the reference input of the ADS127L01. Option 1 presents a single-chip solution with an integrated buffer. Option 2 presents a multichip solution with a precision reference and an external buffer. 9.1.4.1 Single Chip Solution: REF6xxx The REF6xxx is a family of very high-precision, low-noise, and low-drift voltage references. This single-chip solution has an integrated high-bandwidth buffer that presents a low output impedance to the ADC reference input. The REF6025 outputs a fixed 2.5-V output voltage; however, other devices from the same family are available to offer various output voltages and temperature drift specifications The ADS127L01 has the ability to maintain a high level of performance at relatively low levels of power consumption. The REF6025 only adds 750 μA of typical quiescent current to the system power budget, while still showcasing the performance of the ADS127L01 when sampling at full-speed, making it a great fit for low-power applications with limited board space. Figure 114 shows typical connections for the REF6025 as a reference driver circuit to the ADS127L01. The output of the REF6025 uses a Kelvin connection to correct for the voltage drop between the voltage output pins and the pads of the output capacitor. A small series resistance is required to keep the reference output stable. See the REF60xx device datasheet (SBOS708) for more details on the required connections and component values. REF6025 VSUPPLY + 10 F ± 121 k VIN GND_S EN GND_F SS VOUT_F FLT VOUT_S ADS127L01 47 m REFP REFN 47 F 0.1 F 1 F Copyright © 2016, Texas Instruments Incorporated Figure 114. REF6025 Connection to ADS127L01 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 67 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com 9.1.4.2 Multichip Solution: REF50xx + OPA320 The REF50xx is another family of low-noise, low-drift, high-precision voltage references. The REF5025 outputs a fixed 2.5-V output voltage; however, other devices from the same family are available to offer various output voltages. Buffer the output of the REF5025 with a low-noise, wide bandwidth amplifier like the OPA320 to achieve the best performance with the ADS127L01. The OPA320 is a precision, low-voltage CMOS operational amplifier optimized for low noise and wide bandwidth with a typical quiescent current of 1.5 mA. From 0.1 Hz to 10 Hz, the OPA320 features an output noise of 2.8 µVPP. With a unity gain-bandwidth product of 20 MHz, the OPA320 is able to drive the ADS127L01 reference inputs while sampling at full-speed without degrading linear performance of the system. Figure 115 shows an example reference circuit using the REF5025 and the OPA320. The output of the REF5025 is low-pass filtered to less than 2 Hz before the input of the OPA320. The OPA320 is placed in a noninverting buffer configuration with dual-feedback to compensate for the large capacitive output load and maintain stability. See the respective device data sheets for more details on the required connections and component values. 1k ADS127L01 2.2 F REFP REF5025 ± 10 k VIN VOUT 220 m 0.1 F + 47 F OPA320 VSUPPLY + 10 F REFN TEMP TRIM 220 m ± 10 F GND 1 F 22 F Copyright © 2016, Texas Instruments Incorporated Figure 115. REF5025 + OPA320 Connection to ADS127L01 Table 31 compares the performance characteristics of the two reference driver solutions discussed in this section. Table 31. Reference Selection DEVICE IQ (μA) TEMPERATURE DRIFT TYP (μV/°C) TEMPERATURE DRIFT MAX (μV/°C) NOISE (μVPP) (1) TEMPERATURE RANGE (°C) REF5025 + OPA320 2300 8.0 22.9 3.9 -40°C to +125°C REF6025 750 7.5 12.5 11.7 -40°C to +125°C REF6125 750 10.0 20 11.7 -40°C to +125°C (1) Total noise simulated from TINA-TI. The two reference solutions are capable of driving the ADS127L01 to meet data sheet specifications. While the multichip solution has a larger PCB footprint, the multichip solution offers similar noise performance, and allows more customization than the REF6x25, including the ability to low-pass filter the broadband noise of the REF5025. This multichip solution may provide a lower-cost alternative to the REF6x25 for applications that can tolerate a higher component count and power consumption. The REF6x25 has a smaller PCB footprint, and offers tighter drift specifications at a fraction of the power. 68 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 9.1.5 Driving LVDD With an External Supply A portion of the ADC modulator in the ADS127L01 is powered from a separate low-voltage analog supply (LVDD) to achieve lower overall power consumption. This supply is nominally 1.8 V and can be sourced by either an internal LDO (INTLDO = 0) or an external supply (INTLDO = 1). When the internal LDO supply is used, the LVDD current is sourced from AVDD. While LDOs are known to be smaller and less noisy than other power supply topologies, LDOs are much less efficient and can consume large amounts of power. An LDO dissipates excess power as heat in order to regulate the output voltage. The higher the dropout voltage is between the supply input and the LDO output, the more power that is wasted. Alternatively, an external switching power supply can drive LVDD. Switching power supplies are much more efficient and consume less power; however, a small switching ripple could appear on the output. The frequency content from this ripple can appear in the ADC output if: • The switching frequency falls directly in the ADC pass band. • The switching frequency aliases into the ADC pass band from an out-of-band frequency. Consider carefully when choosing the switching frequency (fSW) in order to maintain the highest system powersupply rejection (PSR). The LVDD supply pin offers at least 75 dB of PSR at 60 Hz, and improves with the digital filter stop-band attenuation. If possible, the ideal design synchronizes the switching supply frequency to the modulator clock frequency in order to avoid creating tones from clock intermodulation. Any remaining frequency content that is not suppressed by the LVDD PSR folds back to dc. Otherwise, choose an out-of-band switching frequency that falls within the stop band of the wideband FIR filter, or within the notches of the low-latency sinc filter, as shown in Figure 116 and Figure 117, respectively. fSW Magnitude (dB) Magnitude (dB) fSW Q ‡ IMOD (2n + 1) ‡ IMOD / 2 (n + 1) ‡ IMOD Q ‡ IMOD (2n + 1) ‡ IMOD / 2 (n + 1) ‡ IMOD Frequency (Hz) Frequency (Hz) Figure 116. Suggested fSW for Wideband Filters Figure 117. Suggested fSW for Low-Latency Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 69 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com 9.2 Typical Application Test and measurement applications interface sensor inputs with a precision data-acquisition signal chain. This signal chain must be capable of measuring a wide frequency range with very low noise and minimal harmonic distortion. Figure 118 illustrates the main components of sensor signal chain, consisting of a conditioning and attenuation stage at the sensor output, followed by a high-speed, low-noise amplifier driving a wide-bandwidth, delta-sigma ADC. + ± + ± ADS127L01 + Sensor Output Signal Conditioning ± + ± Differential Driver and ADC Copyright © 2016, Texas Instruments Incorporated Figure 118. Test and Measurement Block Diagram In data-acquisition systems, signal distortion can come from the amplifier, the settling of the switched-capacitor load transients, and the ADC. Choose both the differential drive amplifier and the ADC such that neither one limits the distortion performance of the signal chain. This section details the design procedure for the fullydifferential input stage to an ADC optimized for low noise and minimal harmonic distortion. 9.2.1 Design Requirements Table 32. Design Requirements DESIGN PARAMETER VALUE Analog supply voltage 3.0 V Modulator sampling frequency (fMOD) 16 MHz Filter pass band DC to 100 kHz (DR = 250 kSPS) Antialiasing filter rejection –100 dB at fMOD Total harmonic distortion (THD) –110 dB at –0.5-dBFS input signal amplitude Signal-to-noise ratio (SNR) 70 dB at 100-mV input signal amplitude (104 dB normalized to 2.5-V full-scale) Power consumption 20 mA (50 mW) ADS127L01, input drive amplifier, reference device + drive amplifier 9.2.2 Detailed Design Procedure The ADS127L01 offers a typical THD level of –110 dB for a modulator frequency of 16.384 MHz. Target the distortion from the input driver to be at least 10 dB better than the distortion of the ADC. The THS4551 provides exceptional ac performance with extremely low distortion levels near –120 dB. With a 130-MHz gain-bandwidth product, the THS4551 can drive the switched-capacitor input stage so that the load transients are mostly settled. For higher levels of performance, use a faster amplifier with more bandwidth as long as the increased current consumption fits within the system power budget. At 3.4 nV/√Hz broadband noise density and 1.35 mA of quiescent current, the THS4551 offers an attractive performance versus power tradeoff that is well-suited for these applications. Single-ended inputs have a varying input common-mode, and can produce larger even harmonics and decrease distortion performance. Use a fully-differential input to the ADC to help suppress even harmonics and provide a fixed common-mode voltage for the input signal. 70 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 For this design, the THS4551 is placed in a multiple-feedback (MFB) filter configuration, as shown in Figure 119. Nominal resistance values of 1.2 kΩ are used in the amplifier feedback path to optimize power consumption, while keeping the added broadband noise of the front-end driver circuit less than that of the ADS127L01. An MFB filter produces a second-order, low-pass response. 1.2 k 270 pF 330 THS4551 470 pF 1.2 k 1 nF VOCM 1.2 k + ± 5 10 AINP + ± AP2700 330 22 nF ADS127L01 AINN 5 10 270 pF 1.2 k Copyright © 2016, Texas Instruments Incorporated Figure 119. Multiple Feedback ADC Drive Circuit The discrete low-pass RC filter components (10 Ω and 22 nF) are small enough to increase the antialiasing filter rolloff without adding significant distortion or gain error to the system. Combined with the active MFB filter, the net result is a third-order antialiasing filter. Figure 120 plots the magnitude response of the front-end driver circuit and illustrates how it supplements the wideband 2 FIR filter in the ADS127L01. 40 20 0 Amplitude (dB) -20 -40 -60 -80 -100 -120 -140 MFB Response Digital Filter Response -160 -180 1 2 3 5 710 20 50 100 1000 Frequency (kHz) 10000 100000 D001 Figure 120. THS4551 MFB Filter Magnitude Response The response of the third-order antialiasing filter remains flat beyond the digital filter pass band. Signals within the bandwidth of interest are left unattenuated by the antialiasing filter. The wideband 2 filter is used to provide an average stop-band attenuation of –116 dB beginning at fDATA / 2. This transition band prevents signals from aliasing in the digital domain. At 304 kHz, the antialiasing filter reaches –3 dB, and rolls off sharply at a rate of –60 dB per decade. At 16 MHz, the filter response reaches –100 dB of attenuation, effectively eliminating unwanted frequency content around the modulator rate. The antialiasing filter attenuates the frequency content that alias around the modulator Nyquist frequency (fMOD / 2). The REF6025 circuit proposed in Figure 114 was selected to drive the ADS127L01 reference. This device enables the design to meet the outlined performance goals while remaining within the target power budget. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 71 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com 9.2.3 Application Curves Figure 121 shows a fast Fourier transform (FFT) of the 32,768 samples collected at 250 kSPS (OSR 64). An AP2700 generated a 4-kHz sine wave with a differential amplitude of –0.5 dB below full-scale (±2.36 V). The fundamental input frequency at 4 kHz is the dominate tone in the FFT. The first 15 harmonics are used to calculate the total harmonic distortion (THD) as –114.4 dB. The input amplifier and the antialiasing filter do not degrade the overall distortion performance of the signal chain. 0 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) SNR was measured with a small-signal 100 mVPP (–34 dB from full-scale) input sine wave generated by the AP2700. The SNR result is the difference in magnitude between the fundamental frequency and the integrated noise of the ADC output up until fDATA / 2. Figure 122 shows the FFT of the 32,768 samples collected at 256 kSPS (OSR = 64). The result is then normalized to full-scale to yield 106.3 dB. -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 -200 -200 0 20 40 60 80 Frequency (kHz) 100 120 0 20 40 60 80 Frequency (kHz) D017 fIN = 4 kHz, amplitude = –0.5 dBFS, THD = –114.4 dB 100 120 140 D018 fIN = 4 kHz, amplitude = 100 mVPP, SNR = 106.3 dB (normalized to FS) Figure 121. THD Results Figure 122. SNR Results To verify the effectiveness of an antialiasing filter, input a sine wave at the frequency of interest and measure how much that signal is attenuated at the output. In order to measure the attenuation at fMOD = 16 MHz, input a signal around or at that frequency and measure the alias of the signal that folds into the ADC pass band. Figure 123 shows the FFT results of the 32,768 samples collected at 64 kSPS (OSR 256) for finer frequency bin resolution. An Agilent 33522A was used to generate a differential -0.5 dBFS sine wave input at 16.004 MHz. Because 16.004 MHz is offset from 16 MHz (fMOD) by 4 kHz, the input signal aliases to 4 kHz. The magnitude of the frequency tone is the attenuation level of the antialiasing filter. 0 -20 -40 Amplitude (dB) -60 -80 -100 -120 -140 -160 -180 -200 0 3 6 9 12 15 18 Frequency (kHz) 21 24 27 30 D023 fMOD = 16 MHz, fIN= 16.004 MHz, amplitude = –0.5 dBFS, OSR = 256 (64 kSPS) Figure 123. Antialiasing Filter Attenuation Results 72 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 Table 33 lists the typical current consumption and power dissipation for the ADS127L01, the THS4551, and the REF6025. Table 33. Power Consumption COMPONENT QUIESCENT CURRENT (mA) POWER DISSIPATION (mW) ADS127L01 (AVDD) 10.6 31.8 ADS127L01 (DVDD) 4.4 7.8 THS4551 1.3 3.9 REF6025 0.8 2.3 TOTAL 17.1 45.8 9.3 Do's and Don'ts • • • • • • • • • • • • • Do partition the analog, digital, and power supply circuitry into separate sections on the printed circuit board (PCB). Do use a single ground plane for analog and digital grounds. Do place the analog components close to the ADC pins using short, direct connections. Do keep the SCLK pin free of glitches and noise. Do verify that the analog input voltages are within the specified input voltage range under all input conditions. Do tie unused digital input pins to DGND to minimize input leakage current. Do use an LDO to reduce voltage ripple generated by switch-mode power supplies. Do synchronize clock signals and switching supply frequencies to minimize intermodulation artifacts and noise degradation. Don't cross analog and digital signals. Don't route digital clock traces in the vicinity of the analog inputs or CAP1 and CAP2 analog bias voltages. Don't allow the analog and digital power supply voltages to exceed 3.9 V under any condition, including during power-up and power-down. Don’t use inductive supply or ground connections Don’t isolate analog ground (AGND) from digital ground (DGND). Figure 124 illustrates correct and incorrect ADC circuit connections. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 73 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Do's and Don'ts (continued) 1.8 V 3V 1.8 V 3V CORRECT AVDD INCORRECT Device DVDD AVDD Device 24-Bit û ADC AGND 24-Bit û ADC DGND AGND Low-impedance supply connections. 5V 1.8 V 3V fSW CORRECT AVDD Device INCORRECT AVDD LVDD SCLK 24-Bit û ADC AGND DGND Inductive supply or ground connections. 1.8 V 3V DVDD Device DVDD ÷ 2n CLK 24-Bit û ADC AGND DGND DGND Isolated AGND and DGND. Synchronized clocks and switching supplies. Copyright © 2016, Texas Instruments Incorporated Figure 124. Correct and Incorrect Circuit Connections 9.4 Initialization Setup Figure 125 illustrates a general procedure to configure the ADS127L01 to collect data. 74 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 Initialization Setup (continued) Power Off Set INTLDO Y // Enable or disable analog 1.8-V internal LDO Set Hardware Mode Pins // Pull up or pull down HR, OSR[1:0], FILTER[1:0], FSMODE, and FORMAT pins to DVDD or DGND Power Up Analog + Digital Supplies // Analog and digital supplies can come up together SET RESET/PWDN = 1 Write Registers // Start with power off Using SPI Mode? // RESET/PWDN can come up with power supply // Wait tsu(PWDN) and td(POR) for device to exit POR // Configure ADC registers only if using SPI mode N SET START = 1 or Use Start Command SET START = 1 or Use Start Command Monitor for DRDY Issue Frame-Sync or Monitor for Frame-Sync Collect Data Collect Data // Bring hardware START pin high to begin conversions // If using commands to control conversions, use start command to begin conversions. // Monitor for DRDY output if in SPI mode // Issue FSYNC input at set data rate if in frame-sync slave mode // Monitor for FSYNC output at set data rate if in frame-sync master mode // Wait for settled data to be available and capture on DOUT Copyright © 2016, Texas Instruments Incorporated Figure 125. ADS127L01 Configuration Sequence Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 75 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com 10 Power Supply Recommendations The ADS127L01 requires either two or three power supplies, depending on if the internal LDO is used to supply the LVDD analog supply. The AVDD analog supply is referenced to AGND, the LVDD analog supply is referenced to AGND, and the DVDD digital supply is referenced to DGND. The analog power supply can only be unipolar (for example, AVDD = 3.0 V, AGND = 0 V) and is independent of the digital power supply. If INTLDO = 0, the LVDD supply is internally generated using the AVDD supply. If INTLDO = 1, the internal LDO is disabled and LVDD supply must be externally supplied. The digital supply sets the digital I/O levels. 10.1 Power-Supply Sequencing The power supplies can be sequenced in any order, but in no case must any analog or digital inputs exceed the respective analog or digital power-supply voltage limits. Bring the RESET/PWDN pin high after the analog and digital supplies are up, or bring the pin high with the DVDD supply (assuming the AVDD and LVDD supplies come up with or before DVDD). After all supplies are stabilized, wait for the td(POR) timing for the power-on-reset to complete before communicating with the device in order to allow the power-up reset process to complete. 10.2 Power-Supply Decoupling Good power-supply decoupling is important to achieve optimum performance. AVDD, LVDD, and DVDD must be decoupled with at least a 1-µF capacitor, as shown in Figure 126. Place the bypass capacitors as close to the power-supply pins of the device as possible using low-impedance connections. Use multilayer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoid the use of vias for connecting the capacitors to the device pins for superior noise immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground planes. Connect analog and digital ground together as close to the device as possible. 3V 1.8 V 1 F 1 F AVDD 1.8-V External INTLDO = 1 DVDD CAP1 LVDD 1 F 1 F ADS127L01 CAP2 REFP 10 F 1 F 0.1 F CAP3 REFN AGND DGND 1 F Copyright © 2016, Texas Instruments Incorporated Figure 126. ADS127L01 Recommended Power-Supply Decoupling 76 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 11 Layout 11.1 Layout Guidelines Use a low-impedance connection to ground so that return currents flow undisturbed back to their respective sources. For best performance, dedicate an entire PCB layer to a ground plane and route no other signal traces on this layer. Keep connections to the ground plane as short and direct as possible. When using vias, place multiple vias in parallel to reduce the impedance to ground. If ground plane separation is necessary, make the connection as close to the ADC as possible. Connecting individual ground planes at multiple locations creates ground loops and is not recommended. A single ground plane for analog and digital avoids ground loops. For applications that require isolation, isolate the digital signals between the ADC and the controller or provide the isolation from the controller to the remaining system. If an external crystal is used to provide the ADC clock, connect the crystal and load capacitors directly to the ADC pins using short, direct traces. Bypass the ADC supply pins with a low-ESR ceramic capacitor, and place the bypass capacitors as close to the supply pins as possible using short, direct traces. For optimum performance, use low-impedance connections on the ground-side connections of the bypass capacitors. To make the bypassing most effective, flow the supply current through the bypass capacitor pins first and then to the ADC supply pins (also known as a Kelvin connection). If multiple ADCs are on the same PCB, use wide power-supply traces or dedicated power-supply planes to minimize the potential of crosstalk between ADCs. If external filtering is used for the analog inputs, use C0G-type ceramic capacitors when possible. C0G capacitors have stable properties and low-noise characteristics. Ideally, route differential signals as pairs in order to minimize the loop area between the traces. Route digital circuit traces (such as clock signals) away from all analog pins. When REFN is tied to AVSS, run the two traces separately as a star connection back to the AVSS pin in order to minimize coupling between the power-supply trace and reference-return trace. It is important that the SCLK input of the serial interface is free from noise and glitches. Even with relatively slow SCLK frequencies, short digital-signal rise-and-fall times can cause excessive ringing and noise. For best performance, keep the digital signal traces short, use termination resistors as needed, and make sure all digital signals are routed directly above the ground plane with minimal use of vias. An example of good component placement is shown in Figure 127. Although Figure 127 provides a good example of component placement, the best placement for each application is unique to the geometries, components, and PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every design and careful consideration must always be used when designing with any analog component. Signal Conditioning (RC filters and amplifiers) Supply Generation Interface Tranceiver Microcontroller Optional: Split Ground Cut Device Ground Fill or Ground Plane Ground Fill or Ground Plane Optional: Split Ground Cut Ground Fill or Ground Plane Connector or Antenna Ground Fill or Ground Plane Figure 127. System Component Placement 11.2 Layout Example Figure 128 is an example layout of the ADS127L01, input driver circuit, and reference driver circuit using four PCB layers. In this example, the top and bottom layers are used for analog and digital signals. The first inner layer is dedicated to the ground plane and the second inner layer is dedicated to the power supplies. The PCB is partitioned with analog signals routed on the left, and digital signals routed on the right. Polygon pours are used to provide low-impedance connections between the power supplies and the reference voltage for the ADC. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 77 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Differential Input Place smaller decoupling caps closest to the device. 25. CAP3 26. DGND 27. DVDD 28. RESET/PWDN 29. HR 30. FORMAT 32. AVDD 31. AGND External Clock Input Place bypass capacitor directly across ADC inputs. 13. VS± 14. VS± 15. VS± 16. VS± Consider adding polygon cutouts on internal supply layers underneath the amplifier input and output pins to reduce parasitic capacitance and maintain adequate phase margin. 1. LVDD 24. CLK 1. FB± 12. PD 2. CAP1 23. CS 2. IN+ 11. OUT± 3. AINN 10. OUT+ 4. AINP 22. SCLK THS4551 5. AGND 21. DIN 20. DOUT 16. OSR0 Place bypass capacitor directly across reference inputs. 15. OSR1 17. START 14. FSMODE 18. DAISYIN 8. INTLDO 13. FILTER0 19. DRDY/FSYNC 7. REXT 12. FILTER1 6. AVDD 11. CAP2 8. VS+ 7. VS+ 6. VS+ 5. VS+ 9. VCOM 10. REFN 4. FB+ ADS127L01 9. REFP 3. IN± Match differential signal path for best CMR and THD performance. 6. OUT_F 5. OUT_S 4. FLT 7. GND_F REF6025 3. SS 8. GND_S 2. EN Internal plane connected to GND (AGND = DGND) 1. VIN Use multiple vias in parallel to reduce inductance. Copyright © 2016, Texas Instruments Incorporated Figure 128. Layout Example 78 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 ADS127L01 www.ti.com SBAS607A – APRIL 2016 – REVISED MAY 2016 12 Device and Documentation Support 12.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.2 Trademarks E2E is a trademark of Texas Instruments. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS127L01 79 PACKAGE OPTION ADDENDUM www.ti.com 25-May-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADS127L01IPBS ACTIVE TQFP PBS 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 127L01 ADS127L01IPBSR ACTIVE TQFP PBS 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 127L01 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 25-May-2016 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-May-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS127L01IPBSR Package Package Pins Type Drawing TQFP PBS 32 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 7.2 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.2 1.5 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 26-May-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS127L01IPBSR TQFP PBS 32 1000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2016, Texas Instruments Incorporated