Revised April 2002 CD4070BC Quad 2-Input EXCLUSIVE-OR Gate General Description Features The CD4070BC employs complementary MOS (CMOS) transistors to achieve wide power supply operating range, low power consumption, and high noise margin, the CD4070BC provide basic functions used in the implementation of digital integrated circuit systems. The N- and Pchannel enhancement mode transistors provide a symmetrical circuit with output swing essentially equal to the supply voltage. No DC power other than that caused by leakage current is consumed during static condition. All inputs are protected from damage due to static discharge by diode clamps to VDD and VSS. ■ Wide supply voltage range: 3.0V to 15V ■ High noise immunity: 0.45 VDD typ. ■ Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS ■ Pin compatible to CD4030A Equivalent to MM74C86 and MC14070B Ordering Code: Order Number Package Number Package Description CD4070BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4070BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Inputs Outputs A B L L Y L L H H H L H H H L Top View © 2002 Fairchild Semiconductor Corporation DS005976 www.fairchildsemi.com CD4070BC Quad 2-Input EXCLUSIVE-OR Gate October 1987 CD4070BC Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) (Note 2) −0.5 to +18 VDC DC Supply Voltage (VDD) Input Voltage (VIN) −0.5 to VDD +0.5 VDC −65°C to +150 °C Storage Temperature Range (TS) 700 mW Small Outline 500 mW Symbol IDD Parameter (Note 3) −55°C Conditions Quiescent Device VDD = 5V, Current VIN = VDD or VSS −55°C to +125°C Note 2: VSS = 0V unless otherwise specified. 260 °C DC Electrical Characteristics 0 to VDD VDC Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides conditions for actual device operation. Lead Temperature (TL) (Soldering, 10 seconds) 3V to 15 VDC Input Voltage (VIN) Operating Temperature Range (TA) Power Dissipation (PD) Dual-In-Line DC Supply Voltage (VDD) Min VDD = 10V, +25°C Max Min Typ +125°C Max Min Max 0.25 0.25 7.5 0.5 0.5 15 1.0 1.0 30 VIN = VDD or VSS VDD = 15V, Units µA VIN = VDD or VSS VOL VOH VIL VIH IOL IOH IIN LOW Level |IO| < 1 µA Output Voltage VDD = 5V 0.05 0 0.05 0.05 VDD = 10V 0.05 0 0.05 0.05 VDD = 15V 0.05 0 0.05 0.05 HIGH Level |IO| < 1 µA Output Voltage VDD = 5V 4.95 4.95 5 4.95 VDD = 10V 9.95 9.95 10 9.95 VDD = 15V 14.95 14.95 15 14.95 V LOW Level |IO| < 1 µA Input Voltage VDD = 5V, VO = 4.5V or 0.5V 1.5 1.5 1.5 VDD = 10V, VO = 9V or 1.0V 3.0 3.0 3.0 VDD = 15V, VO = 13.5V or 1.5V 4.0 4.0 4.0 HIGH Level |IO| < 1 µA Input Voltage VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5 VDD = 10V, VO = 1V or 9.0V 7.0 7.0 7.0 VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0 LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 Current VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9 VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4 HIGH Level Output VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36 Current VDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9 VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4 Input Current V V V 0.36 mA mA VDD = 15V, VIN = 0V −0.1 −10−5 −0.1 −1.0 VDD = 15V, VIN = 15V 0.1 10−5 0.1 1.0 µA Note 3: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides conditions for actual device operation. www.fairchildsemi.com 2 (Note 4) TA = 25°C, CL = 50 pF, RL = 200k, tr and tf ≤ 20 ns, unless otherwise specified Typ Max tPHL or Symbol Propagation Delay Time VDD = 5V 110 185 tPLH from Input to Output VDD = 10V 50 90 VDD = 15V 40 75 tTHL or Parameter Transition Time tTLH Conditions Min VDD = 5V 100 200 VDD = 10V 50 100 VDD = 15V 40 80 7.5 CIN Average Input Capacitance Any Input 5 CPD Power Dissipation Capacitance Any Input (Note 5) 20 Units ns ns pF pF Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics Application Note—AN-90. Typical Performance Characteristics Propagation Delay Time vs. Load Capacitance AC Test Circuit and Switching Time Waveforms Note: Delays measured with input t r, tf = 20 ns. tr = tf = 20 ns 3 www.fairchildsemi.com CD4070BC AC Electrical Characteristics CD4070BC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A www.fairchildsemi.com 4 CD4070BC Quad 2-Input EXCLUSIVE-OR Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 5 www.fairchildsemi.com