Cypress CY7B9945V High-speed multi-phase pll clock buffer Datasheet

RoboClock
CY7B9945V
High-speed Multi-phase PLL Clock Buffer
Features
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500 ps max. Total Timing Budget™ (TTB™) window
24–200 MHz input/output operation
Low output-output skew < 200 ps
10 + 1 LVTTL outputs driving 50Ω terminated lines
Dedicated feedback output
Phase adjustments in 625/1300 ps steps up to +10.4 ns
3.3V LVTTL/LVPECL, fault-tolerant, and hot-insertable
reference inputs
Multiply/divide ratios of 1–6, 8, 10, and 12
Individual output bank disable
Output high-impedance option for testing purposes
Integrated phase-locked loop (PLL) with lock indicator
Low cycle-cycle jitter (<100 ps peak-peak)
3.3V operation
Industrial temperature range: –40°C to +85°C
52-pin 1.4-mm TQFP package
Functional Description
The CY7B9945V high-speed multi-phase PLL clock buffer
offers user-selectable control over system clock functions.
Block Diagram
FS
This multiple-output clock driver provides the system
integrator with functions necessary to optimize the timing of
high-performance computer and communication systems.
The device features a guaranteed maximum TTB window
specifying all occurrences of output clocks with respect to the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.
Ten configurable outputs each drive terminated transmission
lines with impedances as low as 50Ω while delivering minimal
and specified output skews at LVTTL levels. The outputs are
arranged in two banks of four and six outputs. These banks
allow a divide function of 1 to 12, with phase adjustments in
625-ps–1300-ps increments up to ±10.4 ns. The dedicated
feedback output allows divide-by functionality from 1 to 12 and
limited phase adjustments. However, if needed, any one of the
ten outputs can be connected to the feedback input as well as
driving other inputs.
Selectable reference input is a fault-tolerant feature which
allows smooth change over to secondary clock source, when
the primary clock source is not in operation. The reference
inputs and feedback inputs are configurable to accommodate
both LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
Pin Configuration
3
REFA+
REFA+
VCCQ
FBK
GND
QF
VCCN
1Q1
VCCN
1Q0
REFBREFSEL
FBK
GND
PLL
FBDS0
LOCK
LOCK
REFB+
FBDS1
REFA-
52 51 50 49 48 47 46 45 44 43 42 41 40
3
1F3
3
1Q2
1Q3
DIS1
REFAREFSEL
REFBREFB+
1F2
FS
GND
1Q2
VCCN
1Q3
FBF0
1F0
VCCQ
DIS2
1F2
MODE
3
GND
3
1DS1
GND
1DS0
1Q1
Divide
and
Phase
Select
2Q5
3
CY7B9945V
VCCN
1F1
1Q0
2Q4
3
DIS1
1F0
QF
1F1
3
1F3
FBDS1
VCCQ
3
3
GND
FBF0
FBDS0
Divide
and
Phase
Select
1
39
2
38
3
37
4
36
5
35
6
34
7
33
8
32
9
31
10
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
1DS0
MODE
2F1
2F0
2DS1
GND
2Q0
VCCN
2Q1
2Q2
VCCN
2Q3
GND
1DS1
2DS0
2Q0
2F0
3
2F1
3
2DS0
3
2DS1
3
2Q1
Divide
and
Phase
Select
2Q2
2Q3
2Q4
2Q5
DIS2
Cypress Semiconductor Corporation
Document #: 38-07336 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised July 24, 2003
RoboClock
CY7B9945V
Pin Definitions
Pin
Name
I/O
Type
Description
34
FS
Input
Three-level Frequency Select. This input must be set according to the nominal frequency
Input
(fNOM). See Table 1.
40,39,
36,37
REFA+, REFAREFB+, REFB-
Input
LVTTL/
LVDIFF
Reference Inputs. These inputs can operate as differential PECL or
single-ended TTL reference inputs to the PLL. When operating as a
single-ended LVTTL input, the complementary input must be left open.
38
REFSEL
Input
LVTTL
Reference Select Input. The REFSEL input controls how the reference input
is configured. When LOW, it will use the REFA pair as the reference input.
When HIGH, it will use the REFB pair as the reference input. This input has
an internal pull-down.
42
FBK
Input
LVTTL
Feedback Input Clock. The PLL will operate such that the rising edges of
the reference and feedback signals are aligned in phase and frequency. This
pin is used to feedback the clock output QF to the phase detector.
28,18,
35,17,
2, 1
1F[0:3], 2F[0:1]
Input
19,26
DIS[1:2]
Input
14,12,
13,3
[1:2]DS[0:1]
Input
3-level Input Output Divider Function Select. Each pair determines the divider ratio of
the respective bank of outputs. See Table 4.
29
FBF0
Input
3-level Input Feedback Output Phase Function Select. This input determines the phase
of the QF output. See Table 3.
50,51
FBDS[0:1]
Input
3-level Input Feedback Output Divider Function Select. This input determines the
divider ratio of the QF output. See Table 4.
3-level Input Output Phase Function Select. Each pair determines the phase of the
respective bank of outputs. See Table 3.
LVTTL
Output Disable. Each input controls the state of the respective output bank.
When HIGH, the output bank is disabled to “HOLD-OFF” or “High-Z” state;
the disable state is determined by MODE. When LOW, outputs 1Q[0:3] and
2Q[0:5] are enabled. See Table 5.
48,46, 1Q[0:3], 2Q[0:5]
32,30,
5,7,8,10
, 20,22
Output
LVTTL
Clock Outputs with Adjustable Phases and fNOM Divide Ratios. The
output frequencies and phases are determined by [1:2]DS[0:1], and 1F[0:3]
and 2F[0:1], respectively. See Table 3 and Table 4.
44
QF
Output
LVTTL
Feedback Clock Output. This output is intended to be connected to the FBK
input. The output frequency and phase are determined by FBDS[0:1] and
FBF0, respectively. See Table 3 and 4.
52
LOCK
Output
LVTTL
PLL Lock Indicator. When HIGH, this output indicates the internal PLL is
locked to the reference signal. When LOW, it indicates that the PLL is
attempting to acquire lock
25
MODE
Input
6,9,21,
31, 45,
47
VCCN
PWR
Power Supply for the Output Buffers
16,27,
41
VCCQ
PWR
Power Supply for the Internal Circuitry
PWR
Device Ground
4,11,15, GND
23,24,
33,43,4
9
Document #: 38-07336 Rev. *D
3-level Input This pin determines the clock outputs’ disable state. When this input is
HIGH, the clock outputs will disable to high impedance state (High-Z). When
this input is LOW, the clock outputs will disable to HOLD-OFF mode. When
in MID, the device will enter factory test mode.
Page 2 of 10
RoboClock
CY7B9945V
Block Diagram Description
The PLL adjusts the phase and the frequency of its output
signal to minimize the delay between the reference (REFA/B+,
REFA/B-) and the feedback (FB) input signals.
The CY7B9945V has a flexible REF input scheme. These
inputs allow the use of either differential LVPECL or
single-ended LVTTL inputs. To configure as single-ended
LVTTL inputs, the complementary pin must be left open (internally pulled to 1.5V), then the other input pin can be used as
a LVTTL input. The REF inputs are also tolerant to hot
insertion.
The REF inputs can be changed dynamically. When changing
from one reference input to the other reference input of the
same frequency, the PLL is optimized to ensure that the clock
outputs period will not be less than the calculated system
budget (tMIN = tREF (nominal reference period) – tCCJ
(cycle-cycle jitter) – tPDEV (max. period deviation)) while
reacquiring lock.
The FS control pin setting determines the nominal operational
frequency range of the divide by one output (fNOM) of the
device. fNOM is directly related to the VCO frequency. The FS
setting for the device is shown in Table 1. For CY7B9945V, the
upper fNOM range extends from 96 MHz to 200 MHz.
Table 1. Frequency Range Select
fNOM (MHz)
FS[1]
Min.
24
48
96
LOW
MID
HIGH
Max.
52
100
200
Time Unit Definition
Selectable skew is in discrete increments of time unit (tU). The
value of a tU is determined by the FS setting and the maximum
nominal output frequency. The equation to be used to
determine the tU value is as follows:
tU = 1/(fNOM*N).
N is a multiplication factor which is determined by the FS
setting. fNOM is nominal frequency of the device. N is defined
in Table 2.
Table 2. N Factor Determination
FS
LOW
MID
HIGH
N
32
16
8
CY7B9945V
fNOM (MHz) at which tU = 1.0 ns
31.25
62.5
125
Divide and Phase Select Matrix
The Divide Select Matrix is comprised of three independent
banks: two banks of clock outputs and one bank for feedback.
The Phase Select Matrix, on the other hand, enables
independent phase adjustments on 1Q[0:1], 1Q[2:3] and
2Q[0:5]. The frequency of 1Q[0:3] is controlled by 1DS[0:1]
while the frequency of 2Q[0:5] is controlled by 2DS[0:1]. The
phase of 1Q[0:1] is controlled by 1F[0:1], that of 1Q[2:3] is
controlled by 1F[2:3] and that of 2Q[0:5] is controlled by
2F[0:1].
The high-fanout feedback output buffer (QF) may connect to
the feedback input (FBK). This feedback output also has one
phase function select input (FBF0) and two divider function
selects FBDS[0:1].
The phase capabilities that are chosen by the phase function
select pins are shown in Table 3. The divide capabilities for
each bank are shown in Table 4.
Table 3. Output Phase Select
Control Signal
1F1
1F0
1F3
1F2
2F1
2F0
FBF0
LOW
LOW
LOW
MID
LOW
HIGH
MID
LOW
MID
MID
MID
HIGH
HIGH
LOW
HIGH
MID
HIGH
HIGH
Output Phase Function
1Q[0:1]
1Q[2:3]
2Q[0:5]
–4tU
–3tU
–2tU
–1tU
0tU
+1tU
+2tU
+3tU
+4tU
–4tU
–3tU
–2tU
–1tU
0tU
+1tU
+2tU
+3tU
+4tU
QF
–8tU
–4tU
–7tU
N/A
–6tU
N/A
BK1Q[0:1][2] N/A
0tU
0tU
BK1Q[2:3][2] N/A
+6tU
N/A
+7tU
N/A
+8tU
+4tU
Table 4. Output Divider Select
Control Signal
[1:2]DS1
[1:2]DS0
and FBDS1
and
FBDS0
LOW
LOW
LOW
MID
LOW
HIGH
MID
LOW
MID
MID
MID
HIGH
HIGH
LOW
HIGH
MID
HIGH
HIGH
Output Divider Function
Bank1
Bank2
Feedback
/1
/2
/3
/4
/5
/6
/8
/ 10
/ 12
/1
/2
/3
/4
/5
/6
/8
/ 10
/ 12
/1
/2
/3
/4
/5
/6
/8
/ 10
/ 12
Figure 1 illustrates the timing relationship of programmable
skew outputs. All times are measured with respect to REF with
the output used for feedback programmed with 0tU skew. The
PLL naturally aligns the rising edge of the FB input and REF
input. If the output used for feedback is programmed to
another skew position, then the whole tU matrix will shift with
respect to REF. For example, if the output used for feedback
is programmed to shift –4tU, then the whole matrix is shifted
forward in time by 4tU. Thus an output programmed with 4tU
of skew will effectively be skewed 8tU with respect to REF.
Notes:
1. The level to be set on FS is determined by the “nominal” operating frequency (fNOM) of the VCO and Phase Generator. fNOM always appears on an output when
the output is operating in the undivided mode. The REF and FB are at fNOM when the output connected to FB is undivided.
2. BK1Q denotes following the skew setting of indicated Bank1 outputs.
Document #: 38-07336 Rev. *D
Page 3 of 10
U
t 0 +6t
U
U
t 0 +5t
t 0 +8t
U
t 0 +4t
U
U
t 0 +3t
t 0 +7t
U
t 0 +2t
t 0 +1t
t0
U
U
0
t – 1t
t 0 – 2t U
t 0 – 3t U
t 0 – 4t U
t 0 – 5t U
t 0 – 6t U
t 0 – 7t U
t 0 – 8t U
RoboClock
CY7B9945V
FBInput
REFInput
1F[0:3]
2F[0:3]
(N/A)
LL
–8tU
(N/A)
LM
–7tU
(N/A)
LH
–6tU
LL
(N/A)
–4tU
LM
(N/A)
–3tU
LH
(N/A)
–2tU
ML
(N/A)
–1tU
MM
MM
0t U
MH
(N/A)
+1t U
HL
(N/A)
+2t U
HM
(N/A)
+3t U
HH
(N/A)
+4t U
(N/A)
HL
+6t U
(N/A)
HM
+7t U
(N/A)
HH
+8t U
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output[3]
Output Disable Description
The output of each output bank can be independently put into
a HOLD-OFF or high-impedance state. The combination of the
MODE and DIS[1:2] inputs determines the clock outputs’ state
for each bank. When the DIS[1:2] is LOW, the outputs of the
corresponding banks will be enabled. When DIS[1:2] is HIGH,
the outputs for that bank will be disabled to a high-impedance
(HI-Z) or HOLD-OFF state. Table 5 defines the disabled
outputs functions.
The HOLD-OFF state is intended to be a power saving feature.
An output bank is disabled to the HOLD-OFF state in a
maximum of six output clock cycles from the time when the
disable input is HIGH. When disabled to the HOLD-OFF state,
outputs are driven to a logic LOW state on their falling edges.
This ensures the output clocks are stopped without a glitch.
When a bank of outputs is disabled to HI-Z state, the
respective bank of outputs will go HI-Z immediately.
Table 5. DIS[1:2] Functionality
MODE
DIS[1:2]
1Q[0:3], 2Q[0:5]
HIGH/LOW
LOW
ENABLED
HIGH
HIGH
HI-Z
LOW
HIGH
HOLD-OFF
MID
X
FACTORY TEST
Note:
3. FB connected to an output selected for “Zero” skew (i.e., FBF0 = MID or XF[1:0] = MID).
Document #: 38-07336 Rev. *D
Page 4 of 10
RoboClock
CY7B9945V
Lock Detect Output Description
The LOCK detect output indicates the lock condition of the
integrated PLL. Lock detection is accomplished by comparing
the phase difference between the reference and feedback
inputs. Phase error is declared when the phase difference
between the two inputs is greater than the specified device
propagation delay limit tPD.
When in the locked state, after four or more consecutive
feedback clock cycles with phase-errors, the LOCK output will
be forced LOW to indicate out-of-lock state.
When in the out-of-lock state, 32 consecutive phase-errorless
feedback clock cycles are required to allow the LOCK output
to indicate lock condition (LOCK = HIGH).
f the feedback clock is removed after LOCK has gone HIGH,
a “Watchdog” circuit is implemented to indicate the out-of-lock
condition after a time-out period by deasserting LOCK LOW.
This time out period is based upon a divided down reference
clock.
on the configurations of the divide, skew and frequency
selection. All clock outputs will stay in High-Z mode and all
FSMs will stay in the deterministic state until DIS2 is
deasserted, which will cause the device to reenter factory test
mode.
Safe Operating Zone
Figure 2 illustrates the operating condition at which the device
does not exceed its allowable maximum junction temperature
of 150°C. Figure 2 shows the maximum number of outputs that
can operate at 185 MHz (with 25-pF load and no air flow) or
200 MHz (with 10-pF load and no air flow) at various ambient
temperatures. At the limit line, all other outputs are configured
to divide-by-two (i.e., operating at 92.5 MHz) or lower
frequencies. The device will operate below maximum
allowable junction temperature of 150°C when its configuration (with the specified constraints) falls within the shaded
region (safe operating zone). Figure 2 shows that at 85°C, the
maximum number of outputs that can operate at 200 MHz is 6.
This assumes that there is activity on the selected REF input.
If there is no activity on the selected REF input then the LOCK
detect pin may not accurately reflect the state of the internal
PLL.
Typical Safe Operating Zone
(25-pF Load, 0-m/s air flow)
Factory Test Mode Description
When in the test mode, the device can be reset to a deterministic state by driving the DIS2 input HIGH. Doing so will cause
all outputs to disable and after the selected reference clock pin
has five positive transitions, all internal finite state machines
(FSM) to be set a deterministic state. The states will depend
Document #: 38-07336 Rev. *D
Ambient Temperature (C)
The device will enter factory test mode when the MODE is
driven to MID. In factory test mode, the device will operate with
its internal PLL disconnected; input level supplied to the
reference input will be used in place of the PLL output. In TEST
mode the FB input must be tied LOW. All functions of the
device are still operational in factory test mode except the
internal PLL and output bank disables. The MODE input is
designed to be a static input. Dynamically toggling this input
from LOW to HIGH may temporarily cause the device to go
into factory test mode (when passing through the MID state).
100
95
90
85
80
75
70
Safe Operating Zone
65
60
55
50
2
4
6
8
10
Number of Outputs at 185 MHz
Figure 2. Typical Safe Operating Zone
Page 5 of 10
RoboClock
CY7B9945V
Absolute Maximum Conditions
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–40°C to +125°C
Output Current into Outputs (LOW)............................. 40 mA
Static Discharge Voltage........................................... > 1100V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................. > ± 200 mA
Operating Range
Ambient Temperature
with Power Applied ..................................... –40°C to +125°C
Range
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
Commercial
DC Input Voltage......................................–0.3V to VCC+0.5V
Industrial
Ambient Temperature
VCC
0°C to +70°C
3.3V ±10%
–40°C to +85°C
3.3V ±10%
Electrical Characteristics Over the Operating Range
Parameter
Description
LVTTL-compatible Output Pins (1Q[0:3],2Q[0:5])
Test Conditions
Min.
Max.
Unit
2.4
2.4
–
–
V
V
–
–
0.5
0.5
V
V
–100
100
µA
2.0
–0.3
VCC + 0.3
0.8
V
V
–
–
100
500
µA
µA
–500
–
µA
Min. < VCC < Max.
0.87 * VCC
–
V
0.47 * VCC 0.53 * VCC
–
0.13 * VCC
–
200
–
400
VOH
LVTTL HIGH Voltage
(QF, 1Q[0:3], 2Q[0:5])
LOCK
VCC = Min., IOH = –30 mA
IOH = –2 mA, VCC = Min.
VOL
LVTTL LOW Voltage
(QF, 1Q[0:3], 2Q[0:5])
LOCK
VCC = Min., IOL= 30 mA
IOL= 2 mA, VCC = Min.
High-impedance State Leakage Current
IOZ
LVTTL-compatible Input Pins (FBK, REF±, DIS[1:2],REFSEL)
VIH
VIL
LVTTL Input HIGH
LVTTL Input LOW
Min. < VCC < Max.
Min. < VCC < Max.
II
IlH
LVTTL VIN >VCC
LVTTL Input HIGH Current
VCC = GND, VIN = 3.63V
VCC = Max., VIN = VCC
LVTTL Input LOW Current
VCC = Max., VIN = GND
IlL
Three-level Input Pins (FS[0:2], 1F[0:3], 2F[0:1], [1:2]DS[0:1], FBFO, FBDS[0:1],MODE)
VIHH
Three-level Input HIGH[4]
MID[4]
VIMM
VILL
Three-level Input
Three-level Input LOW[4]
Min. < VCC < Max.
Min. < VCC < Max.
IIHH
Three-level Input HIGH FS[0:2],IF[0:3],FBDS[0:1]
Current
2F[0:1],[1:2]DS[0:1],FBFO
VIN = VCC
IIMM
Three-level Input MID
Current
VIN = VCC/2
–50
–100
50
100
µA
µA
IILL
Three-level Input LOW FS[0:2],IF[0:3],FBDS[0:1]
Current
2F[0:1],[1:2]DS[0:1],FBFO
VIN = GND
–200
–400
–
–
µA
µA
FS[0:2],IF[0:3],FBDS[0:1]
2F[0:1],[1:2]DS[0:1],FBFO
LVDIFF Input Pins (REF[A:B]±)
VDIFF
Input Differential Voltage
V
V
µA
µA
400
VCC
mV
Highest Input HIGH Voltage
Lowest Input LOW Voltage
1.0
GND
VCC
VCC – 0.4
V
V
Common Mode Range (Crossing Voltage)
VCOM
Operating Current
0.8
VCC – 0.2
V
VIHHP
VILLP
ICCI
ICCN
Internal Operating
Current
Output Current
Dissipation/Pair[6]
CY7B9945V
VCC = Max., fMAX[5]
–
250
mA
CY7B9945V
VCC = Max., CLOAD = 25
pF, RLOAD = 50Ω at VCC/2,
fMAX
–
40
mA
Note:
4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
the unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK
time before all data sheet limits are achieved.
5. ICCI measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (fNOM = 200 MHz) and the other output bank to run at half
the maximum frequency. FS is asserted to the HIGH state.
6. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum ICCN at maximum frequency and maximum
load of 25 pF terminated to 50Ω at VCC/2.
Document #: 38-07336 Rev. *D
Page 6 of 10
RoboClock
CY7B9945V
Capacitance
Parameter
CIN
Description
Test Conditions
Min.
Max.
Unit
–
5
pF
TA = 25°C, f = 1 MHz, VCC = 3.3V
Input Capacitance
Switching Characteristics Over the Operating Range
[7, 8, 9, 10, 11]
CY7B9945V-2 CY7B9945V-5
Min.
Max.
Min.
Max.
Unit
fin
Parameter
Clock Input Frequency
Description
24
200
24
200
MHz
fout
Clock Output Frequency
24
200
24
200
MHz
tSKEWPR
Matched-Pair Skew[12, 13],1Q[0:1],1Q[2:3],2Q[0:1],2Q[2:3],2Q[4:5]
–
200
–
200
ps
Skew[12, 13]
tSKEWBNK
Intrabank
–
250
–
250
ps
tSKEW0
Output-Output Skew (same frequency and phase, rise to rise, fall to fall)[12, 13]
–
250
–
550
ps
tSKEW1
Output-Output Skew (same frequency and phase, other banks at
different frequency, rise to rise, fall to fall)[12, 13]
–
250
–
650
ps
tSKEW2
Output-Output Skew (all output configurations outside of tSKEW0 and
tSKEW1)[12, 13]
–
500
–
800
ps
tCCJ1-3
Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 1, 2, 3)
–
150
–
150
ps
PeakPeak
tCCJ4-12
Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 4, 5,
6, 8, 10, 12)
–
100
–
100
ps
PeakPeak
tPD
Propagation Delay, REF to FB Rise
–250
250
–500
500
ps
TTB
Total Timing Budget window (same frequency and phase)[14, 15]
–
500
–
700
ps
tPDDELTA
Propagation Delay difference between two devices[16]
–
200
–
200
ps
tREFpwh
REF input (Pulse Width HIGH)[5]
2.0
–
2.0
–
ns
tREFpwl
REF input (Pulse Width
LOW)[5]
tr/tf
Output Rise/Fall Time[17]
tLOCK
PLL Lock TIme From Power-Up
–
10
tRELOCK1
PLL Relock Time (from same frequency, different phase) with Stable
Power Supply
–
500
tRELOCK2
PLL Re-Lock Time (from different frequency, different phase) with Stable
Power Supply[18]
–
1000
tODCV
Output duty cycle deviation from 50%[11]
2.0
–
2.0
–
ns
0.15
2.0
0.15
2.0
ns
–
10
ms
–
500
µs
–
1000
µs
–1.0
1.0
–1.0
1.0
ns
tPWH
Output HIGH time deviation from 50%
[19]
–
1.5
–
1.5
ns
tPWL
Output LOW time deviation from 50%[19]
–
2.0
–
2.0
ns
reference[20]
tPDEV
Period deviation when changing from reference to
–
0.025
–
0.025
UI
tOAZ
DIS[1:2] HIGH to output high-impedance from ACTIVE[12, 21]
1.0
10
1.0
10
ns
tOZA
DIS[1:2] LOW to output ACTIVE from output is high-impedance[21, 22]
0.5
14
0.5
14
ns
Notes:
7. This is for non-three-level inputs.
8. Assumes 25 pF Max. Load Capacitance up to 185 MHz. At 200 MHz the max. load is 10 pF.
9. Both outputs of pair must be terminated, even if only one is being used.
10. Each package must be properly decoupled.
11. AC parameters are measured at 1.5V, unless otherwise indicated.
12. Test Load CL= 25 pF, terminated to VCC/2 with 50Ω up to185 MHz and 10-pF load to 200 MHz.
13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when
all outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.
14. Tested initially and after any design or process changes that may affect these parameters.
15. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply
voltage, operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output
skew, cycle-cycle jitter, and dynamic phase error. TTB will be equal to or smaller than the maximum specified value at a given output frequency.
16. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
17. Rise and fall times are measured between 2.0V and 0.8V.
18. fNOM must be within the frequency range defined by the same FS state.
19. tPWH is measured at 2.0V. tPWL is measured at 0.8V.
Document #: 38-07336 Rev. *D
Page 7 of 10
RoboClock
CY7B9945V
AC Test Loads and Waveforms[23]
3.3V
R1
For LOCK output only
R1 = 910 Ω
R2 = 910 Ω
CL < 30 pF
For all other outputs
OUTPUT
R1 = 100Ω
CL
R2 = 100Ω
CL < 25 pF to 185 MHz
or 10 pF at 200 MHz
(Includes fixture and
probe capacitance)
R2
(a) LVTTL AC Test Load
3.3V
2.0V
2.0V
0.8V
GND
0.8V
< 1 ns
< 1 ns
(b) TTL Input Test Waveform
AC Timing Diagram
tREFpwl
tREFpwh
[1:2]Q[0,2]
REF
t SKEWPR
t SKEWPR
t PWH
tPD
t PWL
[1:2]Q[1,3]
2.0V
FB
0.8V
tCCJ1-3,4-12
Q
[1:2]Q[0:3]
t SKEWBNK
t SKEWBNK
[1:2]Q[0:3]
REF TO DEVICE 1 and 2
tODCV
tODCV
tPD
Q
FB DEVICE1
tPDELTA
tPDELTA
t SKEW0,1
t SKEW0,1
Other Q
FB DEVICE2
Notes:
20. UI = unit interval. Examples: 1 UI is a full period. 0.1UI is 10% of period.
21. Measured at 0.5V deviation from starting voltage.
22. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 185 MHz or 10 pF to 200 MHz.
23. These figures are for illustration purposes only. The actual ATE loads may vary.
Document #: 38-07336 Rev. *D
Page 8 of 10
RoboClock
CY7B9945V
Ordering Information
Propagation
Delay (ps)
Max. Speed
(MHz)
Ordering Code
Package Name
Package Type
250
200
CY7B9945V-2AC
A52
52-lead Thin Quad Flat Pack
Operating Range
Commercial
500
200
CY7B9945V-5AC
A52
52-lead Thin Quad Flat Pack
Commercial
250
200
CY7B9945V-2AI
A52
52-lead Thin Quad Flat Pack
Industrial
500
200
CY7B9945V-5AI
A52
52-lead Thin Quad Flat Pack
Industrial
Package Diagram
52-lead Thin Plastic Quad Flat Pack (10 × 10 × 1.4 mm) A52
51-85131-**
RoboClock is a registered trademark, and Total Timing Budget and TTB are trademarks, of Cypress Semiconductor. All product
and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07336 Rev. *D
Page 9 of 10
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
RoboClock
CY7B9945V
Document History Page
Document Title: CY7B9945V RoboClock High-speed Multi-phase PLL Clock Buffer
Document Number: 38-07336
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
111747
03/04/02
CTK
New Data Sheet
*A
116572
09/05/02
HWT
Added TTB Features
*B
119078
10/16/02
HWT
Corrected the following items in the Electrical Characteristics table:
IIIL,IIIH,IIIM specifications from: three-level input pins excluding FBFO to
FS[0:2],IF[0:3],FBDS[0:1] and FBFO to 2F[0:1],[1:2]DS[0:1],FBFO
Common Mode Range (VCOM) from VCC to VCC–0.2
Corrected typo TQFP to LQFP in Features
*C
124645
03/20/03
RGL
Corrected typo LQFP to TQFP in Features
*D
128464
07/25/03
RGL
Added clock input frequency (fin) specifications in the switching characteristics table.
Document #: 38-07336 Rev. *D
Page 10 of 10