ASAHI KASEI [AKD5393 Rev.A] AKD5393 Evaluation board Rev.A for AK5393 General description The AKD5393 is an evaluation board for the AK5393 professional audio 24bit A/D converter. The AKD5393 includes the input buffer circuit and also has a digital interface transmitter. Further, the AKD5393 can evaluate direct interface with AKM’s DAC evaluation boards. I Ordering guide AKD5393 Rev.A --- Evaluation board for AK5393VS Function • On-board Full-differential input buffer circuit • On-board clock generator • Compatible with 2 types of interface 1) Direct interface with AKM’s DAC evaluation boards. 2) On-board CS8402 as DIT which transmits optical output. • A BNC connector for an external clock input. +15V -15V +5V GND +3.3V CS8402 (DIT) Lch Input Rch Buffer Opt Out D/A Data AK5393 10pin Header Clock Generator * Circuit diagram and PCB layout are attached at the end of this manual. <KM059102> 2005/12 -1- ASAHI KASEI [AKD5393 Rev.A] I Input buffer circuit The AKD5393 includes full-differential input buffer circuit with an inverted-amp (gain: -10dB). The capacitor of 10nF between AIN+ /- decreases the clock feed through noise of modulator, and composes a 1st order LPF (fc=360kHz) with 22ohm resistor before the capacitor. This circuit also has a 1st order LPF (fc=370kHz) composed of op-amp. External analog signal can be fed through the BNC connector or the Cannon connector. 910 4.7k VP+ 4.7k Analog In + 8.1Vpp VP- 47µ 3k VA+ 22 + Bias 2.45Vpp AIN+ 910 NJM5532 47µ AK5393 470p 10n 470p 3k - VA=±5V 22 AIN- + VP=±15V 10k Bias Bias 2.45Vpp CAL + 10k 10µ 0.1µ "L" at self calibration ZCAL Figure 1. Full-differential input buffer circuit example 1: In case of using the BNC connector [JP2, JP3, JP4, JP5]: Short [R11, R18]: Open The resistor value of R10 and R19 should be properly selected in order to much the output impedance of the signal source. 2: In case of using the Cannon connector [JP2, JP3, JP4, JP5]: Open The resistor value of R10, R11, R18 and R19 should be properly selected in order to much the output impedance of the signal source. * AKM assumes no responsibility for the trouble when using the above circuit examples. I Power supply and Decoupling VA and VD supplies to the AK5393 are decoupled separately in order to minimize the effect of the digital noise. A system analog supply is fed to VA. VA and VD lines should be distributed separately from the power unit. Decoupling capacitors are connected to AK5393 as near as possible, particularly the ceramic capacitor to the VREFL/R pin. <KM059102> 2005/12 -2- ASAHI KASEI [AKD5393 Rev.A] I Operation sequence (1) Set up the power supply lines VP+=+15V, VP- = -15V, VA+=+5V, VD+=+3.3V∼5.25V, AGND=DGND=0V Each supply line should be distributed from the power unit. (2) Set up the evaluation modes and jumper pins. (See next item) There are many jumper pins to cover many evaluation modes. Please take care of setting. (3) Set up the DIP SW position for the DIT. (See next item) This does not affect AK5393 operation. (4) Power On. The AK5393 should be reset once by bringing PD "L"(SW4) upon power-up. (5) AK5393 can be reset by SW4 during operation. Lower position resets the device, and the upper position is for normal operation. Note: In any case of changing clocks during operation, the device should be reset by bringing PD "L". If not followed, the AK5393 may be destroyed since its internal logic uses dynamic circuit. I The evaluation modes and corresponding jumper pin settings. 1. Evaluation Mode Applicable Evaluation Mode 1-1 Using D/A converter board for the analog performance analysis. 1-2 DIT (Optical Link) [Default] 1-3 All interface signals (MCLK, BICK and LRCK) are fed from external circuit. 1-4 Feed all interface signals to the external circuit through PORT2. 1-1. Using D/A converter board for the analog performance analysis. The AK5393 can be evaluated by distortion analyzer using various AKM's D/A converter evaluation boards through PORT2. [Slave mode] JP9 LR JP12 JP7 JP11 BC EXT XTL XTE MCLK Figure 2. Jumper set up (D/A) <KM059102> 2005/12 -3- ASAHI KASEI [AKD5393 Rev.A] 1-2DIT (Optical Link) PORT1 is used. DIT generates audio Bi-phase signal from received data and which is output through optical connector (TOTX174). It is possible to connect AKM's D/A converter evaluation boards on the digital-amplifier, which equips DIR input. There are two kinds of jumper setting depend on the SMODE1 and SMODE2 pin. The interface signals are output from PORT2. (See the (4)). In case of using external clock through a BNC connector, select EXT on JP11 (MCLK) and short JP12 (XTE). [Slave mode] (Default) JP7 JP9 BC LR JP11 JP12 EXT XTL XTE MCLK [Master mode] JP9 LR JP7 BC JP11 JP12 EXT XTL XTE MCLK Figure 3. Jumper set up (DIT) 1-3 All interface signals (MCLK, BICK and LRCK) are fed from external circuit. [Slave mode] Under the following setup, MCLK, LRCK and SCLK signals needed for the A/D to operate could be Fed through PORT2. JP7 J P9 BC LR JP11 JP12 EXT XTL XTE M CLK Figure 4. Jumper set up (EXT) 1-4 Feed all interface signals to the external circuit through PORT2. [Master, Slave mode] Please set up as same as 1-2. All interfacing signal which drive AK5393 are output through PORT2. However, the FSYNC signal is input when the position of the SDATA is needed to be controlled. * Setting for double speed sampling (fs=96kHz) For the double speed sampling, DFS="L", MCLK=128fs, BICK=64fs(max) are required. So, when BICK and LRCK are created from 74HC4040 on the board, the crystal oscillator should be changed to 24.576MHz and set JP14 (MCLK2) to 128fs side (see the schematics). 2. BIT CLK (BCF) set up JP8 128 64 BCF [JP8] Either 64fs or 128fs for the BCF can be selected. Figure shows 128fs example. When DFS="H", set JP8 to 64 side. 128: 128fs is fed to AK5393 as BICK. 64: 64fs is fed to AK5393 as BICK. <KM059102> 2005/12 -4- ASAHI KASEI [AKD5393 Rev.A] 3. Jumper-set up and explanation Set up the CS8402's data format corresponding the serial data interface of the AK5393. AKD5393 Data Format Slave mode Mater mode I2S Slave mode I2S master mode SMODE2 (SW2-5) ON ON OFF OFF SMODE1 (SW2-4) ON OFF ON OFF 8402 (SW2-1) ON OFF OFF OFF BCF (JP6) F R R R LRP (JP10) H L H H *DIP-SW is ON=”L” OFF=”H” Table 1. Serial data interface of AK5393 and CS8402 [SW2-1]: CS8402's data format ON: MSB justified, 24bit OFF: IIS Compatible [JP6] : Define the polarity of SCLK. F: SCLK is inverted. R: SCLK coincides with AK5393 [JP10]: Define the polarity of LRCK. L: LRCK is inverted. H: LRCK coincides with AK5393. 4. The other function set up No. PIN ON OFF 1 8402 See the Table1. 2 DFS 48k 96k 3 HPFE disable enable Seethe Table 1. 4 SM1 5 SM2 6 CALMODE VCOM AIN Table 2. DIP-SW2 set-up *DIP-SW is ON=”L” OFF=”H” →Selects the sampling rate. →Selects HPF of AK5393. →Selects the reference signal for Offset-Cal of K5383 VCOM:VCOML,VCOMR pin AIN: Analog input pin (AINL±, AINR±) [JP13]: Selects the analog power supply source to VA pin of the AK5393. Open: Supply from the power supply terminal (VA+). Short: Supply from 3-terminal-voltage regulator (+5V) on the board. I The function of the toggle SW. [SW3] Resets the CS8402. Upper position resets the internal counter of CS8402, then Bi-phase signal is not output. Keep the "L" position during normal operation. [SW4] Resets the AK5393. Keep the "H" position during conversion. <KM059102> 2005/12 -5- ASAHI KASEI [AKD5393 Rev.A] I DIP switch set up. (Default is the consumer mode.). The DIP-SW1 sets the C-bit of CS8402. This set up does not affect the evaluation of the AK5383. In case of using DIT, need to set it up correctly. For more detailed configurations, please refer to the CS8402 datasheet. Switch OFF=0,ON=1 8 7,6 PRO = 0 C6 , C7 11 10 01 00 C9 1 0 C1 1 0 TRNPT 0 1 EM1,EM0 11 5 4 3 1,2 10 01 00 Contents Professional mode, C0=1 C6,C7 - Sampling frequency 00 - Not indicated. Receiver default to 48kHz. 01 - 48kHz 10 - 44.1kHz 11 - 32kHz C8,C9,C10,C11 - 1bit of channel mode 0000 - Mode not indicated. Receiver default to 2-channel mode. 0100 - Stereophonic. C1 - Audio mode 0 - Normal audio 1 - Not audio Transparent mode *CS8402 is CRE Normal mode Transparent mode C2,C3,C4 - Encoded audio signal emphasis 000 - Emphasis not indicated. Receiver defaults to no emphasis with manual override enable. 100 - None 110 - 50/15usec 111 - CCITT J.17 Table 3. DIP switch set up of CS8402 (Professional mode) Switch 8 7 Default 6 Default 5 Default 3,4 Default 1,2 Default OFF=0,ON=1 Contents PRO = 1 Consumer mode, C0=0 (Default) C2 C2 - Copy 1 0 - Copy inhibited 0 1 - Copy permitted C3 C3,C4,C5 - Pre-emphasis 1 000 - None 0 100 - 50/15usec C15 C15 - Generation Status 1 0 - See the standard 0 1 - See the standard FC1, FC0 C24,C25,C26,C27- Sampling frequency 0000 - 44.1kHz 00 0100 - 48kHz 01 1100 - 32kHz 10 0000 - 44.1kHz, CD mode 11 C8 , C9 C8-C14 - Category code 0000000 - General 11 0100000 - PCM encoder/decoder 10 1000000 - CD 01 1100000 - DAT 00 Table 4. DIP switch set up of CS8402 (Consumer mode) <KM059102> 2005/12 -6- ASAHI KASEI [AKD5393 Rev.A] AK5393 Measurement Result [Measurement condition] • Measurement unit : ROHDE & SCHWARZ, UPD04 • fs : 48kHz, 96kHz • BW : 20Hz∼20kHz (fs=48kHz), 40Hz∼40kHz (fs=96kHz) • Power Supply : AVDD=3.3V, DVDD=5V • Interface : DIT (fs=48kHz), Serial Multiplex (fs=96kHz) • Temperature : Room fs THD+N(-1dB) DR(-60dB) S/N 48kHz -106.1 114.0 117.2 114.0 117.2 unit [dB] 96kHz -106.0 -103.3 113.5 115.5 105.1 113.5 115.5 105.1 [dB] BW, filter 20Hz∼20kHz 40Hz∼40kHz 20Hz∼20kHz 20Hz∼20kHz , A-weighted 40Hz∼40kHz 20Hz∼20kHz 20Hz∼20kHz, A-weighted 40Hz∼40kHz Plot fs=48kHz Figure 1. FFT (Input Level = -1dB) Figure 2. FFT (Input Level = -60dB) Figure 3. FFT (Input Level =-120dB) Figure 4. FFT (Input =”0”data) Figure 5. THD+N vs Input Frequency (Input level=-1dB) Figure 6. THD+N vs Input Level (fin=1kHz) Figure 7. Linearity Figure 8. Frequency Response Figure 9. Crosstalk fs=96kHz Figure 10. FFT (Input Level = -1dB) Figure 11. FFT (Input Level = -60dB) Figure 12. FFT (Input Level =-120dB) Figure 13. FFT (Input =”0”data) Figure 14. THD+N vs Input Frequency (Input level=-1dB) Figure 15. THD+N vs Input Level (fin=1kHz) Figure 16. Linearity Figure 17. Frequency Response Figure 18. Crosstalk <KM059102> 2005/12 -8- ASAHI KASEI [AKD5393 Rev.A] AK5393(fs=48kHz) <KM059102> Fig. 1 FFT plot (Input Level = -1dB) Fig. 2 FFT plot (Input Level = -60dB) 2005/12 ASAHI KASEI [AKD5393 Rev.A] AK5393(fs=48kHz) Fig. 3 FFT plot (Input Level = -120dB) Fig. 4 <KM059102> FFT plot (Input = “0”data) 2005/12 ASAHI KASEI [AKD5393 Rev.A] AK5393(fs=48kHz) Fig. 5 THD+N vs. Input frequency ( Input level = -1dB) Fig. 6 <KM059102> THD+N vs. Input level (fin=1kHz) 2005/12 ASAHI KASEI [AKD5393 Rev.A] AK5393(fs=48kHz) Fig.7 Fig. 8 <KM059102> Linearity Frequency response 2005/12 ASAHI KASEI [AKD5393 Rev.A] AK5393(fs=48kHz) Fig. 9 <KM059102> Crosstalk 2005/12 ASAHI KASEI [AKD5393 Rev.A] AK5393(fs=96kHz) <KM059102> Fig.10 FFT plot (Input Level = -1dB) Fig.11 FFT plot (Input Level = -60dB) 2005/12 ASAHI KASEI [AKD5393 Rev.A] AK5393(fs=96kHz) Fig.12 FFT plot (Input Level = -120dB) Fig.13 <KM059102> FFT plot (Input = “0”data) 2005/12 ASAHI KASEI [AKD5393 Rev.A] AK5393(fs=96kHz) Fig.14 THD+N vs. Input frequency (Level = -1dB) Fig.15 <KM059102> THD+V vs. Input level (fin = 1kHz) 2005/12 ASAHI KASEI [AKD5393 Rev.A] AK5393(fs=96kHz) Fig.16 Fig.17 <KM059102> Linearity Frequency Response 2005/12 ASAHI KASEI [AKD5393 Rev.A] AK5393(fs=96kHz) Fig.18 <KM059102> Crosstalk 2005/12 ASAHI KASEI [AKD5393 Rev.A] Revision History Date (YY/MM/DD) 98/08/18 Manual Revision KM059100 00/05/29 KM059101 3 Circuit Change 05/12/06 KM059102 4 Circuit Change <KM059102> Board Reason Revision 0 First Edition Contents [1] Value Change: (1) Resistance: R1, R5, R13, R21: 1.5KOhmÆ 910Ohm (2) Resistance: R3, R8, R16, R22: 4.7KOhmÆ 3KOhm (3) Resistance: R4, R9, R17, R23: 51OhmÆ 22Ohm (4) Capacitance: C3, C13, C18, C26: 470pF Æ 110pF Æ 470pF (Re-change) (5) Capacitance: C6, C24: 2.2nF Æ 22nF Æ 10nF (Re-change) (6) Inductance: L1: Non-implement Æ Short [2] Remake to separate TEST pin from digital ground (1) Cut the pattern of digital ground connected to No.20 pin (TEST pin) of U5 (AK5393) on L1 layer, just in front of the pin. [3] Remake to change a part of pattern of digital ground to analog ground: (1) Cut the pattern of digital ground on L2 layer, at 2 points. (2) Connect the floating pattern to analog ground on L2 layer, by solder. [4] Remakes around OP-Amps of Input Buffers: (1) Cut the pattern between R1 (910Ohm) and R4 (22Ohm) around the OP-Amp U3 (NJM5532D). (2) Cut the pattern between R5 (910Ohm) and R9 (22Ohm) around the OP-Amp U3 (NJM5532D). (3) Cut the pattern between R13 (910Ohm) and R17 (22Ohm) around the OP-Amp U8 (NJM5532D). (4) Cut the pattern between R21 (910Ohm) and R23 (22Ohm) around the OP-Amp U8 (NJM5532D). (5) Connect R1 (910Ohm) to No.7 pin of OP-Amp U3 (NJM5532D). (6) Connect R5 (910Ohm) to No.1 pin of OP-Amp U3 (NJM5532D). (7) Connect R13 (910Ohm) to No.7 pin of OP-Amp U8 (NJM5532D). (8) Connect R21 (910Ohm) to No.1 pin of OP-Amp U8 (NJM5532D). [1] Value Change: (1) Capacitance: C55, C56: (Open) Æ 5p 2005/12 ASAHI KASEI [AKD5393 Rev.A] IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. <KM059102> 2005/12