AOSMD AOZ1036 Ezbuckâ ¢ 5a synchronous buck regulator Datasheet

AOZ1036
EZBuck™ 5A Synchronous Buck Regulator
General Description
Features
The AOZ1036 is a high efficiency, easy to use, 5A
synchronous buck regulator. The AOZ1036 works from
4.5V to 18V input voltage range, and provides up to 5A of
continuous output current with an output voltage
adjustable down to 0.8V.
z 4.5V to 18V operating input voltage range
The AOZ1036 comes in both a 5x4 DFN-8 and an
exposed pad SO-8 package and is rated over a
-40°C to +85°C ambient temperature range.
z
z Synchronous Buck: 55mΩ internal high-side switch
z
z
z
z
z
z
z
z
z
and 19mΩ Internal low-side switch
High efficiency: up to 95%
Internal soft start
Output voltage adjustable to 0.8V
5A continuous output current
Fixed 500kHz PWM operation
Cycle-by-cycle current limit
Pre-bias start-up
Short-circuit protection
Thermal shutdown
Thermally enhanced 5x4 DFN-8 and exposed pad
SO-8 packages
Applications
z Point of load DC/DC converters
z LCD TV
z Set top boxes
z DVD / Blu-ray players/recorders
z Cable modems
z PCIe graphics cards
Typical Application
VIN
C1
22µF
Ceramic
VIN
EN
L1
4.7µH
AOZ1036
R1
COMP
RC
CC
VOUT
LX
C2, C3
22µF
Ceramic
FB
AGND
PGND
R2
Figure 1. 3.3V 5A Synchronous Buck Regulator
Rev. 1.1 September 2010
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Page 1 of 17
AOZ1036
Ordering Information
Part Number
Ambient Temperature Range
AOZ1036DI
-40°C to +85°C
AOZ1036PI
Package
Environmental
5x4 DFN-8
Green Product
Exposed Pad SO-8
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
PGND
1
8
LX
PGND
1
7
LX
VIN
2
6
EN
AGND
3
5
COMP
FB
4
8
NC
7
NC
6
EN
5
COMP
LX
VIN
2
AGND
3
PAD
(LX)
GND
FB
4
5x4 DFN-8
Exposed Pad SO-8
(Top View)
(Top View)
Pin Description
Pin Number
5x4 DFN-8
Exposed
Pad SO-8
Pin Name
1
1
PGND
2
2
VIN
Supply voltage input. When VIN rises above the UVLO threshold the
device starts up.
3
3
AGND
Reference connection for controller section. Also used as thermal
connection for controller section. Electrically needs to be connected
to PGND.
4
4
FB
5
5
COMP
6
6
EN
7, 8
Pad
LX
PWM output connection to inductor.
7, 8
NC
No Connect. Pin 7 and 8 are not internally connected. Connect
these two pins externally to LX and use them for better thermal
performance.
Rev. 1.1 September 2010
Pin Function
Power ground. Electrically needs to be connected to AGND.
The FB pin is used to determine the output voltage via a resistor
divider between the output and GND.
External loop compensation pin.
The enable pin is active high. Connect it to VIN if not used and do
not leave it open.
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Page 2 of 17
AOZ1036
Block Diagram
VIN
UVLO
& POR
EN
Internal
+5V
5V LDO
Regulator
OTP
+
ISen
–
Reference
& Bias
Softstart
Q1
ILimit
+
+
0.8V
EAmp
FB
–
–
PWM
Comp
PWM
Control
Logic
+
Level
Shifter
+
FET
Driver
LX
Q2
COMP
+
0.2V
Short Circuit
Detection
Comparator
500kHz
Oscillator
–
AGND
Absolute Maximum Ratings
Recommended Operating Conditions
Exceeding the Absolute Maximum ratings may damage the
device.
Parameter
Supply Voltage (VIN)
The device is not guaranteed to operate beyond the Maximum
Recommended Operating Conditions.
Rating
Parameter
20V
LX to AGND
-0.7V to VIN+0.3V
LX to AGND
23V (<50ns)
EN to AGND
-0.3V to VIN+0.3V
FB to AGND
-0.3V to 6V
COMP to AGND
-0.3V to 6V
PGND to AGND
-0.3V to +0.3V
Junction Temperature (TJ)
+150°C
Storage Temperature (TS)
-65°C to +150°C
ESD Rating(1)
PGND
2.0kV
Supply Voltage (VIN)
Output Voltage Range
Ambient Temperature (TA)
Package Thermal Resistance (ΘJA)
5x4 DFN-8
Exposed Pad SO-8
Rating
4.5V to 18V
0.8V to VIN
-40°C to +85°C
50°C/W
50°C/W
Note:
2. The value of ΘJA is measured with the device mounted on 1-in2 FR-4
board with 2oz. Copper, in a still air environment with TA = 25°C. The
value in any given application depends on the user's specific board
design.
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5kΩ in series with 100pF.
Rev. 1.1 September 2010
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Page 3 of 17
AOZ1036
Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified. Specifications in BOLD indicate a temperature range of
-40°C to +85°C.
Symbol
VIN
Parameter
Conditions
Supply Voltage
Min.
Typ.
4.5
Max
Units
18
V
VUVLO
Input Under-voltage Lockout
Threshold
VIN rising
VIN falling
4.1
3.7
IIN
Supply Current (Quiescent)
IOUT = 0, VFB = 1.2V,
VEN >1.2V
1.6
2.5
mA
IOFF
Shutdown Supply Current
VEN = 0V
1
10
μA
VFB
Feedback Voltage
TA = 25°C
0.8
0.812
V
Load Regulation
0.5
%
Line Regulation
1
%
IFB
Feedback Voltage Input Current
VEN
EN input threshold
VHYS
0.788
V
V
Off threshold
On threshold
200
nA
0.6
V
V
2
EN Input hysteresis
100
mV
MODULATOR
fO
DMAX
Ton_min
Frequency
400
Maximum Duty Cycle
100
500
600
kHz
%
Minimum On Time
150
ns
Error Amplifier Voltage Gain
500
V/V
Error Amplifier Transconductance
200
μA / V
6.5
A
150
100
°C
°C
3
ms
PROTECTION
ILIM
Current Limit
Over-temperature Shutdown Limit
tSS
5.8
TJ rising
TJ falling
Soft Start Interval
OUTPUT STAGE
High-side Switch On-resistance
VIN = 12V
VIN = 5V
55
75
mΩ
Low-side Switch On-resistance
VIN = 12V
VIN = 5V
19
23
mΩ
Rev. 1.1 September 2010
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Page 4 of 17
AOZ1036
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
Light Load Operation
Full Load (CCM) Operation
Vin ripple
0.1V/div
Vin ripple
0.1V/div
Vo ripple
20mV/div
Vo ripple
20mV/div
IL
1A/div
IL
1A/div
VLX
10V/div
VLX
10V/div
1µs/div
2ms/div
Short Circuit Protection
Start Up to Full Load
Vin
10V/div
LX
10V/div
Vo
2V/div
Vo
2V/div
lin
1A/div
IL
2A/div
1ms/div
50µs/div
Short Circuit Recovery
LX
10V/div
Vo
2V/div
IL
2A/div
1ms/div
Rev. 1.1 September 2010
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Page 5 of 17
AOZ1036
Efficiency
Efficiency (VIN = 12V) vs. Load Current
100%
Efficiency (%)
90%
80%
70%
5V OUTPUT
60%
3.3V OUTPUT
1.8V OUTPUT
1.2V OUTPUT
50%
40%
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
4.5
5
Load Current (A)
Efficiency (VIN = 5V) vs. Load Current
100%
Efficiency (%)
90%
80%
70%
60%
3.3V OUTPUT
1.8V OUTPUT
50%
40%
1.2V OUTPUT
0
0.5
1
1.5
2
2.5
3
3.5
4
Load Current (A)
Rev. 1.1 September 2010
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Page 6 of 17
AOZ1036
Detailed Description
The AOZ1036 is a current-mode step down regulator
with integrated high-side PMOS switch and a low-side
NMOS switch. It operates from a 4.5V to 18V input
voltage range and supplies up to 5A of load current.
Features include enable control, Power-On Reset, input
under voltage lockout, output over voltage protection,
active high power good state, fixed internal soft-start and
thermal shut down.
The AOZ1036 comes in both a 5x4 DFN-8 and an
exposed pad SO-8 package.
Enable and Soft Start
The AOZ1036 has internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.1V and voltage
on EN pin is HIGH. In soft start process, the output
voltage is ramped to regulation voltage in typically 3ms.
The 3ms soft start time is set internally.
The EN pin of the AOZ1036 is active high. Connect the
EN pin to VIN if enable function is not used. Pull it to
ground will disable the AOZ1036. Do not leave it open.
The voltage on EN pin must be above 2V to enable the
AOZ1036. When voltage on EN pin falls below 0.6V, the
AOZ1036 is disabled. If an application circuit requires the
AOZ1036 to be disabled, an open drain or open collector
circuit should be used to interface to EN pin.
Steady-State Operation
Under steady-state conditions, the converter operates
in fixed frequency and Continuous-Conduction Mode
(CCM).
The AOZ1036 integrates an internal P-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the
internal transconductance error amplifier. The error
voltage, which shows on the COMP pin, is compared
against the current signal, which is sum of inductor
current signal and ramp compensation signal, at PWM
comparator input. If the current signal is less than the
error voltage, the internal high-side switch is on. The
inductor current flows from the input through the inductor
to the output. When the current signal exceeds the error
voltage, the high-side switch is off. The inductor current is
Rev. 1.1 September 2010
freewheeling through the internal low-side N-MOSFET
switch to output. The internal adaptive FET driver
guarantees no turn on overlap of both high-side and
low-side switch.
Comparing with regulators using freewheeling Schottky
diodes, the AOZ1036 uses freewheeling NMOSFET to
realize synchronous rectification. It greatly improves the
converter efficiency and reduces power loss in the
low-side switch.
The AOZ1036 uses a P-Channel MOSFET as the
high-side switch. It saves the bootstrap capacitor
normally seen in a circuit which is using an NMOS
switch.
Switching Frequency
The AOZ1036 switching frequency is fixed and set by an
internal oscillator. The practical switching frequency
could range from 400kHz to 600kHz due to device
variation.
Light Load Mode
The AOZ1036 includes is a Pulse-Skip architecture for
Light Load operation, enabling increased efficiency
during standby. Under Heavy Loads, the controller
operates in a standard Synchronous Mode using the
high-side PMOS as control FET and low-side NMOS as
synchronous rectifier NMOS. During Light Loads, the
controller automatically switches to a Non-Synchronous
mode using the high-side PMOS as control FET and the
integrated diode as freewheeling rectifier diode.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin by using a resistor divider network. In the
application circuit shown in Figure 1. The resistor divider
network includes R1 and R2. Usually, a design is started
by picking a fixed R2 value and calculating the required
R1 with equation below.
R 1⎞
⎛
V O = 0.8 × ⎜ 1 + -------⎟
R 2⎠
⎝
Some standard value of R1, R2 and most used output
voltage values are listed in Table 1 on the next page.
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Page 7 of 17
AOZ1036
Thermal Protection
Table 1.
Vo (V)
R1 (kΩ)
R2 (kΩ)
0.8
1.0
Open
1.2
4.99
10
1.5
10
11.5
1.8
12.7
10.2
2.5
21.5
10
3.3
31.1
10
5.0
52.3
10
Application Information
The basic AOZ1036 application circuit is show in
Figure 1. Component selection is explained below.
The combination of R1 and R2 should be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
Protection Features
The AOZ1036 has multiple protection features to prevent
system circuit damage under abnormal conditions.
Over Current Protection (OCP)
The sensed inductor current signal is also used for over
current protection. Since the AOZ1036 employs peak
current mode control, the COMP pin voltage is
proportional to the peak inductor current. The COMP pin
voltage is limited to be between 0.4V and 2.5V internally.
The peak inductor current is automatically limited cycle
by cycle.
When the output is shorted to ground under fault
conditions, the inductor current decays very slow during
a switching cycle because of VO = 0V. To prevent
catastrophic failure, a secondary current limit is designed
inside the AOZ1036. The measured inductor current is
compared against a preset voltage which represents the
current limit, between 3.5A and 5.0A. When the output
current is more than current limit, the high side switch will
be turned off. The converter will initiate a soft start once
the over-current condition disappears.
Power-On Reset (POR)
A power-on reset circuit monitors the input voltage.
When the input voltage exceeds 4.1V, the converter
starts operation. When input voltage falls below 3.7V,
the converter will be shut down.
Rev. 1.1 September 2010
An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit and
high side PMOS if the junction temperature exceeds
150ºC. The regulator will restart automatically under the
control of soft-start circuit when the junction temperature
decreases to 100ºC.
Input Capacitor
The input capacitor must be connected to the VIN pin and
PGND pin of AOZ1036 to maintain steady input voltage
and filter out the pulsing input current. The voltage rating
of input capacitor must be greater than maximum input
voltage plus ripple voltage.
The input ripple voltage can be approximated by the
equation below:
VO ⎞ VO
IO
⎛
ΔV IN = ----------------- × ⎜ 1 – ---------⎟ × --------f × C IN ⎝
V IN⎠ V IN
Since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another
concern when selecting the capacitor. For a
buck circuit, the RMS value of input capacitor current
can be calculated by:
VO ⎛
VO ⎞
- ⎜1 – --------⎟
I CIN_RMS = I O × -------V IN ⎝ V IN ⎠
if we let m equal the conversion ratio:
VO
-------- = m
V IN
The relation between the input capacitor RMS current
and voltage conversion ratio is calculated and shown in
Figure 2 on the next page. It can be seen that when VO is
half of VIN, CIN is under the worst current stress. The
worst current stress on CIN is 0.5 x IO.
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Page 8 of 17
AOZ1036
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor need to be checked for
thermal and efficiency requirements.
0.5
0.4
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
ICIN_RMS(m) 0.3
IO
0.2
Output Capacitor
0.1
0
0
0.5
m
1
Figure 2. ICIN vs. Voltage Conversion Ratio
For reliable operation and best performance, the input
capacitors must have current rating higher than ICIN_RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high current rating. Depending on the application
circuits, other low ESR tantalum capacitor may also be
used. When selecting ceramic capacitors, X5R or X7R
type dielectric ceramic capacitors should be used for
their better temperature and voltage characteristics. Note
that the ripple current rating from capacitor manufactures
are based on certain amount of life time. Further derating may be necessary in practical design.
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be
considered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
1
ΔV O = ΔI L × ⎛ ESR CO + -------------------------⎞
⎝
8×f×C ⎠
O
Inductor
where;
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
CO is output capacitor value, and
VO ⎛
VO ⎞
-⎟
ΔI L = ----------- × ⎜1 – -------f × L ⎝ V IN ⎠
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
1
ΔV O = ΔI L × ------------------------8×f×C
The peak inductor current is:
ΔI L
I Lpeak = I O + -------2
O
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on inductor is designed to be 20%
to 30% of output current.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
Rev. 1.1 September 2010
ESRCO is the Equivalent Series Resistor of output capacitor.
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
ΔV O = ΔI L × ESR CO
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum are recommended
to be used as output capacitors.
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Page 9 of 17
AOZ1036
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current.
It can be calculated by:
ΔI L
I CO_RMS = ---------12
G EA
f P2 = ------------------------------------------2π × C C × G VEA
where;
Usually, the ripple current rating of the output capacitor
is a smaller issue because of the low current stress.
When the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
External Schottky Diode for High Input Operation
When VIN is higher than 16V, an external 1A schottky
diode is required between LX and PGND for proper
operation.
Loop Compensation
The AOZ1036 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole can be
calculated by:
1
f P1 = ----------------------------------2π × C O × R L
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
1
f Z1 = -----------------------------------------------2π × C O × ESR CO
GEA is the error amplifier transconductance, which is
200 x 10-6 A/V,
GVEA is the error amplifier voltage gain, which is 500 V/V, and
CC is compensation capacitor in Figure 1.
The zero given by the external compensation network,
capacitor CC and resistor RC, is located at:
1
f Z2 = ----------------------------------2π × C C × R C
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The system
crossover frequency is where control loop has unity gain.
The crossover is the also called the converter bandwidth.
Generally a higher bandwidth means faster response to
load transient. However, the bandwidth should not be too
high because of system stability concern. When
designing the compensation loop, converter stability
under all line and load condition must be considered.
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency. The
AOZ1036 operates at a frequency range from 400kHz to
600kHz. It is recommended to choose a crossover
frequency equal or less than 40kHz.
f C = 40kHz
The strategy for choosing RC and CC is to set the
cross over frequency with Rc and set the compensator
zero with CC. Using selected crossover frequency, fC,
to calculate RC:
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
The compensation design is actually to shape the
converter control loop transfer function to get desired
gain and phase. Several different types of compensation
network can be used for the AOZ1036. For most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ1036, FB pin and COMP pin are the inverting
input and the output of internal error amplifier. A series
Rev. 1.1 September 2010
R and C compensation network connected to COMP
provides one pole and one zero. The pole is:
VO
2π × C C
R C = f C × ---------- × ----------------------------V
G ×G
FB
EA
CS
where;
fC is desired crossover frequency. For best performance,
fC is set to be about 1/10 of switching frequency,
VFB is 0.8V,
GEA is the error amplifier transconductance, which is
200 x 10-6 A/V, and
GCS is the current sense circuit transconductance, which is
6.68 A/V.
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Page 10 of 17
AOZ1036
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of selected
crossover frequency. CC can is selected by:
1.5
C C = ----------------------------------2π × R C × f P1
The actual junction temperature can be calculated with
power dissipation in the AOZ1036 and thermal
impedance from junction to ambient.
T junction = ( P total_loss – P inductor_loss ) × Θ JA
The maximum junction temperature of AOZ1036 is
150ºC, which limits the maximum load current capability.
Please see the thermal de-rating curves for maximum
load current of the AOZ1036 under different ambient
temperature.
The equation above can also be simplified to:
CO × RL
C C = --------------------RC
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
The thermal performance of the AOZ1036 is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC will
operate under the recommended environmental
conditions.
Thermal Management and Layout
Consideration
Several layout tips are listed below for the best electric
and thermal performance.
In the AOZ1036 buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the
LX pin, to the filter inductor, to the output capacitor
and load, and then return to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the low side NMOSFET.
Current flows in the second loop when the low side
NMOSFET is on.
1. The LX pins are connected to internal PFET and
NFET drains. They are low resistance thermal
conduction path and most noisy switching node.
Connected a large copper plane to LX pin to help
thermal dissipation.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input
capacitor, output capacitor, and PGND pin of the
AOZ1036.
In the AOZ1036 buck regulator circuit, the major power
dissipating components are the AOZ1036 and the output
inductor. The total power dissipation of converter circuit
can be measured by input power minus output power.
P total_loss = V IN × I IN – V O × I O
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor.
2. Do not use thermal relief connection to the VIN and
the PGND pin. Pour a maximized copper area to the
PGND pin and the VIN pin to help thermal
dissipation.
3. Input capacitor should be connected to the VIN pin
and the PGND pin as close as possible.
4. A ground plane is preferred. If a ground plane is not
used, separate PGND from AGND and connect them
only at one point to avoid the PGND pin noise
coupling to the AGND pin.
5. Make the current trace from LX pins to L to Co to the
PGND as short as possible.
6. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or
VOUT.
7. Keep sensitive signal trace far away from the LX
pins.
P inductor_loss = IO2 × R inductor × 1.1
Rev. 1.1 September 2010
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Page 11 of 17
AOZ1036
Package Dimensions, 5x4 DFN-8
D
A
Pin #1 IDA
D/2
B
e
1
L
E/2
R
aaa C
E
E3
E2
Index Area
(D/2 x E/2)
D2
aaa C
TOP VIEW
D3
L1
BOTTOM VIEW
ccc C
A3
Seating C
Plane
A
ddd C
A1
b
bbb
CAB
SIDE VIEW
Dimensions in millimeters
Symbols
A
A1
A3
b
D
D2
D3
E
E2
E3
e
L
L1
R
aaa
bbb
ccc
ddd
RECOMMENDED LAND PATTERN
UNIT: mm
Min.
0.80
0.00
0.35
1.975
1.625
2.500
2.050
0.600
0.400
–
–
–
–
Nom.
0.90
0.02
0.20 REF
0.40
5.00 BSC
2.125
1.775
4.00 BSC
2.650
2.200
0.95 BSC
0.700
0.500
0.30 REF
0.15
0.10
0.10
0.08
Max.
1.00
0.05
0.45
2.225
1.875
2.750
2.300
0.800
0.600
–
–
–
–
Dimensions in inches
Symbols
A
A1
A3
b
D
D2
D3
E
E2
E3
e
L
L1
R
aaa
bbb
ccc
ddd
Min.
0.031
0.000
Nom. Max.
0.035 0.039
0.001 0.002
0.008 REF
0.014 0.016 0.018
0.197 BSC
0.078 0.084 0.088
0.064 0.070 0.074
0.157 BSC
0.098 0.104 0.108
0.081 0.087 0.091
0.037 BSC
0.024 0.028 0.031
0.016 0.020 0.024
0.012 REF
–
0.006
–
–
0.004
–
–
0.004
–
–
0.003
–
Notes:
1. Dimensions and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters.
3. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SP-002.
4. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the
optional radius on the other end of the terminal, the dimension b should not be measured in that radius area.
5. Coplanarity applies to the terminals and all other bottom surface metallization.
6. Drawing shown are for illustration only.
Rev. 1.1 September 2010
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Page 12 of 17
AOZ1036
Tape Dimensions, 5x4 DFN-8
Tape
R0
20
0.
.40
T
D1
E1
E2
D0
E
B0
Feeding
Direction
K0
P0
A0
UNIT: mm
Package
DFN 5x4
(12 mm)
A0
5.30
±0.10
B0
4.30
±0.10
K0
D0
D1
E
E1
E2
P0
P1
P2
T
1.20
±0.10
1.50
Min.
Typ.
1.50
+0.10 / –0
12.00
±0.30
1.75
±0.10
5.50
±0.10
8.00
±0.10
4.00
±0.20
2.00
±0.10
0.30
±0.05
Leader/Trailer and Orientation
Trailer Tape
300mm Min.
Rev. 1.1 September 2010
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm Min.
Page 13 of 17
AOZ1036
Reel Dimensions, 5x4 DFN-8
II
R1
59
Reel
I
R1
6.0±1
21
M
R1
27
I
Zoom In
R6
R1
P
R5
5
B
W1
III
Zoom In
Tape Size
Reel Size
M
W1
B
P
ø330
12.40
0.5
+0.3
-4.0
+2.0
-0.0
2.40
±0.3
3-1.8
0.05
12mm
ø330
II
.9
±0
.
"
A A
N=ø100±2
ø9
6±
0.2
05
ø1
/4
A
ø2
3-
3-
3-ø1
/8"
Zoom In
1.8
6.0
1.8
6.45±0.05
8.00
6.2
ø2
2.20
1.
8.9±0.1
14 REF
0
ø90.0
20
0
R1.10
R3.10
2.00
5.0
C
1.8
12 REF
11.90
ø86
.0±0
.1
10°
41.5 REF
43.00
44.5±0.1
44.5±0.1
R3
.95
4.0
6.10
VIEW: C
3-
8.0±0.1
ø3
"
16
ø3
/
3-
38°
40°
10.0
8R
EF
46.0±0.1
R0.5
3.3
6.50
R4
R1
ø13.0
ø17.0
A
0.00
-0.05
/1
2.00
6.50
0.80
3.00
2.5
1.80
+0.05
6"
8.000.00
10.71
6°
Rev. 1.1 September 2010
www.aosmd.com
Page 14 of 17
AOZ1036
Package Dimensions, Exposed Pad SO-8
Gauge plane
0.2500
D0
C
L
L1
E2
E1
E3
E
L1'
D1
Note 5
D
θ
7° (4x)
A2
e
B
A
A1
Dimensions in millimeters
Symbols
A
A1
A2
B
C
Min.
1.40
0.00
1.40
0.31
0.17
Nom.
1.55
0.05
1.50
0.406
—
Max.
1.70
0.10
1.60
0.51
0.25
Symbols
A
A1
A2
B
C
Min.
0.055
0.000
0.055
0.012
0.007
Nom.
0.061
0.002
0.059
0.016
—
Max.
0.067
0.004
0.063
0.020
0.010
D
D0
D1
E
4.80
3.20
3.10
5.80
4.96
3.40
3.30
6.00
5.00
3.60
3.50
6.20
D
D0
D1
E
e
E1
E2
E3
—
3.80
2.21
1.27
—
3.90
4.00
2.41
2.61
0.40 REF
e
E1
E2
E3
0.189
0.126
0.122
0.228
—
0.195
0.134
0.130
0.236
0.050
0.197
0.142
0.138
0.244
—
0.80
L
y
θ
UNIT: mm
| L1–L1' |
0.40
—
0°
—
RECOMMENDED LAND PATTERN
3.70
2.20
5.74
2.71
2.87
1.27
0.635
Dimensions in inches
L1
0.95
—
3°
0.04
1.27
0.10
8°
0.12
1.04 REF
L
y
θ
| L1–L1' |
L1
0.150
0.087
0.153 0.157
0.095 0.103
0.016 REF
0.016 0.037 0.050
—
0°
—
—
0.004
3°
8°
0.002 0.005
0.041 REF
Notes:
1. Package body sizes exclude mold flash and gate burrs.
2. Dimension L is measured in gauge plane.
3. Tolerance 0.10mm unless otherwise specified.
4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
5. Die pad exposure size is according to lead frame design.
6. Followed from JEDEC MS-012
Rev. 1.1 September 2010
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Page 15 of 17
AOZ1036
Tape and Reel Dimensions, Exposed Pad SO-8
Carrier Tape
P1
D1
P2
T
E1
E2
E
B0
K0
A0
D0
P0
Feeding Direction
UNIT: mm
Package
SO-8
(12mm)
A0
6.40
±0.10
B0
5.20
±0.10
K0
2.10
±0.10
D0
1.60
±0.10
D1
1.50
±0.10
E
12.00
±0.10
Reel
E1
1.75
±0.10
E2
5.50
±0.10
P0
8.00
±0.10
P1
4.00
±0.10
P2
2.00
±0.10
T
0.25
±0.10
W1
S
G
N
M
K
V
R
H
W
UNIT: mm
W
N
Tape Size Reel Size
M
12mm
ø330
ø330.00 ø97.00 13.00
±0.10 ±0.30
±0.50
W1
17.40
±1.00
H
K
ø13.00
10.60
+0.50/-0.20
S
2.00
±0.50
G
—
R
—
V
—
Leader/Trailer and Orientation
Trailer Tape
300mm min. or
75 empty pockets
Rev. 1.1 September 2010
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm min. or
125 empty pockets
Page 16 of 17
AOZ1036
Part Marking
5x4 DFN-8
Z1036DI
FAYWLT
Part Number Code
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
Exposed Pad SO-8
Z1036PI
FAYWLT
Part Number Code
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
This datasheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 1.1 September 2010
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Page 17 of 17