a Parallel-Port 16-Bit SoundPort Stereo Codec AD1848K FEATURES Single-Chip Integrated ∑∆ Digital Audio Stereo Codec Supports the Microsoft Windows Sound System® Multiple Channels of Stereo Input Analog and Digital Signal Mixing Programmable Gain and Attenuation On-Chip Signal Filters Digital Interpolation Analog Output Low-Pass Sample Rates from 5.5 kHz to 48 kHz 68-Lead PLCC and 68-Lead TQFP Packages Operation from +5 V Supplies Byte-Wide Parallel Interface to ISA and EISA Buses Supports One or Two DMA Channels and Programmed I/O PRODUCT OVERVIEW The Parallel-Port AD1848K SoundPort® Stereo Codec integrates the key audio data conversion and control functions into a single integrated circuit. The AD1848K is intended to provide a complete, single-chip audio solution for business audio and multimedia applications requiring operation from a single +5 V supply. It provides a direct, byte-wide interface to both ISA (“AT”) and EISA computer buses for simplified implementation on a computer motherboard or add-in card. The AD1848K generates enable and direction controls for IC buffers such as 74_245. The AD1848K SoundPort Stereo Codec supports a DMA request/grant architecture for transferring data with the host computer bus. One or two DMA channels can be supported. Programmed I/O (PIO) mode is also supported for control register accesses and for applications lacking DMA control. Two input control lines support mixed direct and indirect addressing of twenty-one internal control registers over this asynchronous interface. External circuit requirements are limited to a minimal number of low cost support components. Anti-imaging DAC output filters are incorporated on-chip. Dynamic range exceeds 80 dB over the 20 kHz audio band. Sample rates from 5.5 kHz to 48 kHz are supported from external crystals. The Codec includes a stereo pair of ∑∆ analog-to-digital converters and a stereo pair of ∑∆ digital-to-analog converters. Inputs to the ADC can be selected from four stereo pairs of (Continued on page 9) SoundPort is a registered trademark of Analog Devices, Inc. FUNCTIONAL BLOCK DIAGRAM ANALOG SUPPLY DIGITAL SUPPLY CRYSTALS 2 ANALOG POWER DOWN 2 DIGITAL L_LINE R_LINE OSCILLATORS L GAIN 20 dB L_MIC R_MIC ∑∆ A/D CONVERTER 16 µ/ A L A W MUX R GAIN L_AUX1 R_AUX1 ∑∆ A/D CONVERTER 16 DIGITAL MIX PLAYBACK REQ P A R A L L E L PLAYBACK ACK CAPTURE REQ CAPTURE ACK 2 8 GAIN/ATTEN/MUTE L ∑ L_OUT R_OUT L_AUX2 R_AUX2 ∑ R ATTEN/ MUTE ATTEN/ MUTE GAIN/ATTEN/MUTE ANALOG FILTER ANALOG FILTER ∑∆ D/A CONVERTER ∑∆ D/A CONVERTER REFERENCE INTERPOL INTERPOL ATTENUATE ATTENUATE ∑ ∑ µ/ A L A W CONTROL REGS P O R T ADR1:0 DATA7:0 CS WR RD 2 BUS DRIVER CONTROL HOST DMA INTERRUPT 2 EXTERNAL CONTROL 2.25V REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD1848K–SPECIFICATIONS STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature Digital Supply (VDD) Analog Supply (VCC) Word Rate (FS) Input Signal Analog Output Passband ADC FFT Size DAC FFT Size VIH VIL VOH VOL 25 5.0 5.0 48 1008 20 Hz to 20 kHz 2048 8192 2.4 0.8 2.4 0.4 DAC Input Conditions Post-Autocalibrated 0 dB Attenuation –2.0 dB Relative to Full Scale 16-Bit Linear Mode No Output Load Mute Off °C V V kHz Hz ADC Input Conditions Post-Autocalibrated 0 dB Gain –3.0 dB Relative to Full Scale Line Input 16-Bit Linear Mode V V V V ANALOG INPUT Min Input Voltage (RMS Values Assume Sine Wave Input) Line 2.6 Mic with +20 dB Gain (MGE = 1) 0.26 Mic with 0 dB Gain (MGE = 0) Input Impedance Input Capacitance 2.6 20 Typ 1 2.8 0.1 0.28 1 2.8 Max Units 15 V rms V p-p V rms V p-p V rms V p-p kΩ pF 3.0 0.3 3.0 PROGRAMMABLE GAIN AMPLIFIER—ADC Step Size (0 dB to 22.5 dB) (All Steps Tested, –30 dB Input) PGA Gain Range Span* Min Typ Max Units 1.3 1.5 1.7 dB 21.5 22.5 23.5 dB Min Typ Max Units 1.3 1.5 1.7 dB 45.5 46.5 47.5 dB AUXILIARY INPUT ANALOG AMPLIFIERS/ATTENUATORS Step Size (+12.0 dB to –33.0 dB) (All Steps Tested, –14.5 dB Input) Auxiliary Gain/Attenuation Range Span* –2– REV. 0 AD1848K DIGITAL DECIMATION AND INTERPOLATION FILTERS* Passband Passband Ripple Transition Band Stopband Stopband Rejection Group Delay Group Delay Variation Over Passband Min Max Units 0 0.45 3 FS ± 0.1 0.55 3 FS ∞ Hz dB Hz Hz dB 0.45 3 FS 0.55 3 FS 74 30/FS 0.0 µs ANALOG-TO-DIGITAL CONVERTERS Min Resolution (No Missing Codes from ± 10 LSB Ramp Around Midscale)* Dynamic Range (–60 dB Input, THD+N Referenced to Full Scale) THD+N (Referenced to Full Scale) 80 Typ Max Units 16 Bits 86 dB –77 Signal-to-Intermodulation Distortion* ADC Crosstalk* Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) Line to MIC (Input LINE, Ground and Select MIC, Read Both Channels) Line to AUX1 Line to AUX2 Gain Error (Full-Scale Span Relative to Nominal) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error 0.022 –73 90 % dB dB –80 dB –80 dB –80 –80 ±5 ± 0.5 dB dB % dB 50 LSBs Max Units DIGITAL-TO-ANALOG CONVERTERS Resolution* Dynamic Range (–60 dB Input, THD+N Referenced to Full Scale) THD+N (Referenced to Full Scale) Min Typ 80 16 87 –76 Signal-to-Intermodulation Distortion* Gain Error (Full-Scale Span Relative to Nominal) Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk* (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT) Total Out-of-Band Energy* (Measured from 0.55 × FS to 100 kHz) Audible Out-of-Band Energy* (Measured from 0.55 × FS to 22 kHz, All Selectable Sampling Frequencies) *Guaranteed Not Tested. Specifications subject to change without notice. REV. 0 –3– Bits dB 0.02 –74 90 ±5 ± 0.5 % dB dB % dB –80 dB –45 dB –70 dB AD1848K DAC ATTENUATOR Step Size (0 dB to –34.5 dB) Step Size (–60 dB to –94.5 dB)* Output Attenuation Range Span* Min Typ Max Units 1.3 1.0 93.5 1.5 1.5 94.5 1.7 2.0 95.5 dB dB dB Min Typ Max Units 1.85 0.707 2.0 ANALOG OUTPUT Full-Scale Output Voltage Output Impedance External Load Impedance Output Capacitance External Load Capacitance VREF VREF Current Drive VREF Output Impedance Mute Attenuation of 0 dB Fundamental* (OUT) Mute Click (|Muted Output Minus Unmuted Midscale DAC Output|) –80 Vrms V p-p Ω kΩ pF pF V µA kΩ dB 5 mV Max Units 1.0 dB ±1 5 Bit Degrees 2.1 600 10 2.10 15 100 2.40 2.25 100 4 SYSTEM SPECIFICATIONS Min Typ Peak-to-Peak Frequency Response Ripple* (Line In to Line Out) Differential Nonlinearity* Phase Linearity Deviation* STATIC DIGITAL SPECIFICATIONS High Level Input Voltage (VIH) Digital Inputs XTAL1/2I Low Level Input Voltage (VIL) High Level Output Voltage (VOH) at IOH = –2 mA Low Level Output Voltage (VOL) at IOL = 2 mA Input Leakage Current (GO/NOGO Tested) Output Leakage Current (GO/NOGO Tested) –4– Min Max Units 2.4 2.4 –0.3 2.4 (VD+) + 0 3 (VD+) + 0 3 0.8 –10 0.4 10 V V V V V µA –10 10 µA REV. 0 AD1848K TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE AND V DD = VCC = 5.0 V 65%) Min WR/RD Strobe Width (tSTW) WR/RD Rising to WR/RD Falling (tBWND) Write Data Setup to WR Rising (tWDSU) RD Falling to Valid Read Data (tRDDV) CS Setup to WR/RD Falling (tCSSU) CS Hold from WR/RD Rising (tCSHD) Adr Setup to WR/RD Falling (tADSU) Adr Hold from WR/RD Rising (tADHD) DAK Rising to WR/RD Falling (tSUDK1) DAK Falling to WR/RD Rising (tSUDK2) DAK Setup to WR/RD Falling (tDKSU) Data Hold from RD Rising (tDHD1) Data Hold from WR Rising (tDHD2) DRQ Hold from WR/RD Falling (tDRHD) DAK Hold from WR Rising (tDKHDa) DAK Hold from RD Rising (tDKHDb) DBEN/DBDIR delay from WR/RD Falling (tDBDL) 110 110 22 30 10 0 10 10 60 0 25 0 15 0 50 50 0 Max Units 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min Max Units 4.75 4.75 5.25 5.25 120 V V mA 65 55 1 1 600 mA mA mA mA mW 10 mW dB FS Max Units 27 ± 10 MHz % 70 90 ms ms 70 20 25 POWER SUPPLY Power Supply Range – Analog Power Supply Range – 5 V Digital Power Supply Current – 5 V Operating (5 V Supplies, 10 kΩ Load) Analog Supply Current – 5 V Operating (10 kΩ Load) Digital Supply Current – 5 V Operating (10 kΩ Load) Digital Power Supply Current – Power Down Analog Power Supply Current – Power Down Power Dissipation – 5 V Operating (Current • Nominal Supplies) Power Dissipation – Power Down (Current • Nominal Supplies) Power Supply Rejection (100 mV p-p Signal @ 1 kHz)* (At Both Analog and Digital Supply Pins, Both ADCs and DACs) 40 CLOCK SPECIFICATIONS* Min Input Clock Frequency Recommended Clock Duty Cycle Tolerance Initialization Time 16.9344 MHz Crystal Selected 24.576 MHz Crystal Selected *Guaranteed, not tested Specifications subject to change without notice. REV. 0 –5– AD1848K ORDERING GUIDE ABSOLUTE MAXIMUM RATINGS* Min Power Supplies Digital (VDD) Analog (VCC) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature ESD Tolerance (Human Body Model per Method 3015.2 of MIL-STD-883B) Max Units –0.3 –0.3 6.0 6.0 V V –0.3 –0.3 –40 –65 ± 10.0 (VA+) + 0.3 (VD+) + 0.3 +85 +150 mA V V °C °C 1000 Model Temperature Range Package Description Package Option AD1848KP AD1848KST –40°C to +85°C –40°C to +85°C 68-Lead PLCC 64-Lead TQFP P-68A ST-64 V *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1848K features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. DBDIR 53 52 DBEN DATA7 54 51 50 49 GNDD 56 55 DATA6 DATA5 57 DATA4 GNDD 59 58 V DD DATA2 DATA1 61 60 DATA3 64 63 62 68 67 66 65 64 63 62 61 DATA0 GNDD V DD ADR1 DBDIR ESD SENSITIVE DEVICE 64-Lead Thin Quad Flatpack Pinout WR DBEN DATA7 1 GNDD 2 DATA6 3 DATA5 4 DATA4 GNDD 5 VDD 6 DATA2 7 DATA3 8 DATA0 VDD 9 DATA1 ADR1 GNDD 68-Lead Plastic Leaded Chip Carrier Pinout WARNING! ADR0 10 60 RD ADR0 1 48 WR CDAK 11 59 CS CDAK 2 47 RD CDRQ 12 58 XCTL1 CDRQ 3 46 CS PDAK 13 57 INT PDAK 4 45 XCTL1 PDRQ 14 56 XCTL0 PDRQ 5 44 INT V DD 6 43 XCTL0 GNDD 7 42 NC XTAL1I 8 XTAL1O 9 VDD 15 55 NC 54 V DD GNDD 16 XTAL1I 17 53 GNDD AD1848K XTAL1O 18 VDD 19 52 NC 51 NC TOP VIEW GNDD 20 50 NC XTAL2I 21 49 XTAL2O 22 48 NC PWRDWN 23 47 NC VDD 24 46 NC GNDD 25 45 VDD R_FILT 26 41 V DD 40 GNDD V DD 10 39 NC 11 38 NC XTAL2I 12 37 NC XTAL2O 13 36 V DD GNDD NC AD1848K PWRDWN TOP VIEW 14 35 GNDD V DD 15 34 R_AUX2 GNDD 16 33 R_AUX1 –6– L_OUT 32 R_OUT 30 31 L_AUX1 L_AUX2 28 29 GNDA V CC V CC 25 26 27 GNDA V REF (2.25V) 23 24 VREF _F (BYPASS) NC = NO CONNECT 21 22 L_FILT L_MIC 20 L_LINE 19 R_MIC R_AUX2 17 18 R_FILT 43 R_LINE 41 42 R_OUT L_OUT L_AUX1 L_AUX2 VCC GNDA VCC GNDA VREF (2.25V) VREF_F (BYPASS) NC = NO CONNECT L_FILT L_MIC L_LINE R_MIC R_LINE 27 28 29 30 31 32 33 34 35 36 37 38 39 40 R_AUX1 44 GNDD REV. 0 AD1848K PIN DESCRIPTION Parallel Interface Pin Name PLCC TQFP I/O Description CDRQ 12 3 O Capture Data Request. The assertion of this signal indicates that the Codec has a captured audio sample from the ADC ready for transfer. This signal will remain asserted until all the bytes from the capture buffer have been transferred. CDAK 11 2 I Capture Data Acknowledge. The assertion of this active LO signal indicates that the RD cycle occurring is a DMA read from the capture buffer. PDRQ 14 5 O Playback Data Request. The assertion of this signal indicates that the Codec is ready for more DAC playback data. The signal will remain asserted until all the bytes needed for a playback sample have been transferred. PDAK 13 4 I Playback Data Acknowledge. The assertion of this active LO signal indicates that the WR cycle occurring is a DMA write to the playback buffer. ADR1:0 9 & 10 1 & 64 I Codec Addresses. These address pins are asserted by the Codec interface logic during a control register/PIO access. The state of these address lines determine which register is accessed. RD 60 47 I Read Command Strobe. This active LO signal defines a read cycle from the Codec. The cycle may be a read from the control/PIO registers, or the cycles could be a read from the Codec’s DMA sample registers. WR 61 48 I Write Command Strobe. This active LO signal indicates a write cycle to the Codec. The cycle may be a write to the control/PIO registers, or the cycle could be a write to the Codec’s DMA sample registers. CS 59 46 I AD1848K Chip Select. The Codec will not respond to any control/PIO cycle accesses unless this active LO signal is LO. This signal is ignored during DMA transfers. DATA7:0 3–6 & 65–68 52–55 & 58–61 I/O Data Bus. These pins transfer data and control information between the Codec and the host. DBEN 63 50 O Data Bus Enable. This pin enables the external bus drivers. This signal is normally HI. For control register/PIO cycles, DBEN = (WR or RD) and CS For DMA cycles, DBEN = (WR or RD) and (PDAK or CDAK) DBDIR 62 49 O Data Bus Direction. This pin controls the direction of the data bus transceiver. HI enables writes from the host to the AD1848K; LO enables reads from the AD1848K to the host bus. This signal is normally HI. For control register/PIO cycles, DBDIR = RD and CS For DMA cycles, DBDIR = RD and (PDAK or CDAK) REV. 0 –7– AD1848K Analog Signals Pin Name PLCC TQFP I/O Description L_LINE 30 21 I Left Line Input. Line level input for the left channel. R_LINE 27 18 I Right Line Input. Line level input for the right channel. L_MIC 29 20 I Left Microphone Input. Microphone input for the left channel. This signal can be either line level or –20 dB from line level. R_MIC 28 19 I Right Microphone Input. Microphone input for the right channel. This signal can be either line level or –20 dB from line level. L_AUX1 39 30 I Left Auxiliary #1 Line Input R_AUX1 42 33 I Right Auxiliary #1 Line Input L_AUX2 38 29 I Left Auxiliary #2 Line Input R_AUX2 43 34 I Right Auxiliary #2 Line Input L_OUT 40 31 O Left Line Level Output R_OUT 41 32 O Right Line Level Output Miscellaneous Pin Name PLCC TQFP I/O Description XTAL1I 17 8 I 24.576 MHz Crystal #1 Input XTAL1O 18 9 O 24.576 MHz Crystal #1 Output XTAL2I 21 12 I 16.9344 MHz Crystal #2 Input XTAL2O 22 13 O 16.9344 MHz Crystal #2 Output PWRDWN 23 14 I Power-Down Signal. Active LO control places AD1848K in its lowest power consumption mode. All sections of the AD1848K, including the digital interface, are shut down and consume minimal power. INT 57 44 O Host Interrupt Pin. This signal is used to notify the host that the DMA Current Count Register has underflowed. XCTL1:O 56 & 58 43 & 45 O External Control. These signals reflect the current status of register bits inside the AD1848K. They can be used for signaling or to control external logic. VREF 32 23 O Voltage Reference. Nominal 2.25 volt reference available for dc-coupling and level-shifting. VREF should not be used where it will sink or source current. VREF_F 33 24 I Voltage Reference Filter. Voltage reference filter point for external bypassing only. L_FILT 31 22 I Left Channel Filter Input. This pin requires a 1.0 µF capacitor to analog ground for proper operation. R_FILT 26 17 I Right Channel Filter Input. This pin requires a 1.0 µF capacitor to analog ground for proper operation. N/C 46–52, 55 37–39, 42 No Connect. Do not connect. Power Supplies Pin Name PLCC TQFP I/O Description VCC 35 & 36 26 & 27 I Analog Supply Voltage (+5 V) GNDA 34 & 37 25 & 28 I Analog Ground VDD 1, 7, 15, 19, 24, 45, 54 6, 10, 15, 36, 41, 56 I Digital Supply Voltage (+5 V) GNDD 2, 8, 16, 20, 25, 44, 53, 64 7, 11, 16, 35, 40, 51, 63 I Digital Ground –8– REV. 0 AD1848K +20 dB prior to the PGA to compensate for the voltage swing difference between line levels and typical condenser microphones. Alternatively, the mic inputs can bypass the +20 dB fixed gain block and go straight to the input multiplexer. (Continued from page 1) analog signals: line, microphone (“mic”), auxiliary (“aux”) #1, and post-mixed DAC output. The microphone inputs can pass through optional 20 dB gain blocks. A software-controlled programmable gain stage allows independent gain for each channel going into the ADC. The ADCs’ output can be digitally mixed with the DACs’ input. AD1848K ADDRESS DECODE AEN 18 CS SA1 A0 SA0 WR IOWC RD IORC 7 4 8 DBDIR DIR DBEN G B 2 4 5 8 Analog Mixing SA19:2 A1 DATA7:0 The PGA following the input multiplexer allows independent selectable gains for each channel from 0 to 22.5 dB in +1.5 dB steps. The Codec can operate either in a global stereo mode or in a global mono mode with left channel inputs appearing at both channel outputs. AUX1 and AUX2 analog stereo signals can be mixed in the analog domain with the DAC output. Each channel of each auxiliary analog input can be independently gained/attenuated from +12 dB to –34.5 dB in –1.5 dB steps or completely muted. The post mixed DAC output is available on OUT externally and as an input to the ADCs. DATA7:0 Even if the AD1848K is not playing back data from its DACs, the analog mix function can still be active. ISA BUS A PDRQ DRQ<X> CDRQ DRQ<Y> PDAK DAK<X> CDAK DAK<Y> INT Analog-to-Digital Datapath The AD1848K ∑∆ ADCs incorporate a fourth order modulator. A single pole of passive filtering is all that is required for anti-aliasing the analog input due to the ADC’s high 64 times oversampling ratio. The ADCs include linear phase digital decimation filters that low-pass filter the input to 0.45 × FS (“FS” is the word rate or “sampling frequency.”) ADC input overrange conditions will cause register bits to be set that can be read. IRQ<Z> Figure 1. Interface to ISA Bus Digital-to-Analog Datapath The pair of 16-bit outputs from the ADCs is available over a byte-wide bidirectional interface that also supports 16-bit digital input to the DACs and control information. The AD1848K can accept and generate 16-bit twos-complement PCM linear digital data, 8-bit unsigned magnitude PCM linear data, and 8-bit µ-law or A-law companded digital data. The ∑∆ DACs contain a programmable attenuator and a lowpass digital interpolation filter. The anti-imaging interpolation filter nominally oversamples by 64 and digitally filters the higher frequency images. The interpolation ratio is increased at low sample rates to ensure that the shaped quantization noise is inaudible. This feature of the AD1848K represents an improvement over the earlier AD1848J. The attenuator allows independent control of each DAC channel from 0 dB to –94.5 dB in 1.5 dB steps plus full mute. The DACs’ ∑∆ noise shapers also oversample by 64 and convert the signal to a single bit stream. The DAC outputs are then filtered in the analog domain by a combination of switched-capacitor and continuous-time filters. They remove the very high frequency components of the DAC bitstream output. No external components are required. Phase linearity at the analog output is achieved by internally compensating for the group delay variation of the analog output filters. The ∑∆ DACs are preceded by a digital interpolation filter. An attenuator provides independent user volume control over each DAC channel. Nyquist images and shaped quantization noise are removed from the DACs’ analog stereo output by on-chip switched-capacitor and continuous-time filters. Two stereo pairs of auxiliary line-level inputs can also be mixed in the analog domain with the DAC output. AUDIO FUNCTIONAL DESCRIPTION This section overviews the functionality of the AD1848K and is intended as a general introduction to the capabilities of the device. As much as possible, detailed reference information has been placed in “Control Registers” and other sections. The user is not expected to refer repeatedly to this section. Changes in DAC output attenuation take effect only on zero crossings of the digital signal, thereby eliminating “zipper” noise. Each channel has its own independent zero-crossing detector and attenuator change control circuitry. A timer guarantees that requested volume changes will occur even in the absence of an input signal that changes sign. The time-out period is 8 milliseconds at a 48 kHz sampling rate and 48 milliseconds at an 8 kHz sampling rate. (Time out [ms] ≈ 384/FS [kHz].) Analog Inputs The AD1848K SoundPort Stereo Codec accepts stereo line-level and mic-level inputs. LINE, MIC, and AUX1 inputs and post-mixed DAC output analog stereo signals are multiplexed to the internal programmable gain amplifier stage (PGA). Each channel of the mic inputs can be amplified by REV. 0 –9– AD1848K On input, 8-bit companded data is expanded to an internal linear representation, according to whether µ-law or A-law was specified in the Codec’s internal registers. Note that when µ-law compressed data is expanded to a linear format, it requires 14 bits. A-law data expanded requires 13 bits. Digital Mixing Stereo digital output from the ADCs can be mixed digitally with the input to the DACs. Digital output from the ADCs going out of the data port is unaffected by the digital mix. Along the digital mix datapath, the 16-bit linear output from the ADCs is attenuated by an amount specified with control bits. Both channels of the monitor data are attenuated by the same amount. (Note that internally the AD1848K always works with 16-bit PCM linear data, digital mixing included; format conversions take place at the input and output.) 15 COMPRESSED INPUT DATA MSB 15 EXPANSION Sixty-four steps of –1.5 dB attenuation are supported to –94.5 dB. The digital mix datapath can also be completely muted, preventing any mixing of the analog input with the digital input. Note that the level of the mixed signal is also a function of the input PGA settings, since they affect the ADCs’ output. 3/2 MSB 2/1 0 2/1 0 LSB 3/2 15 DAC INPUT 0 8 7 LSB MSB LSB 000/00 Figure 2. A-Law or µ -Law Expansion The attenuated digital mix data is digitally summed with the DAC input data prior to the DACs’ datapath attenuators. The digital sum of digital mix data and DAC input data is clipped at plus or minus full scale and does not wrap around. Because both stereo signals are mixed before the output attenuators, mix data is attenuated a second time by the DACs’ datapath attenuators. When 8-bit companding is specified, the ADCs’ linear output is compressed to the format specified. 15 ADC OUTPUT 0 MSB LSB 15 In case the AD1848K is capturing data but ADC output data is not removed in time (“ADC overrun”), then the last sample captured before overrun will be used for the digital mix. In case the AD1848K is playing back data but input digital DAC data fails to arrive in time (“DAC underrun”), then a midscale zero will be added to the digital mix data. TRUNCATION 15 COMPRESSION 3/2 MSB MSB 2/1 0 LSB 0 8 7 LSB 00000000 Figure 3. A-Law or µ -Law Compression Analog Outputs A stereo line level output is available at external pins. Each channel of this output can be independently muted. When muted, the outputs will settle to a dc value near VREF, the midscale reference voltage. Note that all format conversions take place at input or output. Internally, the AD1848K always uses 16-bit linear PCM representations to maintain maximum precision. Digital Data Types The AD1848K operates from +5 V power supplies. Independent analog and digital supplies are recommended for optimal performance though excellent results can be obtained in single supply systems. A voltage reference is included on the Codec and its 2.25 V buffered output is available on an external pin (VREF). The reference output can be used for biasing op amps used in dc coupling. The internal reference must be externally bypassed to analog ground at the VREF_F pin. Power Supplies and Voltage Reference The AD1848K supports four global data types: 16-bit twoscomplement linear PCM, eight-bit unsigned linear PCM, companded µ-law, and 8-bit companded A-law, as specified by control register bits. Data in all four formats is always transferred MSB first. Eight-bit data is always left justified in 16-bit fields; said in other words, the MSBs of all data types are always aligned; in yet other words, full-scale representations in all four formats correspond to equivalent full-scale signals. The eight least significant bit positions of 8-bit data in 16-bit fields are ignored on input and zeroed on output. Clocks and Sample Rates The 16-bit PCM data format is capable of representing 96 dB of dynamic range. Eight-bit PCM can represent 48 dB of dynamic range. Companded µ-law and A-law data formats use nonlinear coding with less precision for large amplitude signals. The loss of precision is compensated for by an increase in dynamic range to 64 dB and 72 dB, respectively. The AD1848K operates from external crystals. Two crystal inputs are provided to generate a wide range of sample rates. The oscillators for these crystals are on the AD1848K, as is a multiplexer for selecting between them. They can be overdriven with external clocks by the user, if so desired. The recommended crystal frequencies are 16.9344 MHz and 24.576 MHz. From them the following sample rates are divided down: 5.5125, 6.615, 8, 9.6, 11.025, 16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8, 44.1, 48 kHz. –10– REV. 0 AD1848K CONTROL REGISTERS Control Register Architecture The AD1848K SoundPort Stereo Codec accepts both data and control information through its byte-wide parallel port. Indirect addressing minimizes the number of external pins required to access all 21 of its byte-wide internal registers. Only two external address pins, ADR1:0, are required to accomplish all data and control transfers. These pins select one of five direct registers. (ADR1:0 = 3 addresses two registers, depending on whether the transfer is a playback or a capture.) ADR1:0 Register Name 0 1 2 3 Index Address Register Indexed Data Register Status Register PIO Data Registers Figure 4. AD1848K Direct Register Map A write to or a read from the Indexed Data Register will access the indirect register which is indexed by the value most recently written to the Index Address Register. The Status Register and the PIO Data Register are always accessible directly, without indexing. The 16 indirect registers are indexed in Figure 5. Index Register Name 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Left Input Control Right Input Control Left Aux #1 Input Control Right Aux #1 Input Control Left Aux #2 Input Control Right Aux #2 Input Control Left Output Control Right Output Control Clock and Data Format Interface Configuration Pin Control Test and Initialization Miscellaneous Information Digital Mix Upper Base Count Lower Base Count Figure 5. AD1848K Indirect Register Map A detailed map of all direct and indirect register contents is summarized for reference as follows: Direct Registers: ADR1:0 0 1 2 3 3 Data 7 INIT IXD7 CU/L CD7 PD7 Data 6 MCE IXD6 CL/R CD6 PD6 Data 5 TRD IXD5 CRDY CD5 PD5 Data 4 res IXD4 SOUR CD4 PD4 Data 3 IXA3 IXD3 PU/L CD3 PD3 Data 2 IXA2 IXD2 PL/R CD2 PD2 Data 1 IXA1 IXD1 PRDY CD1 PD1 Data 0 IXA0 IXD0 INT CD0 PD0 Indirect Registers: IXA3:0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Data 7 LSS1 RSS1 LMX1 RMX1 LMX2 RMX2 LDM RDM res CPIO XCTL1 COR res DMA5 UB7 LB7 Data 6 LSS0 RSS0 res res res res res res FMT PPIO XCTL0 PUR res DMA4 UB6 LB6 Data 5 LMGE RMGE res res res res LDA5 RDA5 L/C res res ACI res DMA3 UB5 LB5 Data 4 res res LX1A4 RX1A4 LX2A4 RX2A4 LDA4 RDA4 S/M res res DRS res DMA2 UB4 LB4 Data 3 LIG3 RIG3 LX1A3 RX1A3 LX2A3 RX2A3 LDA3 RDA3 CFS2 ACAL res ORR1 ID3 DMA1 UB3 LB3 Data 2 LIG2 RIG2 LX1A2 RX1A2 LX2A2 RX2A2 LDA2 RDA2 CFS1 SDC res ORR0 ID2 DMA0 UB2 LB2 Data 1 LIG1 RIG1 LX1A1 RX1A1 LX2A1 RX2A1 LDA1 RDA1 CFS0 CEN IEN ORL1 ID1 res UB1 LB1 Data 0 LIG0 RIG0 LX1A0 RX1A0 LX2A0 RX2A0 LDA0 RDA0 CSS PEN res ORL0 ID0 DME UB0 LB0 Figure 6. AD1848K Register Summary Note that the only sticky bit in any of the AD1848K control registers is the interrupt (INT) bit. All other bits change with every sample period. REV. 0 –11– AD1848K Direct Control Register Definitions Index Register (ADR1:0 = 0) ADR1:0 0 Data 7 INIT Data 6 MCE Data 5 TRD Data 4 res Data 3 IXA3 Data 2 IXA2 Data 1 IXA1 Data 0 IXA0 IXA3:0 Index Address. These bits define the address of the AD1848K register accessed by the Indexed Data Register. These bits are read/write. res Reserved for future expansion. Always write a zero to this bit. TRD Transfer Request Disable. This bit, when set, causes all data transfers to cease when the Interrupt Status (INT) bit of the Status Register is set. MCE 0 Transfers Enabled During Interrupt. PDRQ and CDRQ pin outputs are generated uninhibited by interrupts. DMA Current Counter Register decrements with every sample period when either PEN or CEN are enabled. 1 Transfers Disabled By Interrupt. PDRQ and CDRQ pin outputs are generated only if INT bit is 0 (when either PEN or CEN, respectively, are enabled). Any pending playback or capture requests are allowed to complete at the time when TRD is set. After pending requests complete, midscale inputs will be internally generated for the DACs, and the ADC output buffer will contain the last valid output. Clearing the sticky INT bit (or the TRD bit) will cause the resumption of playback and/or capture requests (presuming PEN and/or CEN are enabled). The DMA Current Counter Register will not decrement while both the TRD bit is set and the INT bit is a one. Mode Change Enable. This bit must be set whenever the current functional mode of the AD1848K is changed. Specifically, the Clock and Data Format and Interface Configuration registers cannot be changed unless this bit is set. The exceptions are CEN and PEN in the Interface Configuration which can be changed “on-the-fly.” MCE should be cleared at the completion of the desired register changes. The DAC outputs are automatically muted when the MCE bit is set. After MCE is cleared, the DAC outputs will be restored to the state specified by the LDM and RDM mute bits. Both ADCs and DACs are automatically muted for approximately 128 sample cycles after exiting the MCE state to allow the reference and all filters to settle. The ADCs will produce midscale values; the DACs’ analog output will be muted. All converters are internally operating during these ≈128 sample cycles, and the AD1848K will expect playback data and will generate (midscale capture data. Note that the autocalibrate-in-process (ACI) bit will be set on exit from the MCE state regardless of whether or not ACAL was set. ACI will remain HI for these ≈128 sample cycles; system software should poll this bit rather than count cycles. Special sequences must be followed if autocalibrate (ACAL) is set or sample rates are changed (CFS2:0 and or CSS) during mode change enable. See the “Autocalibration” and “Changing Sample Rates” sections below. INIT AD1848K Initialization. This bit is set when the AD1848K is in a state which cannot respond to parallel bus cycles. This bit is read only. Immediately after reset and once the AD1848K has left the INIT state, the initial value of this register will be “0100 0000 (40h).” During AD1848K initialization, this register cannot be written and is always read “1000 0000 (80h).” Indexed Data Register (ADR1:0 = 1) ADR1:0 1 IXD7:0 Data 7 IXD7 Data 6 IXD6 Data 5 IXD5 Data 4 IXD4 Data 3 IXD3 Data 2 IXD2 Data 1 IXD1 Data 0 IXD0 Indexed Register Data. These bits contain the contents of the AD1848K register referenced by the Indexed Data Register. During AD1848K initialization. this register cannot be written and is always read as “1000 0000 (80h).” –12– REV. 0 AD1848K Status Register (ADR1:0 = 2) ADR1:0 2 Data 7 CU/L Data 6 CL/R Data 5 CRDY Data 4 SOUR Data 3 PU/L Data 2 PL/R Data 1 PRDY Data 0 INT INT Interrupt Status. This sticky bit (the only one) indicates the status of the interrupt logic of the AD1848K. This bit is cleared by any host write of any value to this register. The IEN bit of the Pin Control Register determines whether the state of this bit is reflected on the INT pin of the AD1848K. The only interrupt condition supported by the AD1848K is generated by the underflow of the DMA Current Count Register. 0 Interrupt pin inactive 1 Interrupt pin active PRDY Playback Data Register Ready. The PIO Playback Data Register is ready for more data. This bit should only be used when direct programmed I/O data transfers are desired. This bit is read only. 0 DAC data is still valid. Do not overwrite. 1 DAC data is stale. Ready for next host data write value. PL/R Playback Left/Right Sample. This bit indicates whether the PIO playback data needed is for the right channel DAC or left channel DAC. This bit is read only. 0 Right channel needed 1 Left channel or mono PU/L Playback Upper/Lower Byte. This bit indicates whether the PIO playback data needed is for the upper or lower byte of the channel. This bit is read only. 0 Lower byte needed 1 Upper byte needed or any 8-bit mode SOUR Sample Over/Underrun. This bit indicates that the most recent sample was not serviced in time and therefore either a capture overrun (COR) or playback underrun (PUR) has occurred. The bit indicates an overrun for ADC capture and an underrun for DAC playback. If both capture and playback are enabled, the source which set this bit can be determined by reading COR and PUR. This bit changes on a sample-by-sample basis. This bit is read only. CRDY Capture Data Ready. The PIO Capture Data Register contains data ready for reading by the host. This bit should only be used when direct programmed I/O data transfers are desired. This bit is read only. 0 ADC data is stale. Do not reread the information. 1 ADC data is fresh. Ready for next host data read. CL/R Capture Left/Right Sample. This bit indicates whether the PIO capture data waiting is for the right channel ADC or left channel ADC. This bit is read only. 0 Right channel 1 Left channel or mono CU/L Capture Upper/Lower Byte. This bit indicates whether the PIO capture data ready is for the upper or lower byte of the channel. This bit is read only. 0 Lower byte ready 1 Upper byte ready or any 8-bit mode The PRDY, CRDY, and INT bits of this status register can change asynchronously to host accesses. The host may access this register while the bits are transitioning. The host read may return a zero value just as these bits are changing, for example. A one value would not be read until the next host access. This registers’s initial state after reset is “1100 1100.” REV. 0 –13– AD1848K PIO Data Registers (ADRI :0 = 3) ADR1:0 3 3 Data 7 CD7 PD7 Data 6 CD6 PD6 Data 5 CD5 PD5 Data 4 CD4 PD4 Data 3 CD3 PD3 Data 2 CD2 PD2 Data 1 CD1 PD1 Data 0 CD0 PD0 The PIO Data Registers are two registers mapped to the same address. Writes send data to the PIO Playback Data Register (PD7:0). Reads will receive data from the PIO Capture Data Register (CD7:0). During AD1848K initialization, the PIO Playback Data Register cannot be written and the Capture Data Register is always read “1000 0000 (80h).” CD7:0 PIO Capture Data Register. This is the control register where capture data is read during programmed I/O data transfers. The reading of this register will increment the state machine so that the following read will be from the next appropriate byte in the sample. The exact byte which is next to be read can be determined by reading the Status Register. Once all relevant bytes have been read, the state machine will stay pointed to the last byte of the sample until a new sample is received from the ADCs. Once this has occurred, the state machine and status register will point to the first byte of the sample. Until a new sample is received, reads from this register will return the most significant byte of the sample. PD7:0 PIO Playback Data Register. This is the control register where playback data is written during programmed I/O data transfers. Writing data to this register will increment the playback byte tracking state machine so that the following write will be to the correct byte of the sample. Once all bytes of a sample have been written, subsequent byte writes to this port are ignored. The state machine is reset when the current sample is sent to the DACs. Indirect Control Register Definitions The following control registers are accessed by writing index values to IXA3:0 in the Index Address Register (ADR1:0 = 0) followed by a read/write to the Indexed Data Register (ADR1:0 = 1). Left Input Control (IXA3:0 = 0) IXA3:0 0 Data 7 LSS1 Data 6 LSS0 Data 5 LMGE Data 4 res Data 3 LIG3 Data 2 LIG2 Data 1 LIG1 Data 0 LIG0 LIG3:0 Left Input Gain Select. The least significant bit of this gain select represents +1.5 dB. Maximum gain is +22.5 dB. res Reserved for future expansion. Always write a zero to this bit. LMGE Left Input Microphone Gain Enable. Setting this bit will enable the +20 dB gain of the left mic input signal. LSS1:0 Left Input Source Select. These bits select the input source for the left gain stage preceding the left ADC. 0 Left Line Source Selected 1 Left Auxiliary 1 Source Selected 2 Left Microphone Source Selected 3 Left Line Post-Mixed DAC Output Source Selected This register’s initial state after reset is “0000 0000.” –14– REV. 0 AD1848K Right Input Control (IXA3:0 = 1) IXA3:0 1 Data 7 RSS1 Data 6 RSS0 Data 5 RMGE Data 4 res Data 3 RIG3 Data 2 RIG2 Data 1 RIG1 Data 0 RIG0 RIG3:0 Right Input Gain Select. The least significant bit of this gain select represents +1.5 dB. Maximum gain is +22.5 dB. res Reserved for future expansion. Always write a zero to this bit. RMGE Right Input Mic Gain Enable. Setting this bit will enable the +20 dB gain of the right mic input signal. RSS1:0 Right Input Source Select. These bits select the input source for the right channel gain stage preceding the right ADC. 0 Right Line Source Selected 1 Right Auxiliary 1 Source Selected 2 Right Microphone Source Selected 3 Right Post-Mixed DAC Output Source Selected This register’s initial state after reset is “0000 0000.” Left Auxiliary #1 Input Control (IXA3:0 = 2) IXA3:0 2 Data 7 LMX1 Data 6 res Data 5 res Data 4 LX1A4 Data 3 LX1A3 Data 2 LX1A2 Data 1 LX1A1 Data 0 LX1A0 LX1A4:0 Left Auxiliary Input #1 Attenuate Select. The least significant bit of this gain/attenuate select represents –1.5 dB. LX1X4:0 = 0 produces a +12 dB gain. LX1A4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is –34.5 dB. res Reserved for future expansion. Always write zeros to these bits. LMX1 Left Auxiliary #1 Mute. This bit, when set, will mute the left channel of the Auxiliary #1 input source. This bit powers up set. This register’s initial state after reset is “1000 0000 (80h).” Right Auxiliary #1 Input Control (IXA3:0 = 3) IXA3:0 3 RX1A4:0 Data 7 RMX1 Data 6 res Data 5 res Data 4 RX1A4 Data 3 RX1A3 Data 2 RX1A2 Data 1 RX1A1 Data 0 RX1A0 Right Auxiliary Input #1 Attenuate Select. The least significant bit of this gain/attenuate select represents –1.5 dB. RX1A4:0 = 0 produces a +12 dB gain. RX1A4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is –34.5 dB. res Reserved for future expansion. Always write zeros to these bits. RMX1 Right Auxiliary #1 Mute. This bit, when set, will mute the right channel of the Auxiliary #1 input source. This bit powers up set. This register’s initial state after reset is “1000 0000 (80h).” REV. 0 –15– AD1848K Left Auxiliary #2 Input Control (IXA3:0 = 4) IXA3:0 4 Data 7 LMX2 Data 6 res Data 5 res Data 4 LX2A4 Data 3 LX2A3 Data 2 LX2A2 Data 1 LX2A1 Data 0 LX2A0 LX2A4:0 Left Auxiliary Input #2 Attenuate Select. The least significant bit of this gain/attenuate select represents –1.5 dB. LX2A4:0 = 0 produces a +12 dB gain. LX2A4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is –34.5 dB. res Reserved for future expansion. Always write zeros to these bits. LMX2 Left Auxiliary #2 Mute. This bit, when set to 1, will mute the left channel of the Auxiliary #2 input source. This bit powers up set. This register’s initial state after reset is “1000 0000 (80h).” Right Auxiliary #2 Input Control (IXA3:0 = 5) IXA3:0 5 RX2A4:0 Data 7 RMX2 Data 6 res Data 5 res Data 4 RX2A4 Data 3 RX2A3 Data 2 RX2A2 Data 1 RX2A1 Data 0 RX2A0 Right Auxiliary Input #1 Attenuate Select. The least significant bit of this gain/attenuate select represents –1.5 dB. RX2A4:0 = 0 produces a +12 dB gain. RX2A4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is –34.5 dB. res Reserved for future expansion. Always write zeros to these bits. RMX2 Right Auxiliary #2 Mute. This bit, when set, will mute the right channel of the Auxiliary #2 input source. This bit powers up set. This register’s initial state after reset is “1000 0000 (80h).” Left DAC Control (IXA3:0 = 6) IXA3:0 6 Data 7 LDM Data 6 res Data 5 LDA5 Data 4 LDA4 Data 3 LDA3 Data 2 LDA2 Data 1 LDA1 Data 0 LDA0 LDA5:0 Left DAC Attenuate Select. The least significant bit of this attenuate select represents –1.5 dB. LDA5:0 = 0 produces a 0 dB attenuation. Maximum attenuation is –94.5 dB. res Reserved for future expansion. Always write a zero to this bit. LDM Left DAC Mute. This bit, when set to 1, will mute the left DAC output. Auxiliary inputs are muted independently with the Left Auxiliary Input Control Registers. This bit powers up set. This register’s initial state after reset is “1x00 0000.” Right DAC Control (IXA3:0 = 7) IXA3:0 7 Data 7 RDM Data 6 res Data 5 RDA5 Data 4 RDA4 Data 3 RDA3 Data 2 RDA2 Data 1 RDA1 Data 0 RDA0 RDA5:0 Right DAC Attenuate Select. The least significant bit of this attenuate select represents –1.5 dB. RDA5:0 = 0 produces 0 dB attenuation. Maximum attenuation is –94.5 dB. res Reserved for future expansion. Always write a zero to this bit. RDM Right DAC Mute. This bit, when set to 1, will mute the right DAC output. Auxiliary inputs are muted independently with the Right Auxiliary Input Control Registers. This bit powers up set. This register’s initial state after reset is “1x00 0000.” –16– REV. 0 AD1848K Clock and Data Format Register (IXA3:0 = 8) IXA3:0 8 Data 7 res Data 6 FMT Data 5 L/C Data 4 S/M Data 3 CFS2 Data 2 CFS1 Data 1 CFS0 Data 0 CSS The contents of the Clock and Data Format Register cannot be changed except when the AD1848K is in Mode Change Enable (MCE) state. Write attempts to this register when the AD1848K is not in the MCE state will not be successful. CSS CFS2:0 Clock Source Select. This bit selects the crystal clock source which will be used for the audio sample rate. 0 XTAL1 (24.576 MHz) 1 XTAL2 (16.9344 MHz) Clock Frequency Divide Select. These bits select the audio sample rate frequency. The actual audio sample rate depends on which crystal clock source is selected and the frequency of that source. CFS Divide Factor XTAL1 24.576 MHz XTAL2 16.9344 MHz 0 1 2 3 4 5 6 7 3072 1536 896 768 448 384 512 2560 8.0 kHz 16.0 kHz 27.42857 kHz 32.0 kHz Not Supported Not Supported 48.0 kHz 9.6 kHz 5.5125 kHz 11.025 kHz 18.9 kHz 22.05 kHz 37.8 kHz 44.1 kHz 33.075 kHz 6.615 kHz Note that the AD1848K’s internal oscillators can be overdriven by external clock sources at the crystal input pins. If an external clock source is applied, it will be divided down by the selected Divide Factor. It need not be at the recommended crystal frequencies. S/M L/C FMT Stereo/Mono Select. This bit determines how the audio data streams are formatted. Selecting stereo will result with alternating samples representing left and right audio channels. Mono playback plays the same audio sample on both channels. Mono capture only captures data from the left audio channel. 0 Mono 1 Stereo Linear/Companded Select. This bit selects between a linear digital representation of the audio signal or a nonlinear, companded format for all input and output data. The type of linear PCM or the type of companded format is defined by the FMT bits. 0 Linear PCM 1 Companded Format Select. This bit defines the format for all digital audio input and outputs based on the state of the L/C bit. 0 1 res Linear PCM (L/C = 0) Companded (L/C = 1) 8-bit Unsigned PCM 16-bit Twos-Complement PCM 8-bit µ-law Companded 8-bit A-law Companded Reserved for future expansion. Always write a zero to this bit. This register’s initial state after reset is “x000 0000.” REV. 0 –17– AD1848K Interface Configuration Register (IXA3:0 = 9) IXA3:0 9 Data 7 CPIO Data 6 PPIO Data 5 res Data 4 res Data 3 ACAL Data 2 SDC Data 1 CEN Data 0 PEN The contents of the Interface Configuration Register cannot be changed except when the AD1848K is in Mode Change Enable (MCE) state. Write attempts to this register when the AD1848K is not in the MCE state will not be successful. PEN and CEN are exceptions; these bits may always be written. PEN CEN SDC ACAL Playback Enable. This bit will enable the playback of data in the format selected. The AD1848K will generate PDRQ and respond to PDAK signals when this bit is enabled and PPIO = 0. If PPIO = 1, this bit enables Programmed I/O (PIO) playback mode. PEN may be set and reset without setting the MCE bit. 0 Playback disabled (PDRQ and PIO Playback Data Register inactive) 1 Playback enabled Capture Enable. This bit will enable the capture of data in the format selected. The AD1848K will generate CDRQ and respond to CDAK signals when this bit is enabled and CPIO = 0. If CPIO = 1, this bit enables PIO capture mode. CEN may be set and reset without setting the MCE bit. 0 Capture disabled (CDRQ and PIO Capture Data Register inactive) 1 Capture enabled Single DMA Channel. This bit will force both capture and playback DMA requests to occur on the Playback DMA channel. The Capture DMA CDRQ pin will be LO. This bit will allow the AD1848K to be used with only one DMA channel. Simultaneous capture and playback cannot occur in this mode. Should both capture and playback be enabled (CEN = PEN = 1) in the mode, only playback will occur. See “Data and Control Transfers” for further explanation. 0 Dual DMA channel mode 1 Single DMA channel mode Autocalibrate Enable. This bit determines whether the AD1848K performs an autocalibrate whenever the PWRDWN pin is deasserted or from the Mode Change Enable (MCE) bit being reset. ACAL is normally set. See “Autocalibration” below for a description of a complete autocalibration sequence. 0 No autocalibration 1 Autocalibration after power down/reset or mode change res Reserved for future expansion. Always write zeros to these bits. PPIO Playback PIO Enable. This bit determines whether the playback data is transferred via DMA or PIO. CPIO 0 DMA transfers only 1 PIO transfers only Capture PIO Enable. This bit determines whether the capture data is transferred via DMA or PIO. 0 DMA transfers only 1 PIO transfers only This register’s initial state after reset is “00xx 1000 (x8h).” Pin Control Register (IXA3:0 = 10) IXA3:0 10 Data 7 XCTL1 Data 6 XCTL0 Data 5 res Data 4 res Data 3 res Data 2 res Data 1 IEN Data 0 res res Reserved for future expansion. Always write zeros to these bits. IEN Interrupt Enable. This bit enables the interrupt pin. The Interrupt Pin will go active HI when the number of samples programmed in the Base Count Register is reached. 0 Interrupt disabled 1 Interrupt enabled XCTL1:0 External Control. The state of these independent bits is reflected on the respective XCTL1:0 pins of the AD1848K. 0 TTL Logic LO on XCTL1:0 pins 1 TTL Logic HI on XCTL1:0 pins This register’s initial state after reset is “00xx xx0x.” –18– REV. 0 AD1848K Test and Initialization Register (IXA3:0 = 11) IXA3:0 11 ORL1:0 ORR1:0 DRS ACI Data 7 COR Data 6 PUR Data 5 ACI Data 4 DRS Data 3 ORR1 Data 2 ORR0 Data 1 ORL1 Data 0 ORL0 Overrange Left Detect. These bits indicate the overrange on the left input channel. This bit changes on a sample-by sample basis. This bit is read only. 0 Less than –1 dB underrange 1 Between –1 dB and 0 dB underrange 2 Between 0 dB and +1 dB overrange 3 Greater than +1 dB overrange Overrange Right Detect. These bits indicate the overrange on the right input channel. This bit changes on a sample-by sample basis. This bit is read only. 0 Less than –1 dB underrange 1 Between –1 dB and 0 dB underrange 2 Between 0 dB and +1 dB overrange 3 Greater than +1 dB overrange Data Request Status. This bit indicates the current status of the PDRQ and CDRQ pins of the AD1848K. 0 CDRQ and PDRQ are presently inactive (LO) 1 CDRQ or PDRQ are presently active (HI) Autocalibrate-In-Progress. This bit indicates the state of autocalibration or a recent exit from Mode Change Enable (MCE). This bit is read only. 0 Autocalibration is not in progress 1 Autocalibration is in progress or MCE was exited within approximately the last 128 sample periods PUR Playback Underrun. This bit is set when playback data has not arrived from the host in time to be played. As a result, a midscale value will be sent to the DACs. This bit changes on a sample by sample basis. COR Capture Overrun. This bit is set when the capture data has not been read by the host before the next sample arrives. The sample being read will not be overwritten by the new sample. The new sample will be ignored. This bit changes on a sample by sample basis. The occurrence of a PUR and/or COR is designated in the Status Register’s Sample Overrun/Underrun (SOUR) bit. The SOUR bit is the logical OR of the COR and PUR bits. This enables a polling host CPU to detect an overrun/underrun condition while checking other status bits. This register’s initial state after reset is “0000 0000.” Miscellaneous Control Register (IXA3:0 = 12) IXA3:0 12 Data 7 res Data 6 res Data 5 res Data 4 res Data 3 ID3 Data 2 ID2 Data 1 ID1 Data 0 ID0 res Reserved for future expansion. The bits are read only. Do not write to these bits. ID3:0 AD1848K Revision ID. These four bits define the revision level of the AD1848K. Revisions increment by one LSB. The K-Grade revision is ID = “1010.” These bits are read only. This register’s initial state after reset is “xxxx RRRR” where RRRR = Revision ID of the silicon in use. REV. 0 –19– AD1848K Digital Mix Control Register (IXA3:0 = 13) IXA3:0 13 DME Data 7 DMA5 Data 6 DMA4 Data 5 DMA3 Data 4 DMA2 Data 3 DMA1 Data 2 DMA0 Data 1 res Data 0 DME Digital Mix Enable. This bit will enable the digital mix of the ADCs’ output with the DACs’ input. When enabled, the data from the ADCs are digitally mixed with other data being delivered to the DACs (regardless of whether or not playback [PEN] is enabled, i.e., set). If capture is enabled (CEN set) and there is a capture overrun (COR), then the last sample captured before overrun will be used for the digital mix. If playback is enabled (PEN set) and there is a playback underrun (PUR), then a midscale zero will be added to the digital mix data. 0 Digital mix disabled (muted) 1 Digital mix enabled res Reserved for future expansion. Always write a zero to this bit. DMA5:0 Digital Mix Attenuation. These bits determine the attenuation of the ADC data in mixing with the DAC input. Each attenuate step is –1.5 dB ranging to –94.5 dB. This register’s initial state after reset is “0000 00x0.” DMA Base Count Registers (IXA3:0 = 14 & 15) The DMA Base Count Registers in the AD1848K simplify integration of the AD1848K in ISA systems. The ISA DMA controller requires an external count mechanism to notify the host CPU via interrupt of a full DMA buffer. The programmable DMA Base Count Registers will allow such interrupts to occur. The Base Count Registers contain the number of sample periods which will occur before an interrupt is generated on the interrupt (INT) pin. To load, first write a value to the Lower Base Count Register. Writing a value to the Upper Base Register will cause both Base Count Registers to load into the Current Count Register. Once AD1848K transfers are enabled, each sample period the Current Count Register will decrement until zero count is reached. The next sample period after zero will generate the interrupt and reload the Current Count Register with the values in the Base Count Registers. The interrupt is cleared by a write to the Status Register. The Host Interrupt Pin (INT) will go HI during the sample period in which the Current Count Register underflows when Interrupt Enable (IEN) is set. It will go LO when the Interrupt Status (INT) bit is cleared. Note that both the bit and the pin have the same name (INT). The Current Count Register is decremented every sample period when either the PEN or CEN bit is enabled and also either the Transfer Request Disable (TRD) bit or the Interrupt Status (INT) bit are zero. Note that the internal INT bit will become one on counter underflow even if the external interrupt pin is not enabled, i.e., IEN is zero. The Current Count Register is decremented in both PIO and DMA data transfer modes. Upper Base Count Register (IXA3:0 = 14) IXA3:0 14 UB7:0 Data 7 UB7 Data 6 UB6 Data 5 UB5 Data 4 UB4 Data 3 UB3 Data 2 UB2 Data 1 UB1 Data 0 UB0 Upper Base Count. This byte is the upper byte of the base count register containing the eight most significant bits of the 16-bit base register. Reads from this register return the same value which was written. The current count contained in the counters can not be read. This register’s initial state after reset is “0000 0000.” Lower Upper Base Count Register (IXA3:0 = 15) IXA3:0 15 LB7:0 Data 7 LB7 Data 6 LB6 Data 5 LB5 Data 4 LB4 Data 3 LB3 Data 2 LB2 Data 1 LB1 Data 0 LB0 Lower Base Count. This byte is the lower byte of the base count register containing the eight least significant bits of the 16-bit base register. Reads from this register return the same value which was written. The current count contained in the counters cannot be read. This register’s initial state after reset is “0000 0000.” –20– REV. 0 AD1848K DATA AND CONTROL TRANSFERS Control and Programmed I/O (PIO) Transfers The AD1848K SoundPort Stereo Codec supports a DMA request/grant architecture for transferring data with the host computer bus. One or two DMA channels can be supported. Programmed I/O (PIO) mode is also supported for control register accesses and for applications lacking DMA control. PIO transfers can be made on one channel while the other is performing DMA. Transfers to and from the AD1848K SoundPort Codec are asynchronous relative to the internal data conversion clock. Transfers are buffered, but the AD1848K supports no internal FIFOs. The host is responsible for providing playback data before the next digital-to-analog conversion and removing capture data before the next analog-to-digital conversion. This simpler mode of transfers is used both for control register accesses and programmed I/O. The 21 control and PIO data registers cannot be accessed via DMA transfers. Playback PIO is activated when both Playback Enable (PEN) is set and Playback PIO (PPIO) is set. Capture PIO is activated when both Capture Enable (CEN) is set and Capture PIO (CPIO) is set. See Figures 11 and 12 for the detailed timing of the control register/ PIO transfers. The RD and WR signals are used to define the actual read and write cycles, respectively. The host holds CS LO during these transfers. The DMA Capture Data Acknowledge (CDAK) and Playback Data Acknowledge (PDAK) must be held inactive, i.e., HI. Data Ordering CDRQ / PDRQ OUTPUTS The number of byte-wide transfers required depends on the data format selected. The AD1848K is designed for “little endian” formats in which the least significant byte (i.e., occupying the lowest memory address) gets transferred first. So 16-bit data transfers require first transferring the least significant bits 7:0 and then transferring the most significant bits 15:8, where bit 15 is the most significant bit in the word. tSUDK1 CDAK INPUT tCSSU tDBDL DBEN & DBDIR OUTPUTS TIME SAMPLE 5 SAMPLE 4 SAMPLE 3 SAMPLE 2 tSTW SAMPLE 1 MONO MONO MONO MONO BYTE 4 BYTE 3 BYTE 2 BYTE 1 RD INPUT DATA7:0 OUTPUTS tADSU tADHD ADR1:0 INPUTS TIME SAMPLE 3 SAMPLE 2 SAMPLE 2 SAMPLE 1 Figure 11. AD1848K Control Register/PIO Read Cycle SAMPLE 1 RIGHT LEFT RIGHT LEFT BYTE 4 BYTE 3 BYTE 2 BYTE 1 CDRQ/ PDRQ OUTPUTS Figure 8. AD1848K 8-Bit Stereo Data Stream Sequencing SAMPLE 5 SAMPLE 4 SAMPLE 3 SAMPLE 2 PDAK INPUT BYTES 3 & 4 SAMPLE 1 tDBDL DBEN OUTPUT BYTES 1 & 2 Figure 9. AD1848K 16-Bit Mono Data Stream Sequencing DBDIR OUTPUT HI TIME SAMPLE 3 SAMPLE 3 SAMPLE 2 SAMPLE 2 SAMPLE 1 tCSHD tCSSU CS INPUT MONO MONO tSUDK2 tSUDK1 TIME SAMPLE 6 tDHD1 tRDDV Figure 7. AD1848K 8-Bit Mono Data Stream Sequencing SAMPLE 3 tCSHD CS INPUT In addition, left channel data is always transferred before right channel data with the AD1848K. The following figures should make these requirements clear. SAMPLE 6 tSUDK2 tSTW WR INPUT SAMPLE 1 tWDSU RIGHT BYTES 3 & 4 tDHD2 DATA7:0 INPUTS LEFT BYTES 1 & 2 tADSU Figure 10. AD1848K 16-Bit Stereo Data Stream Sequencing tADHD ADR1:0 INPUTS Figure 12. AD1848K Control Register/PIO Write Cycle REV. 0 –21– AD1848K For read/capture cycles, the AD1848K will place data on the DATA7:0 lines while the host is asserting the read strobe, RD, by holding it LO. For write/playback, the host must place data on the DATA7:0 pins while strobing the WR signal LO. The AD1848K latches the write/playback data on the rising edge of the WR strobe. When using PIO data transfers, the Status Register must be polled to determine when data should be transferred. Note that the ADC capture data will be ready (CRDY HI) from the previous sample period shortly before the DAC playback data is ready (PRDY HI) for the next sample period. The user should not wait for both ADCs and DACs to become ready before initiating data transfers. Instead, as soon as capture data is ready, it should be read; as soon as the DACs are ready, playback data should be written. Values written to the XCTL1:0 bits in the Pin Control Register (IXA3:0 = 10) will be reflected in the state of the XCTL1:0 external output pins. This feature allows a simple method for signaling or software control of external logic. Changes in state of the external XCTL pins will occur within one sample period. Because their change is referenced to the internal sample clock, no useful timing diagram can be constructed. Direct Memory Access (DMA) Transfers The second type of bus cycle supported by the AD1848K are DMA transfers. Both dual channel and single channel DMA operations are supported. To enable Playback DMA transfers, playback enable (PEN) must be set and PPIO cleared. To enable Capture DMA transfers, capture enable (CEN) must be set and CPIO cleared. During DMA transfers, the AD1848K asserts HI the Capture Data Request (CDRQ) or the Playback Data Request (PDRQ) followed by the host’s asserting LO the DMA Capture Data Acknowledge (CDAK) or Playback Data Acknowledge (PDAK), respectively. The host’s asserted Acknowledge signals cause the AD1848K to perform DMA transfers. The input address lines, ADR1:0, are ignored. Data is transferred between the proper internal sample registers. The read strobe (RD) and write strobe (WR) delimit valid data for DMA transfers. Chip select (CS) is a “don’t care”; its state is ignored by the AD1848K. The AD1848K asserts the Data Request Signals, CDRQ and PDRQ, at the rate of once per sample period, where PDRQ is asserted near the beginning of an internal sample period and CDRQ is asserted late in the same period to maximize the available processing time. Once asserted, these signals will remain active HI until the corresponding DMA cycle occurs with the host’s Data Acknowledge signals. The Data Request signals will be deasserted after the falling edge of the final RD or WD strobe in the transfer of a sample, which typically consists of multiple bytes. See “Data Ordering” above for a definition of “sample.” DMA transfers may be independently aborted by resetting the Capture Enable (CEN) and/or Playback Enable (PEN) bits in the Interface Configuration Register. The current capture sample transfer will be completed if a capture DMA is terminated. The current playback sample transfer must be completed if a playback DMA is terminated. If CDRQ and/or PDRQ are asserted HI while the host is resetting CEN and/or PEN, the request must be acknowledged. The host must assert CDAK and/ or PDAK LO and complete a final sample transfer. Single-Channel DMA Single-Channel DMA mode allows the AD1848K to be used in systems with only a single DMA channel. It is enabled by setting the SDC bit in the Interface Configuration Register. All captures and playbacks take place on the playback channel. Obviously, the AD1848K cannot perform a simultaneous capture and playback in Single-Channel DMA mode. Playback will occur in single-channel DMA mode exactly as it does in Two-Channel mode. Capture, however, is diverted to the playback channel which means that the capture data request occurs on the PDRQ pin and the capture data acknowledge must be received on the PDAK pin. The CDRQ pin will remain inactive LO. Any inputs to CDAK will be ignored. Playback and capture are distinguished in Single-Channel DMA mode by the state of the playback enable (PEN) or capture enable (CEN) control bits. If both PEN and CEN are set in Single-Channel DMA mode, playback will be presumed. To avoid confusion of the origin of a request when switching between playback and capture in Single-Channel DMA mode, both CEN and PEN should be disabled and all pending requests serviced before enabling the alternative enable bit. Switching between playback and capture in Single-Channel DMA mode no longer requires changing the PPIO and CPIO bits or passing through the Mode Change Enable state except for initial setup. For setup, assign zeros to both PPIO and CPIO. This configures both playback and capture for DMA. Then, switching between playback and capture can be effected entirely by setting and clearing the PEN and CEN control bits, a technique which avoids having to enter the Mode Change Enable state. DMA Timing Below, timing parameters are shown for 8-Bit Mono Sample Read/Capture and Write/Playback DMA transfers in Figures 13 and 14. Note that in single-channel DMA mode, the Read/ Capture cycle timing shown in Figure 13 applies to the PDRQ and PDAK signals, rather than the CDRQ and CDAK signals as shown. The same timing parameters apply to multibyte transfers. The relationship between timing signals is shown in Figures 15 and 16. The Host Interrupt Pin (INT) will go HI during the sample period in which the Current Count Register underflows. This event is referenced to the internal sample period clock which is not available externally. –22– REV. 0 AD1848K ISA BUS BCLK ISA BUS BCLK PDRQ OUTPUT CDRQ OUTPUT tDRHD tDRHD tDKSU PDAK INPUT tDKSU CDAK INPUT tDKHDB tDBDL tDBDL tDKHDA DBEN OUTPUTS DBEN & DBDIR OUTPUTS DBDIR OUTPUT tSTW HI RD INPUT tSTW tRDDV WR INPUT tDHD1 DATA7:0 OUTPUTS tWDSU tDHD2 DATA7:0 INPUTS Figure 13. AD1848K 8-Bit Mono DMA Read/Capture Cycle Figure 14. AD1848K 8-Bit Mono DMA Write/Playback Cycle ISA BUS BCLK CDRQ/ PDRQ OUTPUTS CDAK/ PDAK INPUTS tBWDN RD OR WR INPUTS RIGHT/HIGH BYTE LEFT/LOW BYTE DATA7:0 Figure 15. AD1848K 8-Bit Stereo or 16-Bit Mono DMA Cycle ISA BUS BCLK CDRQ/ PDRQ OUTPUTS CDAK/ PDAK INPUTS tBWDN RD OR WR INPUTS DATA7:0 LOW BYTE HIGH BYTE LEFT SAMPLE LOW BYTE HIGH BYTE RIGHT SAMPLE Figure 16. AD1848K 16-Bit Stereo DMA Cycle REV. 0 –23– AD1848K The completion of autocalibration can be determined by polling the Autocalibrate-In-Progress (ACI) bit in the Test and Initialization Register, which will be set during autocalibration. Transfers enabled during autocalibration do not begin until the completion of autocalibration. DMA Interrupt Writing to the internal 16-bit Base Count Register sets up the count value for the number of samples to be transferred. Note that the number of bytes transferred for a given count will be a function of the selected global data format. The internal Current Count Register is updated with the current contents of the Upper and Lower Base Count Registers when a write occurs to the Upper Base Count Register. The following summarizes the procedure for autocalibration: • Mute left and right DAC outputs, AUX1 and AUX2 inputs, and digital mix. (It is unnecessary to mute the DAC outputs, as this will happen automatically.) The Current Count Register cannot be read by the host. Reading the Base Count Registers will only read back the initialization values written to them. • Set the Mode Change Enable (MCE) bit. • Set the Autocalibration (ACAL) bit. The Current Count Register is decremented every sample period when either the PEN or CEN bit is enabled and also either the Transfer Request Disable (TRD) bit or the Interrupt Status (INT) bit is zero. An interrupt event is generated after the Current Count Register is zero and an additional playback sample is transferred. The INT bit in the Status Register always reflects the current internal interrupt state defined above. The external INT pin will only go active HI if the Interrupt Enable (IEN) bit in the Interface Configuration Register is set. If the IEN bit is zero, the external INT pin will always stay LO, even though the Status Register’s INT bit may be set. • Clear the Mode Change Enable (MCE) bit. • The Autocalibrate-In-Progress (ACI) bit will transition from LO to HI within five sample periods. It will remain HI for approximately 384 sample periods. Poll the ACI bit until it transitions from HI to LO. • Set to desired gain/attenuation values, and unmute DAC outputs (if muted), AUX inputs, and digital mix. POWER UP AND RESET The PWRDWN pin should be held in its active LO state when power is first applied to the AD1848K. Analog Devices recommends waiting one full second after deasserting PWRDWN before commencing audio activity with the AD1848K. This will allow the analog outputs to fully settle to the VREF voltage level prior to system autocalibration. At any point when powered, the AD1848K can be put into a state for minimum power consumption by asserting PWRDWN LO. All analog and digital sections are shut down. The AD1848K’s parallel interface does not function; all bidirectional signal lines are in high impedance threestate. Deasserting PWRDWN by bringing it HI begins the AD1848K’s initialization. While initializing, the AD1848K ignores all writes and all reads will yield “1000 0000 (80h).” At the conclusion of reset initialization, all registers will be set to their default values as listed in “Control Registers” above. The conclusion of the initialization period can be detected by polling the index register for some value other than “1000 0000 (80h).” It is imperative to autocalibrate on power up for proper operation. See next section. AUTOCALIBRATION The AD1848K can calibrate the ADCs and DACs for greater accuracy by minimizing DC offsets. Autocalibration occurs whenever the AD1848K returns from the Mode Change Enable state and the ACAL bit in the Interface Configuration register has been set. If the ACAL bit is not set, the RAM normally containing ADC and DAC offset compensations will be saved, retaining the offsets of the most recent autocalibration. Therefore, it is imperative to autocalibrate on power up for proper operation. During the autocalibration sequence, data output from the ADCs is meaningless. Inputs to the DACs are ignored. Even if the user specified the muting of all analog outputs, near the end of the autocalibration sequence, dc analog outputs very close to VREF will be produced at the line output. CHANGING SAMPLE RATES To change the selection of the current sample rate requires a Mode Change Enable sequence since the bits which control that selection are in the Clock and Data Format Register. The fact that the clocks change requires a special sequence which is summarized as follows: • If autocalibration will take place at the end of this sequence, mute the AUX1 and AUX2 inputs and the digital mix. • Set the Mode Change Enable (MCE) bit. • In a single write cycle, change the Clock Frequency Divide Select (CFS2:0) and/or the Clock Source Select (CSS). • The AD1848K now needs to resynchronize its internal states to the new clock. Writes to the AD1848K will be ignored. Reads will produce “1000 0000 (80h)” until the resynchronization is complete. Poll the Index Register until something other than this value is returned. • Clear the Mode Change Enable (MCE) bit. • If ACAL is set, follow the procedure described in “Autocalibration” above. • Poll the ACI hit until it transitions LO (approximately 128 sample cycles). • Set to desired gain/attenuation values, and unmute DAC outputs (if muted). –24– REV. 0 AD1848K Note that if a battery-powered microphone is used, the buffer and R2s are not needed. The values of R1, R2, and C should be chosen in light of the mic characteristics and intended gain. Typical values for these might be R1 = 20 kΩ, R2 = 2 kΩ, and C = 220 pF. APPLICATIONS CIRCUITS The AD1848K Stereo Codec has been designed to require a minimum of external circuitry. The recommended circuits are shown in Figures 17 through 25. Analog Devices estimates that the total cost of all the components shown in these figures, including crystals but not including connectors, to be less than $10 in the U.S.A. in 10,000 quantities. C See Figure 1 for an illustration of the connection between the AD1848K SoundPort Codec and the Industry Standard Architecture (ISA) computer bus, also known as the “PC-AT bus.” Note that the 74_245 transceiver receives its enable and direction signals directly from the Codec. Analog Devices recommends using the “slowest” 74_245 adequately fast to meet all AD1848K and computer bus timing and drive requirements. So doing will minimize switching transients of the 74_245. This in turn will minimize the digital feedthrough effects of the transceiver when driving the AD1848K, which can cause the audio noise floor to rise. Industry-standard compact disc “line-levels” are 2 V rms centered around analog ground. (For other audio equipment, “line level” is much more loosely defined.) The AD1848K SoundPort is a +5 V only powered device. Line level voltage swings for the AD1848K are defined to be 1 V rms for a sine wave ADC input and 0.707 V rms for a sine wave DAC output. Thus, 2 V rms input analog signals must be attenuated and either centered around the reference voltage intermediate between 0 V and +5 V or ac-coupled. The VREF pin will be at this intermediate voltage, nominally 2.25 V. It has limited drive but can be used as a dc bias to an op amp input. Note, however, that dc-coupled inputs are not recommended, as they provide no performance benefits with the AD1848K architecture. Furthermore, dc offset differences between multiple dc-coupled inputs create the potential for “clicks” when changing the input mux selection. 0.33µF L_LINE 560pF NPO L_AUX1 5.1k 5.1k 0.33µF R2 LEFT ELECTRET CONDENSER MICROPHONE INPUT L_MIC 1/2 SSM-2135 OR AD820 1/2 SSM-2135 OR AD820 VREF C R2 R1 1µF 5.1k 0.33µF R_MIC RIGHT ELECTRET CONDENSER MICROPHONE INPUT 1/2 SSM-2135 OR AD820 VREF Figure 18. AD1848K "Phantom-Powered" Microphone Input Circuit Figure 19 shows ac-coupled line outputs. The resistors are used to center the output signals around analog ground. If dc-coupling is desired, VREF could be used with op amps as mentioned previously. 1µF L_OUT 47k 1µF A circuit for 2 V rms line-level inputs and auxiliaries is shown in Figure 17. Note that this is a divide-by-two resistive divider. The input resistor and 560 pF capacitor provides the single-pole of anti-alias filtering required for the ADCs. If line-level inputs are already at the 1 V rms levels expected by the AD1848K, the resistors in parallel with the 560 pF capacitors can be omitted. 5.1k R1 1µF R_OUT 47k Figure 19. AD1848K Line Output Connections A circuit for headphone drive is illustrated in Figure 20. Drive is supplied by +5 V operational amplifiers. The circuit shown ac couples the line output to the headphones. L_AUX2 18k 20k 470µF L_OUT HEADPHONE LEFT 0.33µF 5.1k R_LINE 560pF NPO VREF R_AUX1 5.1k SSM-2135 470µF R_AUX2 HEADPHONE RIGHT 20k R_OUT Figure 17. AD1848K 2 V rms Line-Level Input Circuit 18k Figure 20. AD1848K Headphone Drive Connections The AD1848K Codec contains an optional +20 dB gain block to accommodate condenser microphones. Particular system requirements will depend upon the characteristics of the intended microphone. Figure 18 illustrates one example of how an electret condenser mike requiring phantom power could be connected to the AD1848K. VREF is shown buffered by an op amp; a transistor like a 2N4124 will also work fine for this purpose. REV. 0 –25– AD1848K power supply is not available, we recommend the circuit shown in Figure 24 for using a single +5 V supply. Ferrite beads suffice for the inductors shown. This circuitry should be as close to the supply pins as is practical. Figure 21 illustrates reference bypassing. VREF_F should only be connected to its bypass capacitors. VREF _F VREF 0.1µF 10µF FERRITE 10µF +5V SUPPLY 0.1µF 1µF 0.1µF Figure 21. AD1848K Voltage Reference Bypassing VDD Figure 22 illustrates signal-path filtering capacitors, L_FILT and R_FILT. Note that AD1848Ks will perform satisfactorily with 0.1 µF capacitors; increasing the value to 1.0 µF does improve performance at very low frequencies, however. L_FILT VDD VDD R_FILT 1µF VCC Figure 24. AD1848K Recommended Power Supply Bypassing XTAL1O XTAL2I Analog Devices recommends a split ground plane as shown in Figure 25. The analog plane and the digital plane are connected directly under the AD1848K. Splitting the ground plane directly under the SoundPort Codec is optimal because analog pins will be located above the analog ground plane and digital pins will be located directly above the digital ground plane for the best isolation. The digital ground and analog grounds should be tied together in the vicinity of the AD1848K. Other schemes may also yield satisfactory results. If the split ground plane recommended here is not possible, the AD1848K should be entirely over the analog ground plane with the 74_245 transceiver over the digital plane. DIGITAL GROUND PLANE XTAL2O GNDD 20–64pF 24.576MHz 0.1µF VCC The crystals shown in the crystal connection circuitry of Figure 23 should be fundamental-mode and parallel-tuned. Two sources for the exact crystals specified are Component Marketing Services in Massachusetts, U.S. at 617-762-4339 and Cardinal Components in New Jersey, U.S. at 201-746-0333. Note that using the exact data sheet frequencies is not required and that external clock sources can be used to overdrive the AD1848K’s internal oscillators. (See the description of the CFS2:0 control bits above.) If using an external clock source, apply it to the crystal input pins while leaving the crystal output pins unconnected. Attention should be paid to providing low jitter external input clocks. 20–64pF VDD 1µF 1.0µF Figure 22. AD1848K External Filter Capacitor Connections XTAL1I 0.1µF 1.6Ω 0.1µF 1.0µF 0.1µF VDD FERRITE VDD VDD 0.1µF 0.1µF 0.1µF 0.1µF 20–64pF ANALOG GROUND PLANE R_AUX2 20–64pF 16.9344MHz Figure 23. AD1848K Crystal Connections AD1848K Analog Devices also recommends a pull-down resistor for PWRDWN. Good, standard engineering practices should be applied for power supply decoupling. Decoupling capacitors should be placed as close as possible to package pins. If a separate analog GNDD R_FILT Figure 25. AD1848K Recommended Ground Plane –26– REV. 0 AD1848K FREQUENCY RESPONSE PLOTS 10 10 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 dB –50 dB –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.0 0.1 0.2 SAMPLE FREQUENCY (FS ) Figure 26. AD1848K Analog-to-Digital Frequency Response (Full-Scale Line-Level Inputs, 0 dB Gain) 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 1.0 –50 dB –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 –120 0.40 0.60 SAMPLE FREQUENCY (FS ) Figure 27. AD1848K Analog-to-Digital Frequency Response—Transition Band (Full-Scale Line-Level Inputs, 0 dB Gain) REV. 0 0.9 10 0 –120 0.40 0.8 Figure 28. AD1848K Digital-to-Analog Frequency Response (Full-Scale Inputs, 0 dB Attenuation) 10 dB 0.3 0.4 0.5 0.6 0.7 SAMPLE FREQUENCY (FS ) 0.42 0.44 0.46 0.48 0.50 0.52 0.54 SAMPLE FREQUENCY (FS ) 0.56 0.58 0.60 Figure 29. AD1848K Digital-to-Analog Frequency Response—Transition Band (Full-Scale Inputs, 0 dB Attenuation) –27– AD1848K OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 9 PIN 1 IDENTIFIER 0.063 (1.60) MAX 0.175 (4.45) 0.169 (4.29) 0.995 (25.27) SQ 0.885 (22.48) 10 ST-64 64-Lead Thin Quad Flatpack 61 60 0.630 ± 0.009 SQ (16.00 ± 0.25) 0.055 ± 0.002 (1.40 ± 0.05) 0.050 (1.27) TYP 0.551 ± 0.004 SQ (14.00 ± 0.10) 0.024 ± 0.006 (0.60 ± 0.15) SEATING PLANE 0.925 (23.50) 0.895 (22.73) 64 49 1 48 12 ° TYP C1847–10–10/93 P-68A 68-Lead Plastic Leaded Chip Carrier TOP VIEW 0.019 (0.48) 0.017 (0.43) TOP VIEW 0.029 (0.74) 0.027 (0.69) 26 44 27 43 0.104 (2.64) TYP 0.004 (0.102) MAX LEAD COPLANARITY 16 6° ± 4 ° 33 17 0° – 7 ° 32 0.031 (0.80) 0.014 (0.35) 0.007 (0.17) MAX INDEX PAGE PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . 2 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PINOUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AUDIO FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . 9 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Analog Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Analog-to-Digital Datapath . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital-to-Analog Datapath . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Digital Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power Supplies and Voltage Reference . . . . . . . . . . . . . . . 10 Clocks and Sample Rates . . . . . . . . . . . . . . . . . . . . . . . . . 10 CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Control Register Architecture . . . . . . . . . . . . . . . . . . . . . . 11 Direct Control Register Definitions . . . . . . . . . . . . . . . . . 12 Indirect Control Register Definitions . . . . . . . . . . . . . . . . 14 DATA AND CONTROL TRANSFERS . . . . . . . . . . . . . . . 21 Data Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Control and Programmed I/O (PIO) Transfers . . . . . . . . 21 Direct Memory Access (DMA) Transfers . . . . . . . . . . . . . 22 Single-Channel DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DMA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DMA Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 POWER UP AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . 24 AUTOCALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CHANGING SAMPLE RATES . . . . . . . . . . . . . . . . . . . . . 24 APPLICATIONS CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . 25 FREQUENCY RESPONSE PLOTS . . . . . . . . . . . . . . . . . 27 PACKAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 –28– PRINTED IN U.S.A. 0.954 (24.23) SQ 0.950 (24.13) REV. 0