ADS7863
AD
S7
863
AD
S78
63
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SBAS383B – JUNE 2007 – REVISED MARCH 2008
Dual, 2MSPS, 12-Bit, 2 + 2 or 3 + 3 Channel, Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
1
• Four Fully- or Six Pseudo-Differential Inputs
• SNR: 71dB, THD: –81dB
• Programmable and Buffered Internal 2.5V
Reference
• Flexible Power-Down Features
• Variable Power-Supply Ranges: 2.7V to 5.5V
• Low-Power Operation: 45mW at 5V
• Operating Temperature Range: –40°C to
+125°C
• Pin-Compatible with ADS7861 and ADS8361
(SSOP package)
The ADS7863 is a dual, 12-bit, 2MSPS,
analog-to-digital converter (ADC) with four fully
differential or six pseudo-differential input channels
grouped into two pairs for high-speed, simultaneous
signal acquisition. Inputs to the sample-and-hold
(S/H) amplifiers are fully differential and are
maintained differential to the input of the ADC. This
architecture provides excellent common-mode
rejection of 72dB at 100kHz, which is a critical
performance characteristic in noisy environments.
2
The ADS7863 is pin-compatible with the ADS7861,
but offers additional features such as a
programmable reference output, flexible supply
voltage (2.7V to 5.5V for AVDD and BVDD), a
pseudo-differential input multiplexer with three
channels per ADC, and several power-down features.
APPLICATIONS
•
•
•
Motor Control
Multi-Axis Positioning Systems
Three-Phase Power Control
The ADS7863 is offered in an SSOP-24 and a
4x4mm QFN-24 package. It is specified over the
extended operating temperature range of –40°C to
+125°C.
SAR
BVDD
AVDD
SDOA
CHA0+
CHA1+
SDOB
Input
MUX
S/H
M0
CDAC
CHA1-
Comparator
CHB0+
CHB0CHB1+
Input
MUX
S/H
CDAC
CHB1-
Serial Interface
CHA0-
M1
SDI
CLOCK
CS
RD
Comparator
BUSY
CONVST
REFIN
SAR
REFOUT
10-Bit DAC
BGND
2.5V Reference
AGND
Functional Block Diagram
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
ADS7863
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SBAS383B – JUNE 2007 – REVISED MARCH 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
PACKAGE DESIGNATOR
SSOP-24
DBQ
4×4 QFN-24
RGE
ORDERING NUMBER
ADS7863IDBQ
ADS7863IDBQR
ADS7863I
(1)
ADS7863IRGET
ADS7863IRGER
For the most current package and ordering information, see the Package Option Addendum at the end of this document or see the TI
web site at www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
ADS7863
UNIT
Supply voltage, AVDD to AGND
–0.3 to +6
V
Supply voltage, BVDD to BGND
–0.3 to +6
V
Supply voltage, BVDD to AVDD
1.5 × AVDD
V
Analog and reference input voltage with respect to AGND
AGND – 0.3 to AVDD + 0.3
V
Digital input voltage with respect to BGND
BGND – 0.3 to BVDD + 0.3
V
Ground voltage difference |AGND – BGND|
0.3
V
Input current to any pin except supply pins
–10 to +10
mA
Maximum virtual junction temperature, TJ
ESD ratings:
(1)
2
+150
°C
Human body model (HBM),
JEDEC standard 22, test method A114-C.01, all pins
±4000
V
Charged device model (CDM),
JEDEC standard 22, test method C101, all pins
±1500
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
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RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range, unless otherwise noted.
ADS7863
PARAMETER
Supply voltage, AVDD to AGND
Supply voltage, BVDD to BGND
MIN
NOM
MAX
2.7
5.0
5.5
Low voltage levels
2.7
5V logic levels
4.5
5.0
5.5
0.5
2.5
2.525
Reference input voltage on REFIN
Analog differential input voltage (CHXX+) – (CHXX–)
Operating ambient temperature range, TA
UNIT
V
3.6
V
V
–VREF
+VREF
V
–40
+125
°C
DISSIPATION RATINGS
PACKAGE
DERATING FACTOR ABOVE
TA = +25°C
TA ≤ +25°C
POWER RATING
TA = +70°C
POWER RATING
TA = +85°C
POWER RATING
TA = +125°C
POWER RATING
SSOP-24
10mW/°C
1250mW
800mW
650mW
250mW
QFN-24
(4mm × 4mm)
22mW/°C
2740mW
1750mW
1420mW
540mW
THERMAL CHARACTERISTICS (1)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
SSOP-24
QFN-24
Low-K thermal resistance
99.8
45.6
High-K thermal resistance
61.0
33.1
UNIT
θJA
Junction-to-air thermal resistance
θJC
Junction-to-case thermal resistance
23.3
35
°C/W
PDISS
Device power dissipation at AVDD = 5V and BVDD = 3.3V
45.3
45.3
mW
(1)
°C/W
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages.
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ELECTRICAL CHARACTERISTICS
At TA = –40°C to +125°C, entire power-supply range, VREF = 2.5V (internal), fCLK = 32MHz, and tDATA = 2MSPS, unless
otherwise noted.
ADS7863
PARAMETER
TEST CONDITIONS
RESOLUTION
MIN
TYP (1)
MAX
12
UNIT
Bits
ANALOG INPUT
FSR
Full-scale differential input range
VIN
Absolute input voltage
CHxx+ or CHxx+ to AGND
(CHxx+) – (CHxx–)
CIN
Input capacitance
CHxx+ or CHxx– to AGND
CID
Differential input capacitance
IIL
Input leakage current
CMRR
Common-mode rejection ratio
–VREF
+VREF
–0.1
AVDD + 0.1
2
Both ADCs, dc to 100kHz
V
pF
4
–1
V
pF
+1
72
nA
dB
DC ACCURACY
–40°C < TA < +125°C
–1.25
±0.6
+1.25
LSB
–40°C < TA < +85°C
–1
±0.5
+1
LSB
Differential nonlinearity (2)
–1
±0.5
+1
LSB
Input offset error
–3
±0.5
+3
LSB
–3
±0.5
+3
INL
Integral nonlinearity
DNL
VOS
VOS match
dVOS/dT
Input offset thermal drift
GERR
Gain error (2)
–0.5
GERR match
–0.5
GERR/dT
Gain error thermal drift
PSRR
Power-supply rejection ratio
AVDD = 5.5V
+1
±0.1
LSB
µV/°C
±3
+0.5
%
%
±1
ppm/°C
70
dB
AC ACCURACY
SINAD
Signal-to-noise + distortion
VIN = 5VPP at 100kHz
69.8
71
dB
SNR
Signal-to-noise ratio
VIN = 5VPP at 100kHz
70
71.5
dB
THD
Total harmonic distortion
VIN = 5VPP at 100kHz
SFDR
Spurious-free dynamic range
VIN = 5VPP at 100kHz
76
1MHz < fCLK ≤ 32MHz
16
–81
–76
84
dB
dB
SAMPLING DYNAMICS (2)
tCONV
Conversion time per ADC
tACQ
Acquisition time
tDATA
Data rate
tA
Aperture delay
tCLK
2
1MHz < fCLK ≤ 32MHz
tCLK
62.5
2000
6
tA match
50
tAJIT
Aperture jitter
fCLK
Clock frequency on CLOCK
TCLK
Clock period
kSPS
ns
ps
50
ps
1
32
31.25
1000
MHz
ns
INTERNAL VOLTAGE REFERENCE
Resolution
Reference output DAC resolution
10
Over 20%...100% DAC range
VREFOUT
Reference output voltage
dVREFOUT/dT
Reference voltage drift
DNLDAC
DAC differential nonlinearity
INLDAC
DAC integral nonlinearity
VOSDAC
(1)
(2)
4
DAC offset error
Bits
0.2VREFOUT
VREFOUT
V
V
DAC = 0x3FF,
–40°C < TA < +125°C
2.485
2.500
2.515
DAC = 0x3FF at +25°C
2.495
2.500
2.505
±10
VREFOUT = 0.5V
V
ppm/°C
–9.76
±2.44
9.76
mV
–4
±1
4
LSB
–9.76
±1.22
9.76
mV
LSB
–4
±0.5
4
–9.76
±2.44
9.76
mV
–4
±1
4
LSB
All typical values at TA = +25°C.
Ensured by design, not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
At TA = –40°C to +125°C, entire power-supply range, VREF = 2.5V (internal), fCLK = 32MHz, and tDATA = 2MSPS, unless
otherwise noted.
ADS7863
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
INTERNAL VOLTAGE REFERENCE, continued
PSRR
Power-supply rejection ratio
IREFOUT
Reference output dc current
73
dB
IREFSC
Reference output short-circuit current (3)
50
mA
tREFON
Reference output settling time
0.5
ms
–2
+2
mA
VOLTAGE REFERENCE INPUT
VREF
Reference input voltage range
IREF
Reference input current
0.5
50
2.525
µA
V
CREF
Reference input capacitance
10
pF
DIGITAL INPUTS (4)
Logic family
CMOS with Schmitt-Trigger
VIH
High-level input voltage
VIL
Low-level input voltage
IIN
Input current
CIN
Input capacitance
VIN = BVDD to BGND
0.7 × BVDD
BVDD + 0.3
–0.3
0.3 × BVDD
V
–50
+50
nA
5
V
pF
DIGITAL OUTPUTS (4)
Logic family
CMOS
VOH
High-level output voltage
BVDD = 4.5V, IOH = –100µA
VOL
Low-level output voltage
BVDD = 4.5V, IOH = 100µA
IOZ
High-impedance-state output current
COUT
Output capacitance
CLOAD
Load capacitance
BVDD – 0.2
V
–50
0.2
V
+50
nA
5
pF
30
pF
POWER SUPPLY
AVDD
Analog supply voltage
AVDD to AGND
2.7
5.0
5.5
V
BVDD
Buffer I/O supply voltage
BVDD to BGND
2.7
3.0
5.5
V
AVDD = 2.7V
4.5
6
AIDD
Analog supply current
AVDD = 5.0V
6.5
8
AVDD = 2.7V, NAP power-down
1.1
1.5
AVDD = 5.0V, NAP power-down
1.4
2.0
AVDD = 2.7V, deep power-down
0.001
AVDD = 5.0V, deep power-down
BIDD
Buffer I/O supply current
PDISS
Power dissipation
(3)
(4)
mA
0.001
BVDD = 2.7V, CLOAD = 10pF
0.5
1.3
BVDD = 3.3V, CLOAD = 10pF
0.9
1.6
AVDD = 2.7V, BVDD = 2.7V
13.5
19.7
AVDD = 5.0V, BVDD = 3.3V
35.5
45.3
mA
mW
Reference output current is not limited internally.
Ensured by design, not production tested.
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DEVICE INFORMATION
ADS7863IDBQ
SSOP-24 (DBQ)
(TOP VIEW)
CHB1-
3
22
SDOB
CHB0+
4
21
BUSY
CHB0-
5
20
CLOCK
CHA1+
6
19
CS
CHA1-
7
18
RD
CHA0+
8
17
CONVST
CHA1+
CHB0-
CHB0+
CHB1-
21
20
19
SDOA
22
BVDD
23
CHA0+
24
2
CHA1-
1
23
BGND
CHB1+
24
ADS7863IRGE
4 x 4 QFN-24 (RGE)
(TOP VIEW)
CHA0-
1
18
CHB1+
REFIN
2
17
BGND
REFOUT
3
16
BVDD
4
15
SDOA
AVDD
5
14
SDOB
M1
6
13
BUSY
14
M1
12
13
AVDD
12
11
AGND
CLOCK
REFOUT
11
M0
RD
15
CS
10
9
REFIN
10
SDI
SDI
16
CONVST
9
8
CHA0-
7
AGND
M0
ADS7863
PIN DESCRIPTIONS
PIN NUMBER
6
SSOP
QFN
NAME
DESCRIPTION
1
17
BGND
Buffer I/O ground. Connect to digital ground plane.
2
18
CHB1+
Noninverting analog input channel B1
3
19
CHB1–
Inverting analog input channel B1
4
20
CHB0+
Noninverting analog input channel B0
5
21
CHB0–
Inverting analog input channel B0
6
22
CHA1+
Noninverting analog input channel A1
7
23
CHA1–
Inverting analog input channel A1
8
24
CHA0+
Noninverting analog input channel A0
9
1
CHA0–
Inverting analog input channel A0
10
2
REFIN
Reference voltage input. A ceramic capacitor of 470nF (min) is required at this terminal.
11
3
REFOUT
12
4
AGND
Analog ground. Connect to analog ground plane.
13
5
AVDD
Analog power supply, 2.7V to 5.5V. Decouple to AGND with a 1µF ceramic capacitor.
14
6
M1
Mode pin 1. Selects between the SDOx digital outputs (see Table 8).
15
7
M0
Mode pin 0. Selects between analog input channels (see Table 8).
16
8
SDI
Serial data input. This pin allows the additional features of the ADS7863 to be used but can also be used
in ADS7861-compatible manner.
17
9
CONVST
Conversion start. The ADC switches from the sample into the hold mode on the rising edge of CONVST,
independent of the status of CLOCK. The conversion itself starts with the next rising edge of CLOCK.
18
10
RD
Read data. Synchronization pulse for the SDOx outputs and SDI input. RD only triggers when CS is low.
19
11
CS
Chip select. When low, the SDOx outputs are active; when high, the SDOx outputs 3-state.
20
12
CLOCK
21
13
BUSY
ADC busy indicator. BUSY goes high when the inputs are in hold mode and returns to low after the
conversion has been finished.
22
14
SDOB
Serial data output for converter B. Data are valid on the falling edge of CLOCK.
23
15
SDOA
Serial data output for converter A. When M1 is high, both SDOA and SDOB are active. Data are valid on
the falling edge of CLOCK.
24
16
BVDD
Buffer I/O supply, 2.7V to 5.5V. Decouple to BGND with a 1µF ceramic capacitor.
Reference voltage output. The programmable internal voltage reference output is available on this pin.
External clock input
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Equivalent Input Circuit
RSER = 200W
RSW = 50W
CHXX+
CPAR = 5pF
CS = 2pF
CPAR = 5pF
CS = 2pF
CHXXRSER = 200W
RSW = 50W
TIMING CHARACTERISTICS
Conversion 1
Conversion 2
tCKH
CLOCK
0
1
2
3
4
5
6
7
8
tCKL
9
10
11
12
13
14
15
t1
16
1
2
3
C1
C0
P1
4
t6
CONVST
t11
t12
tCONV
BUSY
t4
tACQ
t5
t7
RD
t3
C1
C0
P1
P0
SERIAL
DATA A
0
0
D11
D10
SERIAL
DATA B
0
0
D11
D10
SDI
DP
t2
A1
A0
D4
D3
D2
D1
D0
0
0
0
0
D11
D4
D3
D2
D1
D0
0
0
0
0
D11
N
AN
RP
S4
A2
D9
D8
D7
D6
D5
D9
D8
D7
D6
D5
t13
CS
t8
t9
t10
Figure 1. Detailed Timing Diagram (Mode I)
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TIMING CHARACTERISTICS (continued)
CLOCK
Cycle 1
Cycle 2
10ns
10ns
5ns
CONVST
5ns
B
A
C
NOTE: All CONVST commands that occur more than 10ns before the rising edge of cycle ‘1’ of the external clock
(Region ‘A’) initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands that occur 5ns after the rising
edge of cycle ‘1’ or 10ns before the rising edge of cycle 2 (Region ‘B’) initiate a conversion on the rising edge of cycle
‘2’. All CONVST commands that occur 5ns after the rising edge of cycle ‘2’ (Region ‘C’) initiate a conversion on the
rising edge of the next clock period.
The CONVST pin should never be switched from LOW to HIGH in the region 10ns prior to the rising edge of the
CLOCK and 5ns after the rising edge (gray areas). If CONVST is toggled in this gray area, the conversion could begin
on either the same rising edge of the CLOCK or the following edge.
Figure 2. CONVST Timing
TIMING REQUIREMENTS (1)
Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5V, and BVDD = 2.7V to 5V, unless
otherwise noted.
ADS7863
SYMBOL
(1)
(2)
8
PARAMETER
COMMENTS
MIN
MAX
tCONV
Conversion time
fCLOCK = 32MHz
406.25
tACQ
Acquisition time
fCLOCK = 32MHz
62.5
fCLOCK
CLOCK frequency
See Figure 1
1
32
tCLOCK
1000
UNIT
ns
ns
MHz
CLOCK period
See Figure 1
31.25
tCKL
CLOCK low time
See Figure 1
9.4
ns
ns
tCKH
CLOCK high time
See Figure 1
9.4
ns
t1
CONVST high time
See Figure 1
20
ns
t2
SDI setup time to CLOCK falling edge
See Figure 1
10
ns
t3
SDI hold time to CLOCK falling edge
See Figure 1
5
ns
t4
RD high setup time to CLOCK falling edge
See Figure 1
10
ns
t5
RD high hold time to CLOCK falling edge
See Figure 1
5
ns
t6
CONVST low time
See Figure 1
1
tCLOCK
t7
RD low time relative to CLOCK falling edge
See Figure 1
1
tCLOCK
t8
CS low to SDOx valid
See Figure 1
13
t9
SDOx data setup time to CLOCK falling edge See Figure 1
t10
SDOx data hold time to CLOCK falling edge
See Figure 1
2
ns
t11
CONVST rising edge to BUSY high delay
(2)
See Figure 1
3
ns
t12
CLOCK rising edge to BUSY low delay
See Figure 1
3
ns
t13
CS low to RD high delay
See Figure 1
10
ns
ns
16
ns
All input signals are specified with tR = tF = 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2.
Not applicable in auto-NAP power-down mode.
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TYPICAL CHARACTERISTICS
Over entire supply voltage range, VREF = 2.5V (internal), fCLK = 32MHz, and tDATA = 2MSPS, unless otherwise noted.
INTEGRAL NONLINEARITY vs
DATA RATE
INTEGRAL NONLINEARITY vs
TEMPERATURE
1.0
1.00
0.8
0.75
0.6
0.50
0.2
INL (LSB)
INL (LSB)
Positive
Positive
0.4
0
-0.2
Negative
0.25
0
-0.25
Negative
-0.4
-0.50
-0.6
-0.75
-0.8
-1.0
0.50
0.75
1.00
1.25
1.50
1.75
-1.00
-40 -25 -10
2.00
5
Data Rate (MSPS)
20 35 50 65
Temperature (°C)
Figure 3.
110 125
DIFFERENTIAL NONLINEARITY vs CODE
1.00
1.00
0.75
0.75
0.50
0.50
0.25
0.25
DNL (LSB)
INL (LSB)
95
Figure 4.
INTEGRAL NONLINEARITY vs CODE
0
-0.25
0
-0.25
-0.50
-0.50
-0.75
-0.75
-1.00
-1.00
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
Code
2048
2560
3072
3584
4096
Code
Figure 5.
Figure 6.
DIFFERENTIAL NONLINEARITY vs
DATA RATE
DIFFERENTIAL NONLINEARITY vs
TEMPERATURE
1.0
1.00
0.8
0.75
0.6
Positive
0.4
0.50
Positive
DNL (LSB)
DNL (LSB)
80
0.2
0
-0.2
Negative
-0.4
0.25
0
-0.25
Negative
-0.50
-0.6
-0.75
-0.8
-1.0
0.50
0.75
1.00
1.25
1.50
1.75
2.00
-1.00
-40 -25 -10
Data Rate (MSPS)
Figure 7.
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
Over entire supply voltage range, VREF = 2.5V (internal), fCLK = 32MHz, and tDATA = 2MSPS, unless otherwise noted.
OFFSET ERROR AND OFFSET MATCH vs
ANALOG SUPPLY VOLTAGE
OFFSET ERROR AND OFFSET MATCH vs
TEMPERATURE
2.0
0.8
Offset and Offset Match (LSB)
Offset and Offset Match (LSB)
1.0
0.6
0.4
0.2
Offset Match
0
-0.2
Offset
-0.4
-0.6
-0.8
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
1.0
Offset Match
0.5
0
Offset
-0.5
-1.0
-1.5
-2.0
-40 -25 -10
-1.0
2.7
1.5
5.5
5
AVDD (V)
20 35 50 65
Temperature (°C)
80
95
Figure 9.
Figure 10.
GAIN ERROR AND GAIN MATCH vs
ANALOG SUPPLY VOLTAGE
GAIN ERROR AND GAIN MATCH vs
TEMPERATURE
0.10
110 125
0.20
Gain and Gain Match (%)
Gain and Gain Match (%)
0.15
0.05
Gain Match
0
Gain
-0.05
0.10
Gain Match
0.05
0
Gain
-0.05
-0.10
-0.15
-0.20
-40 -25 -10
-0.10
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.5
5
95
110 125
COMMON-MODE REJECTION RATIO vs
ANALOG SUPPLY VOLTAGE
COMMON-MODE REJECTION RATIO vs
TEMPERATURE
74.0
73.5
73.5
73.0
73.0
72.5
72.5
72.0
71.5
72.0
71.5
71.0
71.0
70.5
70.5
70.0
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.5
70.0
-40 -25 -10
AVDD (V)
Figure 13.
10
80
Figure 12.
74.0
2.7
20 35 50 65
Temperature (°C)
Figure 11.
CMRR (dB)
CMRR (dB)
AVDD (V)
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
Over entire supply voltage range, VREF = 2.5V (internal), fCLK = 32MHz, and tDATA = 2MSPS, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 100kHz, fSAMPLE = 1.5MSPS)
0
0
-20
-20
-40
-40
Amplitude (dB)
Amplitude (dB)
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 100kHz)
-60
-80
-60
-80
-100
-100
-120
-120
-140
-140
0
200k
400k
600k
800k
1M
0
100
200
300
Frequency (Hz)
400
500
600
700 750
Frequency (kHz)
Figure 15.
Figure 16.
SIGNAL-TO-NOISE RATIO AND DISTORTION
vs INPUT SIGNAL FREQUENCY
SIGNAL-TO-RATIO AND DISTORTION
vs TEMPERATURE
74
73.0
73
72.5
72
SINAD (dB)
SINAD (dB)
AVDD = 5V
AVDD = 2.7V
71
70
72.0
AVDD = 5V
71.5
AVDD = 2.7V
71.0
69
70.5
68
20
40
60
80
100
120
140
160
180
70.0
-40 -25 -10
200
5
fIN (kHz)
80
Figure 17.
Figure 18.
SIGNAL-TO-NOISE RATIO
vs INPUT SIGNAL FREQUENCY
SIGNAL-TO-NOISE RATIO
vs TEMPERATURE
74
95
110 125
95
110 125
73.0
73
72.5
AVDD = 5V
AVDD = 5V
72
72.0
AVDD = 2.7V
SNR (dB)
SNR (dB)
20 35 50 65
Temperature (°C)
71
71.5
70
71.0
69
70.5
68
20
40
60
80
100
120
140
160
180
200
AVDD = 2.7V
70.0
-40 -25 -10
fIN (kHz)
Figure 19.
5
20 35 50 65
Temperature (°C)
80
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
Over entire supply voltage range, VREF = 2.5V (internal), fCLK = 32MHz, and tDATA = 2MSPS, unless otherwise noted.
TOTAL HARMONIC DISTORTION
vs INPUT SIGNAL FREQUENCY
TOTAL HARMONIC DISTORTION
vs TEMPERATURE
-78
-76
-78
AVDD = 5V
-80
AVDD = 2.7V
-82
AVDD = 2.7V
-82
THD (dB)
THD (dB)
-80
-84
-86
-84
AVDD = 5V
-86
-88
-88
-90
-90
-40 -25 -10
-92
20
fIN (kHz)
20 35 50 65
Temperature (°C)
Figure 21.
Figure 22.
SPURIOUS-FREE DYNAMIC RANGE
vs INPUT SIGNAL FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs TEMPERATURE
40
60
80
100
120
140
160
180
200
92
5
80
95
110 125
90
90
AVDD = 2.7V
88
AVDD = 5V
86
SFDR (dB)
SFDR (dB)
88
AVDD = 5V
84
82
86
84
AVDD = 2.7V
80
82
78
76
20
40
80
-40 -25 -10
fIN (kHz)
20 35 50 65
Temperature (°C)
Figure 23.
Figure 24.
ANALOG SUPPLY CURRENT
vs TEMPERATURE
DIGITAL SUPPLY CURRENT
vs TEMPERATURE
60
80
100
120
140
160
180
200
8
7
0.8
110 125
95
110 125
BVDD = 3.3V
0.7
BVDD (mA)
AVDD (mA)
95
0.9
AVDD = 5V
AVDD = 2.7V
4
3
0.6
0.5
0.4
BVDD = 2.7V
0.3
2
0.2
1
0.1
0
0
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
-40 -25 -10
Figure 25.
12
80
1.0
6
5
5
5
20 35 50 65
Temperature (°C)
80
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
Over entire supply voltage range, VREF = 2.5V (internal), fCLK = 32MHz, and tDATA = 2MSPS, unless otherwise noted.
ANALOG SUPPLY CURRENT
vs DATA RATE
(Auto-NAP Mode)
ANALOG SUPPLY CURRENT
vs TEMPERATURE
(Auto-NAP Mode)
6
1.4
1.2
5
AVDD = 5V
Reference ON
1.0
AVDD (mA)
AVDD (mA)
4
3
Reference OFF
AVDD = 2.7V
0.8
0.6
2
0.4
1
0.2
0
0
0
500
1000
1500
-40 -25 -10
2000
5
20 35 50 65
Temperature (°C)
Data Rate (kSPS)
95
Figure 27.
Figure 28.
ANALOG SUPPLY CURRENT
vs DATA RATE
(Deep Power-Down Mode)
REFERENCE OUTPUT VOLTAGE
vs TEMPERATURE
1400
110 125
2.505
2.504
1200
2.503
Clock ON
1000
2.502
VREFOUT (V)
AVDD (mA)
80
800
600
2.501
2.500
2.499
2.498
400
2.497
200
2.496
Clock OFF
0
2.495
0
10
20
30
40
50
60
70
-40 -25 -10
Data Rate (kSPS)
Figure 29.
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 30.
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APPLICATIONS INFORMATION
GENERAL DESCRIPTION
CHx1+
The ADS7863 includes two 12-bit analog-to-digital
converters (ADCs) that operate based on the
successive-approximation register (SAR) principle.
The ADCs sample and convert simultaneously.
Conversion time can be as low as 406.25ns. Adding
the acquisition time of 62.5ns and an additional clock
cycle for setup/hold time requirements and skew
results in a maximum conversion rate of 2MSPS.
Each ADC has a fully differential, 2:1 multiplexer
front-end. In many common applications, all negative
input signals remain at the same constant voltage (for
example, 2.5V). In this type of application, the
multiplexer can be used in a pseudo-differential 3:1
mode, where CHx0– functions as a common-mode
input and the remaining three inputs (CHx0+, CHx1–,
and CHx1+) operate as separate inputs referred to
the common-mode input.
The ADS7863 also includes a 2.5V internal reference.
The reference drives a 10-bit digital-to-analog
converter (DAC), allowing the voltage at the REFOUT
pin to be adjusted via the serial interface in 2.44mV
steps. A low-noise operational amplifier with unity
gain buffers the DAC output voltage and drives the
REFOUT pin.
The ADS7863 offers a serial interface that is
compatible with the ADS7861. However, instead of
the A0 pin of the ADS7861 that controls the channel
selection, the ADS7863 offers a serial data input
(SDI) pin that supports additional functions described
in the Digital section of this data sheet (see also the
ADS7861 Compatibility section).
ANALOG
This section addresses the analog input circuit, the
ADCs, and the reference design of the device.
Analog Inputs
Each ADC is fed by an input multiplexer; see
Figure 31. Each multiplexer is either used in a
fully-differential 2:1 configuration (as described in
Table 1) or a pseudo-differential 3:1 configuration (as
shown in Table 2). The channel selection is
performed using bits C1 and C0 in the SDI register
(see also the Serial Data Input section).
14
CHx1-
Input
MUX
CHx0+
ADC+
ADC-
CHx0-
Figure 31. Input Multiplexer Configuration
The input path for the converter is fully differential
and provides a common-mode rejection of 72dB at
100kHz. The high CMRR also helps suppress noise
in harsh industrial environments.
Table 1. Fully Differential 2:1 Multiplexer
Configuration
C1
C0
ADC+
ADC–
0
0
CHx0+
CHx0–
1
1
CHx1+
CHx1–
Table 2. Pseudo-Differential 3:1 Multiplexer
Configuration
C1
C0
ADC+
ADC–
0
0
CHx0+
CHx0–
0
1
CHx1–
CHx0–
1
0
CHx1+
CHx0–
Each of the 2pF sample-and-hold capacitors (shown
as CS in the Equivalent Input Circuit) is connected via
switches to the multiplexer output. Opening the
switches holds the sampled data during the
conversion process. After finishing the conversion,
both capacitors are pre-charged for the duration of
one clock cycle to the voltage present at the REFIN
pin. After the pre-charging, the multiplexer outputs
are connected to the sampling capacitors again. The
voltage at the analog input pin is usually different
from the reference voltage; therefore, the sample
capacitors must be charged to within one-half LSB for
12-bit accuracy during the acquisition time tACQ (see
the Timing Characteristics).
Acquisition time is indicated with the BUSY signal
being held low. It starts by closing the input switches
(after finishing the previous conversion and
pre-charging) and finishes with the rising edge of the
CONVST signal. If the ADS7863 operates at full
speed, the acquisition time is typically 62.5ns.
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The minimum –3dB bandwidth of the driving
operational amplifier can be calculated as shown in
Equation 1, with n = 12 being the resolution of the
ADS7863:
ln(2) ´ (n + 1)
f-3dB =
2p ´ tACQ
(1)
With tACQ = 62.5ns, the minimum bandwidth of the
driving amplifier is 23MHz. The required bandwidth
can be lower if the application allows a longer
acquisition time.
A gain error occurs if a given application does not
fulfill the settling requirement shown in Equation 1. As
a result of precharging the capacitors, linearity and
THD are not directly affected, however.
CLOCK
The ADC uses an external clock in the range of
1MHz to 32MHz. 12 clock cycles are needed for a
complete conversion; the following clock cycle is used
for pre-charging the sample capacitors and a
minimum of two clock cycles are required for the
sampling. With a minimum of 16 clocks used for the
entire process, one clock cycle is left for the required
setup and hold times along with some margin for
delay caused by layout. The clock input can remain
low between conversions (after applying the 16th
falling edge to complete a running conversion). It can
also remain low after applying the 14th falling edge
during a DAC register write access if the device is not
required to perform a conversion on CHBx (for
example, during an initiation phase after power-up).
The
OPA365
from
Texas
Instruments
is
recommended as a driver; in addition to offering the
required bandwidth, it provides a low offset and also
offers excellent THD performance.
The CLOCK duty cycle should be 50%. However, the
ADS7863 functions properly with a duty cycle
between 30% and 70%.
The phase margin of the driving operational amplifier
is usually reduced by the ADC sampling capacitor. A
resistor placed between the capacitor and the
amplifier limits this effect; therefore, an internal 200Ω
resistor (RSER) is placed in series with the switch. The
switch resistance (RSW) is typically 50Ω (see
Equivalent Input Circuit).
RESET
The differential input voltage range of the ADC is
±VREF, the voltage at the REFIN pin.
The reference input is not buffered and is directly
connected to the ADC. The converter generates
spikes on the reference input voltage because of
internal switching. Therefore, an external capacitor to
the analog ground (AGND) should be used to
stabilize the reference input voltage. This capacitor
should be at least 470nF. Ceramic capacitors (X5R
type) with values up to 1µF are commonly available
as SMD in 0402 size.
It is important to keep the voltage to all inputs within
the 0.3V limit below AGND and above AVDD while not
allowing dc current to flow through the inputs. Current
is only necessary to recharge the sample-and-hold
capacitors.
Analog-to-Digital Converter (ADC)
The ADS7863 includes two SAR-type, 2MSPS, 12-bit
ADCs (shown in the Functional Block Diagram on the
front page of this data sheet).
CONVST
The analog inputs are held with the rising edge of the
CONVST (conversion start) signal. The setup time of
CONVST referred to the next rising edge of CLOCK
(system clock) is 10ns (minimum). The conversion
automatically starts with the rising CLOCK edge.
CONVST should not be issued during a conversion,
that is, when BUSY is high.
RD (read data) and CONVST can be shorted to
minimize necessary software and wiring. The RD
signal is triggered by the ADS7863 on the falling
edge of CLOCK. Therefore, the combined signals
must be activated with the rising CLOCK edge. The
conversion then starts with the subsequent rising
CLOCK edge.
The ADS7863 features an internal power-on reset
(POR) function. However, an external reset can also
be issued using SDI Register bits A[2:0] (see the
Digital section).
REFIN
REFOUT
The ADS7863 includes a low-drift, 2.5V internal
reference source. This source feeds a 10-bit string
DAC that is controlled via the serial interface. As a
result of this architecture, the voltage at the REFOUT
pin is programmable in 2.44mV steps and can be
adjusted to specific application requirements without
the use of additional external components.
However, the DAC output voltage should not be
programmed below 0.5V to ensure the correct
functionality of the reference output buffer. This buffer
is connected between the DAC and the REFOUT pin,
and is capable of driving the capacitor at the REFIN
pin. A minimum of 470nF is required to keep the
reference stable (see the previous discussion of
REFIN above). For applications that use an external
reference source, the internal reference can be
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disabled using bit RP in the SDI Register (see the
Digital section). The settling time of the REFOUT pin is
500µs, maximum with the reference capacitor
connected. The default value of the REFOUT pin after
power-up is 2.5V.
Table 5. P1 and P0: Additional Features Enable
For operation with a 2.7V analog supply and a 2.5V
reference, the internal reference buffer requires a
rail-to-rail input and output. Such buffers typically
contain two input stages; when the input voltage
passes the mid-range area, a transition occurs at the
output because of switching between the two input
stages. In this voltage range, rail-to-rail amplifiers
generally show a very poor power-supply rejection.
DIGITAL
9
8
7
6
5
4
3
2
1
0
C1
C0
P1
P0
DP
N
AN
RP
S4
A2
A1
A0
ADC A/B
C0
POSITIVE INPUT
NEGATIVE INPUT
0
0
CHA0+/CHB0+
CHA0–/CHB0–
0
1
CHA1–/CHB1–
CHA0–/CHB0–
1
0
CHA1+/CHB1+
CHA0–/CHB0–
1
1
CHA1+/CHB1+
CHA1–/CHB1–
Additional features are not changed
1
Update additional features
1
0
Reserved for factory test (do not
use)
1
1
Additional features are not changed
A1
A0
0
0
No action
FUNCTION
0
0
1
DAC write with next access
0
1
0
No action
0
1
1
DAC read with next access
1
0
0
No action
1
0
1
Device reset
1
1
0
No action
1
1
1
No action
All additional features become active with the rising
edge of the 12th CLOCK signal after issuing the RD
pulse.
The reference DAC is controlled by the 12-bit DAC
register that can also be accessed using the SDI pin
(see Figure 40 for details). Table 7 shows the content
of this register; the default value after power-up is
0x3FF.
Table 4. C1 and C0: Channel Selection
C1
0
0
0
Table 3. SDI Register Contents
10
0
A2
The serial data input or SDI pin is coupled to RD and
clocked into the ADS7863 on each falling edge of
CLOCK. The data word length of the SDI Register is
12 bits. Table 3 shows the register structure. The
data must be transferred MSB-first. Table 4 through
Table 6 describe specific bits of this register. The
default value of this register after power-up is 0x000.
11
FUNCTION
Table 6. A2, A1, and A0: DAC Control and Device
Reset
Serial Data Input (SDI)
SDI REGISTER BIT
P0
DP: Deep power-down enable ('1' = device in
deep power-down mode)
N: Nap power-down enable ('1' = device in Nap
power-down mode)
AN: AutoNap power-down enable ('1' = device in
AutoNap power-down mode)
RP: Reference power-down ('1' = reference
turned off)
S4: Special read mode for Modes II and IV
('1' = special mode enabled)
As a result of this poor performance, the ADS7863
buffer has a fixed transition at DAC code 509
(0x1FD). At this code, the DAC may show a jump of
up to 10mV in its transfer function.
This section addresses the timing and control of the
ADS7863 serial interface.
P1
Table 7. DAC Register Contents
DAC REGISTER CONTENT
(1)
16
11
10
9
8
7
6
5
4
3
2
1
0
X (1)
X
MSB
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X = don't care.
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Serial Data Output (SDOx)
Converted data on the SDOx pins become valid with
the third falling CLOCK edge after generating an RD
pulse. The following sections explain the different
modes of operation in detail.
The digital output code format of the ADS7863 is
binary two's complement, as shown in Table 9.
Timing and Control
IMPORTANT:
Consider the Detailed Timing Diagram (Figure 1)
and CONVST timing diagram (Figure 2) shown in
the Timing Characteristics section. For maximum
data throughput, the descriptions and diagrams
given in this data sheet assume that the
CONVST and RD pins are tied together. Note
that they can also be controlled independently.
The operation of the ADS7863 can be configured in
four different modes by using the mode pins M0 and
M1, as shown in Table 8.
Pin M0 sets either manual or automatic channel
selection. In manual mode, the SDI register bits
C[1:0] are used to select between channels CHx0
and CHx1; in automatic operation, the SDI register
bits C[1:0] are ignored and channel selection is
controlled by the device after each conversion. Pin
M1 selects between serial data being transmitted
simultaneously on both outputs SDOA and SDOB for
each channel respectively, or using only the SDOA
output for transmitting data from both channels (see
Figure 32 through Figure 39 and the associated text
for more information).
Table 8. M0/M1 Truth Table
CHANNEL
SELECTION
M0
M1
SDOx USED
0
0
Manual (via SDI)
SDOA and SDOB
0
1
Manual (via SDI)
SDOA only
1
0
Automatic
SDOA and SDOB
1
1
Automatic
SDOA only
Additionally, the SDI pin is used for controlling device
functionality; see the Serial Data Input section for
details.
Table 9. ADS7863 Output Data Format
DESCRIPTION
DIFFERENTIAL INPUT VOLTAGE
(CHXX+) – (CHXX–)
INPUT VOLTAGE AT CHXX+
(CHXX– = VREF = 2.5V)
BINARY CODE
HEXADECIMAL
CODE
Positive full-scale
VREF
5V
0111 1111 1111
7FF
Mid-scale
0V
2.5V
0000 0000 0000
000
Mid-scale – 1LSB
–VREF/4096
2.49878V
1111 1111 1111
FFF
Negative
full-scale
–VREF
0V
1000 0000 0000
800
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MODE I
With the M0 and M1 pins both set to '0', the ADS7863
enters manual channel control operation and outputs
data on both SDOA and SDOB, respectively. The SDI
pin switches between the channels. A conversion is
initiated by bringing CONVST high.
16 clock cycles are required to perform a single
conversion. With the rising edge of CONVST, the
ADS7863 switches asynchronously to the external
CLOCK from sample to hold mode.
1
After some delay (t12), the BUSY output pin goes high
and remains high for the duration of the conversion
cycle. On the falling edge of the second CLOCK
cycle, the ADS7863 latches in the channel for the
next conversion cycle, depending on the status of the
SDI Register bits C[1:0]. CS must be brought low to
enable both serial outputs. Data are valid on the
falling edge of every 16 clock cycles per conversion.
The first two bits are set to '0'. The subsequent data
contain the 12-bit conversion result (the most
significant bit is transferred first), followed by two '0's
(see Figure 1 and Figure 32).
16 1
16
CLOCK
CONVST
SDI
C[1:0] = '11' ® Convert CHx1 Next
P[1:0] = '11' ® SDI Features Not Used
C[1:0] = '00' ® Convert CHx0 Next
P[1:0] = '00' ® SDI Features Not Used
C[1:0] = '00' ® Convert CHx0 Next
P[1:0] = '00' ® SDI Features Not Used
M0
M1
RD
CS
High-Z
SDOA
0 0
Previous 12-Bit Data CHAx
0 0 0 0
12-Bit Data CHA1
0 0
SDOB
0 0
Previous 12-Bit Data CHBx
0 0 0 0
12-Bit Data CHB1
0 0
High-Z
BUSY
Previous Conversion of Both CHxx
0ms
Conversion of Both CHx1
0.5ms
Conversion of Both CHx0
1.0ms
Figure 32. Mode I Timing Diagram (M0 = 0; M1 = 0)
18
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MODE II
from both ADCs (instead of 16 cycles, if M1 = '0'), the
ADS7863 requires 1.0µs to perform a complete
conversion/read cycle. If the CONVST signal is
issued every 0.5µs (required for the RD signal) as in
Mode I, every second pulse is ignored; see Figure 33.
With M0 = '0' and M1 set to '1', the ADS7863 also
operates in manual channel control mode and outputs
data on the SDOA pin only while SDOB is set to
3-state. All other pins function in the same manner as
they do in Mode I.
The output data consist of a '0' followed by an ADC
indicator ('0' for CHAx or '1' for CHBx), 12 bits of
conversion results, and another '00'.
Because it takes 32 clock cycles to output the results
16
1
1
16
1
16
1
16
1
16
1
1
CLOCK
Every 2nd
CONVST
Is Ignored
CONVST
Every 2nd
CONVST
Is Ignored
Every 2nd
CONVST
Is Ignored
SDI
C[1:0] = '00' ® CHx0 Next
P[1:0] = '00' ® No Features
C[1:0] Is Ignored
P[1:0] = '00’ ® No Features
C[1:0] = '11’ ® CHx1 Next
P[1:0] = '11’ ® No Features
C[1:0] Is Ignored
P[1:0] = '11’ ® No Features
C[1:0] = '00' ® CHx0 Next
P[1:0] = '00’ ® No Features
C[1:0] Is Ignored
P[1:0] = '00’ ® No Features
M0
M1
RD
CS
CHx
B
Previous 12-Bit
Data CHAx
SDOA
A
B
12-Bit
Data CHB0
12-Bit
Data CHA0
A
12-Bit
Data CHB1
12-Bit
Data CHA1
A
12-Bit
Data CHA0
CHx
BUSY
High-Z
Previous 12-Bit
Data
DataCHBx
CHBx
SDOB
Previous Conversion
of Both CHxx
0ms
No Conversion,
Read Access Only
Conversion
of Both CHx0
0.5ms
1.0ms
No Conversion,
Read Access Only
Conversion
of Both CHx1
1.5ms
2.0ms
Conversion
of Both CHx0
2.5ms
3.0ms
Figure 33. Mode II Timing Diagram (M0 = 0; M1 = 1)
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MODE III
With M0 set to '1' and M1 = '0', the ADS7863
automatically cycles between the differential inputs
(ignoring the SDI register bits C[1:0]) while offering
the conversion result of CHAx on SDOA and the
conversion result of CHBx on SDOB (see Figure 34).
1
Output data consist of a channel indicator ('0' for
CHx0 or '1' for CHx1), followed by a '0', 12 bits of
conversion results, and another '00'.
16 1
16
CLOCK
CONVST
SDI
C[1:0] is ignored
P[1:0] = ‘00’ ® SDI features are not used
M0
C[1:0] is ignored
P[1:0] = ‘11’ ® SDI features are not used
C[1:0] is ignored
P[1:0] = ‘11’ ® SDI features are not used
Both channel 0s are converted first,
followed by conversion of both channel 1s.
M1
RD
CS
CH1
Previous 12-Bit Data CHAx
SDOA
CH0
12-Bit Data CHA1
12-Bit Data CHA0
CH1
Previous 12-Bit Data CHBx
SDOB
BUSY
CH0
Previous Conversion of Both CHxx
0ms
12-Bit Data CHB1
12-Bit Data CHB0
Conversion of Both CHx0
0.5ms
Conversion of Both CHx1
1.0ms
Figure 34. Mode III Timing Diagram (M0 = 1; M1 = 0)
20
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MODE IV
In the same way as Mode II, Mode IV uses the SDOA
output line exclusively to transmit data while the
differential channels are switched automatically.
Following the first conversion after M1 goes high, the
SDOB output 3-states (see Figure 35).
16
1
1
16
1
Output data consist of a channel indicator ('0' for
CHx0 or '1' for CHx1), followed by the ADC indicator
('0' for CHAx or '1' for CHBx), 12 bits of conversion
results, and end with '00'.
16
16
1
16
1
1
1
CLOCK
Every 2nd
CONVST
Is Ignored
CONVST
Every 2nd
CONVST
Is Ignored
Every 2nd
CONVST
Is Ignored
SDI
C[1:0] is Ignored
P[1:0] = '00' ® No Features
C[1:0] is Ignored
P[1:0] = '00' ® No Features
C[1:0] is Ignored
P[1:0] = '00' ® No Features
C[1:0] is Ignored
P[1:0] = '00' ® No Features
C[1:0] is Ignored
P[1:0] = '00' ® No Features
C[1:0] is Ignored
P[1:0] = '00' ® No Features
M0
M1
Both channel 0s are converted first,
followed by conversion of both channel 1s.
RD
CS
CHx
0A
Previous 12-Bit
Data CHAx
SDOA
0B
1A
12-Bit
Data CHB0
12-Bit
Data CHA0
1B
12-Bit
Data CHA1
0A
12-Bit
Data CHA0
12-Bit
Data CHB1
CHx
SDOB
Previous 12-Bit
Data CHBx
BUSY
Previous Conversion
of Both CHxx
0m s
High-Z
Conversion
of Both CHx0
0.5ms
Conversion
of Both CHx1
No Conversion,
Read Access Only
1.0ms
1.5ms
Conversion
of Both CHx0
No Conversion,
Read Access Only
2.0ms
2.5ms
3.0ms
Figure 35. Mode IV Timing Diagram (M0 = 1 ; M1 = 1)
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SPECIAL MODE II (Not ADS7861-Compatible)
For Mode II, a special read mode is available in the
ADS7863 where both data results can be read out,
triggered by a single RD pulse. To activate this mode,
bit S4 in the SDI Register must be set to '1' (see also
the Serial Data Input section).
16
1
1
16
1
The CONVST and RD pins can remain tied together,
but do not need to be issued every 16 CLOCK
cycles. Output data are presented on both terminals,
SDOA and SDOB. Figure 36 illustrates the special
read mode.
16
1
16
1
16
1
1
CLOCK
CONVST
SDI
C[1:0] = '00' ® CHx0
P[1:0] = '01' ® Features ON
® S4 = '1'
C[1:0] = '11' ® CHx1
P[1:0] = '11' ® No Updates
® S4 Still = '1'
C[1:0] = '11' ® CHx1
P[1:0] = '11' ® No Updates
® S4 Still = '1'
C[1:0] = '11' ® CHx1
P[1:0] = '11' ® No Updates
® S4 Still = '1'
M0
M1
RD
CS
B
SDOA
Previous 12-Bit
Data CHAx
SDOB
Previous 12-Bit
Data CHBx
BUSY
Previous Conversion
of Both CHxx
0ms
A
B
12-Bit
Data CHB0
12-Bit
Data CHA0
A
12-Bit
Data CHA1
12-Bit
Data CHB1
A
12-Bit
Data CHA1
High-Z
Conversion
of Both CHx0
0.5ms
Conversion
of Both CHx1
No Conversion,
Read Access Only
1.0ms
1.5ms
Conversion
of Both CHx1
No Conversion,
Read Access Only
2.0ms
2.5ms
3.0ms
Figure 36. Special Mode II Timing Diagram (M0 = 0; M1 = 1; S4 = 1)
22
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SPECIAL MODE IV (Not ADS7861-Compatible)
Analogous to Special Mode II, the ADS7863 also
offers a special read mode for Mode IV in which both
data results of a conversion can be read, triggered by
a single RD pulse. In this case as well, bit S4 in the
SDI register must be set to '1' while the CONVST and
RD pins can still be tied together .
16
1
1
16
1
As with Special Mode II, these two pins do not need
to be issued every 16 CLOCK cycles. Data are
available on the SDOA pin.
This special read mode (shown in Figure 37) is not
available in Mode I or Mode III.
16
1
16
1
16
1
1
CLOCK
CONVST
SDI
C[1:0] is Ignored
P[1:0] = '01' ® Features ON
® S4 = '1'
C[1:0] is Ignored
P[1:0] = '11' ® No Updates
® S4 Still = '1'
C[1:0] is Ignored
P[1:0] = '11' ® No Updates
® S4 Still = '1'
C[1:0] is Ignored
P[1:0] = '11' ® No Updates
® S4 Still = '1'
M0
M1
Both channel 0s are converted first,
followed by conversion of both channel 1s.
RD
CS
CHX
0A
Previous 12-Bit
Data CHAx
SDOA
0B
1A
12-Bit
Data CHB0
12-Bit
Data CHA0
1B
12-Bit
Data CHA1
0A
12-Bit
Data CHA0
12-Bit
Data CHB1
CHX
BUSY
High-Z
Previous 12-Bit
Data CHBx
SDOB
Conversion
of Both CHx0
Previous Conversion
of Both CHxx
0ms
0.5ms
Conversion
of Both CHx1
No Conversion,
Read Access Only
1.0ms
1.5ms
Conversion
of Both CHx0
No Conversion,
Read Access Only
2.0ms
2.5ms
3.0ms
Figure 37. Special Mode IV Timing Diagram (M0 = 1; M1 = 1; S4 = 1)
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PSEUDO-DIFFERENTIAL MODE I
(Not ADS7861-Compatible)
In Mode I, the ADS7863 input multiplexers can also
operate in a pseudo-differential manner. In this case,
SDI bits C[1:0] are used to choose the channels
accordingly.
16
1
1
16
1
For more details, see the Serial Data Input section.
Data are available on both output terminals, SDOA
and SDOB.
The input multiplexer cannot be used for
pseudo-differential signals in Mode III or Mode IV.
16
1
16
1
16
1
1
CLOCK
CONVST
SDI
C[1:0] = '00' ® CHx0+/CHx0P[1:0] = '00' ® Features OFF
C[1:0] = '01' ® CHx1-/CHx0P[1:0] = '11' ® Features OFF
C[1:0] = '10' ® CHx1+/CHx0P[1:0] = '00' ® Features OFF
C[1:0] = '00' ® CHx0+/CHx0P[1:0] = '00' ® Features OFF
C[1:0] = '01' ® CHx1-/CHx0P[1:0] = '11' ® Features OFF
C[1:0] = '10' ® CHx1+/CHx0P[1:0] = '00' ® Features OFF
SDOA
Previous 12-Bit
Data CHAx
12-Bit Data
CHA0+/CHA0-
12-Bit Data
CHA1-/CHA0-
12-Bit Data
CHA1+/CHA0-
12-Bit Data
CHA0+/CHA0-
12-Bit Data
CHA1-/CHA0-
SDOB
Previous 12-Bit
Data CHBx
12-Bit Data
CHB0+/CHB0-
12-Bit Data
CHB1-/CHB0-
12-Bit Data
CHB1+/CHB0-
12-Bit Data
CHB0+/CHB0-
12-Bit Data
CHB1-/CHB0-
BUSY
Previous Conversion
of Both CHxx
Conversion of Both
CHx0+/CHx0-
Conversion of Both
CHx1-/CHx0-
Conversion of Both
CHx1+/CHx0-
M0
M1
RD
CS
0 ms
0.5ms
1.0ms
1.5ms
Conversion of Both
CHx0+/CHx02.0ms
Conversion of Both
CHx1-/CHx02.5ms
3.0ms
Figure 38. Pseudo-Differential Mode I (M0 = 0; M1 = 0)
24
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PSEUDO-DIFFERENTIAL MODE II
(Not ADS7861-Compatible)
Channel switching is performed by setting the C[1:0]
bits in the SDI Register accordingly (see also the
Serial Data Input section).
In Mode II, the ADS7863 input multiplexers can also
operate in a pseudo-differential configuration. In this
case, output data are available on terminal SDOA
only, while SDOB is held in 3-state.
16
1
1
16
1
The input multiplexer cannot be used for
pseudo-differential signals in Mode III or Mode IV.
16
1
16
1
16
1
1
CLOCK
Every 2nd
CONVST
Is Ignored
CONVST
Every 2nd
CONVST
Is Ignored
Every 2nd
CONVST
Is Ignored
SDI
C[1:0] = '00' ® CHx0+/CHx0-
C[1:0] Is Ignored
C[1:0] = '01' ® CHx1-/CHx0-
C[1:0] Is Ignored
C[1:0] = '10' ® CHx1+/CHx0-
C[1:0] Is Ignored
P[1:0] = '00' ® Features OFF
P[1:0] = '00' ® Features OFF
P[1:0] = '11' ® Features OFF
P[1:0] = '11’ ® Features OFF
P[1:0] = '00' ® Features OFF
P[1:0] = '00’ ® Features OFF
M0
M1
RD
CS
B
SDOA
Previous 12-Bit
Data CHAx
SDOB
Previous 12-Bit
Data CHBx
BUSY
Previous Conversion
of Both CHxx
0m s
A
B
12-Bit Data
CHB0+/CHB0-
12-Bit Data
CHA0+/CHA0-
12-Bit Data
CHA1+/CHA0-
12-Bit Data
CHA1-/CHA0-
12-Bit Data
CHB1-/CHB0-
A
Conversion of Both
CHx1-/CHx0-
No Conversion,
Read Data Only
Conversion of Both
CHx1+/CHx0-
A
High-Z
Conversion of Both
CHx0+/CHx00.5ms
No Conversion,
Read Data Only
1.0ms
1.5ms
2.0ms
2.5ms
3.0ms
Figure 39. Pseudo-Differential Mode II (M0 = 0; M1 = 1)
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Programming the Reference DAC
(Not ADS7861-Compatible)
The internal reference DAC can be set by issuing an
RD pulse while providing an SDI word with P[1:0] =
'01' and A[2:0] = '001'. Thereafter, a second RD pulse
must be generated with an SDI word starting with the
first two bits being ignored, followed by the actual
10-bit DAC value (see Figure 40).
SDOA output to send '0000' followed by the 10-bit
DAC value and another '00'. During the second RD
access, data present on SDI are ignored, while in
Mode I and Mode III valid conversion data for channel
B are present on SDOB; the conversion results of
channel A are lost. The default value of the DAC
register after power-up is 0x3FF, corresponding to a
reference voltage of 2.5V on the REFOUT pin.
To verify the DAC setting, an RD pulse must be
generated while providing an SDI word containing
P[1:0] = '01' and A[2:0] = '011' to initialize the DAC
read access. Triggering the RD line again causes the
16
1
1
16
1
16
1
16
1
16
1
1
CLOCK
CONVST
10-Bit
DAC Value
SDI
C[1:0] = '00' ® CHx0 is Next
P[1:0] = '01' ® Features ON
A[2:0] = '001' ® Write DAC
Data Interpreted as
DAC Value Only
C[1:0] = '11' ® CHx1 is Next
P[1:0] = '01' ® Features ON
A[2:0] = '011' ® Read DAC
SDOA
Previous 12-Bit
Data CHAx
12-Bit
Data CHA0
12-Bit
Data CHA0
SDOB
Previous 12-Bit
Data CHBx
12-Bi
Data CHB0
12-Bit
Data CHB0
BUSY
Previous Conversion
of Both CHxx
SDI Data Ignored
C[1:0] = '00' ® CHx0 is Next C[1:0] = '00' ® CHx0 is Next
P[1:0] = '00’ ® No Features P[1:0] = '00’ ® No Features
M0
M1
RD
CS
0ms
Conversion of
Both CHx0
0.5ms
10-Bit
DAC Value
12-Bit
Data CHB1
Conversion of
Both CHx0
1.0ms
12-Bit
Data CHA0
12-Bit
Data CHB1
12-Bit
Data CHB0
Conversion of
Both CHx1
Conversion of
Both CHx1
1.5ms
12-Bit
Data CHA1
2.0ms
Conversion of
Both CHx0
2.5ms
3.0ms
Figure 40. DAC Write and Read Access Timing Diagram
26
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Power-Down Modes and Reset
(Not ADS7861-Compatible)
The ADS7863 has a comprehensive built-in
power-down feature. There are three power-down
modes: deep power-down, nap power-down, and
auto-nap power-down. All three power-down modes
are activated with the 12th falling CLOCK edge of the
SDI access, during which the related bit asserts (DP
= '1', N = '1', or AN = '1'). All modes are deactivated
by de-asserting the respective bit in the SDI Register.
Contents of the SDI Register are not affected by any
of the power-down modes. Any ongoing conversion
aborts when deep or nap power-down is initiated.
Table 10 lists the differences among the three
power-down modes.
In deep power-down mode, all functional blocks
except the digital interface are disabled. The analog
block has its bias currents turned off. In this mode,
the power dissipation reduces to 1µA within 2µs. The
wake-up time from deep power-down mode is 1µs.
In nap power-down mode, the ADS7863 turns off
the biasing of the comparator and the mid-voltage
buffer within 200ns. The device goes into nap
power-down mode regardless of the conversion state.
The auto-nap power-down mode is very similar to
the nap mode. The only differences are the methods
of powering down and waking up the device. The SDI
Register bit AN is only used to enable/disable this
feature. If the auto-nap mode is enabled, the
ADS7863 turns off the biasing automatically after
finishing a conversion; thus, the end of conversion
actually activates the auto-nap power-down. The
device powers down within 200ns in this mode, as
well. Triggering a new conversion by applying a
CONVST pulse puts the device back into normal
operation and automatically starts a new conversion
six CLOCK cycles later. Therefore, a complete
conversion cycle takes 19 CLOCK cycles; thus, the
maximum throughput rate in auto-nap power-down
mode is reduced to 1.68MSPS.
To issue a device reset, an RD pulse must be
generated along with an SDI word containing A[2:0] =
'101'. With the 12th falling edge after generating the
RD pulse, the entire device—including the serial
interface—is forced into reset. After approximately
500ns, the serial interface becomes active again.
Table 10. Power-Down Modes
POWER-DOWN
TYPE
ENABLED
BY
ACTIVATED BY
ACTIVATION
TIME
RESUMED
BY
REACTIVATION TIME
DISABLED
BY
Deep
DP = ‘1’
13th clock
2µs
DP = ‘0’
1µs
DP = ‘0’
Nap
N = ‘1’
13th clock
200ns
N = ‘0’
3 clocks
N = ‘0’
Each end of
conversion
200ns
CONVST pulse
3 clocks
AN = ‘0’
Auto-nap
AN = ‘1’
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ADS7861 COMPATIBILITY
REFIN
The ADS7863IDBQ is pin-compatible with the
ADS7861E/EB/EG4. However, there are some
differences between the two devices that must be
considered when migrating from the ADS7861 to the
ADS7863 in an existing design.
The ADS7863 offers an unbuffered REFIN input with a
code-dependent input impedance while featuring a
programmable and buffered reference output
(REFOUT). The ADS7861 offers a high-impedance
(buffered)
reference
input.
If
an
existing
ADS7861-based design uses the internal reference of
the device and relies on an external resistor divider to
adjust the input voltage range of the ADC, migration
to ADS7863 requires one of the following conditions:
• a software change to setup the internal reference
DAC properly via SDI while removing the external
resistors; or
• an additional external buffer between the resistor
divider and the required 470nF (minimum)
capacitor on the REFIN input.
SDI versus A0
One of the differences is that pin 16 (A0), which
updates the internal SDI register of the ADS7863, is
used in conjunction with M0 to select the input
channel on the ADS7861.
If, in an existing design, the ADS7861 is used in
two-channel mode (M0 = '0') and the status of the A0
pin is unchanged within the first four clock cycles
after issuing a conversion start (rising edge of
CONVST), the ADS7863 would act similarly to the
ADS7861 and convert either channels CHx0 (if SDI is
held low during the entire period) or channels CHx1
(if SDI is held high during the entire period).
Figure 33 describes the behavior of the ADS7863 in
such a situation.
The ADS7863 can also be used to replace the
ADS7861 when run in four-channel mode (M0 = '1').
In this case, the A0 pin is held static (high or low)
which is also required in the case of SDI to prevent
accidental update of the SDI register.
In both cases described above, the additional
features of the ADS7863 (pseudo-differential input
mode, programmable reference voltage output, and
the different power-down modes) could not be
accessed but the hardware and software would
remain backward-compatible to the ADS7861.
28
In the latter case, while the capacitor stabilizes the
reference voltage during the entire conversion, the
buffer has to re-charge it by providing an average
current only; thus the required minimum bandwidth of
the buffer can be calculated using Equation 2:
ln(2) ´ 2
f-3dB =
2p ´ 16 ´ TCLK
(2)
The buffer must also be capable of driving the 470nF
load while maintaining its stability.
Timing
The only timing requirement that may cause the
ADS7863
to
malfunction
in
an
existing
ADS7861-based design is the CONVST high time (t1)
which is specified to be 20ns minimum while the
ADS7861 works properly with a pulse as short as
15ns. All the other required minimum setup and hold
times are specified to be either the same as or lower
than the ADS7863; therefore, there are no conflicts
with the ADS7861 requirements.
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APPLICATION INFORMATION
fFILTER =
The absolute minimum configuration of the ADS7863
is shown in Figure 41. In this case, the ADS7863 is
used in dual-channel mode only, with the default
settings of the device after power up.
ln(2) ´ (n + 1)
2´p´2´R´C
(3)
It is recommended to use a capacitor value of at least
20pF.
Keep the acquisition time in mind; the resistor value
can be calculated as shown in Equation 4 for each of
the series resistors (with n = 12, being the resolution
of the ADSS7863).
tACQ
R=
ln(2) ´ (n + 1) ´ 2 ´ C
(4)
The input signal for the amplifiers must fulfill the
common-mode voltage requirements of the ADS7863
in this configuration. The actual values of the
resistors and capacitors depend on the bandwidth
and performance requirements of the application.
Those values can be calculated using Equation 3,
with n = 12 being the resolution of the ADS7863.
BVDD
1mF
0.1mF
ADS7863
AVDD
BGND
OPA2365
AGND
AGND
OPA2365
AGND
AVDD
470nF
(min)
1
BGND
BVDD 24
2
CHB1+
SDOA 23
3
CHB1-
SDOB 22
4
CHB0+
BUSY 21
5
CHB0-
CLOCK 20
6
CHA1+
CS 19
7
CHA1-
RD 18
8
CHA0+
CONVST 17
9
CHA0-
SDI 16
BGND
10
REFIN
M0 15
BVDD
11
REFOUT
M1 14
12
AGND
Controller
Device
BGND
AVDD 13
OPA2365
0.1mF (min)
1mF
AGND
OPA2365
AGND
Figure 41. Minimum ADS7863 Configuration
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LAYOUT
For optimum performance, care should be taken with
the physical layout of the ADS7863 circuitry. This
condition is particularly true if the CLOCK input is
approaching the maximum throughput rate. In this
case, it is recommended to have a fixed phase
relationship between CLOCK and CONVST. The best
performance can be achieved when the digital
interface is run in SPI mode; thus, the CLOCK signal
is switched off after the 16th cycle and remains low
when CONVST is issued.
Additionally, the basic SAR architecture is quite
sensitive to glitches or sudden changes on the power
supply, reference, ground connections, and digital
inputs that occur just before latching the output of the
analog comparator. Therefore, when driving any
single conversion for an n-bit SAR converter, there
are n windows in which large external transient
voltages can affect the conversion result. Such
glitches might originate from switching power
supplies, nearby digital logic, or high-power devices.
The degree of error in the digital output depends on
the reference voltage, layout, and the exact timing of
the external event. These errors can change if the
external event also changes in time with respect to
the CLOCK input.
With this possibility in mind, power to the ADS7863
should be clean and well-bypassed. A 0.1µF ceramic
bypass capacitor should be placed as close to the
device as possible. In addition, a 1µF to 10µF
capacitor is recommended. If needed, an even larger
capacitor and a 5Ω or 10Ω series resistor may be
used to low-pass filter a noisy supply.
If the reference voltage is external and originates
from an operational amplifier, be sure that it can drive
the reference capacitor without oscillation. The
connection between the output of the external
reference driver and REFIN should be of low
resistance
(10Ω
max)
to
minimize
any
code-dependent voltage drop on this path.
Grounding
The xGND pins should be connected to a clean
ground reference. These connections should be kept
as short as possible to minimize the inductance of
these paths. It is recommended to use vias
connecting the pads directly to the ground plane. In
designs without ground planes, the ground trace
should be kept as wide as possible. Avoid
connections that are too near the grounding point of a
microcontroller or digital signal processor.
30
Depending on the circuit density of the board,
placement of the analog and digital components, and
the related current loops, a single solid ground plane
for the entire printed circuit board (PCB) or a
dedicated analog ground area may be used. In an
instance of a separated analog ground area, ensure a
low-impedance connection between the analog and
digital ground of the ADC by placing a bridge
underneath (or next to) the ADC. Otherwise, even
short undershoots on the digital interface with a value
lower than –300mV lead to conduction of ESD
diodes, causing current flow through the substrate
and degrading the analog performance.
During the PCB layout, care should also be taken to
avoid any return currents crossing any sensitive
analog areas or signals. No signal must exceed the
limit of –300mV with respect to the according ground
plane. Figure 42 illustrates the recommended layout
of the ground and power-supply connections for both
package options.
Supply
The ADS7863 has two separate supplies: the BVDD
pin for the digital interface and the AVDD pin for all
remaining circuits.
BVDD can range from 2.7V to 5.5V, allowing the
ADS7863 to easily interface with processors and
controllers. To limit the injection of noise energy from
external digital circuitry, BVDD should be filtered
properly. Bypass capacitors of 0.1µF and 10µF
should be placed between the BVDD pin and the
ground plane.
AVDD supplies the internal analog circuitry. For
optimum performance, a linear regulator (for
example, the UA7805 family) is recommended to
generate the analog supply voltage in the range of
2.7V to 5.5V for the ADS7863 and the necessary
analog front-end circuitry.
Bypass capacitors should be connected to the ground
plane such that the current is allowed to flow through
the pad of the capacitor (that is, the vias should be
placed on the opposite side of the connection
between the capacitor and the power-supply pin of
the ADC).
Digital Interface
To further optimize device performance, a resistor of
10Ω to 100Ω can be used on each digital pin of the
ADS7863. In this way, the slew rate of the input and
output signals is reduced, limiting the noise injection
from the digital interface.
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS7863
ADS7863
www.ti.com
SBAS383B – JUNE 2007 – REVISED MARCH 2008
Figure 42. Optimized Layout Recommendation
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS7863
31
ADS7863
www.ti.com
SBAS383B – JUNE 2007 – REVISED MARCH 2008
REVISION HISTORY
Changes from Revision A (March 2008) to Revision B .................................................................................................. Page
•
32
Changed serial interface timing from 20ns to 500ns in final paragraph .............................................................................. 27
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS7863
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ADS7863IDBQ
ACTIVE
SSOP/
QSOP
DBQ
24
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS7863IDBQG4
ACTIVE
SSOP/
QSOP
DBQ
24
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS7863IDBQR
ACTIVE
SSOP/
QSOP
DBQ
24
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS7863IDBQRG4
ACTIVE
SSOP/
QSOP
DBQ
24
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS7863IRGER
ACTIVE
VQFN
RGE
24
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS7863IRGERG4
ACTIVE
VQFN
RGE
24
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS7863IRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS7863IRGETG4
ACTIVE
VQFN
RGE
24
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS7863IDBQR
SSOP/
QSOP
DBQ
24
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
ADS7863IRGER
VQFN
RGE
24
3000
330.0
12.4
4.3
4.3
1.5
8.0
12.0
Q2
ADS7863IRGET
VQFN
RGE
24
250
330.0
12.4
4.3
4.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS7863IDBQR
SSOP/QSOP
DBQ
24
2500
346.0
346.0
33.0
ADS7863IRGER
VQFN
RGE
24
3000
340.5
333.0
20.6
ADS7863IRGET
VQFN
RGE
24
250
340.5
333.0
20.6
Pack Materials-Page 2
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