Etron EM636327TQ-55 512k x 32 high speed synchronous graphics dram(sgram) Datasheet

EtronTech
EM636327
512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)
Preliminary (12/98)
Features
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Fast access time from clock: 5/5/5.5/6.5/7.5 ns
Fast clock rate: 183/166/143/125/100 MHz
Fully synchronous operation
Internal pipelined architecture
Dual internal banks(256K x 32-bit x 2-bank)
Programmable Mode and Special Mode registers
- CAS# Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst-Read-Single-Write
- Load Color or Mask register
Burst stop function
Individual byte controlled by DQM0-3
Block write and write-per-bit capability
Auto Refresh and Self Refresh
2048 refresh cycles/32ms
Single +3.3V±0.3V power supply
Interface: LVTTL
JEDEC 100-pin Plastic package
-QFP (body thickness=2.8mm)
-TQFP1.4 (body thickness=1.4mm)
-TQFP1.0 (body thickness=1.0mm)
Overview
The EM636327 SGRAM is a high-speed
CMOS synchronous graphics DRAM containing 16
Mbits. It is internally configured as a dual 256K x
32 DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock
signal, CLK). Each of the 256K x 32 bit banks is
organized as 1024 rows by 256 columns by 32 bits.
Read and write accesses to the SGRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in
a programmed sequence. Accesses begin with the
registration of a BankActivate command which is
then followed by a Read or Write command.
The EM636327 provides for programmable
Read or Write burst lengths of 1, 2, 4, 8, or full
Key Specifications
EM636327
tCK3
tRAS
tAC1
tAC3
tRC
- 55/6/7/8/10
Clock Cycle time(min.)
5.5/6/7/8/10 ns
Row Active time(max.)
32/36/42/48/60 ns
Access time from Read command
7/8/13/18/23 ns
Access time from CLK(max.)
5/5/5.5/6.5/7.5 ns
Row Cycle time(min.)
48/54/63/72/90 ns
Ordering Information
Frequency
Package
EM636327Q-10
Part Number
100MHz
QFP
EM636327R-10
100MHz
QFP (Reverse)
EM636327TQ-10
100MHz
TQFP1.4
EM636327JT-10
100MHz
TQFP1.0
EM636327Q-8
125MHz
QFP
EM636327R-8
125MHz
QFP (Reverse)
EM636327TQ-8
125MHz
TQFP1.4
EM636327JT-8
125MHz
TQFP1.0
EM636327Q-7
143MHz
QFP
EM636327TQ-7
143MHz
TQFP1.4
EM636327Q-6
166MHz
QFP
EM636327TQ-6
166MHz
TQFP1.4
EM636327Q-55
183MHz
QFP
EM636327TQ-55
183MHz
TQFP1.4
page, with a burst termination option. An auto
precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end
of the burst sequence. The refresh functions,
either Auto or Self Refresh are easy to use. In
addition, EM636327 features the write-per-bit and
the masked block write functions.
By having a programmable mode register and
special mode register, the system can choose the
most suitable modes to maximize its performance.
These devices are well suited for applications
requiring high memory bandwidth, and when
combined with special graphics functions result in
a device particularly well suited to high
performance graphics applications.
Etron Technology, Inc.
1F, No. 1, Prosperity Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C
TEL: (886)-3-5782345 FAX: (886)-3-5779001
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
EtronTech
EM636327
Block Diagram
CLK
CLOCK
BUFFER
Column Decoder
CS#
RAS#
CAS#
WE#
DSF
Row Decoder
CKE
CONTROL
SIGNAL
GENERATOR
COMMAND
DECODER
1024 X 256 X 32
CELL ARRAY
(BANK #0)
Sense Amplifier
DQM0~3
COLUMN
COUNTER
DQS
BUFFER
A9
COLOR
REGISTER
MASK
REGISTER
MODE
REGISTER
ADDRESS
BUFFER
A0
DQ0
¢x
DQ31
SPECIAL
MODE
REGISTER
A8
BS
Row Decoder
Sense Amplifier
REFRESH
COUNTER
1024 X 256 X 32
CELL ARRAY
(BANK #1)
Column Decoder
Pin Assignment (Top View)
Forward Type
Reverse Type
DQ28
VDDQ
DQ27
DQ26
VSSQ
DQ25
DQ24
VDDQ
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
VSS
VDD
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
DQM3
DQM1
CLK
CKE
DSF
NC
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
VDD
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DQM0
DQM2
WE#
CAS#
RAS#
CS#
BS
A8
A0
A1
A2
A3
VDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
A4
A5
A6
A7
A7
A6
A5
A4
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD
A3
A2
A1
A0
Preliminary
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQ28
VDDQ
DQ27
DQ26
VSSQ
DQ25
DQ24
VDDQ
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
VSS
VDD
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
DQM3
DQM1
CLK
CKE
DSF
NC
A9
EM636327R-xx
EM636327Q-xx
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQ2
VSSQ
DQ1
DQ0
VDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
DQ31
DQ30
VSSQ
DQ29
DQ29
VSSQ
DQ30
DQ31
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
VDD
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DQM0
DQM2
WE#
CAS#
RAS#
CS#
BS
A8
2
December 1998
EtronTech
EM636327
Pin Descriptions
Table 1 shows the details for pin number, symbol, type, and description.
Table 1. Pin Details of EM636327
Pin Number Symbol Type Description
55
CLK
Input Clock: CLK is driven by the system clock. All SGRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst
counter and controls the output registers.
54
CKE
Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal.
If CKE goes low synchronously with clock(set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the
state of output and burst address is frozen as long as the CKE remains low.
When both banks are in the idle state, deactivating the clock controls the
entry to the Power Down and Self Refresh modes. CKE is synchronous
except after the device enters Power Down and Self Refresh modes, where
CKE becomes asynchronous until exiting the same mode. The input buffers,
including CLK, are disabled during Power Down and Self Refresh modes,
providing low standby power.
29
BS
Input Bank Select: BS defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied. BS is also used to program the
10th bit of the Mode and Special Mode registers.
31-34,
A0-A9
Input Address Inputs: A0-A9 are sampled during the BankActivate command (row
address A0-A9) and Read/Write command (column address A0-A7 with A9
defining Auto Precharge) to select one location out of the 256K available in
the respective bank. During a Precharge command, A9 is sampled to
determine if both banks are to be precharged (A9 = HIGH). The address
inputs also provide the op-code during a Mode Register Set or Special Mode
Register Set command.
28
CS#
Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH.
CS# provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
27
RAS#
Input Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive
edges of CLK. When RAS# and CS# are asserted "LOW" and CAS# is
asserted "HIGH," either the BankActivate command or the Precharge
command is selected by the WE# signal. When the WE# is asserted "HIGH,"
the BankActivate command is selected and the bank designated by BS is
turned on to the active state. When the WE# is asserted "LOW," the
Precharge command is selected and the bank designated by BS is switched
to the idle state after the precharge operation.
26
CAS#
Input Column Address Strobe: The CAS# signal defines the operation commands
in conjunction with the RAS# and WE# signals and is latched at the positive
edges of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the
column access is started by asserting CAS# "LOW." Then, the Read or Write
command is selected by asserting WE# "LOW" or "HIGH."
25
WE#
Input Write Enable: The WE# signal defines the operation commands in
conjunction with the RAS# and CAS# signals and is latched at the positive
edges of CLK. The WE# input is used to select the BankActivate or
Precharge command and Read or Write command.
47-50,
30, 51
Preliminary
3
December 1998
EtronTech
53
DSF
EM636327
Input Define Special Function: The DSF signal defines the operation commands
in conjunction with the RAS# and CAS# and WE# signals and is latched at
the positive edges of CLK. The DSF input is used to select the masked write
disable/enable command and block write command, and the Special Mode
Register Set cycle.
23, 56, 24, DQM0 - Input Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O
57
DQM3
buffer controls. The I/O buffers are placed in a high-z state when DQM is
sampled HIGH. Input data is masked when DQM is sampled HIGH during a
write cycle. Output data is masked (two-clock latency) when DQM is sampled
HIGH during a read cycle. DQM3 masks DQ31-DQ24, DQM2 masks DQ23DQ16, DQM1 masks DQ15-DQ8, and DQM0 masks DQ7-DQ0.
97, 98, 100, DQ0- Input/ Data I/O: The DQ0-31 input and output data are synchronized with the
1, 3, 4, 6 , 7, DQ31 Output positive edges of CLK. The I/Os are byte-maskable during Reads and Writes.
60, 61, 63,
The DQs also serve as column/byte mask inputs during Block Writes.
64, 68, 69,
71, 72, 9,
10, 12, 13,
17, 18, 20,
21, 74, 75,
77, 78, 80,
81, 83, 84
36-45, 52,
58, 86-95
NC
2, 8, 14, 22,
59, 67, 73,
79
VDDQ
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
5, 11, 19,
62, 70, 76,
82, 99
VSSQ
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
15, 35, 65,
96
VDD
Supply Power Supply: +3.3V±0.3V
16, 46, 66,
85
VSS
Supply Ground
Preliminary
-
No Connect: These pins should be left unconnected.
4
December 1998
EtronTech
EM636327
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
State
CKEn-1 CKEn DQM(7) BS A9 A0-8 CS# RAS# CAS# WE# DSF
BankActivate & Masked Write Disable
Idle(3)
H
X
X
V
V
V
L
L
H
H
L
BankActivate & Masked Write Enable
Idle(3)
H
X
X
V
V
V
L
L
H
H
H
BankPrecharge
Any
H
X
X
V
L
X
L
L
H
L
L
PrechargeAll
Any
H
X
X
X
H
X
L
L
H
L
L
Write
Active(3)
H
X
X
V
L
V
L
H
L
L
L
Block Write Command
Active(3)
H
X
X
V
L
V
L
H
L
L
H
Write and AutoPrecharge
Active(3)
H
X
X
V
H
V
L
H
L
L
L
Block Write and AutoPrecharge
Active(3)
H
X
X
V
H
V
L
H
L
L
H
Read
Active(3)
H
X
X
V
L
V
L
H
L
H
L
Read and Autoprecharge
Active(3)
H
X
X
V
H
V
L
H
L
H
L
Idle
H
X
X
V
L
V
L
L
L
L
L
Idle(5)
H
X
X
X
X
V
L
L
L
L
H
Any
H
X
X
X
X
X
L
H
H
H
X
Active(4)
H
X
X
X
X
X
L
H
H
L
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
X
AutoRefresh
Idle
H
H
X
X
X
X
L
L
L
H
L
SelfRefresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
L
Idle
L
H
X
X
X
X
H
X
X
X
X
L
H
H
H
X
Mode Register Set
Special Mode Register Set
No-Operation
Burst Stop
SelfRefresh Exit
(SelfRefresh)
Clock Suspend Mode Entry
Active
H
L
X
X
X
X
X
X
X
X
X
Power Down Mode Entry
Any(6)
H
L
X
X
X
X
H
X
X
X
X
L
H
H
H
L
Clock Suspend Mode Exit
Active
L
H
X
X
X
X
X
X
X
X
X
Any
L
H
X
X
X
X
H
X
X
X
X
L
H
H
H
L
X
X
X
X
X
Active
H
X
H
X X X
X
X
X
X
Note: 1. V=Valid X=Don't Care L=Low level H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. The Special Mode Register Set is also available in Row Active State.
6. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
7. DQM0-3
X
Power Down Mode Exit
(PowerDown)
Data Write/Output Enable
Active
H
X
Data Mask/Output Disable
Preliminary
5
L
X
X
X
December 1998
EtronTech
EM636327
Commands
1
BankActivate & Masked Write Disable command
(RAS# = "L", CAS# = "H", WE# = "H", DSF = "L", BS = Bank, A0-A9 = Row Address)
The BankActivate command activates the idle bank designated by the BS (Bank Select) signal.
By latching the row address on A0 to A9 at the time of this command, the selected row access is
initiated. The read or write operation in the same bank can occur after a time delay of tRCD(min.)
from the time of bank activation. A subsequent BankActivate command to a different row in the
same bank can only be issued after the previous active row has been precharged (refer to the
following figure). The minimum time interval between successive BankActivate commands to the
same bank is defined by tRC(min.). The SGRAM has two internal banks on the same chip and
shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back
activation of both banks. tRRD(min.) specifies the minimum time required between activating
different banks. After this command is used, the Write command and the Block Write command
perform the no mask write operation.
T0
T1
T2
T3
Tn+3
CLK
Tn+4
Tn+5
Tn+6
..............
ADDRESS
Bank A
Row Addr.
Bank A
Col Addr.
..............
Bank B
Row Addr.
R/W A with
AutoPrecharge
..............
Bank B
Activate
RAS# - RAS# delay time (tRRD)
RAS# - CAS# delay (tRCD)
COM MAND
Bank A
Activate
NOP
NOP
Bank A
Row Addr.
NOP
NOP
Bank A
Activate
RAS# Cycle time (tRC)
AutoPrecharge
Begin
: "H" or "L"
BankActivate Command Cycle (Burst Length = n, CAS# Latency = 3)
2
BankActivate & Masked Write Enable command (refer to the above figure)
(RAS# = "L", CAS# = "H", WE# = "H", DSF = "H", BS = Bank, A0-A9 = Row Address)
The BankActivate command activates the idle bank designated by BS signal. After this
command is performed, the Write command and the Block Write command perform the masked
write operation. In the masked write and the masked block write functions, the I/O mask data that
was stored in the write mask register is used.
3
BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", DSF = "L", BS = Bank, A9 = "L", A0-A8 = Don't care)
The BankPrecharge command precharges the bank disignated by BS signal. The precharged
bank is switched from the active state to the idle state. This command can be asserted anytime after
tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any
bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed
in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idle
state and is ready to be activated again.
4
PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", DSF = "L", BS = Don't care, A9 = "H", A0-A8 = Don't care)
The PrechargeAll command precharges both banks simultaneously and can be issued even if
both banks are not in the active state. Both banks are then switched to the idle state.
5
Read command
(RAS# = "H", CAS# = "L", WE# = "H", DSF = "L", BS = Bank, A9 = "L", A0-A7 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS# latency after the issue of the Read command. Each subsequent dataout element will be valid by the next positive clock edge (refer to the following figure). The DQs go
Preliminary
6
December 1998
EtronTech
EM636327
into high-impedance at the end of the burst unless other command is initiated. The burst length,
burst sequence, and CAS# latency are determined by the mode register, which is already
programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to
column 0 and continue).
T0
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
NOP
T7
T8
CLK
COM MAND
READ A
CAS# latency=1
tCK1, DQ's
NOP
DOUT A0
CAS# latency=2
tCK2, DQ's
NOP
DOUT A1
DOUT A0
CAS# latency=3
tCK3, DQ's
DOUT A2
DOUT A1
DOUT A0
NOP
NOP
DOUT A3
DOUT A2
DOUT A1
DOUT A3
DOUT A2
DOUT A3
Burst Read Operation(Burst Length = 4, CAS# Latency = 1, 2, 3)
The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier
(i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function
may be interrupted by a subsequent Read or Write/Block Write command to the same bank or the
other active bank before the end of the burst length. It may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank too. The interrupt coming from the Read command can
occur on any clock cycle following a previous Read command (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
DOUT B1
DOUT B2
CLK
COM MAND
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
READ A
READ B
DOUT A0
NOP
DOUT B0
DOUT A0
DOUT B0
DOUT A0
NOP
DOUT B3
DOUT B1
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3)
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes
from a Write/Block Write command. The DQMs must be asserted (HIGH) at least two clocks prior to
the Write/Block Write command to suppress data-out on the DQ pins. To guarantee the DQ pins
against I/O contention, a single cycle with high-impedance on the DQ pins must occur between the
last read data and the Write/Block Write command (refer to the following three figures). If the data
output of the burst read occurs at the second clock of the burst write, the DQMs must be asserted
(HIGH) at least one clock prior to the Write/Block Write command to avoid internal bus contention.
Preliminary
7
December 1998
EtronTech
EM636327
T0
T1
T2
NOP
READ A
NOP
T3
T4
T5
T6
T7
T8
NOP
NOP
CLK
DQM
COM MAND
NOP
NOP
DQ's
NOP
DOUT A0
Must be Hi-Z before
the Write Command
WRITE B
DI NB 0
DINB1
DINB 2
: "H" or "L"
Read to Write Interval (Burst Length ¡Ù 4, CAS# Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
1 Clk Interval
DQM
COM MAND
NOP
NOP
BANKA
ACTIVATE
NOP
CAS# latency=1
tCK1, DQ's
READ A
WRITE A
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DIN A3
DIN A0
DIN A1
DIN A2
DIN A3
Must be Hi-Z before
the Write Command
CAS# latency=2
tCK2, DQ's
: "H" or "L"
Read to Write Interval (Burst Length ¡Ù 4, CAS# Latency = 1, 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COM MAND
NOP
CAS# latency=1
tCK1, DQ's
NOP
READ A
NOP
NOP
DOUT A0
WRITE B
DIN B0
NOP
NOP
NOP
DIN B 1
DIN B2
DIN B3
DIN B 1
DIN B2
DIN B3
Must be Hi-Z before
the Write Command
CAS# latency=2
tCK2, DQ's
DIN B0
: "H" or "L"
Read to Write Interval (Burst Length ¡Ù 4, CAS# Latency = 1, 2)
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS# latency.
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EtronTech
T0
T1
EM636327
T2
T3
T4
T5
T6
T7
T8
CLK
ADDRESS
Bank,
Col A
Bank,
Row
Bank(s)
tRP
COM M AND
READ A
CAS# latency=1
tCK1, DQ's
NOP
DOUT A0
CAS# latency=2
tCK2 , DQ's
NOP
DOUT A1
DOUT A0
CAS# latency=3
tCK3 , DQ's
NOP
Precharge
DOUT A2
DOUT A1
DOUT A0
NOP
NOP
Activate
NOP
DOUT A3
DOUT A2
DOUT A1
DOUT A3
DOUT A2
DOUT A3
Read to Precharge (CAS# Latency = 1, 2, 3)
6
Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", DSF = "L", BS = Bank, A9 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after
the read operation. Once this command is given, any subsequent command cannot occur within a
time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in
this command and the auto precharge function is ignored.
7
Write command
(RAS# = "H", CAS# = "L", WE# = "L", DSF = "L", BS = Bank, A9 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
T0
T1
T2
T3
T4
T5
T6
T7
T8
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DIN A3
don't care
CLK
COM MAND
DQ0 - DQ3
NOP
The first data element and the write
are registered on the same clock edge.
Extra data is masked.
Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3)
Any Write performed to a row that was opened via an BankActivate & Masked Write Enable
command is a masked write (Write-Per-Bit). Data is written to the 32 cells (bits) at the selected
column location subject to the data stored in the Mask register. The overall mask consists of the
DQM inputs, which mask on a per-byte basis, and the Mask register, which masks also on a per-bit
basis. This is shown in the following block diagram.
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EtronTech
DSF
D
BankActivate
command
EM636327
DQM0
Q
DRAM
CELL
CK
DQ7
MR7
DQ6
MR6
DQ5
MR5
DQ4
MR4
DQ3
MR3
DQ2
MR2
DQ1
MR1
DQ0
0 = Masked
1 = Not Masked
MR0
Note: Only the lower byte is shown. The operation is identical for other bytes.
Write Per Bit (I/O Mask) Block Diagram
A write burst without the auto precharge function may be interrupted by a subsequent
Write/Block Write, BankPrecharge/PrechargeAll, or Read command before the end of the burst
length. An interrupt coming from Write/Block Write command can occur on any clock cycle
following the previous Write command (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
DIN B 1
DIN B2
DIN B3
CLK
COMMAND
NOP
WRITE A
WRITE B
1 Clk Interval
DIN A0
DQ's
DIN B0
Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3)
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to
avoid data contention, input data must be removed from the DQs at least one clock cycle before the
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EM636327
first read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
DOUT B1
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
DOUT B0
DOUT B1
CLK
COM MAND
NOP
WRITE A
READ B
CAS# latency=1
tCK1, DQ's
DIN A0
CAS# latency=2
tCK2, DQ's
DIN A0
don't care
CAS# latency=3
tCK3, DQ's
DIN A0
don't care
DOUT B0
don't care
DOUT B3
DOUT B2
DOUT B3
Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
Input data for the write is masked.
Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
COM MAND
WRITE
ADDRESS
BA N K
COL n
Precharge
NOP
NOP
NOP
BANK (S)
Activate
NOP
ROW
tWR
DIN
n
DQ
DIN
n+ 1
: don't care
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
When the Burst-Read-Single-Write mode is selected, the write burst length is 1 regardless of
the read burst length (refer to Figures 21 and 22 in Timing Waveforms).
8
Block Write command
(RAS# = "H", CAS# = "L", WE# = "L", DSF = "H", BS = Bank, A9 = "L", A3-A7 = Column Address,
DQ0-DQ31 = Column Mask)
The block writes are non-burst accesses that write to eight column locations simultaneously. A
single data value, which was previously loaded in the Color register, is written to the block of eight
consecutive column locations addressed by inputs A3~A7. The information on the DQs which are
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EM636327
registered coincident with the Block Write command is used to mask specific column/byte
combinations within the block. The mapping of the DQ inputs to the column/byte combinations is
shown in following table.
The overall Block Write mask consists of a combination of the DQM inputs, the Mask register,
and the column/byte mask information, as shown in the following figure. The DQM and Mask
register masking operates normally as for a Write command, with the exception that the mask
information is applied simultaneously to all eight columns. Therefore, in a Block Write, a given bit is
written only if a "0" is registered for the corresponding DQM input, a "1" is registered for the
corresponding DQ signal, and the corresponding bit in the Mask register is "1".
Block of Columns
(selected by A3-A7 registered
coincident with Block Write command)
Row in Bank
(selected by A0-A9,
and BS registered
coincident with BankActivate
Command)
Column Mask DQ0
on the DQ DQ1
inputs DQ2
DQ3
(registered
DQ4
coincident
DQ5
with Block DQ6
Write Command DQ7
DSF
BankActivate
command
D Q
CK
DQM0
MR0
MR 1
Mask Register
(previously loaded
from corresponding
DQ inputs)
MR2
MR3
MR4
MR5
MR6
CR0
CR 1
CR2
CR3
CR4
CR5
CR6
CR7
MR7
Note: Only the lower byte is shown. The operation is identical for other bytes.
Block-Write Masking Block Diagram
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EtronTech
DQ
EM636327
Column Address DQ Planes
DQ
Column Address DQ Planes
Inputs
A2
A1
A0
Controlled
Inputs
A2
A1
A0
Controlled
DQ0
0
0
0
0~7
DQ16
0
0
0
16~23
DQ1
0
0
1
0~7
DQ17
0
0
1
16~23
DQ2
0
1
0
0~7
DQ18
0
1
0
16~23
DQ3
0
1
1
0~7
DQ19
0
1
1
16~23
DQ4
1
0
0
0~7
DQ20
1
0
0
16~23
DQ5
1
0
1
0~7
DQ21
1
0
1
16~23
DQ6
1
1
0
0~7
DQ22
1
1
0
16~23
DQ7
1
1
1
0~7
DQ23
1
1
1
16~23
DQ8
0
0
0
8~15
DQ24
0
0
0
24~31
DQ9
0
0
1
8~15
DQ25
0
0
1
24~31
DQ10
0
1
0
8~15
DQ26
0
1
0
24~31
DQ11
0
1
1
8~15
DQ27
0
1
1
24~31
DQ12
1
0
0
8~15
DQ28
1
0
0
24~31
DQ13
1
0
1
8~15
DQ29
1
0
1
24~31
DQ14
1
1
0
8~15
DQ30
1
1
0
24~31
DQ15
1
1
1
8~15
DQ31
1
1
1
24~31
A block write access requires a time period of tBWC to execute, so in general, there should be m
NOP cycles(m equals (tBWC - tCK)/tCK rounded up to the next whole number), after the Block Write
command. However, BankActivate or BankPrecharge commands to the other bank are allowed.
When following a Block Write with a BankPrecharge or PrechargeAll command to the same bank,
tBPL must be met.
9
Write and AutoPrecharge command (refer to the following figure)
(RAS# = "H", CAS# = "L", WE# = "L", DSF = "L", BS = Bank, A9 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is
performed in this command and the auto precharge function is ignored.
T0
T1
T2
T3
T4
Write A
NOP
T5
T6
T7
T8
CLK
Bank A
Activate
COM MAND
NOP
NOP
AutoPrecharge
NOP
NOP
NOP
NOP
tDAL
CAS# latency=1
tCK1, DQ's
DIN A0
DIN A1
CAS# latency=2
tCK2, DQ's
DIN A0
DIN A1
*
*
tDAL
tDAL
CAS# latency=3
tCK3, DQ's
DIN A0
DIN A1
*
*
Begin AutoPrecharge
Bank can be reactivated at completion of tDAL
tDAL= tWR + tRP
Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 1, 2, 3)
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EM636327
10
Block Write and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", DSF = "H", BS = Bank, A9 = "H", A3-A7 = Column Address,
DQ0-DQ31 = Column Mask)
The Block Write and AutoPrecharge command performs the precharge operation automatically
after the block write operation. Once this command is given, any subsequent command can not
occur within a time delay of {tBPL + tRP(min.)}.
11
Mode Register Set command
(RAS# = "L", CAS# = "L", WE# = "L", DSF = "L", BS, A0-A9 = Register Data)
The mode register stores the data for controlling the various operating modes of SGRAM. The
Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst
Length in the Mode register to make SGRAM useful for a variety of different applications. The
default values of the Mode Register after power-up are undefined; therefore this command must be
issued at the power-up sequence. The state of pins A0~A8 and BS in the same cycle is the data
written to the mode register. One clock cycle is required to complete the write in the mode register
(refer to the following figure). The contents of the mode register can be changed using the same
command and the clock cycle requirements during operation as long as both banks are in the idle
state.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t CK2
CKE
Clock min.
CS#
RAS#
CA S#
WE#
DSF
BS
A9
Address Key
A0 - A 8
DQM
tRP
DQ
Hi-Z
PrechargeAll
Mode Register
Set Command
Any
Command
Mode Register Set Cycle (CAS# Latency = 1, 2, 3)
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EM636327
The mode register is divided into various fields depending on functionality.
•
Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the
Burst Length to be 1, 2, 4, 8, or full page.
•
A2
A1
A0
Burst Length
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Full Page
Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode.
Sequential Mode supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only
supports burst length of 4 and 8.
A3
Addressing Mode
0
Sequential
1
Interleave
--- Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column
address which is input to the device. The internal column address is varied by the Burst
Length as shown in the following table. When the value of column address, (n + m), in
the table is larger than 255, only the least significant 8 bits are effective.
Data n
0
1
2
3
4
5
6
7
-
255
256
257
-
Column Address
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
-
n+255
n
n+1
-
2 words:
Burst Length
4 words:
8 words:
Full Page: Column address is repeated until terminated.
--- Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting
the address bits in the sequence shown in the following table.
Data n
•
Preliminary
Column Address
Burst Length
Data 0
A7
A6
A5
A4
A3
A2
A1
A0
Data 1
A7
A6
A5
A4
A3
A2
A1
A0#
Data 2
A7
A6
A5
A4
A3
A2
A1# A0
Data 3
A7
A6
A5
A4
A3
A2
A1# A0#
Data 4
A7
A6
A5
A4
A3
A2# A1
A0
Data 5
A7
A6
A5
A4
A3
A2# A1
A0#
Data 6
A7
A6
A5
A4
A3
A2# A1# A0
Data 7
A7
A6
A5
A4
A3
A2# A1# A0#
4 words
8 words
CAS# Latency Field (A6~A4)
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EM636327
This field specifies the number of clock cycles from the assertion of the Read command to
the first read data. The minimum whole value of CAS# Latency depends on the frequency
of CLK. The minimum whole value satisfying the following formula must be programmed
into this field.
tCAC(min) ¡Ø CAS# Latency X tCK
•
•
12
A6
A5
A4
CAS# Latency
0
0
0
Reserved
0
0
1
1 clock
0
1
0
2 clocks
0
1
1
3 clocks
1
X
X
Reserved
Test Mode field (A9~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal
operation.
A9
A8
A7
Test Mode
X
0
0
normal mode
X
0
1
Vendor Use Only
X
1
X
Vendor Use Only
Single Write Mode (BS)
This bit is used to select the write mode. When the BS bit is "0", the Burst-Read-BurstWrite mode is selected. When the BS bit is "1", the Burst-Read-Single-Write mode is
selected.
BS
Single Write Mode
0
Burst-Read-Burst-Write
1
Burst-Read-Single-Write
Special Mode Register Set command
(RAS# = "L", CAS# = "L", WE# = "L", DSF = "H", BS, A0-A9 = Register Data)
The special mode register is used to load the Color and Mask registers, which are used in Block
Write and masked Write cycles. The control information being written to the Special Mode register
is applied to the address inputs and the data to be written to either the Color register or the Mask
register is applied to the DQs. When A6 is "HIGH" during a Special Mode Register Set cycle, the
Color register will be loaded with the data on the DQs. Similarly, when A5 is "HIGH" during a
Special Mode Register Set cycle, the Mask register will be loaded with the data on the DQs.
A6=A5=1 in the Special Mode Register Set cycle is illegal.
Functions
BS
A9 ~ A7
A6
A5
A4 ~ A0
Leave Unchanged
X
X
0
0
X
Load Mask Register
X
X
0
1
X
Load Color Register
X
X
1
0
X
Illegal
X
X
1
1
X
One clock cycle is required to complete the write in the Special Mode register. This command
can be issued during the active state. As in a write operation, this command accepts the data
needed through DQ pins. Therefore, it should be attended not to induce bus contention.
13
No-Operation command
(RAS# = "H", CAS# = "H", WE# = "H")
The No-Operation command is used to perform a NOP to the SGRAM which is selected (CS#
is Low). This prevents unwanted commands from being registered during idle or wait states.
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14
EM636327
Burst Stop command
(RAS# = "H", CAS# = "H", WE# = "L", DSF = "L")
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This
command is only effective in a read/write burst without the auto precharge function. The terminated
read burst ends after a delay equal to the CAS# latency (refer to the following figure). The
termination of a write burst is shown in the following figure.
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
CLK
COMMAND
READ A
CAS# latency=1
tCK1, DQ's
NOP
DOUT A0
CAS# latency=2
tCK2, DQ's
NOP
NOP
Burst Stop
The burst ends after a delay equal to the CAS# latency.
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
CAS# latency=3
tCK3, DQ's
DOUT A3
Termination of a Burst Read Operation (Burst Length ¡Ö 4, CAS# Latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
CLK
COM MAND
CAS# latency=1, 2, 3
DQ's
NOP
WRITE A
NOP
NOP
Burst Stop
DIN A0
DIN A1
DIN A2
don't care
Input data for the Write is masked.
Termination of a Burst Write Operation (Burst Length = X, CAS# Latency = 1, 2, 3)
15
Device Deselect command
(CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE#
and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar
to the No Operation command.
16
AutoRefresh command (refer to Figures 3 & 4 in Timing Waveforms)
(RAS# = "L", CAS# = "L", WE# = "H", DSF = "L", CKE = "H", BS, A0-A9 = Don't care)
The AutoRefresh command is used during normal operation of the SGRAM and is analogous to
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal
refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh
operation must be performed 2048 times within 32ms. The time required to complete the auto
refresh operation is specified by tRC(min.). To provide the AutoRefresh command, both banks need
to be in the idle state and the device must not be in power down mode (CKE is high in the previous
cycle). This command must be followed by NOPs until the auto refresh operation is completed. The
precharge time requirement, tRP(min), must be met before successive auto refresh operations are
performed.
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EM636327
17
SelfRefresh Entry command (refer to Figure 5 in Timing Waveforms)
(RAS# = "L", CAS# = "L", WE# = "H", DSF = "L", CKE = "L", BS, A0-A9 = Don't care)
The SelfRefresh is another refresh mode available in the SGRAM. It is the preferred refresh
mode for data retention and low power operation. Once the SelfRefresh command is registered, all
the inputs to the SGRAM become "don't care" with the exception of CKE, which must remain LOW.
The refresh addressing and timing is internally generated to reduce power consumption. The
SGRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited
by restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).
18
SelfRefresh Exit command (refer to Figure 5 in Timing Waveforms)
(CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H")
This command is used to exit from the SelfRefresh mode. Once this command is registered,
NOP or Device Deselect commands must be issued for tRC(min.) because time is required for the
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are
performed during normal operation, a burst of 2048 auto refresh cycles should be completed just
prior to entering and just after exiting the SelfRefresh mode.
19
Clock Suspend Mode Entry / PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in
Timing Waveforms)
(CKE = "L")
When the SGRAM is operating the burst cycle, the internal CLK is suspended(masked) from
the subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
intact while CLK is suspended. On the other hand, when both banks are in the idle state, this
command performs entry into the PowerDown mode. All input and output buffers (except the CKE
buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or
PowerDown state longer than the refresh period (32ms) since the command does not perform any
refresh operations.
20
Clock Suspend Mode Exit / PowerDown Mode Exit command (refer to Figures 6, 7, and 8 in Timing
Waveforms)
(CKE= "H")
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated
from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is
in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the
active state. tPDE(min.) is required when the device exits from the PowerDown mode. Any
subsequent commands can be issued after one clock cycle from the end of this command.
21
Data Write / Output Enable, Data Mask / Output Disable command
(DQM = "L", "H")
During a write cycle, the DQM signal functions as a Data Mask and can control every word of
the input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is
also used for device selection, byte selection and bus control in a memory system. DQM0 controls
DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, and DQM3 controls
DQ24 to DQ31. DQM masks the DQ's by a byte regardless that the corresponding DQ's are in a
state of write-per-bit masking or pixel masking. Each DQM0-3 corresponds to DQ0-7, DQ8-15,
DQ16-23, and DQ24-31.
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EM636327
Absolute Maximum Rating
Symbol
Item
Rating
Unit
Note
VIN, VOUT
Input, Output Voltage
- 0.3~VDD + 0.3
V
1
VDD, VDDQ
Power Supply Voltage
- 0.3~4.6
V
1
TOPR
Operating Temperature
0~70
°C
1
TSTG
Storage Temperature
- 55~150
°C
1
TSOLDER
Soldering Temperature (10s)
260
°C
1
PD
Power Dissipation
1
W
1
IOUT
Short Circuit Output Current
50
mA
1
Recommended D.C. Operating Conditions (Ta = 0~70°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Note
VDD
Power Supply Voltage
3.0
3.3
3.6
V
2
VDDQ
Power Supply Voltage(for I/O Buffer)
3.0
3.3
3.6
V
2
VIH
LVTTL Input High Voltage
2.0
¡Ð
VDD + 0.3
V
2
VIL
LVTTL Input Low Voltage
- 0.3
¡Ð
0.8
V
2
Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25°C)
Symbol
CI
CI/O
Parameter
Min.
Max.
Unit
Input Capacitance
¡Ð
5
pF
Input/Output Capacitance
¡Ð
7
pF
Note: These parameters are periodically sampled and are not 100% tested.
Preliminary
19
December 1998
EtronTech
EM636327
Recommended D.C. Operating Conditions (VDD = 3.3V±0.3V, Ta = 0~70°C)
Description/Test condition
Symbol
Operating Current
1 bank operation
IDD1
tRC ≥ tRC(min), Outputs Open
2 bank interleave
Address changed once during tCK(min).
IDD1B
operation
Burst Length = 2
Precharge Standby Current in non-power down mode
IDD2N
tCK = tCK(min), CS# ≥ VIH, CKE ≥ VIL(max)
Input signals are changed once during 30ns.
Precharge Standby Current in non-power down mode
IDD2NS
tCK = ∞, CKE ≥ VIL(max), Input signals are stable.
Precharge Standby Current in power down mode
IDD2P
tCK = tCK(min), CKE ≤ VIL(max)
Precharge Standby Current in power down mode
IDD2PS
tCK = ∞, CKE ≤ VIL(max)
Active Standby Current in power down mode
IDD3P
CKE ≤ VIL(max), tCK = tCK(min)
Active Standby Current in non-power down mode
IDD3N
CKE ≥ VIL(max), tCK = tCK(min)
Operating Current (Burst mode)
IDD4
tCK=tCK(min), Outputs Open, Multi-bank interleave,gapless data
Refresh Current
IDD5
tRC ≥ tRC(min)
Self Refresh Current
IDD6
CKE ≤ 0.2V
Operating Current (Block Write)
IDD7
tCK=tCK(min), Outputs Open, tBWC = tBWC(min).
- 55/6/7/8/10
Max.
Unit Note
200/190/180/160/130
3
290/270/250/225/180
3
110/90/85/75/60
3
60/50/45/40/30
3
3
3
mA
18/13/10/9/7
3
100/90/80/70/55
300/280/265/250/200
3, 4
130/125/120/115/110
3
3
250/240/235/230/220
Parameter
Description
Min.
Max.
IIL
Input Leakage Current
( 0V ≤ VIN ≤ VDD, All other pins not under test = 0V )
-5
5
µA
IOL
Output Leakage Current
Output disable, 0V ≤ VOUT ≤ VDDQ)
-5
5
µA
VOH
LVTTL Output "H" Level Voltage
( IOUT = -2mA )
2.4
¡Ð
V
VOL
LVTTL Output "L" Level Voltage
( IOUT = 2mA )
¡Ð
0.4
V
Preliminary
20
Unit Note
December 1998
EtronTech
EM636327
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V¡Ó0.3V, Ta = 0~70°C) (Note: 5, 6, 7, 8)
- 55/6/7/8/10
Symbol
A.C. Parameter
Min.
48/54/63/72/90
9
16/16/16/16/30
9
16/16/16/16/30
9
11/12/14/16/20
9
tWR
Row cycle time
(same bank)
RAS# to CAS# delay
(same bank)
Precharge to refresh/row activate command
(same bank)
Row activate to row activate delay
(different banks)
Row activate to precharge time
(same bank)
Write recovery time
tCK1
CL* = 1
19/20/20/20/30
CL* = 2
7/7.5/8/8/15
CL* = 3
5.5/6/7/8/10
tRC
tRCD
tRP
tRRD
tRAS
tCK2
Clock cycle time
tCK3
32/36/42/48/60
Max.
Unit
Note
100,000
ns
5.5/6/7/8/10
10
tCH
Clock high time
2/2/2.5/3/3.5
11
tCL
Clock low time
2/2/2.5/3/3.5
11
tAC1
Access time from CLK
CL* = 1
7/8/13/18/27
tAC2
(positive edge)
CL* = 2
5.5/6/6.5/7/12
CL* = 3
5/5/5.5/6.5/7.5
tAC3
11
tCCD
CAS# to CAS# Delay time
tOH
Data output hold time
2/2/2/2/3
tLZ
Data output low impedance
1/1/1/2/2
tHZ
Data output high impedance
tIS
Data/Address/Control Input set-up time
tIH
Data/Address/Control Input hold time
tSRX
Minimum CKE "High" for SelfRefresh exit
5.5/6/7/8/10
tPDE
PowerDown Exit set-up time
3.5/4/5/6/8
11
tRSC
(Special) Mode Register Set Cycle time
5.5/6/7/8/10
9
tBWC
Block Write Cycle time
11/12/14/16/20
tBPL
Block Write to Precharge command period
11/12/14/16/20
tREF
Refresh time
1
Cycle
10
3.5/4/5/6/8
8
2/2/2/2.5/3
11
1
11
ns
32
ms
* CL is CAS# Latency.
Preliminary
21
December 1998
EtronTech
EM636327
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 10.
6. A.C. Test Conditions
LVTTL Interface
Reference Level of Output Signals
1.4V / 1.4V
Output Load
Reference to the Under Output Load (B)
Input Signal Levels
2.4V / 0.4V
Transition Time (Rise and Fall) of Input Signals
1ns
Reference Level of Input Signals
1.4V
1.4V
3.3V
50Ω
1.2kΩ
Z0= 5 0 Ω
Output
Output
30pF
30pF
87 0Ω
LVTTL D.C. Test Load (A)
LVTTL A.C. Test Load (B)
7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed
slope (1 ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference
levels.
9. These parameters account for the number of clock cycle and depend on the operating frequency of the
clock as follows:
the number of clock cycles = specified value of timing/Clock cycle time
(count fractions as a whole number)
10.If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.
11.Assumed input rise and fall time tT ( tR & tF ) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e.,
[ ( tR + tF ) / 2 -1] ns should be added to the parameter.
Preliminary
22
December 1998
EtronTech
EM636327
12. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state
and both CKE = "H" and DQM = "H." The CLK signals must be started at the same time.
2) After power-up, a pause of 200µseconds minimum is required. Then, it is recommended that DQM
is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) Both banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of
the device.
Preliminary
23
December 1998
EtronTech
EM636327
Timing Waveforms
Figure 1. AC Parameters for Write Timing (Burst Length=4, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
tCL
tCH
t IS
CKE
t IS
Begin AutoPrecharge
Bank A
Begin AutoPrecharge
Bank B
t IH
t IS
CS#
RAS#
CA S#
WE#
DSF
BS
t IH
A9
RBx
RAx
RAy
RAz
RBy
RAz
RBy
t IS
A0 - A 8
CAx
RBx
CBx
RBx
RAy
CAy
DQM
tRCD
tDAL
tRC
t IS
DQ
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Activate
Write with
Activate
Write with
Activate
Command AutoPrecharge Command AutoPrecharge Command
Bank A
Command
Bank B
Command
Bank A
Bank A
Bank B
Preliminary
24
t WR
tIH
Hi-Z
Ay0
Ay1
Write
Command
Bank A
Ay2
tRP
tRRD
Ay3
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
December 1998
EtronTech
EM636327
Figure 2. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
CLK
tCH tCL
tCK2
CKE
Begin AutoPrecharge
Bank B
t IS
t IS
t IH
tIH
C S#
RAS#
C A S#
WE#
DSF
BS
tIH
A9
RBx
RAx
RAy
t IS
A0 - A 8
RAx
CAx
CBx
RBx
RAy
tRRD
tRAS
tRC
D QM
tAC2
tLZ
tRCD
Hi-Z
DQ
tAC2
Ax0
tRP
t HZ
Ax1
Bx0
t HZ
tOH
Activate
Command
Bank A
Preliminary
Read
Command
Bank A
Activate
Command
Bank B
25
Bx1
Read with
Auto Precharge
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
December 1998
EtronTech
EM636327
Figure 3. Auto Refresh (CBR) (Burst Length=4, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 - A 8
RAx
DQM
tRP
tRC
CAx
tRC
DQ
Ax0
PrechargeAll AutoRefresh
Command
Command
Preliminary
AutoRefresh
Command
Activate
Command
Bank A
26
Ax1
Ax2
Ax3
Read
Command
Bank A
December 1998
EtronTech
EM636327
Figure 4. Power on Sequene and Auto Refresh (CBR)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High level
is reauired
CKE
Minimum of 2 Refresh Cycles are required
CS#
RAS#
CAS#
WE#
DSF
BS
A9
Address Key
A0 - A 8
DQM
tRP
DQ
tRC
Hi-Z
PrechargeALL
Command
Inputs must be
stable for 200 µs
Preliminary
1st AutoRefresh
Command
Mode Register
Set Command
2nd Auto Refresh
Command
27
Any
Command
December 1998
EtronTech
EM636327
Figure 5. Self Refresh Entry & Exit Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
Clock
*Note 1
*Note 2
CKE
*Note 4
tRC(min)
*Note 3
tSRX
*Note 7
tPDE
*Note 5
t IS
CS#
*Note 6
RAS#
*Note 8
*Note 8
CA S#
BS
A0 - A 9
WE#
DSF
DQM
DQ
Hi-Z
Hi-Z
Self Refresh Enter
SelfRefresh Exit
AutoRefresh
Note: To Enter SelfRefresh Mode
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.
Note: To Exit SelfRefresh Mode
4. System clock restart and be stable before returning CKE high.
5. Enable CKE and CKE should be set high for minimum time of tSRX.
6. CS# starts from high.
7. Minimum tRC is required after CKE going high to complete SelfRefresh exit.
8. 2048 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
system uses burst refresh.
Preliminary
28
December 1998
EtronTech
EM636327
Figure 6.1. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 - A 8
RAx
CAx
DQM
tHZ
DQ Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Ax2
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Ax3
Clock Suspend
3 Cycles
Note: CKE to CLK disable/enable = 1 clock
Preliminary
29
December 1998
EtronTech
EM636327
Figure 6.2. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 - A 8
RAx
CAx
DQM
t HZ
DQ Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Clock Suspend
1 Cycle
Ax3
Ax2
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
Note: CKE to CLK disable/enable = 1 clock
Preliminary
30
December 1998
EtronTech
EM636327
Figure 6.3. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0
T1
T 2 T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 - A 8
RAx
CAx
DQM
tHZ
DQ Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Ax2
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Ax3
Clock Suspend
3 Cycles
Note: CKE to CLK disable/enable = 1 clock
Preliminary
31
December 1998
EtronTech
EM636327
Figure 7.1. Clock Suspension During Burst Write (Using CKE)
(Burst Length = 4, CAS# Latency = 1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 - A 8
RAx
CAx
DQM
DQ Hi-Z
DAx0
DAx1
DAx2
Activate
Clock Suspend Clock Suspend
Command
1 Cycle
2 Cycles
Bank A
Write
Command
Bank A
DAx3
Clock Suspend
3 Cycles
Note: CKE to CLK disable/enable = 1 clock
Preliminary
32
December 1998
EtronTech
EM636327
Figure 7.2. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 - A 8
RAx
CAx
DQM
DQ Hi-Z
DAx0
Activate
Command
Bank A
DAx1
DAx2
Clock Suspend Clock Suspend
1 Cycle
2 Cycles
DAx3
Clock Suspend
3 Cycles
Write
Command
Bank A
Note: CKE to CLK disable/enable = 1 clock
Preliminary
33
December 1998
EtronTech
EM636327
Figure 7.3. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
A0 - A 8
RAx
RAx
CAx
DQM
DQ Hi-Z
DAx0
Activate
Command
Bank A
DAx1
Clock Suspend Clock Suspend
1 Cycle
2 Cycles
Write
Command
Bank A
DAx2
DAx3
Clock Suspend
3 Cycles
Note: CKE to CLK disable/enable = 1 clock
Preliminary
34
December 1998
EtronTech
EM636327
Figure 8. Power Down Mode and Clock Mask (Burst Lenght=4, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
tPDE
t IS
CKE
Valid
CS#
RA S#
CA S#
WE#
BS
A9
RAx
A0~ A8
RAx
CAx
DQM
tHZ
Hi-Z
Ax0
DQ
ACTIVE
STANDBY
Activate
Read
Command
Command
Bank A
Bank A
Power Down
Power Down
Mode Entry
Mode Exit
Preliminary
Ax1
Ax2
Clock Mask
Start
Clock Mask
End
Ax3
Precharge
Command
Bank A
Power Down
Mode Entry
35
PRECHARGE
STANDBY
Power Down
Mode Exit
Any
Command
December 1998
EtronTech
EM636327
Figure 9.1. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
A0 ~ A8
RAz
RAw
RAw CAw
CAy
CAx
RAz
CAz
DQM
DQ Hi-Z
Aw0
Activate
Command
Bank A
Read
Command
Bank A
Preliminary
Aw1 Aw2
Aw3 Ax0
Read
Command
Bank A
Ax1
Ay0
Ay1 Ay2
Read
Command
Bank A
Ay3
Az0
Az1 Az2
Az3
Precharge
Read
Command
Command
Bank A
Bank A
Activate
Command
Bank A
36
December 1998
EtronTech
EM636327
Figure 9.2. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAw
A0 ~ A8
RAw
RAz
CAw
CAx
RAz
CAy
CAz
DQM
DQ
Hi-Z
Aw0
Activate
Command
Bank A
Preliminary
Read
Command
Bank A
Aw1 Aw2
Read
Command
Bank A
Aw3
Ax0
Ax1 Ay0
Read
Command
Bank A
Ay1
Ay2
Precharge
Command
Bank A
37
Az0
Ay3
Activate
Command
Bank A
Az1
Az2
Az3
Read
Command
Bank A
December 1998
EtronTech
EM636327
Figure 9.3. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAw
A0 ~ A8
RAw
RAz
CAw
CAx
RAz
CAy
CAz
DQM
DQ
Hi-Z
Aw0
Activate
Command
Bank A
Preliminary
Read
Command
Bank A
Aw1 Aw2
Read
Command
Bank A
Aw3
Read
Command
Bank A
38
Ax0
Ax1
Ay0
Ay1
Precharge
Command
Bank A
Ay2
Az0
Ay3
Activate
Command
Bank A
Read
Command
Bank A
December 1998
EtronTech
EM636327
Figure 10.1. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RBw
A0 ~ A8
RBw
RBz
CBw
CBx
CBy
RBz
CBz
DQM
DQ Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
Activate
Command
Bank A
Write
Command
Bank B
Preliminary
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank B
39
DBz0 DBz1 DBz2 DBz3
Write
Command
Bank B
December 1998
EtronTech
EM636327
Figure 10.2. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RBw
A0 ~ A8
RBw
RBz
CBw
CBx
RBz
CBy
CBz
DQM
DQ
Hi-Z
Activate
Command
Bank A
Preliminary
DBz0 DBz1 DBz2 DBz3
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank B
40
Activate
Command
Bank B
Write
Command
Bank B
December 1998
EtronTech
EM636327
Figure 10.3. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RBw
A0 ~ A8
RBw
RBz
CBw
CBx
RBz
CBy
CBz
DQM
DQ
Hi-Z
Activate
Command
Bank A
Preliminary
DBz0 DBz1 DBz2
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
41
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
December 1998
EtronTech
EM636327
Figure 11.1. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE High
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RBx
A0 ~ A8
RBx
RAx
RAx
CBx
RBy
RBy
CAx
CBy
tRCD
DQ
tRP
tAC1
DQM
Hi-Z
Bx0
Activate
Command
Bank B
Read
Command
Bank B
Preliminary
Bx1
Bx2
Bx3
Bx4
Bx5
Bx6
Bx7
Ax0
Ax1
Activate
Command
Bank A
Ax2
Precharge
Command
Bank B
Activate
Read
Command
Command
Bank B
Bank A
42
Ax3
Ax4
Ax5
Ax6
Ax7
By0
Read
Command
Bank B
By1
By2
Precharge
Command
Bank A
December 1998
EtronTech
EM636327
Figure 11.2. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE High
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RBx
A0 ~ A8
RBx
RAx
RAx
CBx
tRCD
RBy
RBy
CAx
CBy
tRP
tAC2
DQM
DQ Hi-Z
Activate
Command
Bank B
Preliminary
Bx0
Read
Command
Bank B
Bx1
Bx2
Bx3
Bx4
Activate
Command
Bank A
Bx5
Bx6
Bx7
Ax0
Precharge
Command
Bank B
Read
Command
Bank A
43
Ax1
Activate
Command
Bank B
Ax2
Ax3
Ax4
Ax5
Ax6
Ax7
By0
By1
Read
Command
Bank B
December 1998
EtronTech
EM636327
Figure 11.3. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE High
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RBx
A0 ~ A8
RBx
RBy
RAx
CBx
tRCD
RAx
CBy
RBy
CAx
tRP
tAC3
DQM
DQ
Hi-Z
Activate
Command
Bank B
Preliminary
Bx0
Read
Command
Bank B
Bx1
Bx2
Activate
Command
Bank A
Bx3
Bx4
Bx5
Read
Command
Bank A
44
Bx6
Bx7
Precharge
Command
Bank B
Ax0
Ax1
Ax2
Activate
Command
Bank B
Ax3
Ax4 Ax5
Read
Command
Bank B
Ax6
Ax7
By0
Precharge
Command
Bank A
December 1998
EtronTech
EM636327
Figure 12.1. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE High
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 ~ A8
RAx
CAx
RBx
RAy
RBx CBx
RAy
tRCD
tRP
CAy
t WR
DQM
DQHi-Z
Activate
Command
Bank A
Write
Command
Bank A
Preliminary
DAy0 DAy1 DAy2 DAy3
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
45
Precharge
Command
Bank B
Write
Command
Bank A
December 1998
EtronTech
EM636327
Figure 12.2. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE High
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 ~ A8
RAx
CAx
RBx
tRCD
DQM
RAy
RBx
Hi-Z
DQ
Activate
Command
Bank A
CBx
tWR*
RAy
tRP
CAy
tWR*
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1DAy2
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
DAy3 DAy4
Write
Command
Bank A
Precharge
Command
Bank B
* tWR > tWR(min.)
Preliminary
46
December 1998
EtronTech
EM636327
Figure 12.3. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE High
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 ~ A8
RAx
RAy
RBx
CAx
RBx
CBx
tRCD
RAy
tWR*
tRP
CAy
tWR*
DQM
DQ Hi-Z
Activate
Command
Bank A
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
DBx3 DBx4 DBx5 DBx6 DBx7 DAy0
Precharge
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
DAy1 DAy2 DAy3
Precharge
Command
Bank B
* tWR > tWR(min.)
Preliminary
47
December 1998
EtronTech
EM636327
Figure 13.1. Read and Write Cycle (Burst Length=4, CAS# Latency=1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 ~ A8
RAx
CAx
CAy
CAz
DQM
DQ
Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Preliminary
Ax1
Ax2
Ax3
DAy0 DAy1
DAy3
Az0
Read
Write
The Write Data
Command is Masked with a Command
Bank A
Bank A
Zero Clock
Latency
48
Az1
Az3
The Read Data
is Masked with a
Two Clock
Latency
Precharge
Command
Bank B
December 1998
EtronTech
EM636327
Figure 13.2. Read and Write Cycle (Burst Length=4, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 ~ A8
RAx
CAx
CAz
CAy
DQM
DQ
Hi-Z
Ax0
Activate
Command
Bank A
Preliminary
Read
Command
Bank A
Ax1
Ax2
Ax3
DAy0 DAy1
DAy3
Write
The Write Data
Command is Masked with a
Bank A
Zero Clock
Latency
49
Az0
Read
Command
Bank A
Az1
Az3
The Read Data
is Masked with a
Two Clock
Latency
December 1998
EtronTech
EM636327
Figure 13.3. Read and Write Cycle (Burst Length=4, CAS# Latency=3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 ~ A8
RAx
CAy
CAx
CAz
DQM
DQ
Hi-Z
Ax0
Activate
Command
Bank A
Preliminary
Ax1
Ax2
Ax3
Read
Command
Bank A
DAy0 DAy1
DAy3
Write
The Write Data
Read
Command is Masked with a Command
Bank A
Zero Clock
Bank A
Latency
50
Az0
Az1
Az3
The Read Data
is Masked with a
Two Clock
Latency
December 1998
EtronTech
EM636327
Figure 14.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RA S#
CA S#
WE#
DSF
BS
A9
RAx
A0~ A8
RAx
DQM
DQ Hi-Z
RBw
RAx
CBw
Ax2
Ax3
CBy
CBx
CBz
CAy
tRCD tAC1
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Preliminary
RBw
Ax1
Bw0
Activate
Command
Bank B
Read
Command
Bank B
Bw1
Bx0
Read
Command
Bank B
Bx1
By0
Read
Command
Bank B
51
By1
Ay0
Read
Command
Bank A
Ay1
Bz0
Read
Command
Bank B
Bz1
Bz2
Precharge
Command
Bank A
Bz3
Precharge
Command
Bank B
December 1998
EtronTech
EM636327
Figure 14.2. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 ~ A8
RAx
CAy
tRCD
DQM
DQ
RAx
RAx
Preliminary
CBy
CAy
CBz
tAC2
Hi-Z
Ax0
Activate
Command
Bank A
CBx
CBw
Read
Command
Bank A
Ax1
Activate
Command
Bank B
Ax2
Ax3
Read
Command
Bank B
Bw0
Read
Command
Bank B
Bw1
Bx0
Bx1
Read
Command
Bank B
52
By0
By1
Read
Command
Bank A
Ay0
Ay1
Bz0
Read
Command
Bank B
Precharge
Command
Bank A
Bz1
Bz2
Bz3
Precharge
Command
Bank B
December 1998
EtronTech
EM636327
Figure 14.3. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 ~ A8
RAx
RBx
CAx
tRCD
DQM
RBx
Ax0
Activate
Command
Bank A
CBy
CBz
CAy
Bx1
By0 By1
tAC3
DQ Hi-Z
Preliminary
CBx
Read
Command
Bank A
Activate
Command
Bank B
Ax1 Ax2
Read
Command
Bank B
Ax3 Bx0
Read
Command
Bank B
53
Read
Command
Bank B
Bz0
Bz1
Read
Prechaerge
Command Command
Bank A
Bank B
Ay0
Ay1
Ay2
Ay3
Precharge
Command
Bank A
December 1998
EtronTech
EM636327
Figure 15.1. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RA S#
CA S#
WE#
DSF
BS
A9
RAx
A0~ A8
RAx
RBw
CAx
RBw
CBw
CBx
CBy
CBz
CAy
tRP
DQM
tRCD
tWR tRP
tRRD
DQ Hi-Z
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1
Activate
Activate
Command
Command
Bank A
Bank B
Write
Command
Bank A
Preliminary
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
54
Write
Command
Bank A
DBz0 DBz1 DBz2 DBz3
Write
Command
Bank B
Precharge
Command
Bank A
Precharge
Command
Bank B
December 1998
EtronTech
EM636327
Figure 15.2. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
C S#
RA S#
CA S#
WE#
DSF
BS
A9
RAx
A0~A8
RAx
DQM
RBw
CAx
RBw
CBw
CBx
CBy
CAy
tRCD
CBz
tRP
t WR
tRP
tRRD
DQ Hi-Z
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Activate
Command
Bank A
Preliminary
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
55
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank A
Precharge
Command
Bank B
December 1998
EtronTech
EM636327
Figure 15.3. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 ~ A8
RAx
RBw
CAx
RBw
CBw
CBx
CBy
CAy
tRCD
DQM
CBz
tWR
tRP
tWR(min)
tRRD > tRRD(min)
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Activate
Command
Bank A
Preliminary
Activate
Command
Bank B
Write
Command
Bank A
Write
Command
Bank B
Write
Command
Bank B
56
Write
Command
Bank B
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank A
Precharge
Command
Bank B
December 1998
EtronTech
EM636327
Figure 16.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
High
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 ~ A8
RAx
RBy
RBx
RBx CBx
CAx
CAy
RBy
Bx3
Ay0
RBz
CBy
RBz
CBz
DQM
DQ
Hi-Z
Activate
Command
Bank A
Read
Command
Bank A
Preliminary
Ax0
Ax1
Ax2
Ax3
Bx0
Activate
Command
Bank B
Read with
Auto Precharge
Command
Bank B
Bx1
Bx2
Activate
Command
Bank B
Read with
Auto Precharge
Command
Bank A
57
Ay1
Ay2
Ay3
By0
Read with
Auto Precharge
Command
Bank B
By1
By2
By3
Bz0
Bz1
Bz2
Bz3
Activate
Command
Bank B
Read with
Auto Precharge
Command
Bank B
December 1998
EtronTech
EM636327
Figure 16.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
High
CS#
RA S#
CA S #
DSF
WE #
BS
A9
RAx
A0 ~ A 8
RAx
RBx
CAx
RAz
RBy
RBx
CBx
RBy
RAy
CBy
CAz
RAz
DQM
DQ
Hi-Z
Activate
Command
Bank A
Preliminary
Ax0
Read
Command
Bank A
Ax1
Ax2
Ax3
Read with
Activate
Command Auto Precharge
Command
Bank B
Bank B
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
By0
By1
By2
By3
Az0
Az1
Az2
Read with
Activate
Read with
Activate
Read with
Auto Precharge Command Auto Precharge Command Auto Precharge
Command
Bank B
Command
Bank A
Command
Bank A
Bank B
Bank A
58
December 1998
EtronTech
EM636327
Figure 16.3. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE High
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 ~ A8
RAx
RBx
CAx
RBy
CBx
RBx
CAy
CBy
RBy
DQM
DQ
Hi-Z
Activate
Command
Bank A
Preliminary
Ax0
Activate
Command
Bank B
Read
Command
Bank A
Ax1
Ax2
Read with
Auto Precharge
Command
Bank B
Ax3
Bx0
Bx1
Bx2
Read with
Auto Precharge
Command
Bank A
59
Bx3
Ay0
Activate
Command
Bank B
Ay1
Ay2
Ay3
By0
By1
By2
By3
Read with
Auto Precharge
Command
Bank B
December 1998
EtronTech
EM636327
Figure 17.1. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
T9
CLK
tCK1
CKE
High
CS#
RAS#
CA S#
WE#
WE#
BS
A9
A0 ~ A8
RAx
RBx
RAx CAx
RBx
RAz
RBy
CBx
RBy
CAy
CBy
RAz
CAz
DQM
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 DBy0 DBy1 DBy2 DBy3
Activate
Command
Bank A
Write
Command
Bank A
Preliminary
Write with
Activate
Command Auto Precharge
Command
Bank B
Bank B
Write with
Auto Precharge
Command
Bank A
Write with
Activate
Command Auto Precharge
Command
Bank B
Bank B
60
DAz0 DAz0 DAz0 DAz0
Activate
Command
Bank A
Write with
Auto Precharge
Command
Bank A
December 1998
EtronTech
EM636327
Figure 17.2. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
High
CS#
RAS#
CA S#
WE#
WE#
BS
A9
A0 ~ A8
RBx
RAx
RAx
CAx
RBx
RAz
RBy
CBx
CAy
RBy
CBy
RAz
CAz
DQM
DQ
Hi-Z
Activate
Command
Bank A
Preliminary
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3
Write
Command
Bank A
Activate
Write with
Command Auto Precharge
Bank B
Command
Bank B
Write with
Auto Precharge
Command
Bank A
61
DBy0 DBy1 DBy2 DBy3 DAz0 DAz1 DAz2 DAz3
Activate
Write with
Activate
Write with
Command Auto Precharge Command Auto Precharge
Bank B
Command
Bank A
Command
Bank B
Bank A
December 1998
EtronTech
EM636327
Figure 17.3. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE High
CS#
RA S#
CA S#
WE#
DSF
`
BS
A9
RAx
A0~ A8
RAx
RBy
RBx
CAx
RBx
CBx
CAy
RBy
CBy
DQM
DQ Hi-Z
Activate
Command
Bank A
Preliminary
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3
Activate
Command
Bank B
Write
Command
Bank A
Write with
Auto Precharge
Command
Bank B
Write with
Auto Precharge
Command
Bank A
62
Activate
Command
Bank B
DBy0 DBy1 DBy2 DBy3
Write with
Auto Precharge
Command
Bank B
December 1998
EtronTech
EM636327
Figure 18.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE High
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
RBx
A0 ~ A8
RAx
CAx RBx
CBx
RBy
tRP
tRRD
DQM
DQ
RBy
Hi-Z
Ax
Activate
Activate
Command Command
Bank A
Bank B
Read
Command
Bank A
Preliminary
Ax+1 Ax+2 Ax-2 Ax-1
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Ax
Ax+1 Bx
Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6 Bx+7
Read
Command
Bank B
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
63
Precharge
Command
Bank B
Burst Stop
Activate
Command
Command
Bank B
December 1998
EtronTech
EM636327
Figure 18.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
High
CS#
RA S#
CA S#
WE#
DSF
BS
A9
RAx
A0~ A8
RAx
RBy
RBx
CAx
RBx
RBy
CBx
tRP
DQM
DQ Hi-Z
Activate
Command
Bank A
Preliminary
Ax
Read
Command
Bank A
Ax+1 Ax+2 Ax-2
Ax-1
Ax
Ax+1
Bx
Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6
Activate
Read
Precharge
Command
CommandFull Page burst operation does not
Command
Bank B
Bank B terminate when the burst length is satisfied;
Bank B
The burst counter wraps
the burst counter increments and continues
from the highest order
bursting beginning with the starting address.
page address back to zero
Burst Stop
during this time interval
Command
64
Activate
Command
Bank B
December 1998
EtronTech
EM636327
Figure 18.3. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE High
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 ~ A8
RAx
RBy
RBx
CAx
RBx
CBx
RBy
tRP
DQM
DQ
Hi-Z
Activate
Command
Bank A
Preliminary
Ax
Read
Command
Bank A
Activate
Command
Bank B
Ax+1 Ax+2 Ax-2
Ax-1
Read
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
65
Ax
Ax+1
Bx
Bx+1 Bx+2 Bx+3 Bx+4 Bx+5
Full Page burst operation does not Precharge
Command
terminate when the burst length is
Bank B
satisfied; the burst counter
increments and continues
bursting beginning with the
Burst Stop
starting address.
Command
Activate
Command
Bank B
December 1998
EtronTech
EM636327
Figure 19.1. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE High
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 ~ A8
RAx
RBy
RBx
CAx
RBx
CBx
RBy
DQM
DQ
Hi-Z
DAx DAx+ 1 DAx+ 2 DAx+ 3 DA x- 1 DAx DAx+ 1 DBx
Activate
Command
Bank B
The burst counter wraps
from the highest order
Write
page address back to zero
Command
during this time interval
Bank A
Activate
Command
Bank A
Preliminary
DBx+ 1 DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5 DBx+ 6 DBx+ 7
Write
Command
Bank B
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
beginning with the starting address.
66
Data is ignored
Precharge
Command
Bank B
Burst Stop
Activate
Command
Command
Bank B
December 1998
EtronTech
EM636327
Figure 19.2. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
High
CS#
RAS#
CA S#
WE#
DSF
BS
A9
A0 ~ A8
RAx
RAx
RBx
CAx
RBx
RBy
CBx
RBy
DQM
DQ
Hi-Z
Activate
Command
Bank A
Preliminary
DAx DAx+ 1 DAx+ 2 DAx+ 3 DA x- 1 DAx DAx+ 1 DBx
Write
Command
Bank A
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
DBx+ 1 DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5 DBx+ 6
Write
Command
Bank B
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
beginning with the starting address.
67
Data is ignored
Precharge
Command
Bank B
Burst Stop
Command
Activate
Command
Bank B
December 1998
EtronTech
EM636327
Figure 19.3. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE High
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 ~ A8
RAx
RBx
CAx
RBx
RBy
RBy
CBx
DQM
Data is ignored
DQ
Hi-Z
Activate
Command
Bank A
Preliminary
DAx DAx+ 1 DAx+ 2 DAx+ 3 DA x- 1 DAx DAx+ 1 DBx
Write
Command
Bank A
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
DBx+ 1 DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5
Write
Command
Bank B
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
beginning with the starting address.
68
Precharge
Command
Bank B
Burst Stop
Command
Activate
Command
Bank B
December 1998
EtronTech
EM636327
Figure 20. Byte Write Operation (Burst Length=4, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
High
CS#
RAS#
CA S#
WE #
DSF
BS
A9
RAx
A0 ~ A 8
RAx
CAy
CAx
CAz
DQM0
DQM1~3
DQ0 - DQ7
Ax0
DQ8 - DQ31
Activate
Command
Bank A
Preliminary
Ax1
Ax2
Ax1
Ax2
Read Upper 3 Bytes
Command are masked
Bank A
Lower Byte
is masked
DAy1 DAy2
Ax3
DAy0 DAy1
DAy3
Write
Upper 3 Bytes
Read
Command are masked Command
Bank A
Bank A
69
Az0
Az1
Az2
Az1
Az2
Lower Byte
is masked
Az3
Lower Byte
is masked
December 1998
EtronTech
EM636327
Figure 21. Burst Read and Single Write Operation (Burst Length=4, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE High
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0~ A8
RAx
CAw
CAx
CAx
CAz
CAy
DQM0
DQM1~3
DQ0 - DQ7
DQ8 - DQ31
Hi-Z
Ax0
Ax1
Ax2
Ax3
DQw0
Ax0
Ax1
Ax2
Ax3
DQw0
Ay0 Ay1
Hi-Z
Activate
Command
Bank A
Preliminary
Read
Command
Bank A
Single Write Single Write
Command Command
Bank A
Bank A
70
Ay0
DQx0
Read
Command
Bank A
Lower Byte
is masked
Lower Byte
is masked
Ay2
Ay3
Az0
Ay3
Az0
Single Write
Command
Bank A
Lower Byte
is masked
December 1998
EtronTech
EM636327
Figure 22. Full Page Burst Read and Single Write Operation
(Burst Length=Full Page, CAS# Latency=3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE High
CS#
RAS#
CA S#
WE#
DSF
BS
A9
A0~ A8
RAv
RAv
CAv
CAw
CAx
CAy
DQM0
DQM1~3
DQ0 - DQ7
Av0
Av1
Av2
Av3
DQw0
DQx0
Ay0
Ay1
Ay2
Ay3
DQ8 - DQ31
Av0
Av1
Av2
Av3
DQw0
DQx0
Ay0
Ay1
Ay2
Ay3
Activate
Command
Bank A
Preliminary
Read
Command
Bank A
Burst Stop
Command
Single Write Single Write
Command
Command
Bank A
Bank A
71
Read
Command
Bank A
Burst Stop
Command
December 1998
EtronTech
EM636327
Figure 23. Random Row Read (Interleaving Banks)
(Burst Length=2, CAS# Latency=1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
High
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
CS#
RA S#
CA S#
WE#
DSF
BS
A9
RBu
A0~ A8
RBu
CBu
RAu
RBv
RAv
RAu CAu
RBv CBv
RAv
tRP
DQM
DQ
Bu0
Bu1 Au0
CAv
tRP
Au1
RAw
RBw
RBw CBw
t RP
Bv0 Bv1
Av0
RAw CAw RBx
t RP
Av1
RBx
tRP
Bw0 Bw1
RAx
CBx RAx CAx
t RP
Aw0
Aw1 Bx0
RAy
RBy CBy
RAy CAy RBz
tRP
Bx1
RBz
RBy
tRP
Ax0
Ax1 By0
tRP
By1
RAz
CBz RAz
t RP
Ay0 Ay1
Bz0
Activate
Command
Bank B
Activate
Activate
Activate
Activate
Activate
Activate
Activate
Activate
Activate
Activate
Activate
Command
Command
Command
Command
Command
Command
Command
Command
Command
Command
Command
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
with Auto
with Auto
with Auto
with Auto
with Auto
with Auto
with Auto
with Auto
with Auto
with Auto
with Auto
Precharge
Precharge
Precharge
Precharge
Precharge
Precharge
Precharge
Precharge
Precharge
Precharge
Precharge
Preliminary
72
December 1998
EtronTech
EM636327
Figure 24. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RA S#
CA S #
WE #
DSF
BS
A9
RAx
A0 ~ A 8
RAx
RBx
RBx
RBw
CAx
CBx
CAy
CBy
CAz
CBz
RBw
tRP
DQM
tRRD
tRCD
DQ
Ax0
Activate
Command
Bank A
Preliminary
Activate
Command
Bank B
Read
Command
Bank B
Read
Read
Command
Command
Bank
A
Bank A
Bx0
Ay0 Ay1
Read
Command
Bank B
By0
Read
Command
Bank A
73
By1
Az0 Az1
Read
Command
Bank B
Az2
Bz0 Bz1
Bz2
Precharge
Command Bank B
(Precharge Temination)
Activate
Command
Bank B
December 1998
EtronTech
EM636327
Figure 25. Full Page Random Column Write (Burst Length=Full Page, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
A0 ~ A8
RAx
RBx
RAx
RBx
RBw
CAx
CBx
CAy
CBy
CAz
CBz
RBw
t WR
tRP
DQM
tRRD
DQ
DAx0 DBx0 DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1 DBz2
Activate
Command
Bank A
Preliminary
tRCD
Activate
Write
Command
Command
Bank B
Bank B
Write
Write
Command
Command
Bank
A
Bank A
Write
Command
Bank B
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command Bank B
(Precharge Temination)
Write Data
is masked
74
Activate
Command
Bank B
December 1998
EtronTech
EM636327
Figure 26.1. Precharge Termination of a Burst (Burst Length=Full Page, CAS# Latency=1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CA S#
WE#
DSF
BS
A9
RAx
A0 ~ A8
RAx
RAy
RAz
RAy CAy
CAx
RAz CAz
tRP
tWR tRP
DQM
DQ
Activate
Precharge Termination
Command
of a Write Burst.
Bank A
Write data is masked.
Write
Command
Bank A
Preliminary
Ay0
DAx0 DAx1 DAx2 DAx3 DAx4
Read
Precharge
Command
Command
Bank
A
Bank A
Activate
Command
Bank A
75
Ay1
Ay2
Precharge
Termination of
a Read Burst.
DAz0
DAz1 DAz2 DAz3
DAz4 DAz5
DAz6 DAz7
Precharge
Write
Command
Command
Bank A
Bank A
Activate
Command
Bank A
December 1998
EtronTech
EM636327
Figure 26.2. Precharge Termination of a Burst
(Burst Length=8 or Full Page, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
High
CS#
RAS#
CA S#
WE#
DSF
BS
A9
A0 ~ A8
RAx
RAx
RAy
RAy
CAx
tWR
RAz
CAy
RAz
tRP
CAz
tRP
tRP
DQM
DQ
DAx0 DAx1DAx2 DAx3
Activate
Command
Bank A
Write
Command
Bank A
Ay0
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Precharge Termination
of a Write Burst.
Write data is masked.
Preliminary
76
Ay1
Precharge
Command
Bank A
Ay2
Activate
Command
Bank A
Az0
Az1
Az2
Precharge
Read
Command
Command
Bank A
Bank A
Precharge Termination
of a Read Burst
December 1998
EtronTech
EM636327
Figure 26.3. Precharge Termination of a Burst
(Burst Length=4, 8 or Full Page, CAS# Latency=3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
High
CS#
RAS#
CA S#
WE#
DSF
BS
A9
A0 ~ A8
RAx
RAx
RAy
RAy
CAx
t WR
RAz
CAy
RAz
tRP
tRP
DQM
DQ
Ay0
DAx0 DAx1
Activate
Command
Bank A
Write
Command
Bank A
Write Data
is masked
Preliminary
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Ay1
Ay2
Activate Precharge Termination
Command
of a Read Burst
Bank A
Precharge Termination
of a Write Burst
77
December 1998
EtronTech
EM636327
100 Pin 14x20 mm Package Outline Drawing Information
D
D1
(D3)
(E3)
A
θ
E1
E
A
PIN #1
L
(L1)
SECTION A - A
e
A2
A
SEATING PLANE
b
y
A1
C
Packaging Dimensions
Unit = mm
EM636327Q-XX
Symbol
A
A1
A2
b
C
D
D1
D3
E
E1
E3
e
L
L1
y
θ
Definition
Overall Height
Stand Off
Body Thickness
Lead Width
Lead Thickness
Terminal Dimension
Package Body
Reference
Terminal Dimension
Package Body
Reference
Lead Pitch
Foot Length
Lead Length
Coplanarity
Lead Angle
Preliminary
min
0.25
2.60
0.22
0.13
22.95
19.90
16.95
13.90
0.65
0.00°
EM636327TQ-XX
EM636327JT-XX
min
normal
3.00
0.38
0.23
23.45
20.10
0.05
1.35
0.22
0.09
21.90
19.90
0.10
1.40
0.32
17.45
14.10
15.90
13.90
0.95
0.45
0.10
7.00°
0.00°
normal
max
3.40
2.80
0.30
0.15
23.20
20.00
18.85 REF.
17.20
14.00
12.35 REF.
0.65 REF.
0.80
1.60 REF.
78
22.00
20.00
18.85 REF.
16.00
14.00
12.35 REF.
0.65 REF.
0.60
1.00 REF.
max
1.60
0.15
1.45
0.38
0.20
22.10
20.10
min
normal
0.05
0.95
0.25
0.12
23.00
19.90
16.10
14.10
17.00
13.90
0.75
0.73
0.10
1.00
0.32
0.145
23.20
20.00
18.85 REF.
17.20
14.00
12.35 REF.
0.65 REF.
0.88
1.60 REF.
0.10
7.00°
0.00°
max
1.27
0.15
1.12
0.40
0.23
23.40
20.10
17.40
14.10
1.03
0.10
7.00°
December 1998