TI DAC8568IBPW 12-/14-/16-bit, octal-channel, ultra-low glitch, voltage output digital-to-analog converters with 2.5v, 2ppm/â°c internal reference Datasheet

DAC7568
DAC8168
DAC8568
www.ti.com ..................................................................................................................................................... SBAS430A – JANUARY 2009 – REVISED APRIL 2009
12-/14-/16-Bit, Octal-Channel, Ultra-Low Glitch, Voltage Output
DIGITAL-TO-ANALOG CONVERTERS with 2.5V, 2ppm/°C Internal Reference
FEATURES
APPLICATIONS
• Relative Accuracy:
– DAC7568 (12-Bit): 0.3 LSB INL
– DAC8168 (14-Bit): 1 LSB INL
– DAC8568 (16-Bit): 4 LSB INL
• Glitch Energy: 0.1nV-s
• Internal Reference:
– 2.5V Reference Voltage (disabled by
default)
– 0.004% Initial Accuracy (typ)
– 2ppm/°C Temperature Drift (typ)
– 5ppm/°C Temperature Drift (max)
– 20mA Sink/Source Capability
• Power-On Reset to Zero Scale or Midscale
• Ultra-Low Power Operation: 1.25mA at 5V
Including Internal Reference Current
• Wide Power-Supply Range: +2.7V to +5.5V
• Monotonic Over Entire Temperature Range
• Low-Power Serial Interface with
Schmitt-Triggered Inputs: Up to 50MHz
• On-Chip Output Buffer Amplifier with
Rail-to-Rail Operation
• Temperature Range: –40°C to +125°C
•
•
•
•
1
234
AVDD
•
DESCRIPTION
The DAC7568, DAC8168, and DAC8568 are
low-power, voltage-output, eight-channel, 12-, 14-,
and 16-bit digital-to-analog converters (DACs),
respectively. These devices include a 2.5V, 2ppm/°C
internal reference (disabled by default), giving a
full-scale output voltage range of 2.5V or 5V. The
internal reference has an initial accuracy of 0.004%
and can source up to 20mA at the VREFIN/VREFOUT
pin. These devices are monotonic, providing excellent
linearity and minimizing undesired code-to-code
transient voltages (glitch). They use a versatile 3-wire
serial interface that operates at clock rates up to
50MHz. The interface is compatible with standard
SPI™, QSPI™, Microwire™, and digital signal
processor (DSP) interfaces.
VREFIN/VREFOUT
DAC7568
DAC8168
DAC8568
2.5V
Reference
DAC Register H
12-/14-/16-Bit
DAC
VOUTH
Data Buffer G
DAC Register G
12-/14-/16-Bit
DAC
VOUTG
Data Buffer F
DAC Register F
12-/14-/16-Bit
DAC
VOUTF
Data Buffer E
DAC Register E
12-/14-/16-Bit
DAC
VOUTE
Data Buffer D
DAC Register D
12-/14-/16-Bit
DAC
VOUTD
Data Buffer C
DAC Register C
12-/14-/16-Bit
DAC
VOUTC
Data Buffer B
DAC Register B
12-/14-/16-Bit
DAC
VOUTB
Data Buffer A
DAC Register A
12-/14-/16-Bit
DAC
VOUTA
Buffer Control
Register Control
Data Buffer H
Portable Instrumentation
Closed-Loop Servo-Control/Process Control
Data Acquisition Systems
Programmable Attenuation, Digital Gain, and
Offset Adjustment
Programmable Voltage and Current Sources
The DAC7568, DAC8168, and DAC8568 incorporate
a power-on-reset circuit that ensures the DAC output
powers up at either zero scale or midscale until a
valid code is written to the device. These devices
contain a power-down feature, accessed over the
serial interface, that reduces current consumption to
typically 0.18µA at 5V. Power consumption (including
internal reference) is typically 2.9mW at 3V, reducing
to less than 1µW in power-down mode. The low
power consumption, internal reference, and small
footprint make these devices ideal for portable,
battery-operated equipment.
The DAC7568, DAC8168, and DAC8568 are drop-in
and function-compatible with each other, and are
available in TSSOP-16 and TSSOP-14 packages.
SYNC
SCLK
32-Bit Shift Register
DIN
Power-Down
Control Logic
Control Logic
GND
LDAC
CLR
DEVICE COMPARISON
12-BIT
14-BIT
16-BIT
Pin- and
Function-Compatible
DAC7568
DAC8168
DAC8568
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
DAC7568
DAC8168
DAC8568
SBAS430A – JANUARY 2009 – REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
MAXIMUM
RELATIVE
ACCURACY
(LSB)
MAXIMUM
DIFFERENTIAL
NONLINEARITY
(LSB)
MAXIMUM
REFERENCE
DRIFT
(ppm/°C)
OUTPUT
VOLTAGE
FULL-SCALE
RANGE
DAC8568A
±12
±1
25
DAC8568B
±12
±1
25
DAC8568C
±12
±1
5
DAC8568D
±12
±1
DAC8168A
±4
±0.5
DAC8168C
±4
±0.5
DAC7568A
±1
DAC7568C
±1
(1)
RESET TO
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
2.5V
Zero
TSSOP-16
PW
–40°C to +125°C
DA8568A
2.5V
Midscale
TSSOP-16
PW
–40°C to +125°C
DA8568B
5V
Zero
TSSOP-16
PW
–40°C to +125°C
DA8568C
5
5V
Midscale
TSSOP-16
PW
–40°C to +125°C
DA8568D
25
2.5V
Zero
TSSOP-14
PW
–40°C to +125°C
DA8168A
5
5V
Zero
TSSOP-16
PW
–40°C to +125°C
DA8168C
±0.25
25
2.5V
Zero
TSSOP-14
PW
–40°C to +125°C
DA7568A
±0.25
5
5V
Zero
TSSOP-16
PW
–40°C to +125°C
DA7568C
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
AVDD to GND
DAC7568/DAC8168/DAC8568
UNIT
–0.3 to +6
V
Digital input voltage to GND
–0.3 to +AVDD + 0.3
V
VOUT to GND
–0.3 to +AVDD + 0.3
V
VREF to GND
–0.3 to +AVDD + 0.3
V
Operating temperature range
–40 to +125
°C
Storage temperature range
–65 to +150
°C
+150
°C
Junction temperature range (TJ max)
Power dissipation
(TJ max – TA)/θJA
W
Thermal impedance, θJA
+118
°C/W
Thermal impedance, θJC
+29
°C/W
(1)
2
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
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ELECTRICAL CHARACTERISTICS
At AVDD = 2.7V to 5.5V and over –40°C to +125°C (unless otherwise noted).
DAC7568/DAC8168/DAC8568
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE (1)
Resolution
DAC8568
16
Relative accuracy
Measured by the line passing through codes 485 and
64714
Differential nonlinearity
16-bit monotonic
Resolution
DAC8168
Relative accuracy
Measured by the line passing through codes 120 and
16200
Differential nonlinearity
14-bit monotonic
±12
LSB
±0.2
±1
LSB
Bits
±1
±4
LSB
±0.1
±0.5
LSB
12
Relative accuracy
Measured by the line passing through codes 30 and
4050
Differential nonlinearity
12-bit monotonic
Offset error
±4
14
Resolution
DAC7568
Bits
Extrapolated from two-point line (1), unloaded
Offset error drift
Bits
±0.3
±1
LSB
±0.05
±0.25
LSB
±1
±4
Full-scale error
DAC register loaded with all '1's
±0.03
±0.2
Zero-code error
DAC register loaded with all '0's
1
4
Zero-code error drift
Gain error
mV
µV/°C
±0.5
% of FSR
mV
µV/°C
±2
Extrapolated from two-point line (1), unloaded
±0.01
Gain temperature coefficient
±0.15
% of FSR
ppm of
FSR/°C
±1
OUTPUT CHARACTERISTICS (2)
Output voltage range
Output voltage settling time
AVDD ≥ 2.7V; grades A and B: maximum output
voltage 2.5V when using internal reference
AVDD ≥ 5V; grades C and D: maximum output voltage
5V when using internal reference
DACs unloaded; 1/4 scale to 3/4 scale to ±0.024%
RL = 1MΩ
Slew rate
Capacitive load stability
0
AVDD
5
10
10
0.75
RL = ∞
1000
RL = 2kΩ
3000
V
µs
V/µs
pF
Code change glitch impulse
1LSB change around major carry
0.1
nV-s
Digital feedthrough
SCLK toggling, SYNC high
0.1
nV-s
RL = 2kΩ, CL = 470pF, AVDD = 5.5V
10
mV
RL = 2kΩ, CL = 470pF, AVDD = 2.7V
6
mV
0.1
LSB
Power-on glitch impulse
Channel-to-channel dc crosstalk
Full-scale swing on adjacent channel
Channel-to-channel ac crosstalk
RL = 2kΩ, CL = 420pF, 1kHz full-scale sine wave,
outputs unloaded
DC output impedance
At mid-code input
Short-circuit current
DAC outputs at full-scale, DAC outputs shorted to
GND
Power-up time, including settling time
Coming out of power-down mode
(1)
(2)
–109
dB
4
Ω
11
mA
50
µs
16-bit: codes 485 and 64714; 14-bit: codes 120 and 16200; 12-bit: codes 30 and 4050
Specified by design or characterization; not production tested.
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC7568 DAC8168 DAC8568
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DAC8168
DAC8568
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ELECTRICAL CHARACTERISTICS (continued)
At AVDD = 2.7V to 5.5V and over –40°C to +125°C (unless otherwise noted).
DAC7568/DAC8168/DAC8568
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE (3)
SNR
TA = +25°C, BW = 20kHz, AVDD = 5V, fOUT = 1kHz,
first 19 harmonics removed for SNR calculation,
at 16-bit level
THD
SFDR
SINAD
83
dB
–63
dB
63
dB
62
dB
DAC output noise density
TA = +25°C, at zero-code input, fOUT = 1kHz
90
nV/√Hz
DAC output noise
TA = +25°C, at mid-code input, 0.1Hz to 10Hz
2.6
µVPP
AVDD = 5.5V
360
µA
AVDD = 3.6V
348
µA
80
µA
REFERENCE
Internal reference current consumption
External reference current
VREFIN
Reference input range
External VREF = 2.5V (when internal reference is
disabled), all eight channels active
Grades A/B, AVDD = 2.7V to 5.5V
0
AVDD
Grades C/D, AVDD = 5.0V to 5.5V
0
AVDD/2
Reference input impedance
8
V
V
kΩ
REFERENCE OUTPUT
Output voltage
TA = +25°C; all grades
2.4995
2.5
2.5005
V
Initial accuracy
TA = +25°C, all grades
–0.02
±0.004
0.02
%
DAC7568/DAC8168/DAC8568 (4),grades A/B
5
25
DAC7568/DAC8168/DAC8568 (5), grades C/D
2
5
Output voltage temperature drift
Output voltage noise
ppm/°C
µVPP
f = 0.1Hz to 10Hz
12
TA = +25°C, f = 1MHz, CL = 0µF
50
TA = +25°C, f = 1MHz, CL = 1µF
20
TA = +25°C, f = 1MHz, CL = 4µF
16
Load regulation, sourcing (6)
TA = +25°C
30
µV/mA
Load regulation, sinking (6)
TA = +25°C
15
µV/mA
Output voltage noise density
(high-frequency noise)
Output current load capability (3)
Line regulation
TA = +25°C
Long-term stability/drift (aging) (6)
TA = +25°C, time = 0 to 1900 hours
Thermal hysteresis (6)
LOGIC INPUTS
First cycle
nV/√Hz
±20
mA
10
µV/V
50
ppm
100
Additional cycles
ppm
25
(3)
Input current
µA
±1
VINL
Logic input LOW voltage
2.7V ≤ AVDD ≤ 5.5V
VINH
Logic input HIGH voltage
2.7V ≤ AVDD ≤ 5.5V
0.8
V
3
pF
1.8
Pin capacitance
(3)
(4)
(5)
(6)
4
V
Specified by design or characterization; not production tested.
Reference is trimmed and tested at room temperature, and is characterized from –40°C to +125°C.
Reference is trimmed and tested at two temperatures (+25°C and +105°C), and is characterized from –40°C to +125°C.
Explained in more detail in the Application Information section of this data sheet.
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DAC7568
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ELECTRICAL CHARACTERISTICS (continued)
At AVDD = 2.7V to 5.5V and over –40°C to +125°C (unless otherwise noted).
DAC7568/DAC8168/DAC8568
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER REQUIREMENTS
AVDD
2.7
Normal mode, internal
reference switched off
IDD (7)
Normal mode, internal
reference switched on
All power-down modes
Normal mode, internal
reference switched off
Power
dissipation (7)
Normal mode, internal
reference switched on
All power-down modes
5.5
AVDD = 3.6V to 5.5V
VINH = AVDD and VINL = GND
0.95
1.4
AVDD = 2.7V to 3.6V
VINH = AVDD and VINL = GND
0.81
1.3
AVDD = 3.6V to 5.5V
VINH = AVDD and VINL = GND
1.25
2.0
AVDD = 2.7V to 3.6V
VINH = AVDD and VINL = GND
1.1
1.9
AVDD = 3.6V to 5.5V
VINH = AVDD and VINL = GND
0.18
3
AVDD = 2.7V to 3.6V
VINH = AVDD and VINL = GND
0.10
2.5
AVDD = 3.6V to 5.5V
VINH = AVDD and VINL = GND
3.4
7.7
AVDD = 2.7V to 3.6V
VINH = AVDD and VINL = GND
2.2
4.7
AVDD = 3.6V to 5.5V
VINH = AVDD and VINL = GND
4.5
11
AVDD = 2.7V to 3.6V
VINH = AVDD and VINL = GND
2.9
6.8
AVDD = 3.6V to 5.5V
VINH = AVDD and VINL = GND
0.6
16
AVDD = 2.7V to 3.6V
VINH = AVDD and VINL = GND
0.3
9
V
mA
mA
µA
mW
mW
µW
TEMPERATURE RANGE
Specified performance
(7)
–40
+125
°C
Input code = midscale, no load.
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC7568 DAC8168 DAC8568
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DAC7568
DAC8168
DAC8568
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PIN CONFIGURATIONS
PW PACKAGE
TSSOP-16
(TOP VIEW)
PW PACKAGE
TSSOP-14
(TOP VIEW)
LDAC
1
16
SCLK
SYNC
2
15
DIN
AVDD
3
14
GND
VOUTA
4
13
VOUTB
VOUTC
VOUTC
5
12
VOUTD
VOUTE
VOUTE
6
11
VOUTF
VOUTG
7
10
VOUTH
VREFIN/VREFOUT
8
9
CLR
DAC7568
DAC8168
DAC8568
SYNC
AVDD
VOUTA
VOUTG
VREFIN/VREFOUT
1
14
SCLK
2
13
DIN
3
12
GND
11
VOUTB
5
10
VOUTD
6
9
VOUTF
7
8
VOUTH
4
DAC7568
DAC8168
PIN DESCRIPTIONS
16-PIN
14-PIN
NAME
1
—
LDAC
Load DACs.
SYNC
Level-triggered control input (active low). This input is the frame synchronization signal for the input
data. When SYNC goes low, it enables the input shift register, and data are sampled on subsequent
falling clock edges. The DAC output updates following the 32nd clock. If SYNC is taken high before
the 31st clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored
by the DAC7568/DAC8168/DAC8568. Schmitt-Trigger logic input.
(1)
6
DESCRIPTION
2
1
3
2
AVDD
Power-supply input, 2.7V to 5.5V
4
3
VOUTA
Analog output voltage from DAC A
5
4
VOUTC
Analog output voltage from DAC C
6
5
VOUTE
Analog output voltage from DAC E
7
6
VOUTG
Analog output voltage from DAC G
8
7
VREFIN/
VREFOUT
9
—
CLR
10
8
VOUTH
Analog output voltage from DAC H
Positive reference input / reference output 2.5V if internal reference used. (1)
Asynchronous clear input.
11
9
VOUTF
Analog output voltage from DAC F
12
10
VOUTD
Analog output voltage from DAC D
13
11
VOUTB
Analog output voltage from DAC B
14
12
GND
15
13
DIN
16
14
SCLK
Ground reference point for all circuitry on the device
Serial data input. Data are clocked into the 32-bit input shift register on each falling edge of the serial
clock input. Schmitt-Trigger logic input.
Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic input.
Grades A and B, external VREFIN (max) ≤ AVDD; grades C and D, external VREFIN (max) ≤ AVDD/2.
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TIMING DIAGRAM
t2
t1
t3
SCLK
t4
t6
t5
t8
t7
SYNC
t9
DIN
t10
DB31
DB0
t11
t12
LDAC(1)
t13
t14
LDAC(2)
t15
CLR
(1)
Asynchronous LDAC update mode. For more information and details, see the LDAC Functionality section.
(2)
Synchronous LDAC update mode. For more information and details, see the LDAC Functionality section.
Figure 1. Serial Write Operation
TIMING REQUIREMENTS (1) (2)
At AVDD = 2.7V to 5.5V and over –40°C to +125°C (unless otherwise noted).
DAC7568/DAC8168/DAC8568
PARAMETER
TEST CONDITIONS
MIN
SCLK falling edge to SYNC falling edge (for
successful write operation)
AVDD = 2.7V to 5.5V
10
ns
SCLK cycle time
AVDD = 2.7V to 5.5V
20
ns
t3
SYNC rising edge to 31st SCLK falling edge
(for successful SYNC interrupt)
AVDD = 2.7V to 5.5V
13
t4
Minimum SYNC HIGH time
AVDD = 2.7V to 5.5V
80
ns
t5
SYNC to SCLK falling edge setup time
AVDD = 2.7V to 5.5V
13
ns
t6
SCLK LOW time
AVDD = 2.7V to 5.5V
8
ns
t7
SCLK HIGH time
AVDD = 2.7V to 5.5V
8
ns
t8
SCLK falling edge to SYNC rising edge
AVDD = 2.7V to 5.5V
10
ns
t9
Data setup time
AVDD = 2.7V to 5.5V
6
ns
t10
Data hold time
AVDD = 2.7V to 5.5V
4
ns
t11
SCLK falling edge to LDAC falling edge for
asynchronous LDAC update mode
AVDD = 2.7V to 5.5V
40
ns
t12
LDAC pulse width LOW time
AVDD = 2.7V to 5.5V
80
ns
t13
LDAC falling edge to SCLK falling edge for
synchronous LDAC update mode
AVDD = 2.7V to 5.5V
4 × t1
ns
t14
32nd SCLK falling edge to LDAC rising edge
AVDD = 2.7V to 5.5V
40
ns
t15
CLR pulse width LOW time
AVDD = 2.7V to 5.5V
80
ns
t1
t2
(3)
(1)
(2)
(3)
TYP
MAX
UNIT
ns
All input signals are specified with tR = tF = 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2.
See the Serial Write Operation timing diagram.
Maximum SCLK frequency is 50MHz at AVDD = 2.7V to 5.5V.
Copyright © 2009, Texas Instruments Incorporated
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DAC8168
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TYPICAL CHARACTERISTICS: Internal Reference
At TA = +25°C, unless otherwise noted.
INTERNAL REFERENCE VOLTAGE
vs TEMPERATURE (Grades A and B)
2.503
2.503
2.502
2.502
2.501
2.501
VREF (V)
VREF (V)
INTERNAL REFERENCE VOLTAGE
vs TEMPERATURE (Grades C and D)
2.500
2.500
2.499
2.499
2.498
2.498
10 Units Shown
2.497
-40 -25 -10
5
20
35
50
65
80
95
13 Units Shown
2.497
-40 -25 -10
110 125
5
20
Temperature (°C)
35
50
65
80
95
110 125
Temperature (°C)
Figure 2.
Figure 3.
REFERENCE OUTPUT TEMPERATURE DRIFT
(–40°C to +125°C, Grades C and D)
REFERENCE OUTPUT TEMPERATURE DRIFT
(–40°C to +125°, Grades A and B)
40
30
Typ: 5ppm/°C
Max: 25ppm/°C
Typ: 2ppm/°C
Max: 5ppm/°C
20
Population (%)
Population (%)
30
20
10
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1
5.0
5
7
9
11
13
15
Temperature Drift (ppm/°C)
Figure 4.
Figure 5.
REFERENCE OUTPUT TEMPERATURE DRIFT
(0°C to +125°C, Grades C and D)
LONG-TERM
STABILITY/DRIFT (1)
17
19
200
40
Typ: 1.2ppm/°C
Max: 3ppm/°C
150
100
Drift (ppm)
30
Population (%)
3
Temperature Drift (ppm/°C)
20
10
50
0
-50
Average
-100
-150
-200
0.5
(1)
8
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
300
600
900
1200
Temperature Drift (ppm/°C)
Time (Hours)
Figure 6.
Figure 7.
1500
1800
1900
20 Units Shown
0
See the Application Information section of this data sheet for more details.
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TYPICAL CHARACTERISTICS: Internal Reference (continued)
At TA = +25°C, unless otherwise noted.
INTERNAL REFERENCE NOISE DENSITY
vs FREQUENCY
INTERNAL REFERENCE NOISE
0.1Hz TO 10Hz
300
250
VNOISE (5mV/div)
VN (nV/ÖHz)
12mV (peak-to-peak)
200
Reference Unbuffered
CREF = 0mF
150
100
50
CREF = 4.8mF
0
10
100
1k
10k
100k
Time (2s/div)
1M
Frequency (Hz)
Figure 8.
Figure 9.
INTERNAL REFERENCE VOLTAGE
vs LOAD CURRENT (Grades C and D)
INTERNAL REFERENCE VOLTAGE
vs LOAD CURRENT (Grades A and B)
2.505
2.505
2.504
2.504
2.503
2.503
2.502
-40°C
2.501
VREF (V)
VREF (V)
2.502
2.500
2.499
+25°C
2.498
2.501
+25°C
2.500
2.499
2.498
+125°C
2.497
+125°C
2.497
-40°C
2.496
2.496
2.495
-25
-20 -15 -10
0
-5
5
10
15
20
2.495
-25
25
-20 -15 -10
0
-5
5
10
15
ILOAD (mA)
ILOAD (mA)
Figure 10.
Figure 11.
INTERNAL REFERENCE VOLTAGE
vs SUPPLY VOLTAGE (Grades C and D)
INTERNAL REFERENCE VOLTAGE
vs SUPPLY VOLTAGE (Grades A and B)
2.503
20
25
2.503
+125°C
2.502
-40°C
+125°C
2.501
VREF (V)
VREF (V)
2.502
2.500
2.501
+25°C
2.500
+25°C
2.499
2.499
2.498
2.498
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40°C
2.5
3.0
3.5
4.0
AVDD (V)
AVDD (V)
Figure 12.
Figure 13.
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4.5
5.0
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9
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V
Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all
DAC codes in straight binary data format, unless otherwise noted.
6
4
2
0
-2
-4
-6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
Channel B
LE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
AVDD = 5.5V, Ext. Ref. = 5.0V
0.5
0
-0.5
-1.0
16384 24576 32768 40960 49152
Digital Input Code
0
-0.5
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Figure 15.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
Channel F
AVDD = 5.5V, Ext. Ref. = 5.0V
6
4
2
0
-2
-4
-6
Channel G
AVDD = 5.5V, Ext. Ref. = 5.0V
1.0
0.5
0
-0.5
-1.0
0.5
0
-0.5
-1.0
0
6
4
2
0
-2
-4
-6
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
Figure 16.
Figure 17.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
LE (LSB)
Channel B
AVDD = 5.5V, Ext. Ref. = 5.0V
6
4
2
0
-2
-4
-6
Channel C
AVDD = 5.5V, Ext. Ref. = 5.0V
1.0
DLE (LSB)
1.0
0.5
0
-0.5
-1.0
0.5
0
-0.5
-1.0
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Figure 18.
10
57344 65536
Figure 14.
DLE (LSB)
DLE (LSB)
0.5
57344 65536
LE (LSB)
LE (LSB)
6
4
2
0
-2
-4
-6
8192
1.0
LE (LSB)
AVDD = 5.5V, Ext. Ref. = 5.0V
-1.0
0
DLE (LSB)
Channel C
1.0
DLE (LSB)
DLE (LSB)
1.0
6
4
2
0
-2
-4
-6
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57344 65536
Figure 19.
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DAC8168
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued)
Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all
DAC codes in straight binary data format, unless otherwise noted.
6
4
2
0
-2
-4
-6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
Channel F
LE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
AVDD = 5.5V, Ext. Ref. = 5.0V
0.5
0
-0.5
-1.0
16384 24576 32768 40960 49152
Digital Input Code
0
-0.5
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
Figure 20.
Figure 21.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+125°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+125°C)
Channel B
AVDD = 5.5V, Ext. Ref. = 5.0V
6
4
2
0
-2
-4
-6
Channel C
AVDD = 5.5V, Ext. Ref. = 5.0V
1.0
DLE (LSB)
DLE (LSB)
0.5
57344 65536
LE (LSB)
LE (LSB)
6
4
2
0
-2
-4
-6
8192
1.0
0.5
0
-0.5
-1.0
0.5
0
-0.5
-1.0
0
6
4
2
0
-2
-4
-6
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
Figure 22.
Figure 23.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+125°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+125°C)
Channel F
LE (LSB)
LE (LSB)
AVDD = 5.5V, Ext. Ref. = 5.0V
-1.0
0
AVDD = 5.5V, Ext. Ref. = 5.0V
6
4
2
0
-2
-4
-6
Channel G
AVDD = 5.5V, Ext. Ref. = 5.0V
1.0
DLE (LSB)
1.0
DLE (LSB)
Channel G
1.0
DLE (LSB)
DLE (LSB)
1.0
6
4
2
0
-2
-4
-6
0.5
0
-0.5
-1.0
0.5
0
-0.5
-1.0
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Figure 24.
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Product Folder Link(s): DAC7568 DAC8168 DAC8568
57344 65536
Figure 25.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued)
Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all
DAC codes in straight binary data format, unless otherwise noted.
OFFSET ERROR
vs TEMPERATURE
POWER-SUPPLY CURRENT
vs TEMPERATURE
1.6
1100
AVDD = 5.5V
Internal Reference Disabled
Offset Error (mV)
0.8
0.4
0
-0.4
Ch A
Ch B
Ch C
Ch D
-0.8
AVDD = 5.5V
External Reference = 5V
Internal Reference Disabled
-1.2
-1.6
-40 -25 -10
5
20
35
50
65
80
Ch E
Ch F
Ch G
Ch H
95
Power-Supply Current (mA)
1.2
1000
900
800
700
-40 -25 -10
110 125
5
Temperature (°C)
50
65
80
Figure 26.
Figure 27.
FULL-SCALE ERROR
vs TEMPERATURE
POWER-SUPPLY CURRENT
vs TEMPERATURE
95
110 125
95
110 125
1600
AVDD = 5.5V
External VREF = 5V
Internal Reference Disabled
Ch A
Ch B
Ch C
Ch D
Ch E
Ch F
Ch G
Ch H
0.005
0
-0.005
-0.010
AVDD = 5.5V
Internal Reference Enabled
Power-Supply Current (mA)
Full-Scale Error (mV)
0.010
35
Temperature (°C)
0.020
0.015
20
1400
1200
-0.015
-0.020
-40 -25 -10
5
20
35
50
65
80
95
1000
-40 -25 -10
110 125
5
0.035
Gain Error (mV)
0.025
35
50
65
80
Figure 28.
Figure 29.
GAIN ERROR
vs TEMPERATURE
POWER-DOWN CURRENT
vs TEMPERATURE
1..5
AVDD = 5.5V
External VREF = 5V
Internal Reference Disabled
Ch A
Ch B
Ch C
Ch D
Ch E
Ch F
Ch G
Ch H
0.015
0.005
-0.005
-0.015
-0.025
AVDD = 5.5V
Power-Down Current (mA)
0.045
20
Temperature (°C)
Temperature (°C)
1.0
0.5
-0.035
-0.045
-40 -25 -10
5
20
35
50
65
80
95
110 125
0
-40 -25 -10
5
Figure 30.
12
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20
35
50
65
80
95
110 125
Temperature (°C)
Temperature (°C)
Figure 31.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued)
Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all
DAC codes in straight binary data format, unless otherwise noted.
SOURCE CURRENT AT POSITIVE RAIL
(Grades C and D)
SINK CURRENT AT NEGATIVE RAIL
(All Grades)
0.6
5.5
Channel C
Channel C
5.0
0.4
VOUT (V)
VOUT (V)
4.5
4.0
3.5
0.2
3.0
AVDD = 5.5V
Internal Reference Enabled
DAC Loaded with FFFFh
2.5
2.0
0
1
2
3
4
AVDD = 5.5V
Internal Reference Enabled
DAC Loaded with 0000h
0
5
6
7
8
9
10
0
1
2
3
4
ISOURCE (mA)
5
6
7
8
9
10
ISINK (mA)
Figure 32.
Figure 33.
SOURCE CURRENT AT POSITIVE RAIL
(Grades C and D)
SINK CURRENT AT NEGATIVE RAIL
(All Grades)
0.6
5.5
Channel D
Channel D
5.0
0.4
VOUT (V)
VOUT (V)
4.5
4.0
3.5
0.2
3.0
AVDD = 5.5V
Internal Reference Enabled
DAC Loaded with FFFFh
2.5
2.0
0
1
2
3
4
AVDD = 5.5V
Internal Reference Enabled
DAC Loaded with 0000h
0
5
6
7
8
9
10
0
1
2
3
4
ISOURCE (mA)
5
6
7
8
9
10
ISINK (mA)
Figure 34.
Figure 35.
SOURCE CURRENT AT POSITIVE RAIL
(Grades C and D)
SINK CURRENT AT NEGATIVE RAIL
(All Grades)
0.6
5.5
Channel H
Channel H
5.0
0.4
VOUT (V)
VOUT (V)
4.5
4.0
3.5
0.2
3.0
AVDD = 5.5V
Internal Reference Enabled
DAC Loaded with FFFFh
2.5
2.0
0
1
2
3
4
AVDD = 5.5V
Internal Reference Enabled
DAC Loaded with 0000h
0
5
6
7
8
9
10
0
1
2
ISOURCE (mA)
Figure 36.
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC7568 DAC8168 DAC8568
3
4
5
6
7
8
9
10
ISINK (mA)
Figure 37.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued)
Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all
DAC codes in straight binary data format, unless otherwise noted.
POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE
1.1
1.4
1.0
1.3
Power-Supply Current (mA)
Power-Supply Current (mA)
POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE
0.9
0.8
0.7
0.6
AVDD = 5.5V
External Reference = 5V
Internal Reference Disabled,
Code Loaded to all Eight DAC Channels
0.5
1.2
1.1
1.0
0.9
AVDD = 5.5V
Internal Reference Enabled and Included,
Code Loaded to all Eight DAC Channels
0.8
0.7
0.4
0
0
8192 16384 24576 32768 40960 49152 57344 65536
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Digital Input Code
Figure 38.
Figure 39.
POWER-SUPPLY CURRENT
vs POWER-SUPPLY VOLTAGE
POWER-SUPPLY CURRENT
vs POWER-SUPPLY VOLTAGE
1000
1300
AVDD = 2.7V to 5.5V
Internal Reference Enabled
Power-Supply Current (mA)
Power-Supply Current (mA)
AVDD = 2.7V to 5.5V
Internal Reference Disabled
900
800
700
1200
1100
1000
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
3.1
3.5
AVDD (V)
3.9
4.3
4.7
5.1
5.5
AVDD (V)
Figure 40.
Figure 41.
POWER-DOWN CURRENT
vs POWER-SUPPLY VOLTAGE
0.20
Power-Down Current (mA)
AVDD = 2.7V to 5.5V
0.15
0.10
0.05
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
AVDD (V)
Figure 42.
14
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued)
Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all
DAC codes in straight binary data format, unless otherwise noted.
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
3200
AVDD = 5.5V
Internal Reference Disabled
SYNC Input (All other digital inputs = GND)
2400
Power-Supply Current (mA)
2000
Sweep from 0V to 5.5V
1600
1200
Sweep from
5.5V to 0V
800
AVDD = 5.5V
Internal Reference Enabled
SYNC Input (All other digital inputs = GND)
2800
2400
Sweep from 0V to 5.5V
2000
1600
Sweep from
5.5V to 0V
1200
400
800
3
4
5
6
0
1
2
Logic Input Voltage (V)
POWER-SUPPLY CURRENT
HISTOGRAM
POWER-SUPPLY CURRENT
HISTOGRAM
35
30
15
IDD (mA)
IDD (mA)
Figure 45.
Figure 46.
1450
1400
1250
1150
1200
1100
1050
1000
0
950
0
900
5
850
5
1350
10
1200
10
20
1150
15
AVDD = 5.5V
Internal Reference Enabled
VREF = 2.5V
1100
20
800
6
25
Occurrences (%)
25
750
5
Figure 44.
AVDD = 5.5V
Internal Reference Disabled
700
Occurrences (%)
30
4
Figure 43.
1050
35
3
Logic Input Voltage (V)
1550
2
1500
1
1300
0
1250
Power-Supply Current (mA)
2800
SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY
95
93
91
SNR (dB)
89
87
Ch A
Ch B
Ch C
Ch D
85
83
81
79
Ch E
Ch F
Ch G
Ch H
AVDD = 5.5V, External VREF = 5V
fS = 225kSPS, -1dB FSR Digital Input
Measurement Bandwidth = 20kHz
77
75
0
1
2
3
4
5
fOUT (kHz)
Figure 47.
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SBAS430A – JANUARY 2009 – REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued)
Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all
DAC codes in straight binary data format, unless otherwise noted.
SECOND HARMONIC DISTORTION
vs OUTPUT FREQUENCY
POWER SPECTRAL DENSITY
0
-40
AVDD = 5.5V, External VREF = 5V
fOUT = 1kHz, fS = 225kSPS
Measurement Bandwidth = 20kHz
-20
-50
-40
THD (dB)
Gain (dB)
-60
-60
-80
Ch A
Ch B
Ch C
Ch D
-70
Ch E
Ch F
Ch G
Ch H
-80
-100
AVDD = 5.5V, External VREF = 5V
fS = 225kSPS, -1dB FSR Digital Input
Measurement Bandwidth = 20kHz
-90
-120
-140
-100
0
5
10
15
20
0
1
2
Frequency (Hz)
Figure 49.
THIRD HARMONIC DISTORTION
vs OUTPUT FREQUENCY
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
5
-40
AVDD = 5.5V, External VREF = 5V
fS = 225kSPS, -1dB FSR Digital Input
Measurement Bandwidth = 20kHz
-70
-80
Ch A
Ch B
Ch C
Ch D
-90
AVDD = 5.5V, External VREF = 5V
fS = 225kSPS, -1dB FSR Digital Input
Measurement Bandwidth = 20kHz
-50
THD (dB)
-60
THD (dB)
4
Figure 48.
-50
Ch E
Ch F
Ch G
Ch H
-60
-70
Ch A
Ch B
Ch C
Ch D
-80
-100
Ch E
Ch F
Ch G
Ch H
-90
0
1
2
3
4
5
0
1
2
3
4
fOUT (kHz)
fOUT (kHz)
Figure 50.
Figure 51.
FULL-SCALE SETTLING TIME:
5V RISING EDGE
FULL-SCALE SETTLING TIME:
5V FALLING EDGE
Zoomed Rising Edge
200mV/div
Trigger Pulse 5V/div
5
AVDD = 5.5V
From Code: FFFFh
To Code: 0000h
Internal Reference Enabled
Zoomed Falling Edge
200mV/div
Falling
Edge
1V/div
Rising
Edge
1V/div
AVDD = 5.5V
From Code: 0000h
To Code: FFFFh
Internal Reference Enabled
Trigger Pulse 5V/div
Time (2ms/div)
Time (2ms/div)
Figure 52.
16
3
fOUT (kHz)
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Figure 53.
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DAC8568
www.ti.com ..................................................................................................................................................... SBAS430A – JANUARY 2009 – REVISED APRIL 2009
TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued)
Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all
DAC codes in straight binary data format, unless otherwise noted.
HALF-SCALE SETTLING TIME:
5V RISING EDGE
HALF-SCALE SETTLING TIME:
5V FALLING EDGE
AVDD = 5.5V
From Code: 4000h
To Code: C000h
Internal Reference Enabled
AVDD = 5.5V
Zoomed Falling Edge
From Code: C000h
200mV/div
To Code: 4000h
Falling
Internal Reference Enabled
Edge
1V/div
Zoomed Rising Edge
200mV/div
Rising
Edge
1V/div
Trigger Pulse 5V/div
Trigger Pulse 5V/div
Time (2ms/div)
Time (2ms/div)
Figure 55.
CLOCK FEEDTHROUGH
2MHz, MIDSCALE
POWER-ON GLITCH
RESET TO ZERO SCALE
AVDD (5V/div)
Channel D ~4mVPP
AVDD = 5.5V
External Reference = 2.5V
DAC = Zero Scale
Load = 470pF || 2kW
Time (4ms/div)
Figure 57.
POWER-ON GLITCH
RESET TO MIDSCALE
POWER-OFF GLITCH
Channels A/B
AVDD
AVDD = 5.5V
External Reference = 2.5V
DAC = Midscale
Load = 470pF || 2kW
VOUT (20mV/div)
Figure 56.
~4mVPP
Channel C
Channel D
AVDD (5V/div)
AVDD (1V/div)
~18mVPP
Channel C
Time (1ms/div)
VOUT (200mV/div)
SCLK (5V/div)
VOUT (2mV/div)
AVDD = 5.5V
Clock Feedthrough Impulse ~0.5nV-s
Internal Reference Enabled
VOUT (20mV/div)
Figure 54.
AVDD = 5.5V
DAC = Zero Scale
Load = 470pF || 2kW
Time (20ms/div)
Time (4ms/div)
Figure 58.
Figure 59.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued)
Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all
DAC codes in straight binary data format, unless otherwise noted.
GLITCH ENERGY:
5V, 1LSB STEP, RISING EDGE
GLITCH ENERGY:
5V, 1LSB STEP, FALLING EDGE
AVDD = 5.5V
From Code:8000h
To Code: 7FFFh
Channel C as Example
Glitch Impulse
~0.15nV-s
LDAC/Clock Feedthrough
VOUT (100mV/div)
VOUT (100mV/div)
AVDD = 5.5V
From Code:7FFFh
To Code: 8000h
Channel C as Example
Glitch Impulse
~0.1nV-s
LDAC Trigger Pulse 5V/div
LDAC Trigger Pulse 5V/div
Time (5ms/div)
Time (5ms/div)
Figure 60.
Figure 61.
GLITCH ENERGY:
5V, 4LSB STEP, RISING EDGE
GLITCH ENERGY:
5V, 4LSB STEP, FALLING EDGE
LDAC/Clock Feedthrough
Glitch Impulse
~0.15nV-s
LDAC/Clock Feedthrough
VOUT (100mV/div)
VOUT (100mV/div)
AVDD = 5.5V
From Code:7FFCh
To Code: 8000h
Channel D as Example
AVDD = 5.5V
From Code:8000h
To Code: 7FFCh
Channel D as Example
LDAC Trigger Pulse 5V/div
Time (5ms/div)
Figure 62.
Figure 63.
GLITCH ENERGY:
5V, 16LSB STEP, RISING EDGE
GLITCH ENERGY:
5V, 16LSB STEP, FALLING EDGE
AVDD = 5.5V
From Code:7FF0h
To Code: 8000h
Channel H as Example
LDAC/Clock Feedthrough
Glitch Impulse
~0.06nV-s
LDAC/Clock Feedthrough
LDAC Trigger Pulse 5V/div
VOUT (200mV/div)
VOUT (200mV/div)
Glitch Impulse
~0.1nV-s
LDAC Trigger Pulse 5V/div
Time (5ms/div)
AVDD = 5.5V
From Code:8000h
To Code: 7FF0h
Channel H as Example
Time (5ms/div)
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Glitch Impulse
~0.01nV-s
LDAC Trigger Pulse 5V/div
Time (5ms/div)
Figure 64.
18
LDAC/Clock Feedthrough
Figure 65.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued)
Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all
DAC codes in straight binary data format, unless otherwise noted.
DAC OUTPUT NOISE DENSITY
vs FREQUENCY (1)
DAC OUTPUT NOISE
0.1Hz TO 10Hz
600
VNOISE (1mV/div)
500
Noise (nV/ÖHz)
AVDD = 5.5V
DAC = Midscale, No Load
Internal Reference = 2.5V
Channel D
AVDD = 5V
DAC VOUTA Unloaded
Internal Reference Enabled
400
Full Scale
300
200
Midscale
~3mVPP
100
Zero Scale
0
10
100
1k
10k
100k
Time (2s/div)
Frequency (Hz)
Figure 66.
(1)
Figure 67.
See the Application Information section of this data sheet for more details.
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DAC8168
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TYPICAL CHARACTERISTICS: DAC at AVDD = 3.6V
Channel-specific information provided as examples. At TA = +25°C, internal reference used, and DAC output not loaded, all
DAC codes in straight binary data format, unless otherwise noted
POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE
POWER-SUPPLY CURRENT
vs TEMPERATURE
1.30
900
AVDD = 3.6V
Internal Reference Disabled
Power-Supply Current (mA)
Power-Supply Current (mA)
1.25
1.20
1.15
1.10
1.05
1.00
0.95
AVDD = 3.6V
Internal Reference Enabled and Included,
Code Loaded to all Eight DAC Channels
0.90
0.85
0.80
0
700
600
-40 -25 -10
8192 16384 24576 32768 40960 49152 57344 65536
5
50
65
80
Figure 68.
Figure 69.
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
POWER-SUPPLY CURRENT
vs TEMPERATURE
95
110 125
1400
1400
1200
Sweep from 0V to 3.6V
1000
800
600
Power-Supply Current (mA)
AVDD = 3.6V
Internal Reference Enabled
AVDD = 3.6V
Internal Reference Disabled
SYNC Input (All other digital inputs = GND)
Sweep from
3.6V to 0V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1300
1200
1100
1000
900
-40 -25 -10
4.0
5
Logic Input Voltage (V)
20
35
50
65
80
95
110 125
Temperature (°C)
Figure 70.
Figure 71.
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
POWER-DOWN CURRENT
vs TEMPERATURE
2000
1.0
AVDD = 3.6V
AVDD = 3.6V
Internal Reference Enabled
SYNC Input (All other digital inputs = GND)
1800
1600
Sweep from 0V to 3.6V
1400
1200
1000
Sweep from
3.6V to 0V
800
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Power-Down Current (mA)
Power-Supply Current (mA)
35
Temperature (°C)
400
0.8
0.6
0.4
0.2
0
-40 -25 -10
5
Logic Input Voltage (V)
Submit Documentation Feedback
20
35
50
65
80
95
110 125
Temperature (°C)
Figure 72.
20
20
Digital Input Code
1600
Power-Supply Current (mA)
800
Figure 73.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 3.6V (continued)
Channel-specific information provided as examples. At TA = +25°C, internal reference used, and DAC output not loaded, all
DAC codes in straight binary data format, unless otherwise noted
POWER-SUPPLY CURRENT
HISTOGRAM
35
IDD (mA)
IDD (mA)
Figure 74.
Figure 75.
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1400
1350
1300
1250
1050
1000
950
900
850
800
750
0
700
5
0
650
10
5
1200
15
10
1150
15
20
1100
20
25
1050
25
1000
Occurrences (%)
30
600
Occurrences (%)
30
AVDD = 3.6V
Internal Reference Enabled
VREF = 2.5V
950
35
40
AVDD = 3.6V
Internal Reference Disabled
900
40
POWER-SUPPLY CURRENT
HISTOGRAM
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V
Channel-specific information provided as examples. At TA = +25°C, internal reference used, and DAC output not loaded, all
DAC codes in straight binary data format, unless otherwise noted
6
4
2
0
-2
-4
-6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
Channel A
LE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
AVDD = 2.7V, Int. Ref. = 2.5V
0.5
0
-0.5
-1.0
16384 24576 32768 40960 49152
Digital Input Code
0
-0.5
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Figure 77.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
Channel E
AVDD = 2.7V, Int. Ref. = 2.5V
6
4
2
0
-2
-4
-6
Channel H
AVDD = 2.7V, Int. Ref. = 2.5V
1.0
0.5
0
-0.5
-1.0
0.5
0
-0.5
-1.0
0
6
4
2
0
-2
-4
-6
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
Figure 78.
Figure 79.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
LE (LSB)
Channel A
AVDD = 2.7V, Int. Ref. = 2.5V
6
4
2
0
-2
-4
-6
Channel D
AVDD = 2.7V, Int. Ref. = 2.5V
1.0
DLE (LSB)
1.0
0.5
0
-0.5
-1.0
0.5
0
-0.5
-1.0
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Figure 80.
22
57344 65536
Figure 76.
DLE (LSB)
DLE (LSB)
0.5
57344 65536
LE (LSB)
LE (LSB)
6
4
2
0
-2
-4
-6
8192
1.0
LE (LSB)
AVDD = 2.7V, Int. Ref. = 2.5V
-1.0
0
DLE (LSB)
Channel D
1.0
DLE (LSB)
DLE (LSB)
1.0
6
4
2
0
-2
-4
-6
Submit Documentation Feedback
57344 65536
Figure 81.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
Channel-specific information provided as examples. At TA = +25°C, internal reference used, and DAC output not loaded, all
DAC codes in straight binary data format, unless otherwise noted
6
4
2
0
-2
-4
-6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
Channel E
LE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
AVDD = 2.7V, Int. Ref. = 2.5V
0.5
0
-0.5
-1.0
16384 24576 32768 40960 49152
Digital Input Code
0
-0.5
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
Figure 82.
Figure 83.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
Channel A
AVDD = 2.7V, Int. Ref. = 2.5V
6
4
2
0
-2
-4
-6
Channel D
AVDD = 2.7V, Int. Ref. = 2.5V
1.0
DLE (LSB)
DLE (LSB)
0.5
57344 65536
LE (LSB)
LE (LSB)
6
4
2
0
-2
-4
-6
8192
1.0
0.5
0
-0.5
-1.0
0.5
0
-0.5
-1.0
0
6
4
2
0
-2
-4
-6
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
Figure 84.
Figure 85.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
Channel E
LE (LSB)
LE (LSB)
AVDD = 2.7V, Int. Ref. = 2.5V
-1.0
0
AVDD = 2.7V, Int. Ref. = 2.5V
6
4
2
0
-2
-4
-6
Channel H
AVDD = 2.7V, Int. Ref. = 2.5V
1.0
DLE (LSB)
1.0
DLE (LSB)
Channel H
1.0
DLE (LSB)
DLE (LSB)
1.0
6
4
2
0
-2
-4
-6
0.5
0
-0.5
-1.0
0.5
0
-0.5
-1.0
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Figure 86.
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57344 65536
Figure 87.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
Channel-specific information provided as examples. At TA = +25°C, internal reference used, and DAC output not loaded, all
DAC codes in straight binary data format, unless otherwise noted
OFFSET ERROR
vs TEMPERATURE
POWER-SUPPLY CURRENT
vs TEMPERATURE
1.6
900
AVDD = 2.7V
Internal Reference Disabled
Offset Error (mV)
0.8
0.4
0
-0.4
Ch A
Ch B
Ch C
Ch D
-0.8
-1.2
AVDD = 2.7V
Internal VREF = 2.5V
-1.6
-40 -25 -10
5
20
35
50
65
80
Ch E
Ch F
Ch G
Ch H
95
Power-Supply Current (mA)
1.2
800
700
600
500
-40 -25 -10
110 125
65
80
Figure 89.
FULL-SCALE ERROR
vs TEMPERATURE
POWER-SUPPLY CURRENT
vs TEMPERATURE
95
110 125
95
110 125
AVDD = 2.7V
Internal Reference Enabled
0.020
0.010
0
-0.010
Ch A
Ch B
Ch C
Ch D
-0.020
AVDD = 2.7V
Internal VREF = 2.5V
5
20
35
50
65
80
Ch E
Ch F
Ch G
Ch H
95
Power-Supply Current (mA)
Full-Scale Error (mV)
50
1300
-0.040
-40 -25 -10
1200
1100
1000
900
800
-40 -25 -10
110 125
5
20
35
50
65
80
Temperature (°C)
Temperature (°C)
Figure 90.
Figure 91.
vs
POWER-DOWN CURRENT
vs TEMPERATURE
0.045
1.0
Ch E
Ch F
Ch G
Ch H
0.015
0.005
-0.005
-0.015
-0.025
AVDD = 2.7V
Power-Down Current (mA)
Ch A
Ch B
Ch C
Ch D
AVDD = 2.7V
Internal VREF = 2.5V
0.025
Gain Error (mV)
35
Figure 88.
0.030
0.035
20
Temperature (°C)
0.040
-0.030
5
Temperature (°C)
0.8
0.6
0.4
0.2
-0.035
-0.045
-40 -25 -10
5
20
35
50
65
80
95
110 125
0
-40 -25 -10
5
Temperature (°C)
Submit Documentation Feedback
35
50
65
80
95
110 125
Temperature (°C)
Figure 92.
24
20
Figure 93.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
Channel-specific information provided as examples. At TA = +25°C, internal reference used, and DAC output not loaded, all
DAC codes in straight binary data format, unless otherwise noted
SOURCE CURRENT AT POSITIVE RAIL
(Grades A and B)
SINK CURRENT AT NEGATIVE RAIL
(All Grades)
2.7
0.6
Channel A
Channel A
2.5
VOUT (V)
VOUT (V)
0.4
2.3
0.2
2.1
AVDD = 2.7V
Internal Reference Enabled
DAC Loaded with FFFFh
1.9
0
1
2
3
4
AVDD = 2.7V
Internal Reference Enabled
DAC Loaded with 0000h
0
5
6
7
8
9
10
0
1
2
3
4
ISOURCE (mA)
5
6
7
8
9
10
ISINK (mA)
Figure 94.
Figure 95.
SOURCE CURRENT AT POSITIVE RAIL
(Grades A and B)
SINK CURRENT AT NEGATIVE RAIL
(All Grades)
2.7
0.6
Channel B
Channel B
2.5
VOUT (V)
VOUT (V)
0.4
2.3
0.2
2.1
AVDD = 2.7V
Internal Reference Enabled
DAC Loaded with FFFFh
1.9
0
1
2
3
4
AVDD = 2.7V
Internal Reference Enabled
DAC Loaded with 0000h
0
5
6
7
8
9
10
0
1
2
3
4
ISOURCE (mA)
5
6
7
8
9
10
ISINK (mA)
Figure 96.
Figure 97.
SOURCE CURRENT AT POSITIVE RAIL
(Grades A and B)
SINK CURRENT AT NEGATIVE RAIL
(All Grades)
2.7
0.6
Channel G
Channel G
2.5
VOUT (V)
VOUT (V)
0.4
2.3
0.2
2.1
AVDD = 2.7V
Internal Reference Enabled
DAC Loaded with FFFFh
1.9
0
1
2
3
4
AVDD = 2.7V
Internal Reference Enabled
DAC Loaded with 0000h
0
5
6
7
8
9
10
0
1
2
ISOURCE (mA)
Figure 98.
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3
4
5
6
7
8
9
10
ISINK (mA)
Figure 99.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
Channel-specific information provided as examples. At TA = +25°C, internal reference used, and DAC output not loaded, all
DAC codes in straight binary data format, unless otherwise noted
POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE
POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE
1.25
1000
1.20
Power-Supply Current (mA)
1.10
1.05
1.00
0.95
0.90
AVDD = 2.7V
Internal Reference Enabled and Included,
Code Loaded to all Eight DAC Channels
0.85
700
600
AVDD = 2.7V
External Reference = 2.5V
Internal Reference Disabled and Not Included
Code Loaded to all Eight DAC Channels
500
400
0.80
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Digital Input Code
Figure 100.
Figure 101.
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
1100
1400
AVDD = 2.7V
Internal Reference Disabled
SYNC Input (All other digital inputs = GND)
1000
Power-Supply Current (mA)
900
800
Sweep from
0V to 2.7V
700
Sweep from
2.7V to 0V
600
500
AVDD = 2.7V
Internal Reference Enabled
SYNC Input (All other digital inputs = GND)
1300
1200
Sweep from
0V to 2.7V
1100
1000
400
Sweep from
2.7V to 0V
900
800
1.5
2.0
2.5
3.0
0
0.5
1.0
Logic Input Voltage (V)
Figure 103.
POWER-SUPPLY CURRENT
HISTOGRAM
POWER-SUPPLY CURRENT
HISTOGRAM
45
40
35
20
15
25
20
15
950
900
850
800
750
0
700
5
0
650
10
5
600
10
IDD (mA)
IDD (mA)
Figure 104.
Figure 105.
Submit Documentation Feedback
3.0
30
1200
Occurrences (%)
25
550
Occurrences (%)
30
26
2.5
AVDD = 2.7V
Internal Reference Enabled
VREF = 2.5V
1000
AVDD = 2.7V
Internal Reference Disabled
950
35
2.0
Figure 102.
900
40
1.5
Logic Input Voltage (V)
1300
1.0
1250
0.5
1150
0
1100
Power-Supply Current (mA)
800
1050
Power-Supply Current (mA)
900
1.15
Copyright © 2009, Texas Instruments Incorporated
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www.ti.com ..................................................................................................................................................... SBAS430A – JANUARY 2009 – REVISED APRIL 2009
TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
Channel-specific information provided as examples. At TA = +25°C, internal reference used, and DAC output not loaded, all
DAC codes in straight binary data format, unless otherwise noted
FULL-SCALE SETTLING TIME:
2.7V RISING EDGE
FULL-SCALE SETTLING TIME:
2.7V FALLING EDGE
Zoomed Rising Edge
200mV/div
Falling
Edge
1V/div
Rising
Edge
1V/div
Zoomed Falling Edge
200mV/div
AVDD = 2.7V
From Code: 0000h
To Code: FFFFh
Trigger Pulse
5V/div
AVDD = 2.7V
From Code: FFFFh
To Code: 0000h
Trigger
Pulse
5V/div
Time (2ms/div)
Rising
Edge
1V/div
Time (2ms/div)
Figure 106.
Figure 107.
HALF-SCALE SETTLING TIME:
2.7V RISING EDGE
HALF-SCALE SETTLING TIME:
2.7V FALLING EDGE
Zoomed Rising Edge
200mV/div
AVDD = 2.7V
From Code: 4000h
To Code: C000h
Trigger
Pulse
5V/div
AVDD = 2.7V
From Code: C000h
To Code: 4000h
Falling
Edge
1V/div
Zoomed Falling Edge
200mV/div
Trigger
Pulse
5V/div
Time (2ms/div)
Time (2ms/div)
Figure 109.
CLOCK FEEDTHROUGH
2.7V, 2MHz, MIDSCALE
POWER-ON GLITCH
RESET TO ZERO SCALE
Channel E
~8mVPP
Channel F ~4mVPP
AVDD (5V/div)
SCLK (5V/div)
VOUT (500mV/div)
AVDD = 2.7V
Clock Feedthrough Impulse ~0.4nV-s
Internal Reference Enabled
VOUT (20mV/div)
Figure 108.
AVDD = 2.7V
External Reference = 2.5V
DAC = Zero Scale
Load = 470pF || 2kW
Time (4ms/div)
Time (1ms/div)
Figure 110.
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Figure 111.
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DAC8168
DAC8568
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
Channel-specific information provided as examples. At TA = +25°C, internal reference used, and DAC output not loaded, all
DAC codes in straight binary data format, unless otherwise noted
Channels G/H
AVDD
AVDD = 2.7V
External Reference = 2.5V
DAC = Midscale
Load = 470pF || 2kW
VOUT (20mV/div)
POWER-OFF GLITCH
Channel C
Channel D
AVDD (5V/div)
AVDD (500mV/div) VOUT (200mV/div)
POWER-ON GLITCH
RESET TO MIDSCALE
AVDD = 2.7V
DAC = Zero Scale
Load = 470pF || 2kW
Time (20ms/div)
Time (4ms/div)
Figure 112.
Figure 113.
GLITCH ENERGY:
2.7V, 1LSB STEP, RISING EDGE
GLITCH ENERGY:
2.7V, 1LSB STEP, FALLING EDGE
AVDD = 2.7V
From Code:8000h
To Code: 7FFFh
Channel E as Example
LDAC/Clock Feedthrough
Glitch Impulse
~0.15nV-s
VOUT (100mV/div)
VOUT (100mV/div)
AVDD = 2.7V
From Code:7FFFh
To Code: 8000h
Channel E as Example
Glitch Impulse
~0.2nV-s
LDAC Trigger Pulse 5V/div
LDAC Trigger Pulse 5V/div
Time (5ms/div)
Figure 115.
GLITCH ENERGY:
2.7V, 4LSB STEP, RISING EDGE
GLITCH ENERGY:
2.7V, 4LSB STEP, FALLING EDGE
AVDD = 2.7V
From Code:8000h
To Code: 7FFCh
Channel A as Example
Glitch Impulse
~0.1nV-s
LDAC/Clock Feedthrough
VOUT (100mV/div)
VOUT (100mV/div)
Time (5ms/div)
Figure 114.
AVDD = 2.7V
From Code:7FFCh
To Code: 8000h
Channel A as Example
LDAC Trigger Pulse 5V/div
Time (5ms/div)
Time (5ms/div)
Figure 116.
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LDAC/Clock Feedthrough
Glitch Impulse
~0.08nV-s
LDAC Trigger Pulse 5V/div
28
LDAC/Clock Feedthrough
Figure 117.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
Channel-specific information provided as examples. At TA = +25°C, internal reference used, and DAC output not loaded, all
DAC codes in straight binary data format, unless otherwise noted
GLITCH ENERGY:
2.7V, 16LSB STEP, RISING EDGE
GLITCH ENERGY:
2.7V, 16LSB STEP, FALLING EDGE
LDAC/Clock Feedthrough
Glitch Impulse
~0.2nV-s
LDAC/Clock Feedthrough
VOUT (200mV/div)
VOUT (200mV/div)
AVDD = 2.7V
From Code:7FF0h
To Code: 8000h
Channel B as Example
AVDD = 2.7V
From Code:8000h
To Code: 7FF0h
Channel B as Example
LDAC Trigger Pulse 5V/div
Time (5ms/div)
Glitch Impulse
~0.04nV-s
LDAC Trigger Pulse 5V/div
Time (5ms/div)
Figure 118.
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DAC8168
DAC8568
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THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER (DAC)
VREF
The DAC7568, DAC8168, and DAC8568 architecture
consists of eight string DACs each followed by an
output buffer amplifier. The devices include an
internal 2.5V reference with 2ppm/°C temperature
drift performance, and offer either 5V or 2.5V full
scale output voltage. Figure 120 shows a principal
block diagram of the DAC architecture.
VREFH
50kW
VREF
2
R
50kW
To Output Amplifier
(2x Gain)
R
62kW
VOUTX
REF(+)
Resistor String
REF(-)
DAC
Register
RDIVIDER
VREFL
Figure 120. Device Architecture
The input coding to the DAC7568, DAC8168, and
DAC8568 is straight binary, so the ideal output
voltage is given by Equation 1:
VOUT =
DIN
2n
´ VREF ´ Gain
R
(1)
Where:
DIN = decimal equivalent of the binary code that
is loaded to the DAC register. It can range from 0
to 4095 for DAC7568 (12 bit), 0 to 16,383 for
DAC8168 (14 bit), and 0 to 65535 for DAC8568
(16 bit).
n = resolution in bits; either 12 (DAC7568), 14
(DAC8168) or 16 (DAC8568)
Gain = 1 for A/B grades or 2 for C/D grades.
RESISTOR STRING
The resistor string section is shown in Figure 121. It
is simply a string of resistors, each of value R. The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier. It is
monotonic because it is a string of resistors.
30
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R
Figure 121. Resistor String
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output, giving a maximum
output range of 0V to AVDD. It is capable of driving a
load of 2kΩ in parallel with 3000pF to GND. The
source and sink capabilities of the output amplifier
can be seen in the Typical Characteristics. The
typical slew rate is 0.75V/µs, with a typical full-scale
settling time of 5µs with the output unloaded.
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INTERNAL REFERENCE
Enable/Disable Internal Reference
The DAC7568, DAC8168, and DAC8568 include a
2.5V internal reference that is disabled by default.
The internal reference is externally available at the
VREFIN/VREFOUT pin. A minimum 100nF capacitor is
recommended between the reference output and
GND for noise filtering.
The internal reference in the DAC7568, DAC8168,
and DAC8568 is disabled by default for debugging,
evaluation purposes, or when using an external
reference. The internal reference can be powered up
and powered down using a serial command that
requires a 32-bit write sequence (see the Serial
Interface section), as shown in Table 1 and Table 3.
During the time that the internal reference is disabled,
the DAC functions normally using an external
reference. At this point, the internal reference is
disconnected from the VREFIN/VREFOUT pin (3-state
output). Do not attempt to drive the VREFIN/VREFOUT
pin externally and internally at the same time
indefinitely.
The internal reference of the DAC7568, DAC8168,
and DAC8568 is a bipolar, transistor-based, precision
bandgap voltage reference. Figure 122 shows the
basic bandgap topology. Transistors Q1 and Q2 are
biased such that the current density of Q1 is greater
than that of Q2. The difference of the two
base-emitter voltages (VBE1 – VBE2) has a positive
temperature coefficient and is forced across resistor
R1. This voltage is gained up and added to the
base-emitter voltage of Q2, which has a negative
temperature coefficient. The resulting output voltage
is virtually independent of temperature. The
short-circuit current is limited by design to
approximately 100mA.
There are two modes that allow communication with
the internal reference: Static and Flexible. In Flexible
mode, DB19 must be set to '1'.
Static Mode (see Table 1 and Table 2)
Enabling Internal Reference:
To enable the internal reference, write the 32-bit
serial command shown in Table 1. When performing
a power cycle to reset the device, the internal
reference is switched off (default mode). In the
default mode, the internal reference is powered down
until a valid write sequence is applied to power up the
internal reference. If the internal reference is powered
up, it automatically powers down when all DACs
power down in any of the power-down modes (see
the Power Down Modes section). The internal
reference automatically powers up when any DAC is
powered up.
VREF
Reference
Disable
Q1
1
N
Q2
R1
Disabling Internal Reference:
To disable the internal reference, write the 32-bit
serial command shown in Table 2. When performing
a power cycle to reset the device, the internal
reference is put back into its default mode and
switched off (default mode).
R2
Figure 122. Bandgap Reference Simplified
Schematic
Table 1. Write Sequence for Enabling Internal Reference (Static Mode)
(Internal Reference Powered On—08000001h)
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
F3
F2
F1
F0
X
D12
X
D13
X
DB0
D14
X
| Address Bits |
DB4
D15
0
A0
0
A1
0
A2
1
|-- Prefix Bits --| |- Control Bits -|
DB19
A3
X
X
C0
X
X
C1
X
X
DB23
C2
0
0
DB27
C3
DB31
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
|-------------------------------------- Data Bits --------------------------------------|
| Feature Bits |
Table 2. Write Sequence for Disabling Internal Reference (Static Mode)
(Internal Reference Powered On—08000000h)
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
F3
F2
F1
F0
X
D12
X
D13
X
DB0
D14
X
| Address Bits |
DB4
D15
0
A0
0
A1
0
A2
1
|-- Prefix Bits --| |- Control Bits -|
DB19
A3
X
X
C0
X
X
C1
X
X
DB23
C2
0
0
DB27
C3
DB31
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
|-------------------------------------- Data Bits --------------------------------------|
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Flexible Mode (see Table 3, Table 4, and Table 5)
performing a power cycle to reset the device, the
internal reference is switched off (default mode). In
the default mode, the internal reference is powered
down until a valid write sequence is applied to power
up the internal reference. When the internal reference
is powered up, it remains powered up, regardless of
the state of the DACs.
Enabling Internal Reference:
Method 1) To enable the internal reference, write the
32-bit serial command shown in Table 3. When
performing a power cycle to reset the device, the
internal reference is switched off (default mode). In
the default mode, the internal reference is powered
down until a valid write sequence is applied to power
up the internal reference. If the internal reference is
powered up, it automatically powers down when all
DACs power down in any of the power-down modes
(see the Power Down Modes section). The internal
reference powers up automatically when any DAC is
powered up.
Disabling Internal Reference:
To disable the internal reference, write the 32-bit
serial command shown in Table 5. When performing
a power cycle to reset the device, the internal
reference is switched off (default mode).
When the internal reference is operated in Flexible
mode, Static mode is disabled and does not work. To
switch from Flexible mode to Static mode, use the
command shown in Table 6.
Method 2) To always enable the internal reference,
write the 32-bit serial command shown in Table 4.
When the internal reference is always enabled, any
power-down command to the DAC channels does not
change the internal reference operating mode. When
Table 3. Write Sequence for Enabling Internal Reference (Flexible Mode)
(Internal Reference Powered On—09080000h)
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
F3
F2
F1
F0
X
D12
X
D13
X
DB0
D14
X
| Address Bits |
DB4
D15
1
A0
0
A1
0
A2
1
|-- Prefix Bits --| |- Control Bits -|
DB19
A3
X
X
C0
X
X
C1
X
X
DB23
C2
0
0
DB27
C3
DB31
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
|-------------------------------------- Data Bits --------------------------------------|
| Feature Bits |
Table 4. Write Sequence for Enabling Internal Reference (Flexible Mode)
(Internal Reference Always Powered On—090A0000h)
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
F3
F2
F1
F0
X
D12
X
D13
X
DB0
D14
X
| Address Bits |
DB4
D15
1
A0
0
A1
0
A2
1
|-- Prefix Bits --| |- Control Bits -|
DB19
A3
X
X
C0
X
X
C1
X
X
DB23
C2
0
0
DB27
C3
DB31
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
|-------------------------------------- Data Bits --------------------------------------|
| Feature Bits |
Table 5. Write Sequence for Disabling Internal Reference (Flexible Mode)
(Internal Reference Always Powered Down—090C0000h)
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
F3
F2
F1
F0
X
D12
X
D13
X
DB0
D14
X
| Address Bits |
DB4
D15
1
A0
0
A1
0
A2
1
|-- Prefix Bits --| |- Control Bits -|
DB19
A3
X
X
C0
X
X
C1
X
X
DB23
C2
0
0
DB27
C3
DB31
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
|-------------------------------------- Data Bits --------------------------------------|
| Feature Bits |
Table 6. Write Sequence for Switching from Flexible Mode to Static Mode for Internal Reference
(Internal Reference Always Powered Down—09000000h)
32
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D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
F3
F2
F1
F0
X
D12
X
D13
X
DB0
D14
X
| Address Bits |
DB4
D15
1
A0
0
A1
0
A2
1
|-- Prefix Bits --| |- Control Bits -|
DB19
A3
X
X
C0
X
X
C1
X
X
DB23
C2
0
0
DB27
C3
DB31
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
|-------------------------------------- Data Bits --------------------------------------|
| Feature Bits |
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SERIAL INTERFACE
The DAC7568, DAC8168, and DAC8568 have a
3-wire serial interface (SYNC, SCLK, and DIN; see the
Pin Configurations) compatible with SPI, QSPI, and
Microwire interface standards, as well as most DSPs.
See the Serial Write Operation timing diagram
(Figure 1) for an example of a typical write sequence.
The DAC7568, DAC8168, and DAC8568 input shift
register is 32-bits wide, consisting of four prefix bits
(DB31 to DB28), four control bits (DB27 to DB24), 16
data bits (DB23 to DB4), and four feature bits. The 16
data bits comprise the 16-, 14-, or 12-bit input code.
When writing to the DAC register (data transfer), bits
DB0 to DB3 (for 16-bit operation), DB0 to DB5 (for
14-bit operation), and DB0 to DB7 (for 12-bit
operation) are ignored by the DAC and should be
treated as don't care bits (see Table 7 to Table 9). All
32 bits of data are loaded into the DAC under the
control of the serial clock input, SCLK.
DB31 (MSB) is the first bit that is loaded into the DAC
shift register and must be always set to '0'. It is
followed by the rest of the 32-bit word pattern,
left-aligned. This configuration means that the first 32
bits of data are latched into the shift register and any
further clocking of data is ignored. When the DAC
registers are being written to, the DAC7568,
DAC8168, and DAC8568 receive all 32 bits of data,
ignore DB31 to DB28, and decode the second set of
four bits (DB27 to DB24) in order to determine the
DAC operating/control mode (see Table 10). Bits
DB23 to DB20 are used to address selected DAC
channels. The next 16/14/12 bits of data that follow
are decoded by the DAC to determine the equivalent
analog output. The last four data bits (DB0 to DB3 for
DAC8568), last data six bits (DB0 to DB5 for
DAC8168), or last eight data bits (DB0 to DB7 for
DAC7568) are ignored in this case. For more details
on these and other commands (such as write to
LDAC register, power down DACs, etc.), see
Table 10.
The data format is straight binary with all '0's
corresponding to 0V output and all '1's corresponding
to full-scale output. For all documentation purposes,
the data format and representation used here is a
true 16-bit pattern (that is, FFFFh for data word for
full-scale) that the DAC7568, DAC8168, and
DAC8568 require.
The write sequence begins by bringing the SYNC line
low. Data from the DIN line are clocked into the 32-bit
shift register on each falling edge of SCLK. The serial
clock frequency can be as high as 50MHz, making
the DAC7568, DAC8168, and DAC8568 compatible
with high-speed DSPs. On the 32nd falling edge of
the serial clock, the last data bit is clocked into the
shift register and the shift register locks. Further
clocking does not change the shift register data. After
receiving the 32nd falling clock edge, the DAC7568,
DAC8168, and DAC8568 decode the four control bits
and four address bits and 16/14/12 data bits to
perform the required function, without waiting for a
SYNC rising edge. A new write sequence starts at the
next falling edge of SYNC. A rising edge of SYNC
before the 31st-bit sequence is complete resets the
SPI interface; no data transfer occurs. After the 32nd
falling edge of SCLK is received, the SYNC line may
be kept low or brought high. In either case, the
minimum delay time from the 32nd falling SCLK edge
to the next falling SYNC edge must be met in order to
properly begin the next cycle; see the Serial Write
Operation timing diagram (Figure 1). To assure the
lowest power consumption of the device, care should
be taken that the levels are as close to each rail as
possible. Refer to the 5.5V, 3.6V, and 2.7V Typical
Characteristics sections for the Power-Supply Current
vs Logic Input Voltage graphs (Figure 43, Figure 44,
Figure 70, Figure 72, Figure 102, and Figure 103).
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INPUT SHIFT REGISTER
DB4), and four additional feature bits. The 16 data
bits comprise the 16-, 14-, or 12-bit input code.
The input shift register (SR) of the DAC7568,
DAC8168, and DAC8568 is 32 bits wide (as shown in
Table 7, Table 8, and Table 9, respectively), and
consists of four Prefix bits (DB31 to DB28), four
control bits (DB27 to DB24), 16 data bits (DB23 to
The DAC7568, DAC8168, and DAC8568 support a
number of different load commands. The load
commands are summarized in Table 10.
Table 7. DAC8568 Data Input Register Format
|-- Prefix Bits --| |- Control Bits -|
| Address Bits |
|-------------------------------------- Data Bits --------------------------------------|
F0
F1
F2
DB0
F3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
DB4
D14
D15
A0
A1
DB19
A2
A3
X
C0
X
C1
X
DB23
C2
0
DB27
C3
DB31
| Feature Bits |
Table 8. DAC8168 Data Input Register Format
|-- Prefix Bits --| |- Control Bits -|
| Address Bits |
|-------------------------------- Data Bits --------------------------------|
F0
F1
X
F2
X
DB0
F3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
DB4
D12
D13
A0
A1
DB19
A2
A3
X
C0
X
C1
X
DB23
C2
0
DB27
C3
DB31
| Feature Bits |
Table 9. DAC7568 Data Input Register Format
|-- Prefix Bits --| |- Control Bits -|
34
| Address Bits |
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|-------------------------- Data Bits --------------------------|
X
F0
X
F1
X
F2
X
DB0
F3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DB4
D10
D11
A0
A1
DB19
A2
A3
X
C0
X
C1
X
DB23
C2
0
DB27
C3
DB31
| Feature Bits |
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Table 10. Control Matrix for the DAC7568, DAC8168, and DAC8568
DB31
DB30DB28
0
Don't
Care
0
Don't
Care
C3
C2
C1
C0
A3
A2
A1
A0
D14
0
Don't
Care
C3
C2
C1
C0
A3
A2
A1
A0
1
X
X
X
X
X
X
X
X
X
DB27
C3
DB26
DB25
C2
C1
DB24
DB23
C0
A3
DB22
A2
DB21
A1
DB20
A0
DB17
DB16DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DESCRIPTION
D14
D13D7
D6
D5
D4
D3
D2
D1
F3
F2
F1
F0
GENERAL DATA FORMAT FOR 16-BIT DAC8568
D13
D12
D11D5
D4
D3
D2
D1
X
X
F3
F2
F1
F0
GENERAL DATA FORMAT FOR 14-BIT DAC8168
D12
D11
D10
D9-D3
D2
D1
X
X
X
X
F3
F2
F1
F0
GENERAL DATA FORMAT FOR 12-BIT DAC7568
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Reserved Bit - Not valid; device does not perform
to specified conditions
DB19
D16
DB18
D15
Write to Selected DAC Input Register
0
X
0
0
0
0
0
0
0
0
Data
X
X
X
X
Write to input register - DAC Channel A
0
X
0
0
0
0
0
0
0
1
Data
X
X
X
X
Write to input register - DAC Channel B
0
X
0
0
0
0
0
0
1
0
Data
X
X
X
X
Write to input register - DAC Channel C
0
X
0
0
0
0
0
0
1
1
Data
X
X
X
X
Write to input register - DAC Channel D
0
X
0
0
0
0
0
1
0
0
Data
X
X
X
X
Write to input register - DAC Channel E
0
X
0
0
0
0
0
1
0
1
Data
X
X
X
X
Write to input register - DAC Channel F
0
X
0
0
0
0
0
1
1
0
Data
X
X
X
X
Write to input register - DAC Channel G
0
X
0
0
0
0
0
1
1
1
Data
X
X
X
X
Write to input register - DAC Channel H
0
X
0
0
0
0
1
X
X
X
X
X
X
X
X
Invalid code - No DAC channel is updated
0
X
0
0
0
0
1
1
1
1
Data
X
X
X
X
Broadcast mode - Write to all DAC channels
Update Selected DAC Registers
0
X
0
0
0
1
0
0
0
0
Data
X
X
X
X
Update DAC register - DAC Channel A
0
X
0
0
0
1
0
0
0
1
Data
X
X
X
X
Update DAC register - DAC Channel B
0
X
0
0
0
1
0
0
1
0
Data
X
X
X
X
Update DAC register - DAC Channel C
0
X
0
0
0
1
0
0
1
1
Data
X
X
X
X
Update DAC register - DAC Channel D
0
X
0
0
0
1
0
1
0
0
Data
X
X
X
X
Update DAC register - DAC Channel E
0
X
0
0
0
1
0
1
0
1
Data
X
X
X
X
Update DAC register - DAC Channel F
0
X
0
0
0
1
0
1
1
0
Data
X
X
X
X
Update DAC register - DAC Channel G
0
X
0
0
0
1
0
1
1
1
Data
X
X
X
X
Update DAC register - DAC Channel H
0
X
0
0
0
1
1
X
X
X
X
X
X
X
X
Invalid code - No DAC channel is updated
0
X
0
0
0
1
1
1
1
1
Data
X
X
X
X
Broadcast mode - Update all DAC registers
Write to Clear Code Register
0
X
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
Write to clear code register; clear to zero scale
0
X
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
Write to clear code register; clear to midscale
0
X
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
Write to clear code register; clear to full-scale
0
X
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
Write to clear code register; ignore CLR pin
0
1
1
0
X
X
X
X
X
X
X
X
X
X
DAC
H
DAC
G
DAC
F
DAC
E
DAC
D
DAC
C
DAC
B
DAC
A
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Write to LDAC Register
0
X
Write to LDAC register. Default setting of these bits
is '0'. If bit is set to '1', the LDAC pin is overridden.
See the LDAC Functionality section for details.
Software Reset
0
X
Software reset (power-on reset)
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Table 10. Control Matrix for the DAC7568, DAC8168, and DAC8568 (continued)
DB31
DB30DB28
0
Don't
Care
0
Don't
Care
C3
C2
C1
C0
A3
A2
A1
A0
D14
0
Don't
Care
C3
C2
C1
C0
A3
A2
A1
A0
D12
0
DB27
C3
DB26
C2
DB25
C1
DB24
C0
DB23
A3
DB22
A2
DB21
A1
DB17
DB16DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DESCRIPTION
D14
D13D7
D6
D5
D4
D3
D2
D1
F3
F2
F1
F0
GENERAL DATA FORMAT FOR 16-BIT DAC8568
D13
D12
D11D5
D4
D3
D2
D1
X
X
F3
F2
F1
F0
GENERAL DATA FORMAT FOR 14-BIT DAC8168
D11
D10
D9-D3
D2
D1
X
X
X
X
F3
F2
F1
F0
GENERAL DATA FORMAT FOR 12-BIT DAC7568
Data
X
X
X
X
Write to DAC input register Ch A and update all
DAC registers (SW LDAC)
1
Data
X
X
X
X
Write to DAC Input Register Ch B and update all
DAC registers (SW LDAC)
DB20
A0
DB19
D16
DB18
D15
Write to Selected DAC Input Register and Update All DAC Registers
0
X
0
0
1
0
0
0
0
0
X
0
0
1
0
0
0
0
0
X
0
0
1
0
0
0
1
0
Data
X
X
X
X
Write to DAC Input Register Ch C and update all
DAC registers (SW LDAC)
0
X
0
0
1
0
0
0
1
1
Data
X
X
X
X
Write to DAC Input Register Ch D and update all
DAC registers (SW LDAC)
0
X
0
0
1
0
0
1
0
0
Data
X
X
X
X
Write to DAC Input Register Ch E and update all
DAC registers (SW LDAC)
0
X
0
0
1
0
0
1
0
1
Data
X
X
X
X
Write to DAC Input Register Ch F and update all
DAC registers (SW LDAC)
0
X
0
0
1
0
0
1
1
0
Data
X
X
X
X
Write to DAC Input Register Ch G and update all
DAC registers (SW LDAC)
0
X
0
0
1
0
0
1
1
1
Data
X
X
X
X
Write to DAC Input Register Ch H and update all
DAC registers (SW LDAC)
0
X
0
0
1
0
1
X
X
X
X
X
X
X
X
Invalid code - No DAC Channel is updated
0
X
0
0
1
0
1
1
1
1
Data
X
X
X
X
Broadcast mode - Write to all DAC input registers
and update all DAC registers (SW LDAC)
Write to Selected DAC Input Register and Update Respective DAC Register
36
0
X
0
0
1
1
0
0
0
0
Data
X
X
X
X
Write to DAC input register Ch A and update DAC
register Ch A
0
X
0
0
1
1
0
0
0
1
Data
X
X
X
X
Write to DAC Input Register Ch B and update DAC
register Ch B
0
X
0
0
1
1
0
1
0
Data
X
X
X
X
Write to DAC Input Register Ch C and update DAC
register Ch C
0
X
0
0
1
1
0
0
1
1
Data
X
X
X
X
Write to DAC Input Register Ch D and update DAC
register Ch D
0
X
0
0
1
1
0
1
0
0
Data
X
X
X
X
Write to DAC Input Register Ch E and update DAC
register Ch E
0
X
0
0
1
1
0
1
0
1
Data
X
X
X
X
Write to DAC Input Register Ch F and update DAC
register Ch F
0
X
0
0
1
1
0
1
1
0
Data
X
X
X
X
Write to DAC Input Register Ch G and update DAC
register Ch G
0
X
0
0
1
1
0
1
1
1
Data
X
X
X
X
Write to DAC Input Register Ch H and update DAC
register Ch H
0
X
0
0
1
1
1
X
X
X
X
X
X
X
X
Invalid code - No DAC channel is updated
0
X
0
0
1
1
1
1
1
1
Data
X
X
X
X
Broadcast mode - Write to all DAC input registers
and update all DAC registers (SW LDAC)
0
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Table 10. Control Matrix for the DAC7568, DAC8168, and DAC8568 (continued)
DB31
DB30DB28
0
Don't
Care
0
Don't
Care
C3
C2
C1
C0
A3
A2
A1
A0
D14
0
Don't
Care
C3
C2
C1
C0
A3
A2
A1
A0
DB27
C3
DB26
C2
DB25
C1
DB24
DB23
C0
A3
DB22
A2
DB21
A1
DB20
A0
DB17
DB16DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DESCRIPTION
D14
D13D7
D6
D5
D4
D3
D2
D1
F3
F2
F1
F0
GENERAL DATA FORMAT FOR 16-BIT DAC8568
D13
D12
D11D5
D4
D3
D2
D1
X
X
F3
F2
F1
F0
GENERAL DATA FORMAT FOR 14-BIT DAC8168
D12
D11
D10
D9-D3
D2
D1
X
X
X
X
F3
F2
F1
F0
GENERAL DATA FORMAT FOR 12-BIT DAC7568
0
0
DAC
H
DAC
G
DAC
F
DAC
E
DAC
D
DAC
C
DAC
B
DAC
A
Power-up DAC A, B, C, D, E, F, G, H by setting
respective bit to '1'
DB19
D16
DB18
D15
Power-Down Commands
0
X
0
1
0
0
X
X
X
X
X
X
X
X
0
X
0
1
0
0
X
X
X
X
X
X
X
X
0
1
DAC
H
DAC
G
DAC
F
DAC
E
DAC
D
DAC
C
DAC
B
DAC
A
Power-down DAC A, B, C, D, E, F, G, H, 1kΩ to
GND by setting respective bit to '0'
0
X
0
1
0
0
X
X
X
X
X
X
X
X
1
0
DAC
H
DAC
G
DAC
F
DAC
E
DAC
D
DAC
C
DAC
B
DAC
A
Power-down DAC A, B, C, D, E, F, G, H, 100kΩ to
GND by setting respective bit to '0'
0
X
0
1
0
0
X
X
X
X
X
X
X
X
1
1
DAC
H
DAC
G
DAC
F
DAC
E
DAC
D
DAC
C
DAC
B
DAC
A
Power-down DAC A, B, C, D, E, F, G, H, High-Z to
GND by setting respective bit to '0'
Internal Reference Commands
0
X
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
Power down internal reference - static mode
(default), must use external reference to operate
device; see Table 2
0
X
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
Power up internal reference - static mode; see
Table 1 (NOTE: When all DACs power down, the
reference powers down; when any DAC powers up,
the reference powers up)
0
X
1
0
0
1
X
X
X
X
1
0
0
X
X
X
X
X
X
X
X
X
X
X
Power up internal reference - flexible mode; see
Table 3 (NOTE: When all DACs power down, the
reference powers down; when any DAC powers up,
the reference powers up)
0
X
1
0
0
1
X
X
X
X
1
0
1
X
X
X
X
X
X
X
X
X
X
X
Power up internal reference all the time regardless
of state of DACs - flexible mode; see Table 4
0
X
1
0
0
1
X
X
X
X
1
1
0
X
X
X
X
X
X
X
X
X
X
X
Power down internal reference all the time
regardless of state of DACs - flexible mode; see
Table 5 (NOTE: External reference must be used to
operate device)
0
X
1
0
0
1
X
X
X
X
0
0
0
X
X
X
X
X
X
X
X
X
X
X
Switching internal reference mode from flexible
mode to static mode
Reserved Bits
0
X
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Reserved Bit - not valid; device does not perform to
specified conditions
0
X
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Reserved Bit - not valid; device does not perform to
specified conditions
0
X
1
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Reserved Bit - not valid; device does not perform to
specified conditions
0
X
1
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Reserved Bit - not valid; device does not perform to
specified conditions
0
X
1
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Reserved Bit - not valid; device does not perform to
specified conditions
0
X
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Reserved Bit - not valid; device does not perform to
specified conditions
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SYNC INTERRUPT
In a normal write sequence, the SYNC line stays low
for at least 32 falling edges of SCLK and the
addressed DAC register updates on the 32nd falling
edge. However, if SYNC is brought high before the
31st falling edge, it acts as an interrupt to the write
sequence; the shift register resets and the write
sequence is discarded. Neither an update of the data
buffer contents, DAC register contents, nor a change
in the operating mode occurs (as shown in
Figure 123).
POWER-ON RESET TO ZERO SCALE OR
MIDSCALE
The DAC7568, DAC8168, and DAC8568 contain a
power-on reset circuit that controls the output voltage
during power-up. For device grades A and C on
power-up, all DAC registers are filled with zeros and
the output voltages of all DAC channels are set to
zero scale. For device grades B and D all DAC
registers are set to have all DAC channels power up
in midscale. All DAC channels remain that way until a
valid write sequence and load command are made to
the respective DAC channel. The power-on reset is
useful in applications where it is important to know
the state of the output of each DAC while the device
is in the process of powering up. No device pin
should be brought high before power is applied to the
device. The internal reference is powered off / down
by default and remains that way until a valid
reference-change command is executed.
LDAC FUNCTIONALITY
The DAC7568, DAC8168, and DAC8568 offer both a
software and hardware simultaneous update and
control
function.
The
DAC
double-buffered
architecture has been designed so that new data can
be entered for each DAC without disturbing the
analog outputs.
DAC7568, DAC8168, and DAC8568 data updates
can be performed either in synchronous or in
asynchronous mode.
In synchronous mode, data are updated with the
falling edge of the 32nd SCLK cycle, which follows a
falling edge of SYNC. For such synchronous updates,
the LDAC pin is not required and it must be
connected to GND permanently.
In asynchronous mode, the LDAC pin is used as a
negative
edge
triggered
timing
signal
for
simultaneous DAC updates. Multiple single-channel
updates can be done in order to set different channel
buffers to desired values and then make a falling
edge on LDAC pin to simultaneously update the DAC
output registers. Data buffers of all channels must be
loaded with desired data before an LDAC falling
edge. After a high-to-low LDAC transition, all DACs
are simultaneously updated with the last contents of
the corresponding data buffers. If the content of a
data buffer is not changed, the corresponding DAC
output remains unchanged after the LDAC pin is
triggered.
Alternatively, all DAC outputs can be updated
simultaneously using the built-in software function of
LDAC. The LDAC register offers additional flexibility
and control by allowing the selection of which DAC
channel(s) should be updated simultaneously when
the LDAC pin is being brought low. The LDAC
register is loaded with an 8-bit word (DB0 to DB7)
using control bits C3, C2, C1, and C0 (see Table 10).
The default value for each bit, and therefore for each
DAC channel, is zero. The external LDAC pin
operates in normal mode. If the LDAC register bit is
set to '1', it overrides the LDAC pin (the LDAC pin is
internally tied low for that particular DAC channel)
and this DAC channel updates synchronously after
the falling edge of the 32nd SCLK cycle. However, if
the LDAC register bit is set to '0', the DAC channel is
controlled by the LDAC pin.
The combination of software and hardware
simultaneous update functions is particularly useful in
applications when updating only selective DAC
channels simultaneously, while keeping the other
channels unaffected and updating those channels
synchronously; see Table 10 for more information.
31st Falling Edge
32nd Falling Edge
CLK
SYNC
DIN
DB31
DB0
DB31
DB0
Invalid/Interrupted Write Sequence:
Output/Mode Does Not Update on the 32nd Falling Edge
Valid Write Sequence:
Output/Mode Updates on the 32nd Falling Edge
Figure 123. SYNC Interrupt Facility
38
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POWER-DOWN MODES
The DAC7568, DAC8168, and DAC8568 have two
separate sets of power-down commands. One set is
for the DAC channels and the other set is for the
internal reference. For more information on powering
down the reference, see the Enable/Disable Internal
Reference section.
DAC Power-Down Commands
The DAC7568, DAC8168, and DAC8568 use four
modes of operation. These modes are accessed by
setting control bits C3, C2, C1, and C0, and
power-down register bits DB8 and DB9. The control
bits must be set to '0100'. Once the control bits are
set correctly, the four different power down modes
are software programmable by setting bits DB8 and
DB9 in the control register. Table 10 and Table 11
shows how to control the operating mode with data
bits PD0 (DB8), and PD1 (DB9).
Table 11. DAC Operating Modes
PD1
(DB9)
PD0
(DB8)
0
0
Power up selected DACs
0
1
Power down selected DACs 1kΩ to GND
1
0
Power down selected DACs 100kΩ to GND
1
1
Power down selected DACs High-Z to GND
DAC OPERATING MODES
The DAC7568, DAC8168, and DAC8568 treat the
power-down condition as data; all the operational
modes are still valid for power-down. It is possible to
broadcast a power-down condition to all the
DAC8568, DAC8168, DAC7568s in a system. It is
also possible to power-down a channel and update
data on other channels. Furthermore, it is possible to
write to the DAC register/buffer of the DAC channel
that is powered down. When the DAC channel is then
powered up, it will power up to this new value (see
the Operating Examples section).
When both the PD0 and PD1 bits are set to '0', the
device works normally with its typical current
consumption of 1.25mA at 5.5V. The reference
current is included with the operation of all eight
DACs. However, for the three power-down modes,
the supply current falls to 0.18µA at 5.5V (0.10µA at
3.6V). Not only does the supply current fall, but the
output stage also switches internally from the output
of the amplifier to a resistor network of known values.
The advantage of this switching is that the output
impedance of the device is known while it is in
power-down mode. As described in Table 11, there
are three different power-down options. VOUT can be
connected internally to GND through a 1kΩ resistor, a
100kΩ resistor, or open circuited (High-Z). The output
stage is shown in Figure 124. In other words, DB27,
DB26, DB25, and DB24 = '0100' and DB9 and DB8 =
'11' represent a power-down condition with High-Z
output impedance for a selected channel. DB9 and
DB8 = '01' represents a power-down condition with
1kΩ output impedance, and '10' represents a
power-down condition with 100kΩ output impedance.
Resistor
String
DAC
Amplifier
Power-Down
Circuitry
VOUTX
Resistor
Network
Figure 124. Output Stage During Power-Down
All analog channel circuits are shut down when the
power-down mode is exercised. However, the
contents of the DAC register are unaffected when in
power down. By setting both bits, DB8 and DB9, to
different values, any combination of DAC channels
can be powered down or powered up. If a DAC
channel is being powered up from a previously power
down situation, this DAC channel powers up to the
value in its DAC register. The time required to exit
power-down is typically 2.5µs for AVDD = 5V, and 4µs
for AVDD = 3V. See the Typical Characteristics for
more information.
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CLEAR CODE REGISTER and CLR PIN
sequence, this write sequence is aborted and the
DAC registers and DAC buffers are cleared as
described previously.
The DAC7568, DAC8168, and DAC8568 contain a
clear code register. The clear code register can be
accessed via the serial peripheral interface (SPI) and
is user-configurable. Bringing the CLR pin low clears
the content of all DAC registers and all DAC buffers,
and replaces the code with the code determined by
the clear code register. The clear code register can
be written to by applying the commands showed in
Table 12. The control bits must be set as follows to
access the clear code register that is programmed via
the feature bits, F0 and F1: C3 = '0', C2 = '1', C1 =
'0', and C0 = '1'. The default setting of the clear code
register sets the output of all DAC channels to 0V
when CLR pin is brought low. The CLR pin is
falling-edge triggered; therefore, the device exits clear
code mode on the 32nd falling edge of the next write
sequence. If CLR pin is brought low during a write
When performing a software reset of the device, the
clear code register is set back to its default mode
(DB1 = DB0 = '0'). Setting the clear code register to
DB1 = DB0 = '1' ignores any activity on the external
CLR pin.
SOFTWARE RESET FUNCTION
The DAC7568, DAC8168, and DAC8568 contain a
software reset feature. If the software reset feature is
executed, all registers inside the device are reset to
default settings; that is, all DAC channels are reset to
the power-on reset code (power on reset to zero
scale for grades A and C; power on reset to midscale
for grades B and D).
DB3
DB2
D6
D5
D4
D3
D2
D1
F3
F2
DB0
DB4
A0
D16D7
DB1
DB5
DB21
A1
DB6
A2
DB7
A3
DB22
DB23
DB24
C0
DB8
C1
DB19DB10
DB9
C2
DB20
C3
DB25
0
Don't
Care
DB26
DB30DB28
DB27
DB31
Table 12. Clear Code Register
F1
F0
GENERAL DATA FORMAT
DESCRIPTION
0
X
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
Clear all DAC outputs to zero scale (default
mode)
0
X
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
Clear all DAC outputs to midscale
0
X
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
Clear all DAC outputs to full-scale
0
X
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
Ignore external CLR pin
A0
X
X
X
X
X
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DB0
A1
1
DB1
A2
1
DB2
A3
1
DB3
C0
0
DB4
C1
X
DB5
C2
0
DB6
C3
D16D7
DB7
0
Don't
Care
DB8
DB19DB10
DB9
DB20
DB21
DB22
DB23
DB24
DB25
DB26
DB30DB28
40
DB27
DB31
Table 13. Software Reset
D6
D5
D4
D3
D2
D1
F3
F2
F1
F0
X
X
X
X
X
X
X
X
X
X
DESCRIPTION
GENERAL DATA FORMAT
Software reset
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC7568 DAC8168 DAC8568
DAC7568
DAC8168
DAC8568
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OPERATING EXAMPLES: DAC7568/DAC8168/DAC8568
For the following examples X = don't care; value can be either '0' or '1'.
Example 1: Write to Data Buffer A, B, G, H; Load DAC A, B, G, H Simultaneously
DB26
DB25
DB24
DB23
DB22
DB21
DB20
0
0
DB30DB28
Don't
Care
X
DB27
DB31
1st: Write to data buffer A:
C3
0
C2
0
C1
0
C0
0
A3
0
A2
0
A1
0
A0
0
DB19DB10
D16D7
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D6
D5
D4
DATA
D3
D2
D1
F3
X
F2
X
F1
X
F0
X
DB20
DB21
C3
C2
C1
C0
A3
A2
A1
A0
D16D7
0
X
0
0
0
0
0
0
0
1
DB21
DB22
0
Don't
Care
DB22
DB23
DB19DB10
DB23
DB24
DB30DB28
DB24
DB25
DB26
DB27
DB31
2nd: Write to data buffer B:
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D6
D5
D4
D3
D2
D1
DATA
F3
F2
F1
F0
X
X
X
X
DB30DB28
DB20
DB25
DB26
DB27
DB31
3rd: Write to data buffer G:
DB19DB10
0
Don't
Care
C3
C2
C1
C0
A3
A2
A1
A0
D16D7
0
X
0
0
0
0
0
1
1
0
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D6
D5
D4
D3
D2
D1
DATA
F3
F2
F1
F0
X
X
X
X
DB31
DB30DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
4th: Write to data buffer H and simultaneously update all DACs:
DB19DB10
0
Don't
Care
C3
C2
C1
C0
A3
A2
A1
A0
D16D7
0
X
0
0
1
0
0
1
1
1
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D6
D5
D4
DATA
D3
D2
D1
F3
F2
F1
F0
X
X
X
X
The DAC A, DAC B, DAC G, and DAC H analog outputs simultaneously settle to the specified values upon
completion of the 4th write sequence. (The DAC voltages update simultaneously after the 32nd SCLK falling
edge of the fourth write cycle).
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DAC8168
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Example 2: Load New Data to DAC C, D, E, F Sequentially
DB26
DB25
DB24
DB23
DB22
DB21
DB20
0
0
DB30DB28
Don't
Care
X
DB27
DB31
1st: Write to data buffer C and load DAC C: DAC C output settles to specified value upon completion:
C3
0
C2
0
C1
1
C0
1
A3
0
A2
0
A1
1
A0
0
DB19DB10
D16D7
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D6
D5
D4
DATA
D3
D2
D1
F3
X
F2
X
F1
X
F0
X
DB30DB28
DB20
DB21
DB22
DB23
DB24
DB25
DB26
DB27
DB31
2nd: Write to data buffer D and load DAC D: DAC D output settles to specified value upon completion:
DB19DB10
0
Don't
Care
C3
C2
C1
C0
A3
A2
A1
A0
D16D7
0
X
0
0
1
1
0
0
1
1
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D6
D5
D4
D3
D2
D1
DATA
F3
F2
F1
F0
X
X
X
X
DB30DB28
DB20
DB21
DB22
DB23
DB24
DB25
DB26
DB27
DB31
3rd: Write to data buffer E and load DAC E: DAC E output settles to specified value upon completion:
DB19DB10
0
Don't
Care
C3
C2
C1
C0
A3
A2
A1
A0
D16D7
0
X
0
0
1
1
0
1
0
0
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D6
D5
D4
D3
D2
D1
DATA
F3
F2
F1
F0
X
X
X
X
DB30DB28
DB20
DB21
DB22
DB23
DB24
DB25
DB26
DB27
DB31
4th: Write to data buffer F and load DAC F: DAC F output settles to specified value upon completion:
DB19DB10
0
Don't
Care
C3
C2
C1
C0
A3
A2
A1
A0
D16D7
0
X
0
0
1
1
0
1
0
1
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D6
D5
D4
D3
D2
D1
DATA
F3
F2
F1
F0
X
X
X
X
After completion of each write cycle, the DAC analog output settles to the voltage specified.
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DAC7568
DAC8168
DAC8568
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Example 3: Power-Down DAC A, DAC B and DAC H to 1kΩ and Power-Down DAC C, DAC D, and DAC F
to 100kΩ
DB26
DB25
DB24
DB23
DB22
DB21
DB20
0
0
DB30DB28
Don't
Care
X
DB27
DB31
1st: Write power-down command to DAC channel A and DAC channel B: DAC A and DAC B to 1kΩ.
C3
0
C2
1
C1
0
C0
0
A3
0
A2
0
A1
0
A0
0
DB19DB10
D16D7
0
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D6
0
D5
1
D4
0
D3
0
D2
0
D1
0
F3
0
F2
0
F1
1
F0
1
DB31
DB30DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
2nd: Write power-down command to DAC channel H: DAC H to 1kΩ.
DB19DB10
0
Don't
Care
C3
C2
C1
C0
A3
A2
A1
A0
D16D7
D6
D5
D4
D3
D2
D1
F3
F2
F1
F0
0
X
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB30DB28
0
Don't
Care
C3
C2
C1
C0
A3
A2
A1
0
X
0
1
0
0
0
0
0
DB20
DB21
DB22
DB23
DB24
DB25
DB26
DB27
DB31
3rd: Write power-down command to DAC channel C and DAC channel D: DAC C and DAC D to 100kΩ.
DB19DB10
A0
D16D7
D6
D5
D4
D3
D2
D1
F3
F2
F1
F0
0
0
1
0
0
0
0
0
1
1
0
0
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB31
DB30DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
4th: Write power-down command to DAC channel F: DAC F to 100kΩ.
DB19DB10
0
Don't
Care
C3
C2
C1
C0
A3
A2
A1
A0
D16D7
D6
D5
D4
D3
D2
D1
F3
F2
F1
F0
0
X
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
The DAC A, DAC B, DAC C, DAC D, DAC F, and DAC H analog outputs power-down to each respective
specified mode.
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DAC8168
DAC8568
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Example 4: Power-Down All Channels Simultaneously while Reference is Always Powered Up
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
0
0
DB30DB28
Don't
Care
X
DB27
DB31
1st: Write sequence for enabling the DAC7568, DAC8168, and DAC8568 internal reference all the time:
C3
1
C2
0
C1
0
C0
1
A3
X
A2
X
A1
X
A0
X
D16
1
D15
0
D14
1
DB16DB7
D13D4
X
DB6 DB5 DB4 DB3 DB2 DB1 DB0
D3
X
D2
X
D1
X
F3
X
F2
X
F1
X
F0
X
DB30DB28
0
Don't
Care
C3
C2
C1
C0
A3
A2
A1
0
X
0
1
0
0
X
X
X
DB20
DB21
DB22
DB23
DB24
DB25
DB26
DB27
DB31
2nd: Write sequence to power-down all DACs to high-impedance:
DB19DB10
A0
D16D7
D6
D5
D4
D3
D2
D1
F3
F2
F1
F0
X
X
1
1
1
1
1
1
1
1
1
1
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
The DAC A, DAC B, DAC C, DAC D, DAC E, DAC F, DAC G, and DAC H analog outputs simultaneously
power-down to high-impedance upon completion of the first and second write sequences, respectively.
Example 5: Write a Specific Value to All DACs while Reference is Always Powered Down
DB30DB28
0
Don't
Care
C3
C2
C1
C0
A3
A2
A1
A0
D16
D15
0
X
1
0
0
1
X
X
X
X
1
1
DB17
DB18
DB19
DB20
DB21
DB22
DB23
DB24
DB25
DB26
DB27
DB31
1st: Write sequence for disabling the DAC7568, DAC8168, and DAC8568 internal reference all the time
(after this sequence, these devices require an external reference source to function):
DB16DB7
D14
D13D4
D3
D2
D1
F3
F2
F1
F0
0
X
X
X
X
X
X
X
X
DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB30DB28
DB20
DB21
DB22
DB23
DB24
DB25
DB26
DB27
DB31
2nd: Write sequence to write specified data to all DACs:
DB19DB10
0
Don't
Care
C3
C2
C1
C0
A3
A2
A1
A0
D16D7
0
X
0
0
1
1
1
1
1
1
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D6
D5
D4
D3
DATA
D2
D1
F3
F2
F1
F0
X
X
X
X
The DAC A, DAC B, DAC C, DAC D, DAC E, DAC F, DAC G, and DAC H analog outputs simultaneously settle
to the specified values upon completion of the second write sequence. (The DAC voltages update simultaneously
after the 32nd SCLK falling edge of the second write cycle). Reference is always powered-down (External
reference must be used for proper operation).
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DAC7568
DAC8168
DAC8568
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APPLICATION INFORMATION
INTERNAL REFERENCE
The internal reference of the DAC7568, DAC8168,
and DAC8568 does not require an external load
capacitor for stability because it is stable with any
capacitive load. However, for improved noise
performance, an external load capacitor of 150nF or
larger connected to the VREFH/VREFOUT output is
recommended. Figure 125 shows the typical
connections required for operation of the DAC7568,
DAC8168, and DAC8568 internal reference. A supply
bypass capacitor at the AVDD input is also
recommended.
DAC7568
DAC8168
DAC8568
AVDD
1
LDAC
SCLK 16
2
SYNC
DIN 15
3
AVDD
4
VOUTA
VOUTB 13
5
VOUTC
VOUTD 12
6
VOUTE
VOUTF 11
7
VOUTG
VOUTH 10
8
VREFIN/VREFOUT
GND 14
1mF
CLR
9
150nF
Figure 125. Typical Connections for Operating the
DAC7568/DAC8168/DAC8568 Internal Reference
(16-Pin Version Shown)
Supply Voltage
The internal reference features an extremely low
dropout voltage. It can be operated with a supply of
only 5mV above the reference output voltage in an
unloaded condition. For loaded conditions, refer to
the Load Regulation section. The stability of the
internal reference with variations in supply voltage
(line regulation, dc PSRR) is also exceptional. Within
the specified supply voltage range of 2.7V to 5.5V,
the variation at VREFH/VREFOUT is less than 10µV/V;
see the Typical Characteristics.
Temperature Drift
The internal reference is designed to exhibit minimal
drift error, defined as the change in reference output
voltage over varying temperature. The drift is
calculated using the box method described by
Equation 2:
Drift Error =
VREF_MAX - VREF_MIN
VREF ´ TRANGE
6
´ 10 (ppm/°C)
(2)
Where:
VREF_MAX = maximum reference voltage observed
within temperature range TRANGE.
VREF_MIN = minimum reference voltage observed
within temperature range TRANGE.
VREF = 2.5V, target value for reference output
voltage.
The internal reference (grade C only) features an
exceptional typical drift coefficient of 2ppm/°C from
–40°C to +125°C. Characterizing a large number of
units, a maximum drift coefficient of 5ppm/°C (grade
C only) is observed. Temperature drift results are
summarized in the Typical Characteristics.
Noise Performance
Typical 0.1Hz to 10Hz voltage noise can be seen in
Figure 9, Internal Reference Noise. Additional filtering
can be used to improve output noise levels, although
care should be taken to ensure the output impedance
does not degrade the ac performance. The output
noise spectrum at VREFH/VREFOUT without any
external components is depicted in Figure 8, Internal
Reference Noise Density vs Frequency. A second
noise density spectrum is also shown in Figure 8.
This spectrum was obtained using a 4.8µF load
capacitor at VREFH/VREFOUT for noise filtering.
Internal reference noise impacts the DAC output
noise; see the DAC Noise Performance section for
more details.
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DAC8168
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Load Regulation
Thermal Hysteresis
Load regulation is defined as the change in reference
output voltage as a result of changes in load current.
The load regulation of the internal reference is
measured using force and sense contacts as shown
in Figure 126. The force and sense lines reduce the
impact of contact and trace resistance, resulting in
accurate measurement of the load regulation
contributed solely by the internal reference.
Measurement results are summarized in the Typical
Characteristics. Force and sense lines should be
used for applications that require improved load
regulation.
Thermal hysteresis for a reference is defined as the
change in output voltage after operating the device at
+25°C, cycling the device through the operating
temperature range, and returning to +25°C.
Hysteresis is expressed by Equation 3:
Output Pin
Contact and
Trace Resistance
VOUT
Force Line
IL
Sense Line
Meter
Load
Figure 126. Accurate Load Regulation of the
DAC7568/DAC8168/DAC8568 Internal Reference
Long-Term Stability
Long-term stability/aging refers to the change of the
output voltage of a reference over a period of months
or years. This effect lessens as time progresses (see
Figure 7, the typical long-term stability curve). The
typical drift value for the internal reference is 50ppm
from 0 hours to 1900 hours. This parameter is
characterized by powering-up 20 units and measuring
them at regular intervals for a period of 1900 hours.
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VHYST =
|VREF_PRE - VREF_POST|
VREF_NOM
6
´ 10 (ppm/°C)
(3)
Where:
VHYST = thermal hysteresis.
VREF_PRE = output voltage measured at +25°C
pre-temperature cycling.
VREF_POST = output voltage measured after the
device cycles through the temperature range of
–40°C to +125°C, and returns to +25°C.
DAC NOISE PERFORMANCE
Typical noise performance for the DAC7568,
DAC8168, and DAC8568 with the internal reference
enabled is shown in Figure 66 to Figure 67. Output
noise spectral density at the VOUT pin versus
frequency is depicted in Figure 66 for full-scale,
midscale, and zero-scale input codes. The typical
noise density for midscale code is 120nV/√Hz at
1kHz and 100nV/√Hz at 1MHz. High-frequency noise
can be improved by filtering the reference noise.
Integrated output noise between 0.1Hz and 10Hz is
close to 6µVPP (midscale), as shown in Figure 67.
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BIPOLAR OPERATION USING THE
DAC7568/DAC8168/DAC8568
The DAC7568, DAC8168, and DAC8568 are
designed for single-supply operation, but a bipolar
output range is also possible using the circuit in either
Figure 127 or Figure 128. The circuit shown gives an
output voltage range of ±VREF. Rail-to-rail operation at
the amplifier output is achievable using an OPA703
as the output amplifier.
The output voltage for any input code can be
calculated with Equation 4:
VOUT = VREF ´ Gain ´
DIN
2n
R 1 + R2
´
R1
R1
(4)
Where:
V
REF
With VREFIN/VREFOUT = 5V, R1 = R2 = 10kΩ, for
grades A and B.
VOUT =
R2
- VREF ´
DIN = decimal equivalent of the binary code that
is loaded to the DAC register. It can range from 0
to 4095 for DAC7568 (12 bit), 0 to 16,383 for
DAC8168 (14 bit), and 0 to 65535 for DAC8568
(16 bit).
n = resolution in bits; either 12 (DAC7568), 14
(DAC8168) or 16 (DAC8568)
Gain = 1 for A/B grades or 2 for C/D grades.
10 ´ DIN
- 5V
2n
This result has an output voltage range of ±5V with
0000h corresponding to a –5V output and FFFFh
corresponding to a +5V output for the 16-bit
DAC8568, as shown in Figure 127. Similarly, using
the internal reference, a ±2.5V output voltage range
can be achieved, as Figure 128 shows.
R2
10kW
AV
EXT
(5)
DD
+6V
R1
10kW
±5V
OPA703
AVDD
VOUT
DAC7568
VREFIN/
DAC8168
VREFOUT DAC8568
10mF
0.1mF
-6V
GND
3-Wire
Serial Interface
Figure 127. Bipolar Output Range Using External Reference at 5V
R2
10kW
AV
DD
+6V
R1
10kW
OPA703
AVDD
±2.5V
VOUT
VREFIN/ DAC7568
DAC8168
VREFOUT
DAC8568
-6V
150nF
GND
3-Wire
Serial Interface
Figure 128. Bipolar Output Range Using Internal Reference
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DAC8168
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MICROPROCESSOR INTERFACING
DAC7568/DAC8168/DAC8568 to an 8051 Interface
Figure 129 shows a serial interface between the
DAC7568, DAC8168, and DAC8568 and a typical
8051-type microcontroller. The setup for the interface
is as follows: TXD of the 8051 drives SCLK of the
DAC7568, DAC8168, or DAC8568, while RXD drives
the serial data line of the device. The SYNC signal is
derived from a bit-programmable pin on the port of
the 8051; in this case, port line P3.3 is used. When
data are to be transmitted to the DAC7568,
DAC8168, and DAC8568, P3.3 is taken low. The
8051 transmits data in 8-bit bytes; thus, only eight
falling clock edges occur in the transmit cycle. To
load data to the DAC, P3.3 is left low after the first
eight bits are transmitted; then, a second write cycle
is initiated to transmit the second byte of data. P3.3 is
taken high following the completion of the third write
cycle. The 8051 outputs the serial data in a format
that has the LSB first. The DAC7568, DAC8168, and
DAC8568 require the data with the MSB as the first
bit received. Therefore, the 8051 transmit routine
must take this requirement into account, and mirror
the data as needed.
80C51/80L51(1)
DAC8568(1)
P3.3
SYNC
TXD
SCLK
RXD
DIN
NOTE: (1) Also applies to DAC7568 and DAC8168. Additional pins omitted for clarity.
Figure 129. DAC7568/DAC8168/DAC8568 to
80C51/80L51 Interface
DAC7568/DAC8168/DAC8568 to Microwire
Interface
Figure 130 shows an interface between the
DAC7568, DAC8168, and DAC8568 and any
Microwire-compatible device. Serial data are shifted
out on the falling edge of the serial clock and are
clocked into the DAC7568, DAC8168, and DAC8568
on the rising edge of the SK signal.
48
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Microwireä
DAC8568(1)
CS
SYNC
SK
SCLK
SO
DIN
NOTE: (1) Also applies to DAC7568 and DAC8168. Additional pins omitted for clarity.
Figure 130. DAC7568/DAC8168/DAC8568 to
Microwire Interface
DAC7568/DAC8168/DAC8568 to 68HC11 Interface
Figure 131 shows a serial interface between the
DAC7568/DAC8168/DAC8568 and the 68HC11
microcontroller. SCK of the 68HC11 drives the SCLK
of the DAC7568, DAC8168, and DAC8568, while the
MOSI output drives the serial data line of the DAC.
The SYNC signal derives from a port line (PC7),
similar to the 8051 diagram.
68HC11(1)
DAC8568(1)
PC7
SYNC
SCK
SCLK
MOSI
DIN
NOTE: (1) Also applies to DAC7568 and DAC8168. Additional pins omitted for clarity.
Figure 131. DAC7568/DAC8168/DAC8568 to
68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data are
being transmitted to the DAC, the SYNC line is held
low (PC7). Serial data from the 68HC11 are
transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data are
transmitted MSB first.) In order to load data to the
DAC7568, DAC8168, and DAC8568, PC7 is left low
after the first eight bits are transferred; then, a second
and third serial write operation are performed to the
DAC. PC7 is taken high at the end of this procedure.
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC7568 DAC8168 DAC8568
DAC7568
DAC8168
DAC8568
www.ti.com ..................................................................................................................................................... SBAS430A – JANUARY 2009 – REVISED APRIL 2009
LAYOUT
A precision analog component requires careful layout,
adequate bypassing, and clean, well-regulated power
supplies.
The DAC7568, DAC8168, and DAC8568 offer
single-supply operation, and are often used in close
proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The
more digital logic present in the design and the higher
the switching speed, the more difficult it is to keep
digital noise from appearing at the output.
As a result of the single ground pin of the DAC7568,
DAC8168, and DAC8568, all return currents
(including digital and analog return currents for the
DAC) must flow through a single point. Ideally, GND
would be connected directly to an analog ground
plane. This plane would be separate from the ground
connection for the digital components until they were
connected at the power-entry point of the system.
The power applied to AVDD should be well-regulated
and low noise. Switching power supplies and dc/dc
converters often have high-frequency glitches or
spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes
as their internal logic switches states. This noise can
easily couple into the DAC output voltage through
various paths between the power connections and
analog output.
As with the GND connection, AVDD should be
connected to a power-supply plane or trace that is
separate from the connection for digital logic until
they are connected at the power-entry point. In
addition, a 1µF to 10µF capacitor and 0.1µF bypass
capacitor are strongly recommended. In some
situations, additional bypassing may be required,
such as a 100µF electrolytic capacitor or even a Pi
filter made up of inductors and capacitors—all
designed to essentially low-pass filter the supply and
remove the high-frequency noise.
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC7568 DAC8168 DAC8568
Submit Documentation Feedback
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DAC8168
DAC8568
SBAS430A – JANUARY 2009 – REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com
PARAMETER DEFINITIONS
With the increased complexity of many different
specifications listed in product data sheets, this
section summarizes selected specifications related to
digital-to-analog converters.
STATIC PERFORMANCE
Static performance parameters are specifications
such as differential nonlinearity (DNL) or integral
nonlinearity (INL). These are dc specifications and
provide information on the accuracy of the DAC. They
are most important in applications where the signal
changes slowly and accuracy is required.
Resolution
Generally, the DAC resolution can be expressed in
different forms. Specifications such as IEC 60748-4
recognize the numerical, analog, and relative
resolution. The numerical resolution is defined as the
number of digits in the chosen numbering system
necessary to express the total number of steps of the
transfer characteristic, where a step represents both
a digital input code and the corresponding discrete
analogue output value. The most commonly-used
definition of resolution provided in data sheets is the
numerical resolution expressed in bits.
Least Significant Bit (LSB)
Full-Scale Error
Full-scale error is defined as the deviation of the real
full-scale output voltage from the ideal output voltage
while the DAC register is loaded with the full-scale
code (0xFFFF). Ideally, the output should be AVDD –
1 LSB. The full-scale error is expressed in percent of
full-scale range (%FSR).
Offset Error
The offset error is defined as the difference between
actual output voltage and the ideal output voltage in
the linear region of the transfer function. This
difference is calculated by using a straight line
defined by two codes (code 485 and 64714). Since
the offset error is defined by a straight line, it can
have a negative or positive value. Offset error is
measured in mV.
Zero-Code Error
The zero-code error is defined as the DAC output
voltage, when all '0's are loaded into the DAC
register. Zero-scale error is a measure of the
difference between actual output voltage and ideal
output voltage (0V). It is expressed in mV. It is
primarily caused by offsets in the output amplifier.
The least significant bit (LSB) is defined as the
smallest value in a binary coded system. The value of
the LSB can be calculated by dividing the full-scale
output voltage by 2n, where n is the resolution of the
converter.
Gain Error
Most Significant Bit (MSB)
Full-Scale Error Drift
The most significant bit (MSB) is defined as the
largest value in a binary coded system. The value of
the MSB can be calculated by dividing the full-scale
output voltage by 2. Its value is one-half of full-scale.
Full-scale error drift is defined as the change in
full-scale error with a change in temperature.
Full-scale error drift is expressed in units of
%FSR/°C.
Relative Accuracy or Integral Nonlinearity (INL)
Offset Error Drift
Relative accuracy or integral nonlinearity (INL) is
defined as the maximum deviation between the real
transfer function and a straight line passing through
the endpoints of the ideal DAC transfer function. DNL
is measured in LSBs.
Offset error drift is defined as the change in offset
error with a change in temperature. Offset error drift
is expressed in µV/°C.
Differential Nonlinearity (DNL)
Zero-code error drift is defined as the change in
zero-code error with a change in temperature.
Zero-code error drift is expressed in µV/°C.
Differential nonlinearity (DNL) is defined as the
maximum deviation of the real LSB step from the
ideal 1LSB step. Ideally, any two adjacent digital
codes correspond to output analog voltages that are
exactly one LSB apart. If the DNL is less than 1LSB,
the DAC is said to be monotonic.
50
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Gain error is defined as the deviation in the slope of
the real DAC transfer characteristic from the ideal
transfer function. Gain error is expressed as a
percentage of full-scale range (%FSR).
Zero-Code Error Drift
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC7568 DAC8168 DAC8568
DAC7568
DAC8168
DAC8568
www.ti.com ..................................................................................................................................................... SBAS430A – JANUARY 2009 – REVISED APRIL 2009
Gain Temperature Coefficient
Digital Feedthrough
The gain temperature coefficient is defined as the
change in gain error with changes in temperature.
The gain temperature coefficient is expressed in ppm
of FSR/°C.
Digital feedthrough is defined as impulse seen at the
output of the DAC from the digital inputs of the DAC.
It is measured when the DAC output is not updated. It
is specified in nV-s, and measured with a full-scale
code change on the data bus; that is, from all '0's to
all '1's and vice versa.
Power-Supply Rejection Ratio (PSRR)
Power-supply rejection ratio (PSRR) is defined as the
ratio of change in output voltage to a change in
supply voltage for a full-scale output of the DAC. The
PSRR of a device indicates how the output of the
DAC is affected by changes in the supply voltage.
PSRR is measured in decibels (dB).
Monotonicity
Monotonicity is defined as a slope whose sign does
not change. If a DAC is monotonic, the output
changes in the same direction or remains at least
constant for each step increase (or decrease) in the
input code.
Channel-to-Channel DC Crosstalk
Channel-to-channel dc crosstalk is defined as the dc
change in the output level of one DAC channel in
response to a change in the output of another DAC
channel. It is measured with a full-scale output
change on one DAC channel while monitoring
another DAC channel remains at midscale. It is
expressed in LSB.
Channel-to-Channel AC Crosstalk
Dynamic performance parameters are specifications
such as settling time or slew rate, which are important
in applications where the signal rapidly changes
and/or high frequency signals are present.
AC crosstalk in a multi-channel DAC is defined as the
amount of ac interference experienced on the output
of a channel at a frequency (f) (and its harmonics),
when the output of an adjacent channel changes its
value at the rate of frequency (f). It is measured with
one channel output oscillating with a sine wave of
1kHz frequency, while monitoring the amplitude of
1kHz harmonics on an adjacent DAC channel output
(kept at zero scale). It is expressed in dB.
Slew Rate
Signal-to-Noise Ratio (SNR)
The output slew rate (SR) of an amplifier or other
electronic circuit is defined as the maximum rate of
change of the output voltage for all possible input
signals.
Signal-to-noise ratio (SNR) is defined as the ratio of
the root mean-squared (RMS) value of the output
signal divided by the RMS values of the sum of all
other spectral components below one-half the output
frequency, not including harmonics or dc. SNR is
measured in dB.
DYNAMIC PERFORMANCE
SR = max
DVOUT(t)
Dt
Where ΔVOUT(t) is the output produced by the
amplifier as a function of time t.
Output Voltage Settling Time
Settling time is the total time (including slew time) for
the DAC output to settle within an error band around
its final value after a change in input. Settling times
are specified to within ±0.003% (or whatever value is
specified) of full-scale range (FSR).
Code Change/Digital-to-Analog Glitch Energy
Digital-to-analog glitch impulse is the impulse injected
into the analog output when the input code in the
DAC register changes state. It is normally specified
as the area of the glitch in nanovolt-seconds (nV-s),
and is measured when the digital input code is
changed by 1LSB at the major carry transition.
Total Harmonic Distortion (THD)
Total harmonic distortion + noise is defined as the
ratio of the RMS values of the harmonics and noise
to the value of the fundamental frequency. It is
expressed in a percentage of the fundamental
frequency amplitude at sampling rate fS.
Spurious-Free Dynamic Range (SFDR)
Spurious-free dynamic range (SFDR) is the usable
dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is
the measure of the difference in amplitude between
the fundamental and the largest harmonically or
non-harmonically related spur from dc to the full
Nyquist bandwidth (half the DAC sampling rate, or
fS/2). A spur is any frequency bin on a spectrum
analyzer, or from a Fourier transform, of the analog
output of the DAC. SFDR is specified in decibels
relative to the carrier (dBc).
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC7568 DAC8168 DAC8568
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DAC8168
DAC8568
SBAS430A – JANUARY 2009 – REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com
Signal-to-Noise plus Distortion (SINAD)
DAC Output Noise
SINAD includes all the harmonic and outstanding
spurious components in the definition of output noise
power in addition to quantizing any internal random
noise power. SINAD is expressed in dB at a specified
input frequency and sampling rate, fS.
DAC output noise is defined as any voltage deviation
of DAC output from the desired value (within a
particular frequency band). It is measured with a DAC
channel kept at midscale while filtering the output
voltage within a band of 0.1Hz to 10Hz and
measuring its amplitude peaks. It is expressed in
terms of peak-to-peak voltage (Vpp).
DAC Output Noise Density
Output
noise
density
is
defined
as
internally-generated random noise. Random noise is
characterized as a spectral density (nV/√Hz). It is
measured by loading the DAC to midscale and
measuring noise at the output.
52
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Full-Scale Range (FSR)
Full-scale range (FSR) is the difference between the
maximum and minimum analog output values that the
DAC is specified to provide; typically, the maximum
and minimum values are also specified. For an n-bit
DAC, these values are usually given as the values
matching with code 0 and 2n.
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC7568 DAC8168 DAC8568
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DAC7568IAPW
ACTIVE
TSSOP
PW
14
DAC7568IAPWR
ACTIVE
TSSOP
PW
14
DAC7568ICPW
ACTIVE
TSSOP
PW
16
DAC7568ICPWR
ACTIVE
TSSOP
PW
16
DAC8168IAPW
ACTIVE
TSSOP
PW
14
DAC8168IAPWR
ACTIVE
TSSOP
PW
14
DAC8168ICPW
ACTIVE
TSSOP
PW
16
DAC8168ICPWR
ACTIVE
TSSOP
PW
16
DAC8568IAPW
ACTIVE
TSSOP
PW
16
DAC8568IAPWR
ACTIVE
TSSOP
PW
16
DAC8568IBPW
ACTIVE
TSSOP
PW
16
DAC8568IBPWR
ACTIVE
TSSOP
PW
16
DAC8568ICPW
ACTIVE
TSSOP
PW
16
DAC8568ICPWR
ACTIVE
TSSOP
PW
16
DAC8568IDPW
ACTIVE
TSSOP
PW
16
DAC8568IDPWR
ACTIVE
TSSOP
PW
16
90
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
90
90
90
90
90
90
90
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2009
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DAC8168ICPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
DAC8568IAPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
DAC8568IBPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
DAC8568ICPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
DAC8568IDPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC8168ICPWR
TSSOP
PW
16
2000
346.0
346.0
29.0
DAC8568IAPWR
TSSOP
PW
16
2000
346.0
346.0
29.0
DAC8568IBPWR
TSSOP
PW
16
2000
346.0
346.0
29.0
DAC8568ICPWR
TSSOP
PW
16
2000
346.0
346.0
29.0
DAC8568IDPWR
TSSOP
PW
16
2000
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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