H EE GEN FR ALO CAT28LV256 256K-Bit CMOS PARALLEL E2PROM LE A D F R E ETM FEATURES ■ 3.0V to 3.6V Supply ■ CMOS and TTL Compatible I/O ■ Read Access Times: 200/250/300 ns ■ Automatic Page Write Operation: – 1 to 64 Bytes in 10ms – Page Load Timer ■ Low Power CMOS Dissipation: – Active: 15 mA Max. – Standby: 150 µA Max. ■ End of Write Detection: – Toggle Bit – DATA Polling ■ Simple Write Operation: – On-Chip Address and Data Latches – Self-Timed Write Cycle with Auto-Clear ■ Hardware and Software Write Protection ■ 100,000 Program/Erase Cycles ■ Fast Write Cycle Time: – 10ms Max. ■ 100 Year Data Retention ■ Commercial, Industrial and Automotive Temperature Ranges DESCRIPTION The CAT28LV256 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC– approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC packages. The CAT28LV256 is a fast, low power, low voltage CMOS Parallel E2PROM organized as 32K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the self-timed write cycle. Additionally, the CAT28LV256 features hardware and software write protection. BLOCK DIAGRAM A6–A14 ADDR. BUFFER & LATCHES ROW DECODER VCC INADVERTENT WRITE PROTECTION HIGH VOLTAGE GENERATOR CE OE WE CONTROL LOGIC 64 BYTE PAGE REGISTER I/O BUFFERS TIMER A0–A5 32,768 x 8 E2PROM ARRAY DATA POLLING AND TOGGLE BIT ADDR. BUFFER & LATCHES I/O0–I/O7 COLUMN DECODER 28LV256 F01 © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1071, Rev. B CAT28LV256 PIN CONFIGURATION PLCC Package (N, G) 1 28 2 3 27 26 VCC WE A13 A6 A5 4 5 25 24 A8 A9 A4 A3 A2 6 7 23 A11 OE I/O1 I/O2 VSS 10 11 12 13 14 19 18 17 16 15 A10 CE I/O7 I/O6 5 29 6 7 28 27 A3 A2 A1 8 9 26 25 A0 NC I/O0 I/O5 I/O4 I/O3 TOP VIEW 10 11 24 23 12 22 13 21 14 15 16 17 18 19 20 I/O1 I/O2 VSS NC A1 A0 I/O0 8 9 22 21 20 4 3 2 1 32 31 30 A6 A5 A4 A8 A9 A11 NC OE A10 CE I/O7 I/O6 I/O3 I/O4 I/O5 A14 A12 A7 A7 A12 A14 NC VCC WE A13 DIP Package (P, L) TSOP Top View (8mm X 13.4mm) (T13, H13) OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIN FUNCTIONS Pin Name Function Pin Name Function A0–A14 Address Inputs WE Write Enable I/O0–I/O7 Data Inputs/Outputs VCC 3.0 to 3.6 V Supply CE Chip Enable VSS Ground OE Output Enable NC No Connect Doc. No. 1071, Rev. B 2 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 CAT28LV256 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(2) ........... –2.0V to +VCC + 2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(3) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol Units Test Method 100,000 Cycles/Byte MIL-STD-883, Test Method 1033 Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH(1)(4) Latch-Up 100 mA NEND (1) TDR(1) (1) Parameter Min. Endurance Max. JEDEC Standard 17 CAPACITANCE TA = 25°C, f = 1.0 MHz Symbol Test Max. Units Conditions CI/O(1) Input/Output Capacitance 10 pF VI/O = 0V CIN(1) Input Capacitance 6 pF VIN = 0V CE WE OE Read L H Byte Write (WE Controlled) L MODE SELECTION Mode Byte Write (CE Controlled) I/O Power L DOUT ACTIVE H DIN ACTIVE L H DIN ACTIVE Standby, and Write Inhibit H X X High-Z STANDBY Read and Write Inhibit X H H High-Z ACTIVE Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V. 3 Doc. No. 1071, Rev. B CAT28LV256 D.C. OPERATING CHARACTERISTICS VCC = 3.0V to 3.6V, unless otherwise specified Limits Symbol Parameter ICC Min. Typ. Max. Units VCC Current (Operating, TTL) 15 mA CE = OE = VIL, f = 1/tRC min, All I/O’s Open ISBC(2) VCC Current (Standby, CMOS) 150 µA CE = VIHC, All I/O’s Open ILI Input Leakage Current –1 1 µA VIN = GND to VCC ILO Output Leakage Current –5 5 µA VOUT = GND to VCC, CE = VIH VIH(2) High Level Input Voltage 2 VCC +0.3 V VIL Low Level Input Voltage –0.3 0.6 V VOH High Level Output Voltage VOL Low Level Output Voltage VWI Write Inhibit Voltage 2 0.3 2 Test Conditions V IOH = –100µA V IOL = 1.0mA V A.C. CHARACTERISTICS, Read Cycle VCC = 3.0V to 3.6V, unless otherwise specified Symbol Parameter 28LV256-20 28LV256-25 Min. Min. Max. 200 Max. Min. Max. Units tRC Read Cycle Time tCE CE Access Time 200 250 300 ns tAA Address Access Time 200 250 300 ns tOE OE Access Time 80 100 110 ns tLZ(1) CE Low to Active Output 0 0 0 ns tOLZ(1) OE Low to Active Output 0 0 0 ns tHZ(1)(3) CE High to High-Z Output 50 55 60 ns tOHZ(1)(3) OE High to High-Z Output 50 55 60 ns tOH(1) Output Hold from Address Change 0 250 28LV256-30 0 300 0 Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) VIHC = VCC –0.3V to VCC +0.3V. (3) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer. Doc. No. 1071, Rev. B 4 ns ns CAT28LV256 Figure 1. A.C. Testing Input/Output Waveform(2) VCC - 0.3V 2.0 V INPUT PULSE LEVELS REFERENCE POINTS 0.6 V 0.0 V 28LV256 F04 Figure 2. A.C. Testing Load Circuit (example) Vcc 1.8K DEVICE UNDER TEST OUTPUT 1.3K CL = 100 pF CL INCLUDES JIG CAPACITANCE 28LV256 F05 A.C. CHARACTERISTICS, Write Cycle VCC = 3.0V to 3.6V, unless otherwise specified 28LV256-20 28LV256-25 28LV256-30 Min. Min. Min. Symbol Parameter Max. tWC Write Cycle Time tAS Address Setup Time 0 0 0 ns tAH Address Hold Time 100 100 100 ns tCS CE Setup Time 0 0 0 ns tCH CE Hold Time 0 0 0 ns tCW(3) CE Pulse Time 150 150 150 ns tOES OE Setup Time 0 0 0 ns tOEH OE Hold Time 0 0 0 ns tWP(3) WE Pulse Width 150 150 150 ns tDS Data Setup Time 50 50 50 ns tDH Data Hold Time 0 0 0 ns tINIT(1) Write Inhibit Period After Power-up 5 10 5 10 5 10 ms tBLC(1)(4) Byte Load Cycle Time 0.15 100 0.15 100 0.15 100 µs 10 Max. 10 Max. Units 10 ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Input rise and fall times (10% and 90%) < 10 ns. (3) A write pulse of less than 20ns duration will not initiate a write cycle. (4) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within tBLC max. stops the timer. 5 Doc. No. 1071, Rev. B CAT28LV256 Byte Write DEVICE OPERATION A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 10 ms. Read Data stored in the CAT28LV256 is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architecture can be used to eliminate bus contention in a system environment. Figure 3. Read Cycle tRC ADDRESS tCE CE tOE OE VIH tLZ WE tOHZ HIGH-Z DATA OUT tHZ tOH tOLZ DATA VALID DATA VALID tAA 28LV256 F06 WE Controlled] Figure 4. Byte Write Cycle [WE tWC ADDRESS tAS tAH tCH tCS CE OE tOES tWP tOEH WE tBLC DATA OUT DATA IN HIGH-Z DATA VALID tDS tDH 28LV256 F07 Doc. No. 1071, Rev. B 6 CAT28LV256 Page Write (which can be loaded in any order) during the first and subsequent write cycles. Each successive byte load cycle must begin within tBLC MAX of the rising edge of the preceding WE pulse. There is no page write window limitation as long as WE is pulsed low within tBLC MAX. The page write mode of the CAT28LV256 (essentially an extended BYTE WRITE mode) allows from 1 to 64 bytes of data to be programmed within a single E2PROM write cycle. This effectively reduces the byte-write time by a factor of 64. Upon completion of the page write sequence, WE must stay high a minimum of tBLC MAX for the internal automatic program cycle to commence. This programming cycle consists of an erase cycle, which erases any data that existed in each addressed cell, and a write cycle, which writes new data back into the cell. A page write will only write data to the locations that were addressed and will not rewrite the entire page. Following an initial WRITE operation (WE pulsed low, for tWP, and then high) the page write mode can begin by issuing sequential WE pulses, which load the address and data bytes into a 64 byte temporary buffer. The page address where data is to be written, specified by bits A6 to A14, is latched on the last falling edge of WE. Each byte within the page is defined by address bits A0 to A5 CE Controlled] Figure 5. Byte Write Cycle [CE tWC ADDRESS tAS tAH tBLC tCW CE tOEH OE tCS tOES tCH WE HIGH-Z DATA OUT DATA IN DATA VALID tDS tDH 28LV256 F08 Figure 6. Page Mode Write Cycle OE CE t WP t BLC WE ADDRESS t WC I/O LAST BYTE BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2 28LV256 F09 7 Doc. No. 1071, Rev. B CAT28LV256 DATA Polling Toggle Bit DATA polling is provided to indicate the completion of write cycle. Once a byte write or page write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O7 (I/O0–I/O6 are indeterminate) until the programming cycle is complete. Upon completion of the self-timed write cycle, all I/O’s will output true data during a read cycle. In addition to the DATA Polling feature, the device can determine the completion of a write cycle, while a write cycle is in progress, by reading data from the device. This results in I/O6 toggling between one and zero. Once the write is complete, however, I/O6 stops toggling and valid data can be read from the device. Figure 7. DATA Polling ADDRESS CE WE tOEH tOES tOE OE tWC I/O7 DIN = X DOUT = X DOUT = X 28LV256 F10 Figure 8. Toggle Bit WE CE tOEH tOES tOE OE I/O6 (1) (1) tWC 28LV256 F11 Note: (1) Beginning and ending state of I/O6 is indeterminate. Doc. No. 1071, Rev. B 8 CAT28LV256 HARDWARE DATA PROTECTION The following hardware data protection features are incorporated into the CAT28LV256. (4) Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. (1) VCC sense provides write protection when VCC falls below 2.0V min. SOFTWARE DATA PROTECTION The CAT28LV256 features a software controlled data protection scheme which, once enabled, requires a data algorithm to be issued to the device before a write can be performed. The device is shipped from Catalyst with the software protection NOT ENABLED (the CAT28LV256 is in the standard operating mode). (2) A power on delay mechanism, tINIT (see AC characteristics), provides a 5 to 10 ms delay before a write sequence, after VCC has reached 2.4V min. (3) Write inhibit is activated by holding any one of OE low, CE high, or WE high. Figure 9. Write Sequence for Activating Software Data Protection WRITE DATA: ADDRESS: WRITE DATA: ADDRESS: WRITE DATA: ADDRESS: Figure 10. Write Sequence for Deactivating Software Data Protection WRITE DATA: AA ADDRESS: 5555 WRITE DATA: 55 ADDRESS: 2AAA WRITE DATA: A0 ADDRESS: 5555 SOFTWARE DATA (1) PROTECTION ACTIVATED WRITE DATA: WRITE DATA: XX WRITE DATA: TO ANY ADDRESS ADDRESS: WRITE LAST BYTE TO LAST ADDRESS WRITE DATA: ADDRESS: ADDRESS: 28LV256 F12 AA 5555 55 2AAA 80 5555 AA 5555 55 2AAA 20 5555 28LV256 F13 Note: (1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC Max., after SDP activation. 9 Doc. No. 1071, Rev. B CAT28LV256 To activate the software data protection, the device must be sent three write commands to specific addresses with specific data (Figure 9). This sequence of commands (along with subsequent writes) must adhere to the page write timing specifications (Figure 11). Once this is done, all subsequent byte or page writes to the device must be preceded by this same set of write commands. The data protection mechanism is activated until a deactivate sequence is issued, regardless of power on/off transitions. This gives the user added inadvertent write protection on power-up in addition to the hardware protection provided. To allow the user the ability to program the device with an E2PROM programmer (or for testing purposes) there is a software command sequence for deactivating the data protection. The six step algorithm (Figure 10) will reset the internal protection circuitry, and the device will return to standard operating mode (Figure 12 provides reset timing). After the sixth byte of this reset sequence has been issued, standard byte or page writing can commence. Figure 11. Software Data Protection Timing DATA ADDRESS AA 5555 55 2AAA tWC A0 5555 CE tWP tBLC BYTE OR PAGE WRITES ENABLED WE Figure 12. Resetting Software Data Protection Timing DATA ADDRESS AA 5555 55 2AAA 80 5555 AA 5555 55 2AAA 20 5555 tWC SDP RESET CE DEVICE UNPROTECTED WE Doc. No. 1071, Rev. B 10 CAT28LV256 ORDERING INFORMATION Prefix Device # CAT 28LV256 Optional Company ID Product Number Suffix N I Package P: PDIP N: PLCC T13: TSOP (8mmx13.4mm) L: PDIP (Lead free, Halogen free) G: PLCC (Lead free, Halogen free) H13: TSOP (Lead free, Halogen free) -25 T Speed 20: 200ns* 25: 250ns 30: 300ns Tape & Reel T: 500/Reel Temperature Range Blank = Commercial (0˚C to +70˚C) I = Industrial (-40˚C to +85˚C) A = Automotive (-40˚ to +105˚C) E = Extended (-40˚C to +125˚C) * Commercial and industrial temperature range only. Notes: (1) The device used in the above example is a CAT28LV256NI-25T (100,000 Cycle Endurance, PLCC, Industrial temperature, 250 ns Access Time, Tape & Reel). 11 Doc. No. 1071, Rev. B REVISION HISTORY Date Rev. Reason 2/3/2004 A Assigned doc number Updated Ordering Info 2/27/2004 B Added Green Packages Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: Type: 1071 B 2/27/04 Final