TI1 DS30EA101 0.15 to 3.125 gbps adaptive cable equalizer Datasheet

DS30EA101
0.15 to 3.125 Gbps Adaptive Cable Equalizer
General Description
Features
The DS30EA101 is an adaptive cable equalizer optimized for
equalizing data transmitted over copper cables. The equalizer
operates over a range of data rates from 150 Mbps to
3.125 Gbps and automatically adapts to equalize signals sent
over any cable length from zero meters to lengths that attenuate the signal by 50 dB at 1.5 GHz.
The DS30EA101 allows either single-ended or differential input. This enables equalization of signals over coaxial cables
as well as twisted pair cables.
Additional features include an LOS detect and output enable
which, when tied together, disable the output when no input
signal is present.
The DS30EA101 is powered from a single 2.5V supply and
consumes 115 mW (typical). It operates over the full industrial
temperature range of -40°C to +85°C and is available in a
4 x 4 mm 16-pin LLP package.
■
■
■
■
■
Automatic equalization of coaxial and twisted pair cables
Data rates from 150 Mbps to 3.125 Gbps
Supports SD and HD video resolutions
Power consumption: 115 mW typical
Industrial temperature range: -40°C to +85°C
Applications
■ Cable extension
■ Data recovery equalization
■ Security and surveillance
Typical Application
30151901
© 2012 Texas Instruments Incorporated
301519 SNLS404
www.ti.com
DS30EA101 0.15 to 3.125 Gbps Adaptive Cable Equalizer
February 9, 2012
DS30EA101
Connection Diagram
30151903
The exposed die attach pad is a negative electrical terminal for this device. It should be connected to the negative power supply voltage.
16-Pin LLP
Order Number DS30EA101SQ
Package Number SQB16A
Ordering Information
Part Number
Package
Quantity
DS30EA101SQ
16-Pin LLP, 4.0 x 4.0 x 0.8 mm, 0.65 mm pitch
Reel of 1000
DS30EA101SQE
16-Pin LLP, 4.0 x 4.0 x 0.8 mm, 0.65 mm pitch
Reel of 250
DS30EA101SQX
16-Pin LLP, 4.0 x 4.0 x 0.8 mm, 0.65 mm pitch
Reel of 4500
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2
DS30EA101
Pin Descriptions
Pin
Name
I/O, Type
Description
1
VEE
Ground
Negative power supply (ground).
2
IN+
I, Data
Non-inverting input.
3
IN-
I, Data
Inverting input.
4
VEE
Ground
Negative power supply (ground).
5
DNC
N/A
Do not connect – leave open.
6
DNC
N/A
Do not connect – leave open.
7
VEE
Ground
Negative power supply (ground).
8
VEE
Ground
Negative power supply (ground).
9
VEE
Ground
Negative power supply (ground).
10
OUT-
O, LVDS
Inverting output.
11
OUT+
O, LVDS
Non-inverting output.
12
VEE
Ground
Negative power supply (ground).
13
VCC
Power
Positive power supply (+2.5V).
14
EN
I, LVCMOS
Output enable. LOS may be tied to this pin to inhibit the output when no input signal
is present. This pin has an internal pulldown.
H = Outputs disabled.
L = Outputs enabled.
15
LOS
O, LVCMOS
Loss of signal.
H = No input signal detected.
L = Input signal detected.
16
VCC
Power
Positive power supply (+2.5V).
DAP
VEE
Ground
Connect exposed DAP to negative power supply (ground).
3
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DS30EA101
Recommended Operating
Conditions
Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage (all inputs)
Storage Temperature Range
Junction Temperature
Package Thermal Resistance
θJA 16-pin LLP
θJC 16-pin LLP
ESD Rating (HBM)
3.1V
−0.3V to VCC+0.3V
−65°C to +150°C
+125°C
Supply Voltage (VCC)
Input Coupling Capacitance
Operating Free Air Temperature (TA)
2.5V ±5%
1.0 µF
-40°C to +85°C
+40°C/W
+6°C/W
≥±6 kV
≥±300V
≥±2 kV
ESD Rating (MM)
ESD Rating (CDM)
DC Electrical Characteristics
Over recommended supply voltage and operating temperature ranges, unless otherwise specified. (Note 2, Note 3)
Symbol Parameter
Conditions
Reference
Min
Typ
Max
Units
VIN
Input Voltage
0m cable length
IN+, IN-
720
800
880
mVP−P
VSS
Steady State Differential Output
Voltage
100Ω load, Figure 1
OUT+, OUT-
500
700
900
mVP-P
VOD
Differential Output Voltage
250
350
450
mV
ΔVOD
Change in Magnitude of VOD for
Complimentary Output States
50
mV
VOS
Offset Voltage
1.35
V
ΔVOS
Change in Magnitude of VOS for
Complimentary Output States
50
mV
IOS
Output Short Circuit Current
VIH
Input Voltage High Level
VIL
Input Voltage Low Level
VOH
Output Voltage High Level
IOH = -2 mA
VOL
Output Voltage Low Level
IOL = +2 mA
ICC
Supply Current
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1.1
EN
LOS
1.2
30
mA
1.7
VCC
V
VEE
0.7
V
2.0
V
45
4
0.2
V
65
mA
Over recommended supply voltage and operating temperature ranges, unless otherwise specified. (Note 2, Note 3)
Symbol Parameter
DRIN
tJIT
Conditions
Input Data Rate
Total Jitter at BER
10-12
Reference
Min
IN+, IN-
150
Typ
Max
Units
3125
Mbps
(Note 5) 3.125 Gbps,
0-10 meters CAT6
0.35
UI
2.5 Gbps,
0-25 meters CAT6
0.35
UI
1.5 Gbps,
0-50 meters CAT6
0.35
UI
3.125 Gbps,
0-100 meters RG59
0.3
UI
2.5 Gbps,
0-110 meters RG59
0.35
UI
1.5 Gbps,
0-120 meters RG59
0.2
UI
tTLH
Transition Time Low to High
tTHL
Transition Time High to Low
20% - 80%, 100Ω load,
(Note 4), Figure 1
OUT+, OUT-
90
130
ps
90
130
ps
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device my occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: Typical values represent most likely parametric norms at VCC = +2.5V, TA = +25°C, and at the Recommended Operating Conditions at the time of product
characterization and are not guaranteed.
Note 4: Specification is guaranteed by characterization and is not tested in production.
Note 5: The total jitter at BER 10-12 is calculated as DJ + (14 x RJ), where DJ is deterministic jitter and RJ is random jitter. The jitter is expressed as a portion of
the unit interval (UI). The UI is the reciprocal of the data rate.
Timing Diagrams
30151908
FIGURE 1. LVDS Output Voltage, Offset, and Timing Parameters
5
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DS30EA101
AC Electrical Characteristics
DS30EA101
EN can be used to manually disable or enable the OUT+ and
OUT- output signals. Applying a high input to EN will disable
the DS30EA101 outputs by forcing the output to a logic 1, and
applying a low input to EN will force the outputs to be active.
EN has an internal pulldown to enable the outputs by default.
LOS and EN may be tied together to automatically disable the
DS30EA101 outputs when no input signal is present.
Device Operation
The DS30EA101 equalizes data transmitted over copper cables. It automatically adjusts its gain to reverse the effects of
the cable loss and restore the original signal. For proper operation, the launch amplitude of the signal going into the cable
(the signal amplitude prior to the cable attenuation) must be
set appropriately. If the signal is single-ended, its single-ended amplitude must be 800 mVP-P ±10%. If the signal is differential, its differential amplitude must be 800 mVP-P ±10% (400
mVP-P single-ended).
Application Information
CABLE EXTENDER APPLICATION
The DS30EA101 together with the DS30BA101 form a cable
extender chipset optimized for extending serial data streams
from serializer/deseralizer (SerDes) pairs and FPGAs over
100Ω differential cables and 75Ω coaxial cables. Setting the
correct DS30BA101 output amplitude and proper cable termination are essential for optimal operation. Figure 2 shows
the recommended chipset configuration for 100Ω differential
cable and Figure 3 shows the recommended chipset configuration for 75Ω coaxial cable.
INPUT INTERFACING
The DS30EA101 accepts either differential or single-ended
input. The input must be AC coupled. Figure 2 and Figure 3
show the typical configurations for differential input and single-ended input, respectively. For single-ended input, the
unused input must be properly terminated as shown.
OUTPUT INTERFACING
The DS30EA101 output signals (OUT+ and OUT- ) are internally terminated 100Ω LVDS outputs. These outputs can be
DC coupled to most common differential receivers.
LOS AND EN
LOS indicates the loss of signal at the DS30EA101 input. LOS
is high when no input signal is present and low when a valid
input signal is detected.
30151931
FIGURE 2. Cable Extender Chipset Application Circuit for 100Ω Differential Cable
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6
DS30EA101
30151932
FIGURE 3. Cable Extender Chipset Application Circuit for 75Ω Coaxial Cable
7
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DS30EA101
Physical Dimensions inches (millimeters) unless otherwise noted
16-Pin LLP
Order Number DS30EA101SQ
Package Number SQB16A
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8
DS30EA101
Notes
9
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DS30EA101 0.15 to 3.125 Gbps Adaptive Cable Equalizer
Notes
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