Am29PDL127H Data Sheet RETIRED PRODUCT This product has been retired and is not recommended for designs. For new and current designs, S29PL127J supersedes Am29PDL127H and is the factory-recommended migration path. Please refer to the S29PL127J datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. June 2005 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Publication Number 26864 Revision A Amendment +6 Issue Date June 07, 2005 THIS PAGE LEFT INTENTIONALLY BLANK. PRELIMINARY Am29PDL127H 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIOTM Control This product has been retired and is not recommended for designs. For new and current designs, S29PL127J supersedes Am29PDL127H and is the factory-recommended migration path. Please refer to the S29PL127J datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ 128 Mbit Page Mode device — Page size of 8 words: Fast page read access from random locations within the page ■ Single power supply operation — Full Voltage range: 2.7 to 3.6 volt read, erase, and program operations for battery-powered applications ■ Simultaneous Read/Write Operation — Data can be continuously read from one bank while executing erase/program functions in another bank — Zero latency switching from write to read operations ■ FlexBank Architecture — 4 separate banks, with up to two simultaneous operations per device — Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31) — Bank B: 48 Mbit (32 Kw x 96) — 18 mA program/erase current — 1 µA typical standby mode current SOFTWARE FEATURES ■ Software command-set compatible with JEDEC 42.4 standard — Backward compatible with Am29F and Am29LV families ■ CFI (Common Flash Interface) complaint — Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices ■ Erase Suspend / Erase Resume — Suspends an erase operation to allow read or program operations in other sectors of same bank ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences — Bank C: 48 Mbit (32 Kw x 96) HARDWARE FEATURES — Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31) ■ Ready/Busy# pin (RY/BY#) ■ Enhanced VersatileI/OTM (VIO) Control — Output voltage generated and input voltages tolerated on all control inputs and I/Os is determined by the voltage on the VIO pin — VIO options at 1.8 V and 3 V I/O ■ SecSiTM (Secured Silicon) Sector region — Up to 128 words accessible through a command sequence — Up to 64 factory-locked words — Up to 64 customer-lockable words ■ Both top and bottom boot blocks in one device ■ Manufactured on 0.13 µm process technology ■ 20-year data retention at 125°C ■ Minimum 1 million erase cycle guarantee per sector PERFORMANCE CHARACTERISTICS ■ High Performance — Page access times as fast as 20 ns — Random access times as fast as 55 ns ■ Power consumption (typical values at 10 MHz) — 45 mA active read current — Provides a hardware method of detecting program or erase cycle completion ■ Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data ■ WP#/ ACC (Write Protect/Acceleration) input — At VIL, hardware level protection for the first and last two 4K word sectors. — At VIH, allows removal of sector protection — At VHH, provides accelerated programming in a factory setting ■ Persistent Sector Protection — A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector — Sectors can be locked and unlocked in-system at VCC level ■ Password Sector Protection — A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password ■ Package options — 80-ball Fine-pitch BGA — Multi Chip Packages (MCP) This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 26864 Rev: A Amendment/+6 Issue Date: June 07, 2005 P R E L I M I N A R Y DISTINCTIVE CHARACTERISTICS — 18 mA program/erase current — 1 µA typical standby mode current ARCHITECTURAL ADVANTAGES ■ 128 Mbit Page Mode device — Page size of 8 words: Fast page read access from random locations within the page ■ Single power supply operation — Full Voltage range: 2.7 to 3.6 volt read, erase, and program operations for battery-powered applications ■ Software command-set compatible with JEDEC 42.4 standard — Backward compatible with Am29F and Am29LV families ■ CFI (Common Flash Interface) complaint ■ Simultaneous Read/Write Operation — Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices — Data can be continuously read from one bank while executing erase/program functions in another bank — Zero latency switching from write to read operations ■ Erase Suspend / Erase Resume ■ FlexBank Architecture — 4 separate banks, with up to two simultaneous operations per device — Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31) — Bank B: 48 Mbit (32 Kw x 96) — Suspends an erase operation to allow read or program operations in other sectors of same bank ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences — Bank C: 48 Mbit (32 Kw x 96) HARDWARE FEATURES — Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31) ■ Ready/Busy# pin (RY/BY#) ■ Enhanced VersatileI/OTM (VIO) Control — Output voltage generated and input voltages tolerated on all control inputs and I/Os is determined by the voltage on the VIO pin — VIO options at 1.8 V and 3 V I/O — Up to 128 words accessible through a command sequence — Up to 64 factory-locked words — Up to 64 customer-lockable words ■ Both top and bottom boot blocks in one device ■ 20-year data retention at 125°C ■ Minimum 1 million erase cycle guarantee per sector ■ High Performance — Page access times as fast as 20 ns — Random access times as fast as 55 ns ■ Power consumption (typical values at 10 MHz) — 45 mA active read current ■ Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data — At VIL, hardware level protection for the first and last two 4K word sectors. — At VIH, allows removal of sector protection — At VHH, provides accelerated programming in a factory setting ■ Persistent Sector Protection ■ Manufactured on 0.13 µm process technology PERFORMANCE CHARACTERISTICS — Provides a hardware method of detecting program or erase cycle completion ■ WP#/ ACC (Write Protect/Acceleration) input ■ SecSiTM (Secured Silicon) Sector region 2 SOFTWARE FEATURES — A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector — Sectors can be locked and unlocked in-system at VCC level ■ Password Sector Protection — A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password ■ Package options — 80-ball Fine-pitch BGA — Multi Chip Packages (MCP) Am29PDL127H June 07, 2005 P R E L I M I N A R Y GENERAL DESCRIPTION The Am29PDL127H is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8 Mwords. The device is offered in an 80-ball Fine-pitch BGA package, and various multi-chip packages. The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations. The device offers fast page access times of 20 to 30 ns, with corresponding random access times of 55 to 70 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Simultaneous Read/Write Operation with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as follows: Bank Sectors A 16 Mbit (4 Kw x 8 and 32 Kw x 31) B 48 Mbit (32 Kw x 96) C 48 Mbit (32 Kw x 96) D 16 Mbit (4 Kw x 8 and 32 Kw x 31) Page Mode Features The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. Standard Flash Memory Features The device requires a single 3.0 volt power supply (2.7 V to 3.6 V or 2.7 V to 3.3 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Com- June 07, 2005 mands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD’s Flash technology combined years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Am29PDL127H 3 P R E L I M I N A R Y TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Simultaneous Operation Block Diagram . . . . . . . 6 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10 Reset Command ..................................................................... 35 Autoselect Command Sequence ............................................ 35 Enter SecSi™ Sector/Exit SecSi Sector Command Sequence .............................................................. 35 Word Program Command Sequence ...................................... 36 Unlock Bypass Command Sequence ..................................... 36 Table 1. Am29PDL127H Device Bus Operations ...........................10 Chip Erase Command Sequence ........................................... 37 Sector Erase Command Sequence ........................................ 37 Requirements for Reading Array Data ................................... 10 Random Read (Non-Page Read) ........................................... 10 Page Mode Read .................................................................... 10 Table 2. Page Select .......................................................................11 Simultaneous Operation ......................................................... 11 Table 3. Bank Select .......................................................................11 Writing Commands/Command Sequences ............................ 11 Accelerated Program Operation ............................................. 11 Autoselect Functions .............................................................. 11 Automatic Sleep Mode ........................................................... 12 RESET#: Hardware Reset Pin ............................................... 12 Output Disable Mode .............................................................. 12 Table 4. Am29PDL127H Sector Architecture ..................................13 Table 5. SecSiTM Sector Addresses ...............................................20 Table 6. Autoselect Codes (High Voltage Method) ........................21 Table 7. Am29PDL127H Boot Sector/Sector Block Addresses for Protection/Unprotection ...................................................................22 Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 23 Persistent Sector Protection ................................................... 23 Persistent Protection Bit (PPB) ............................................... 23 Persistent Protection Bit Lock (PPB Lock) ............................. 23 Dynamic Protection Bit (DYB) ................................................ 23 Table 8. Sector Protection Schemes ...............................................24 Persistent Sector Protection Mode Locking Bit ...................... 24 Password Protection Mode ..................................................... 24 Password and Password Mode Locking Bit ........................... 25 64-bit Password ...................................................................... 25 Write Protect (WP#) ................................................................ 25 Persistent Protection Bit Lock ................................................. 25 High Voltage Sector Protection .............................................. 26 Figure 1. In-System Sector Protection/ Sector Unprotection Algorithms ...................................................... 27 Temporary Sector Unprotect .................................................. 28 Figure 2. Temporary Sector Unprotect Operation........................... 28 SecSi™ (Secured Silicon) Sector Flash Memory Region ............................................................ 28 Factory-Locked Area (64 words) ............................................ 28 Customer-Lockable Area (64 words) ...................................... 28 Figure 3. SecSi Sector Protection Algorithm................................... 29 SecSi Sector Protection Bits ................................................... 30 Figure 4. SecSi Sector Protect Verify.............................................. 30 Hardware Data Protection ...................................................... 30 Low VCC Write Inhibit ............................................................ 30 Write Pulse “Glitch” Protection ............................................... 30 Logical Inhibit .......................................................................... 30 Power-Up Write Inhibit ............................................................ 30 Common Flash Memory Interface (CFI) . . . . . . . 30 Command Definitions . . . . . . . . . . . . . . . . . . . . . 35 Reading Array Data ................................................................ 35 4 Figure 5. Program Operation ......................................................... 37 Figure 6. Erase Operation.............................................................. 38 Erase Suspend/Erase Resume Commands ........................... 38 Password Program Command ................................................ 38 Password Verify Command .................................................... 39 Password Protection Mode Locking Bit Program Command .. 39 Persistent Sector Protection Mode Locking Bit Program Command ............................................................................... 39 SecSi Sector Protection Bit Program Command .................... 39 PPB Lock Bit Set Command ................................................... 39 DYB Write Command ............................................................. 39 Password Unlock Command .................................................. 40 PPB Program Command ........................................................ 40 All PPB Erase Command ........................................................ 40 DYB Write Command ............................................................. 40 PPB Lock Bit Set Command ................................................... 40 PPB Status Command ............................................................ 40 PPB Lock Bit Status Command .............................................. 40 Sector Protection Status Command ....................................... 40 Table 13. Memory Array Command Definitions ............................. 41 Table 14. Sector Protection Command Definitions ........................ 42 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 43 DQ7: Data# Polling ................................................................. 43 Figure 7. Data# Polling Algorithm .................................................. 43 DQ6: Toggle Bit I .................................................................... 44 Figure 8. Toggle Bit Algorithm........................................................ 44 DQ2: Toggle Bit II ................................................................... 45 Reading Toggle Bits DQ6/DQ2 ............................................... 45 DQ5: Exceeded Timing Limits ................................................ 45 DQ3: Sector Erase Timer ....................................................... 45 Table 15. Write Operation Status ................................................... 46 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 47 Figure 9. Maximum Negative Overshoot Waveform ...................... 47 Figure 10. Maximum Positive Overshoot Waveform...................... 47 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 48 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 11. Test Setup.................................................................... 49 Table 16. Test Specifications ......................................................... 49 Figure 12. Input Waveforms and Measurement Levels ................. 49 AC Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . 50 Read-Only Operations ........................................................... 50 Figure 13. Read Operation Timings ............................................... 51 Figure 14. Page Read Operation Timings...................................... 51 Hardware Reset (RESET#) .................................................... 52 Figure 15. Reset Timings ............................................................... 52 Erase and Program Operations .............................................. 53 Figure 16. Program Operation Timings.......................................... Figure 17. Accelerated Program Timing Diagram.......................... Figure 18. Chip/Sector Erase Operation Timings .......................... Figure 19. Back-to-back Read/Write Cycle Timings ...................... Am29PDL127H 54 54 55 56 June 07, 2005 P R E L I M I N A R Y Figure 20. Data# Polling Timings (During Embedded Algorithms).. 56 Figure 21. Toggle Bit Timings (During Embedded Algorithms)....... 57 Figure 22. DQ2 vs. DQ6.................................................................. 57 Temporary Sector Unprotect .................................................. 58 Figure 23. Temporary Sector Unprotect Timing Diagram ............... 58 Figure 24. Sector/Sector Block Protect and Unprotect Timing Diagram .............................................................. 59 Alternate CE# Controlled Erase and Program Operations ..... 60 Erase And Programming Performance. . . . . . . . 62 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 62 BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . 62 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 VBB080—80-Ball Fine-pitch Ball Grid Array 11.5 x 9 mm package ........................................................................... 63 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 25. Alternate CE# Controlled Write (Erase/Program) Operation Timings........................................................................... 61 June 07, 2005 Am29PDL127H 5 P R E L I M I N A R Y PRODUCT SELECTOR GUIDE Part Number Am29PDL127H VCC,VIO = 2.7–3.6 V Speed Option 53 63 VCC = 2.7–3.6 V, VIO = 1.65–1.95 V 68 Max Access Time, ns (tACC) 55 Max CE# Access, ns (tCE) 60 Max Page Access, ns (tPACC) 20 Max OE# Access, ns (tOE) 65 65 70 25 30 88 85 30 BLOCK DIAGRAM DQ15–DQ0 RY/BY# (See Note) VCC VSS Sector Switches VIO RESET# Input/Output Buffers Erase Voltage Generator WE# State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE# OE# Y-Decoder A22–A3 Y-Gating Timer Address Latch VCC Detector Data Latch X-Decoder Cell Matrix A2–A0 Note:RY/BY# is an open drain output. 6 Am29PDL127H June 07, 2005 P R E L I M I N A R Y SIMULTANEOUS OPERATION BLOCK DIAGRAM VCC VSS OE# Mux Bank A Bank B X-Decoder A22–A0 Status DQ15–DQ0 Control Mux DQ15–DQ0 CE# WP#/ACC STATE CONTROL & COMMAND REGISTER X-Decoder A22–A0 DQ0–DQ15 Bank C Address Bank C X-Decoder A22–A0 Bank D Address Y-gate RESET# WE# DQ15–DQ0 Bank B Address DQ15–DQ0 RY/BY# DQ15–DQ0 A22–A0 X-Decoder Y-gate Bank A Address A22–A0 Bank D Mux June 07, 2005 Am29PDL127H 7 P R E L I M I N A R Y CONNECTION DIAGRAMS 80-Ball Fine-pitch BGA Top View, Balls Facing Down A8 B8 C8 D8 E8 F8 G8 H8 J8 K8 L8 M8 NC NC NC A22 NC VIO VSS NC NC NC NC NC A7 B7 C7 D7 E7 F7 G7 H7 J7 K7 L7 M7 NC NC A13 A12 A14 A15 A16 NC DQ15 VSS NC NC C6 D6 E6 F6 G6 H6 J6 K6 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 C5 D5 E5 F5 G5 H5 J5 K5 WE# RESET# A21 A19 DQ5 DQ12 VCC DQ4 C4 D4 E4 F4 G4 H4 J4 K4 A18 A20 DQ2 DQ10 DQ11 DQ3 RY/BY# WP#/ACC C3 D3 E3 F3 G3 H3 J3 K3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 NC NC A3 A4 A2 A1 A0 CE# OE# VSS NC NC A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 NC NC NC NC NC NC NC VIO NC NC NC NC Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP, BGA, PDIP, SSOP, PLCC). 8 The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am29PDL127H June 07, 2005 P R E L I M I N A R Y PIN DESCRIPTION A22–A0 = LOGIC SYMBOL 23-bit address bus for 128 Mb device. A9 supports 12 V autoselect inputs. A22–A0 16 DQ15–DQ0 DQ15–DQ0 = 16-bit data inputs/outputs/float CE# = Chip Enable Inputs OE# = Output Enable Input WE# = Write Enable VSS = Device Ground NC = Pin Not Connected Internally RY/BY# = Ready/Busy output and open drain. When RY/BY#= VIH, the device is ready to accept read operations and commands. When RY/BY#= VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset operation. CE# OE# WE# WP#/ACC RESET# WP#/ACC = Write Protect/Acceleration Input. When WP/ACC#= VIL, the highest and lowest two 4K-word sectors are write protected regardless of other sector protection configurations. When WP/ACC#= VIH, these sector are unprotected unless the DYB or PPB is programmed. When WP/ACC#= 12V, program and erase operations are accelerated. VIO = Input/Output Buffer Power Supply (1.65 V to 1.95 V or 2.7 V to 3.6 V) VCC = Chip Power Supply (2.7 V to 3.6 V) RESET# = Hardware Reset Pin June 07, 2005 23 Am29PDL127H RY/BY# VIO (VCCQ) 9 P R E L I M I N A R Y ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29PDL127 H 53 VK I OPTIONAL PROCESSING Blank = Standard Processing N = 16-byte ESN devices (Contact an AMD representative for more information) TEMPERATURE RANGE I = Industrial (–40°C to +85°C) PACKAGE TYPE VK = 80-Ball Fine-pitch Ball Grid Array 0.8 mm pitch, 11.5 x 9 mm package (VBB080) SPEED OPTION See Product Selector Guide and Valid Combinations Process Technology H = 0.13 µm DEVICE NUMBER/DESCRIPTION Am29PDL127H 128 Megabit (8 M x 16-Bit) CMOS Flash Memory 3.0 Volt-only Read, Program, and Erase Valid Combinations Valid Combinations for BGA Packages Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Order Number Package Marking Speed (ns) VIO Range Am29PDL127H53 VKI PD127H53V 55 2.7– 3.6 V Am29PDL127H63 VKI PD127H63V 65 2.7– 3.6 V Am29PDL127H68 VKI PD127H68V 65 1.65– 1.95 V Am29PDL127H88 VKI PD127H88V 85 1.65– 1.95 V I Note: For the Am29PDL127H, the last digit of the speed grade specifies the VIO range of the device. Speed grades ending in 3 (e.g., 53, 63) indicate a 3 Volt VIO range. Speed ending in 8 (e.g., 68, 88) indicate a 1.8 Volt VIO range. Contact AMD or Fujitsu for availability of 1.8V VIO range devices. 10 Am29PDL127H June 07, 2005 P R E L I M I N A R Y DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the Table 1. register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Am29PDL127H Device Bus Operations CE# OE# WE# RESET# WP#/ACC Addresses (A22–A0) DQ15– DQ0 Read L L H H X AIN DOUT Write L H L H X AIN DIN VIO± 0.3 V X X VIO ± 0.3 V X (Note 2) X High-Z Output Disable L H H H X X High-Z Reset X X X L X X High-Z Temporary Sector Unprotect (High Voltage) X X X VID X AIN DIN Operation Standby Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 8.5–9.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the High Voltage Sector Protection section. 2. WP#/ACC must be high when writing to sectors 0, 1, 268, or 269. Requirements for Reading Array Data Random Read (Non-Page Read) To read array data from the outputs, the system must drive the OE# and appropriate CE# pins to VIL. CE# is the power control. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (t CE ) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The output enable access time is the delay from the falling edge of the OE# to valid data at the output inputs (assuming the addresses have been stable for at least tACC–tOE time). The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to the AC Characteristics table for timing specifications and to Figure 11 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. June 07, 2005 Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. Address bits A22–A3 select an 8 word page, and address bits A2–A0 select a specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. The random or initial page access is tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted (CE#=VIH), the reassertion of CE# for subsequent ac- Am29PDL127H 11 P R E L I M I N A R Y cess has access time of tACC or tCE. Here again, CE# selects the device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by keeping A22–A3 constant and changing A2–A0 to select the specific word within that page. Table 2. Page Select Word A2 A1 A0 Word 0 0 0 0 Word 1 0 0 1 Word 2 0 1 0 Word 3 0 1 1 Word 4 1 0 0 Word 5 1 0 1 Word 6 1 1 0 Word 7 1 1 1 Simultaneous Operation In addition to the conventional features (read, program, erase-suspend read, and erase-suspend program), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation). The bank can be selected by bank addresses (A22–A20) with zero latency. The simultaneous operation can execute multi-function mode in the same bank. Table 3. Bank Select Bank A22–A20 Bank A 000 Bank B 001, 010, 011 Bank C 100, 101, 110 Bank D 111 An erase operation can erase one sector, multiple sectors, or the entire device. Table 4 indicates the address space that each sector occupies. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” refers to the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin should be raised to VCC when not in use. That is, the WP#/ACC pin should not be left floating or unconnected; inconsistent behavior of the device may result. Autoselect Functions Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The “Word Program Command Sequence” section has details on 12 programming data to the device using both standard and Unlock Bypass command sequences. If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO ± 0.3 V. Am29PDL127H June 07, 2005 P R E L I M I N A R Y (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. I CC3 in the DC Characteristics table represents the CMOS standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 150 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Note that during automatic sleep mode, OE# must be at VIH before the device reduces current to the stated sleep mode specification. ICC5 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all June 07, 2005 read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristic tables for RESET# parameters and to Figure 15 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#) are placed in the highest Impedance state Am29PDL127H 13 P R E L I M I N A R Y Table 4. Bank A Bank 14 Am29PDL127H Sector Architecture Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16) SA0 00000000000 4 000000h–000FFFh SA1 00000000001 4 001000h–001FFFh SA2 00000000010 4 002000h–002FFFh SA3 00000000011 4 003000h–003FFFh SA4 00000000100 4 004000h–004FFFh SA5 00000000101 4 005000h–005FFFh SA6 00000000110 4 006000h–006FFFh SA7 00000000111 4 007000h–007FFFh SA8 00000001XXX 32 008000h–00FFFFh SA9 00000010XXX 32 010000h–017FFFh SA10 00000011XXX 32 018000h–01FFFFh SA11 00000100XXX 32 020000h–027FFFh SA12 00000101XXX 32 028000h–02FFFFh SA13 00000110XXX 32 030000h–037FFFh SA14 00000111XXX 32 038000h–03FFFFh SA15 00001000XXX 32 040000h–047FFFh SA16 00001001XXX 32 048000h–04FFFFh SA17 00001010XXX 32 050000h–057FFFh SA18 00001011XXX 32 058000h–05FFFFh SA19 00001100XXX 32 060000h–067FFFh SA20 00001101XXX 32 068000h–06FFFFh SA21 00001110XXX 32 070000h–077FFFh SA22 00001111XXX 32 078000h–07FFFFh SA23 00010000XXX 32 080000h–087FFFh SA24 00010001XXX 32 088000h–08FFFFh SA25 00010010XXX 32 090000h–097FFFh SA26 00010011XXX 32 098000h–09FFFFh SA27 00010100XXX 32 0A0000h–0A7FFFh SA28 00010101XXX 32 0A8000h–0AFFFFh SA29 00010110XXX 32 0B0000h–0B7FFFh SA30 00010111XXX 32 0B8000h–0BFFFFh SA31 00011000XXX 32 0C0000h–0C7FFFh SA32 00011001XXX 32 0C8000h–0CFFFFh SA33 00011010XXX 32 0D0000h–0D7FFFh SA34 00011011XXX 32 0D8000h–0DFFFFh SA35 00011100XXX 32 0E0000h–0E7FFFh SA36 00011101XXX 32 0E8000h–0EFFFFh SA37 00011110XXX 32 0F0000h–0F7FFFh SA38 00011111XXX 32 0F8000h–0FFFFFh Am29PDL127H June 07, 2005 P R E L I M I N A R Y Table 4. Bank B Bank June 07, 2005 Am29PDL127H Sector Architecture Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16) SA39 00100000XXX 32 100000h–107FFFh SA40 00100001XXX 32 108000h–10FFFFh SA41 00100010XXX 32 110000h–117FFFh SA42 00100011XXX 32 118000h–11FFFFh SA43 00100100XXX 32 120000h–127FFFh SA44 00100101XXX 32 128000h–12FFFFh SA45 00100110XXX 32 130000h–137FFFh SA46 00100111XXX 32 138000h–13FFFFh SA47 00101000XXX 32 140000h–147FFFh SA48 00101001XXX 32 148000h–14FFFFh SA49 00101010XXX 32 150000h–157FFFh SA50 00101011XXX 32 158000h–15FFFFh SA51 00101100XXX 32 160000h–167FFFh SA52 00101101XXX 32 168000h–16FFFFh SA53 00101110XXX 32 170000h–177FFFh SA54 00101111XXX 32 178000h–17FFFFh SA55 00110000XXX 32 180000h–187FFFh SA56 00110001XXX 32 188000h–18FFFFh SA57 00110010XXX 32 190000h–197FFFh SA58 00110011XXX 32 198000h–19FFFFh SA59 00110100XXX 32 1A0000h–1A7FFFh SA60 00110101XXX 32 1A8000h–1AFFFFh SA61 00110110XXX 32 1B0000h–1B7FFFh SA62 00110111XXX 32 1B8000h–1BFFFFh SA63 00111000XXX 32 1C0000h–1C7FFFh SA64 00111001XXX 32 1C8000h–1CFFFFh SA65 00111010XXX 32 1D0000h–1D7FFFh SA66 00111011XXX 32 1D8000h–1DFFFFh SA67 00111100XXX 32 1E0000h–1E7FFFh SA68 00111101XXX 32 1E8000h–1EFFFFh SA69 00111110XXX 32 1F0000h–1F7FFFh SA70 00111111XXX 32 1F8000h–1FFFFFh SA71 01000000XXX 32 200000h–207FFFh SA72 01000001XXX 32 208000h–20FFFFh SA73 01000010XXX 32 210000h–217FFFh SA74 01000011XXX 32 218000h–21FFFFh SA75 01000100XXX 32 220000h–227FFFh SA76 01000101XXX 32 228000h–22FFFFh SA77 01000110XXX 32 230000h–237FFFh SA78 01000111XXX 32 238000h–23FFFFh Am29PDL127H 15 P R E L I M I N A R Y Table 4. Bank B Bank 16 Am29PDL127H Sector Architecture Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16) SA79 01001000XXX 32 240000h–247FFFh SA80 01001001XXX 32 248000h–24FFFFh SA81 01001010XXX 32 250000h–257FFFh SA82 01001011XXX 32 258000h–25FFFFh SA83 01001100XXX 32 260000h–267FFFh SA84 01001101XXX 32 268000h–26FFFFh SA85 01001110XXX 32 270000h–277FFFh SA86 01001111XXX 32 278000h–27FFFFh SA87 01010000XXX 32 280000h–287FFFh SA88 01010001XXX 32 288000h–28FFFFh SA89 01010010XXX 32 290000h–297FFFh SA90 01010011XXX 32 298000h–29FFFFh SA91 01010100XXX 32 2A0000h–2A7FFFh SA92 01010101XXX 32 2A8000h–2AFFFFh SA93 01010110XXX 32 2B0000h–2B7FFFh SA94 01010111XXX 32 2B8000h–2BFFFFh SA95 01011000XXX 32 2C0000h–2C7FFFh SA96 01011001XXX 32 2C8000h–2CFFFFh SA97 01011010XXX 32 2D0000h–2D7FFFh SA98 01011011XXX 32 2D8000h–2DFFFFh SA99 01011100XXX 32 2E0000h–2E7FFFh SA100 01011101XXX 32 2E8000h–2EFFFFh SA101 01011110XXX 32 2F0000h–2F7FFFh SA102 01011111XXX 32 2F8000h–2FFFFFh SA103 01100000XXX 32 300000h–307FFFh SA104 01100001XXX 32 308000h–30FFFFh SA105 01100010XXX 32 310000h–317FFFh SA106 01100011XXX 32 318000h–31FFFFh SA107 01100100XXX 32 320000h–327FFFh SA108 01100101XXX 32 328000h–32FFFFh SA109 01100110XXX 32 330000h–337FFFh SA110 01100111XXX 32 338000h–33FFFFh SA111 01101000XXX 32 340000h–347FFFh SA112 01101001XXX 32 348000h–34FFFFh SA113 01101010XXX 32 350000h–357FFFh SA114 01101011XXX 32 358000h–35FFFFh SA115 01101100XXX 32 360000h–367FFFh SA116 01101101XXX 32 368000h–36FFFFh SA117 01101110XXX 32 370000h–377FFFh SA118 01101111XXX 32 378000h–37FFFFh Am29PDL127H June 07, 2005 P R E L I M I N A R Y Table 4. Bank C Bank B Bank June 07, 2005 Am29PDL127H Sector Architecture Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16) SA119 01110000XXX 32 380000h–387FFFh SA120 01110001XXX 32 388000h–38FFFFh SA121 01110010XXX 32 390000h–397FFFh SA122 01110011XXX 32 398000h–39FFFFh SA123 01110100XXX 32 3A0000h–3A7FFFh SA124 01110101XXX 32 3A8000h–3AFFFFh SA125 01110110XXX 32 3B0000h–3B7FFFh SA126 01110111XXX 32 3B8000h–3BFFFFh SA127 01111000XXX 32 3C0000h–3C7FFFh SA128 01111001XXX 32 3C8000h–3CFFFFh SA129 01111010XXX 32 3D0000h–3D7FFFh SA130 01111011XXX 32 3D8000h–3DFFFFh SA131 01111100XXX 32 3E0000h–3E7FFFh SA132 01111101XXX 32 3E8000h–3EFFFFh SA133 01111110XXX 32 3F0000h–3F7FFFh SA134 01111111XXX 32 3F8000h–3FFFFFh SA135 10000000XXX 32 400000h–407FFFh SA136 10000001XXX 32 408000h–40FFFFh SA137 10000010XXX 32 410000h–417FFFh SA138 10000011XXX 32 418000h–41FFFFh SA139 10000100XXX 32 420000h–427FFFh SA140 10000101XXX 32 428000h–42FFFFh SA141 10000110XXX 32 430000h–437FFFh SA142 10000111XXX 32 438000h–43FFFFh SA143 10001000XXX 32 440000h–447FFFh SA144 10001001XXX 32 448000h–44FFFFh SA145 10001010XXX 32 450000h–457FFFh SA146 10001011XXX 32 458000h–45FFFFh SA147 10001100XXX 32 460000h–467FFFh SA148 10001101XXX 32 468000h–46FFFFh SA149 10001110XXX 32 470000h–477FFFh SA150 10001111XXX 32 478000h–47FFFFh SA151 10010000XXX 32 480000h–487FFFh SA152 10010001XXX 32 488000h–48FFFFh SA153 10010010XXX 32 490000h–497FFFh SA154 10010011XXX 32 498000h–49FFFFh SA155 10010100XXX 32 4A0000h–4A7FFFh SA156 10010101XXX 32 4A8000h–4AFFFFh SA157 10010110XXX 32 4B0000h–4B7FFFh SA158 10010111XXX 32 4B8000h–4BFFFFh Am29PDL127H 17 P R E L I M I N A R Y Table 4. Bank C Bank 18 Am29PDL127H Sector Architecture Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16) SA159 10011000XXX 32 4C0000h–4C7FFFh SA160 10011001XXX 32 4C8000h–4CFFFFh SA161 10011010XXX 32 4D0000h–4D7FFFh SA162 10011011XXX 32 4D8000h–4DFFFFh SA163 10011100XXX 32 4E0000h–4E7FFFh SA164 10011101XXX 32 4E8000h–4EFFFFh SA165 10011110XXX 32 4F0000h–4F7FFFh SA166 10011111XXX 32 4F8000h–4FFFFFh SA167 10100000XXX 32 500000h–507FFFh SA168 10100001XXX 32 508000h–50FFFFh SA169 10100010XXX 32 510000h–517FFFh SA170 10100011XXX 32 518000h–51FFFFh SA171 10100100XXX 32 520000h–527FFFh SA172 10100101XXX 32 528000h–52FFFFh SA173 10100110XXX 32 530000h–537FFFh SA174 10100111XXX 32 538000h–53FFFFh SA175 10101000XXX 32 540000h–547FFFh SA176 10101001XXX 32 548000h–54FFFFh SA177 10101010XXX 32 550000h–557FFFh SA178 10101011XXX 32 558000h–15FFFFh SA179 10101100XXX 32 560000h–567FFFh SA180 10101101XXX 32 568000h–56FFFFh SA181 10101110XXX 32 570000h–577FFFh SA182 10101111XXX 32 578000h–57FFFFh SA183 10110000XXX 32 580000h–587FFFh SA184 10110001XXX 32 588000h–58FFFFh SA185 10110010XXX 32 590000h–597FFFh SA186 10110011XXX 32 598000h–59FFFFh SA187 10110100XXX 32 5A0000h–5A7FFFh SA188 10110101XXX 32 5A8000h–5AFFFFh SA189 10110110XXX 32 5B0000h–5B7FFFh SA190 10110111XXX 32 5B8000h–5BFFFFh SA191 10111000XXX 32 5C0000h–5C7FFFh SA192 10111001XXX 32 5C8000h–5CFFFFh SA193 10111010XXX 32 5D0000h–5D7FFFh SA194 10111011XXX 32 5D8000h–5DFFFFh SA195 10111100XXX 32 5E0000h–5E7FFFh SA196 10111101XXX 32 5E8000h–5EFFFFh SA197 10111110XXX 32 5F0000h–5F7FFFh SA198 10111111XXX 32 5F8000h–5FFFFFh Am29PDL127H June 07, 2005 P R E L I M I N A R Y Table 4. Bank C Bank June 07, 2005 Am29PDL127H Sector Architecture Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16) SA199 11000000XXX 32 600000h–607FFFh SA200 11000001XXX 32 608000h–60FFFFh SA201 11000010XXX 32 610000h–617FFFh SA202 11000011XXX 32 618000h–61FFFFh SA203 11000100XXX 32 620000h–627FFFh SA204 11000101XXX 32 628000h–62FFFFh SA205 11000110XXX 32 630000h–637FFFh SA206 11000111XXX 32 638000h–63FFFFh SA207 11001000XXX 32 640000h–647FFFh SA208 11001001XXX 32 648000h–64FFFFh SA209 11001010XXX 32 650000h–657FFFh SA210 11001011XXX 32 658000h–65FFFFh SA211 11001100XXX 32 660000h–667FFFh SA212 11001101XXX 32 668000h–66FFFFh SA213 11001110XXX 32 670000h–677FFFh SA214 11001111XXX 32 678000h–67FFFFh SA215 11010000XXX 32 680000h–687FFFh SA216 11010001XXX 32 688000h–68FFFFh SA217 11010010XXX 32 690000h–697FFFh SA218 11010011XXX 32 698000h–69FFFFh SA219 11010100XXX 32 6A0000h–6A7FFFh SA220 11010101XXX 32 6A8000h–6AFFFFh SA221 11010110XXX 32 6B0000h–6B7FFFh SA222 11010111XXX 32 6B8000h–6BFFFFh SA223 11011000XXX 32 6C0000h–6C7FFFh SA224 11011001XXX 32 6C8000h–6CFFFFh SA225 11011010XXX 32 6D0000h–6D7FFFh SA226 11011011XXX 32 6D8000h–6DFFFFh SA227 11011100XXX 32 6E0000h–6E7FFFh SA228 11011101XXX 32 6E8000h–6EFFFFh SA229 11011110XXX 32 6F0000h–6F7FFFh SA230 11011111XXX 32 6F8000h–6FFFFFh Am29PDL127H 19 P R E L I M I N A R Y Table 4. Bank D Bank 20 Am29PDL127H Sector Architecture Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16) SA231 11100000XXX 32 700000h–707FFFh SA232 11100001XXX 32 708000h–70FFFFh SA233 11100010XXX 32 710000h–717FFFh SA234 11100011XXX 32 718000h–71FFFFh SA235 11100100XXX 32 720000h–727FFFh SA236 11100101XXX 32 728000h–72FFFFh SA237 11100110XXX 32 730000h–737FFFh SA238 11100111XXX 32 738000h–73FFFFh SA239 11101000XXX 32 740000h–747FFFh SA240 11101001XXX 32 748000h–74FFFFh SA241 11101010XXX 32 750000h–757FFFh SA242 11101011XXX 32 758000h–75FFFFh SA243 11101100XXX 32 760000h–767FFFh SA244 11101101XXX 32 768000h–76FFFFh SA245 11101110XXX 32 770000h–777FFFh SA246 11101111XXX 32 778000h–77FFFFh SA247 11110000XXX 32 780000h–787FFFh SA248 11110001XXX 32 788000h–78FFFFh SA249 11110010XXX 32 790000h–797FFFh SA250 11110011XXX 32 798000h–79FFFFh SA251 11110100XXX 32 7A0000h–7A7FFFh SA252 11110101XXX 32 7A8000h–7AFFFFh SA253 11110110XXX 32 7B0000h–7B7FFFh SA254 11110111XXX 32 7B8000h–7BFFFFh SA255 11111000XXX 32 7C0000h–7C7FFFh SA256 11111001XXX 32 7C8000h–7CFFFFh SA257 11111010XXX 32 7D0000h–7D7FFFh SA258 11111011XXX 32 7D8000h–7DFFFFh SA259 11111100XXX 32 7E0000h–7E7FFFh SA260 11111101XXX 32 7E8000h–7EFFFFh SA261 11111110XXX 32 7F0000h–7F7FFFh SA262 11111111000 4 7F8000h–7F8FFFh SA263 11111111001 4 7F9000h–7F9FFFh SA264 11111111010 4 7FA000h–7FAFFFh SA265 11111111011 4 7FB000h–7FBFFFh SA266 11111111100 4 7FC000h–7FCFFFh SA267 11111111101 4 7FD000h–7FDFFFh SA268 11111111110 4 7FE000h–7FEFFFh SA269 11111111111 4 7FF000h–7FFFFFh Am29PDL127H June 07, 2005 P R E L I M I N A R Y Table 5. SecSiTM Sector Addresses Am29PDL127H Sector Size Address Range 128 words 000000h–00007Fh Factory-Locked Area 64 words 000000h-00003Fh Customer-Lockable Area 64 words 000040h-00007Fh Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programm ing algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins must be as shown in Table 6. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see June 07, 2005 Table 4). Table 6 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0. However, the autoselect codes can also be accessed in-system through the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 13. Note that if a Bank Address (BA) on address bits A22–A20 is asserted during the third write cycle of the autoselect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 13. This method does not require V ID. Refer to the Autoselect Command Sequence section for more information. Am29PDL127H 21 P R E L I M I N A R Y Table 6. Autoselect Codes (High Voltage Method) CE# OE# WE# A22 to A12 A10 A9 A8 A7 A6 A5 to A4 A3 A2 A1 A0 DQ15 to DQ0 Manufacturer ID: AMD L L H X X VID X L L X L L L L 0001h Read Cycle 1 L L L L H 227Eh Read Cycle 2 L H H H L 2220 Read Cycle 3 L H H H H 2200h Sector Protection Verification L L H SA X VID X L L L L L H L 0001h (protected), 0000h (unprotected) SecSi Indicator Bit (DQ7, DQ6) L L H X X VID X X L X L L H H 00C0h (factory and customer locked), 0080h (factory locked) Device ID Description L H X X VID X L L L Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care. Note: The autoselect codes may also be accessed in-system via command sequences 22 Am29PDL127H June 07, 2005 P R E L I M I N A R Y Table 7. Am29PDL127H Boot Sector/Sector Block Addresses for Protection/Unprotection Sector A22-A12 Sector/ Sector Block Size SA131-SA134 011111XXXXX 128 (4x32) Kwords SA135-SA138 100000XXXXX 128 (4x32) Kwords Sector A22-A12 Sector/ Sector Block Size SA0 00000000000 4 Kwords SA139-SA142 100001XXXXX 128 (4x32) Kwords SA1 00000000001 4 Kwords SA143-SA146 100010XXXXX 128 (4x32) Kwords SA2 00000000010 4 Kwords SA147-SA150 100011XXXXX 128 (4x32) Kwords SA3 00000000011 4 Kwords SA151-SA154 100100XXXXX 128 (4x32) Kwords SA4 00000000100 4 Kwords SA155-SA158 100101XXXXX 128 (4x32) Kwords SA5 00000000101 4 Kwords SA159-SA162 100110XXXXX 128 (4x32) Kwords SA6 00000000110 4 Kwords SA163-SA166 100111XXXXX 128 (4x32) Kwords SA167-SA170 101000XXXXX 128 (4x32) Kwords SA171-SA174 101001XXXXX 128 (4x32) Kwords SA175-SA178 101010XXXXX 128 (4x32) Kwords SA179-SA182 101011XXXXX 128 (4x32) Kwords SA7 00000000111 4 Kwords SA8-SA10 00000001XXX 00000010XXX 00000011XXX 96 (3x32) Kwords SA11-SA14 000001XXXXX 128 (4x32) Kwords SA183-SA186 101100XXXXX 128 (4x32) Kwords SA15-SA18 000010XXXXX 128 (4x32) Kwords SA187-SA190 101101XXXXX 128 (4x32) Kwords SA19-SA22 000011XXXXX 128 (4x32) Kwords SA191-SA194 101110XXXXX 128 (4x32) Kwords SA23-SA26 000100XXXXX 128 (4x32) Kwords SA195-SA198 101111XXXXX 128 (4x32) Kwords SA27-SA30 000101XXXXX 128 (4x32) Kwords SA199-SA202 110000XXXXX 128 (4x32) Kwords SA31-SA34 000110XXXXX 128 (4x32) Kwords SA203-SA206 110001XXXXX 128 (4x32) Kwords SA35-SA38 000111XXXXX 128 (4x32) Kwords SA207-SA210 110010XXXXX 128 (4x32) Kwords SA39-SA42 001000XXXXX 128 (4x32) Kwords SA211-SA214 110011XXXXX 128 (4x32) Kwords SA43-SA46 001001XXXXX 128 (4x32) Kwords SA215-SA218 110100XXXXX 128 (4x32) Kwords SA47-SA50 001010XXXXX 128 (4x32) Kwords SA219-SA222 110101XXXXX 128 (4x32) Kwords SA51-SA54 001011XXXXX 128 (4x32) Kwords SA223-SA226 110110XXXXX 128 (4x32) Kwords SA55-SA58 001100XXXXX 128 (4x32) Kwords SA227-SA230 110111XXXXX 128 (4x32) Kwords SA59-SA62 001101XXXXX 128 (4x32) Kwords SA231-SA234 111000XXXXX 128 (4x32) Kwords SA63-SA66 001110XXXXX 128 (4x32) Kwords SA235-SA238 111001XXXXX 128 (4x32) Kwords SA67-SA70 001111XXXXX 128 (4x32) Kwords SA239-SA242 111010XXXXX 128 (4x32) Kwords SA71-SA74 010000XXXXX 128 (4x32) Kwords SA243-SA246 111011XXXXX 128 (4x32) Kwords SA75-SA78 010001XXXXX 128 (4x32) Kwords SA247-SA250 111100XXXXX 128 (4x32) Kwords SA79-SA82 010010XXXXX 128 (4x32) Kwords SA251-SA254 111101XXXXX 128 (4x32) Kwords SA83-SA86 010011XXXXX 128 (4x32) Kwords SA255-SA258 111110XXXXX 128 (4x32) Kwords SA87-SA90 010100XXXXX 128 (4x32) Kwords SA91-SA94 010101XXXXX 128 (4x32) Kwords SA259-SA261 96 (3x32) Kwords SA95-SA98 010110XXXXX 128 (4x32) Kwords 11111100XXX 11111101XXX 11111110XXX SA99-SA102 010111XXXXX 128 (4x32) Kwords SA262 11111111000 4 Kwords SA103-SA106 011000XXXXX 128 (4x32) Kwords SA263 11111111001 4 Kwords 11111111010 4 Kwords SA107-SA110 011001XXXXX 128 (4x32) Kwords SA264 SA111-SA114 011010XXXXX 128 (4x32) Kwords SA265 11111111011 4 Kwords SA115-SA118 011011XXXXX 128 (4x32) Kwords SA266 11111111100 4 Kwords SA119-SA122 011100XXXXX 128 (4x32) Kwords SA267 11111111101 4 Kwords SA123-SA126 011101XXXXX 128 (4x32) Kwords SA268 11111111110 4 Kwords SA127-SA130 011110XXXXX 128 (4x32) Kwords SA269 11111111111 4 Kwords June 07, 2005 Am29PDL127H 23 P R E L I M I N A R Y SECTOR PROTECTION The Am29PDL127H features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: ■ Persistently Locked—The sector is protected and cannot be changed. Persistent Sector Protection ■ Dynamically Locked—The sector is protected and can be changed by a simple command. A command sector protection method that replaces the old 12 V controlled protection method. ■ Unlocked—The sector is unprotected and can be changed by a simple command. Password Sector Protection To achieve these states, three types of “bits” are used: A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted WP# Hardware Protection A write protect pin that can prevent program or erase operations in sectors 0, 1, 268, and 269. The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen. Selecting a Sector Protection Mode All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. If the Persistent Sector Protection method is desired, programming the Persistent Sector Protection Mode Locking Bit permanently sets the device to the Persistent Sector Protection mode. If the Password Sector Protection method is desired, programming the Password Mode Locking Bit permanently sets the device to the Password Sector Protection mode. It is not possible to switch between the two protection modes once a locking bit has been set. One of the two modes must be selected when the device is first programmed. This prevents a program or virus from later setting the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at the factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode for details. Persistent Sector Protection The Persistent Sector Protection method replaces the 12 V controlled protection method in previous AMD flash devices. This new method provides three different sector protection states: 24 Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). All 4 Kword boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. The device erases all PPBs in parallel. If any PPB requires erasure, the device must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Otherwise, a previously erased sector PPBs can potentially be over-erased. The flash device does not have a built-in means of preventing sector PPBs over-erasure. Persistent Protection Bit Lock (PPB Lock) The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to “1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through the DYB Write Command. When the par ts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state – meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to Am29PDL127H June 07, 2005 P R E L I M I N A R Y switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are non-volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to “1”. Setting the PPB Lock disables all program and erase commands to the non-volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed; for example, to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PPBs during system operation. The WP#/ACC write protect pin adds a final level of hardware protection to sectors 0, 1, 268, and 269. When this pin is low it is not possible to change the contents of these sectors. These sectors generally hold system boot code. The WP#/ACC pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again. The best protection is achieved by executing the PPB lock bit set command early in the boot code, and protect the boot code by holding WP#/ACC = VIL. June 07, 2005 Table 8. Sector Protection Schemes DYB PPB PPB Lock 0 0 0 Unprotected—PPB and DYB are changeable 0 0 1 Unprotected—PPB not changeable, DYB is changeable 0 1 0 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 Sector State Protected—PPB and DYB are changeable Protected—PPB not changeable, DYB is changeable Table 8 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the sector. In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 µs before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 µs after which the device returns to read mode without having erased the protected sector. The programming of the DYB, PPB, and PPB lock for a g i v e n s e c t o r c a n b e ve r i f i e d b y w r i t i n g a DYB/PPB/PPB lock verify command to the device. Persistent Sector Protection Mode Locking Bit Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode. Password Protection Mode The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differences between the Persistent Sector Protection and the Password Sector Protection Mode: Am29PDL127H 25 P R E L I M I N A R Y ■ When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. ■ The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each “password check.” This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the password. The password may be correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: 1. Permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. 2. Disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further 26 password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see “Password Verify Command”). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device. Write Protect (WP#) The Write Protect feature provides a hardware method of protecting sectors 0, 1, 268, and 269 without using VID. This function is provided by the WP# pin and overrides the previously discussed High Voltage Sector Protection method. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 4 Kword sectors on both ends of the flash array independent of whether it was previously protected or unprotected. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether sectors 0, 1, 268, and 269 were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in High Voltage Sector Protection. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit is not set. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Am29PDL127H June 07, 2005 P R E L I M I N A R Y Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode. June 07, 2005 High Voltage Sector Protection Sector protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (VID ) to be placed on the RESET# pin. Refer to Figure 1 for details on this procedure. Note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle. Am29PDL127H 27 P R E L I M I N A R Y START START Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PLSCNT = 1 RESET# = VID Wait 4 μs Temporary Sector Unprotect Mode No PLSCNT = 1 RESET# = VID Wait 4 μs First Write Cycle = 60h? First Write Cycle = 60h? Temporary Sector Unprotect Mode Yes Yes Set up sector address No All sectors protected? Sector Protect: Write 60h to sector address with A7-A0 = 00000010 Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A7-A0 = 01000010 Wait 100 µs Increment PLSCNT No Verify Sector Protect: Write 40h to sector address with A7-A0 = 00000010 Reset PLSCNT = 1 Read from sector address with A7-A0 = 00000010 Wait 1.2 ms Verify Sector Unprotect: Write 40h to sector address with A7-A0 = 00000010 Increment PLSCNT No No PLSCNT = 25? Yes Yes Remove VID from RESET# Write reset command Sector Protect complete Device failed Read from sector address with A7-A0 = 00000010 Data = 01h? Protect another sector? No Yes PLSCNT = 1000? No Remove VID from RESET# Write reset command Sector Protect complete Sector Protect Algorithm Yes Remove VID from RESET# Write reset command Sector Unprotect complete Device failed Set up next sector address No Data = 00h? Yes Last sector verified? No Yes Remove VID from RESET# Write reset command Sector Unprotect complete Sector Unprotect Algorithm Figure 1. In-System Sector Protection/ Sector Unprotection Algorithms 28 Am29PDL127H June 07, 2005 P R E L I M I N A R Y Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 2 shows the algorithm, and Figure 23 shows the timing diagrams, for this feature. While PPB lock is set, the device cannot enter the Temporary Sector Unprotection Mode. START tection mode and Password Protection mode. It uses i nd i cato r bi ts ( D Q6 , D Q7 ) to in di ca te the factory-locked and customer-locked status of the part. The system accesses the SecSi Sector through a command sequence (see “Enter SecSi™ Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Factory-Locked Area (64 words) T h e fa c t o r y - l o cke d a r e a o f t h e S e c S i S e c t o r (000000h-00003Fh) is locked when the par t is shipped, whether or not the area was programmed at the factory. The SecSi Sector Factory-locked Indicator Bit (DQ7) is permanently set to a “1”. AMD offers the ExpressFlash service to program the factory-locked area with a random ESN, a customer-defined code, or any combination of the two. Because only AMD can program and protect the factory-locked area, this method ensures the security of the ESN once the product is shipped to the field. Contact an AMD representative for details on using AMD’s ExpressFlash service. RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed (Note 2) Customer-Lockable Area (64 words) Notes: 1. All protected sectors unprotected (If WP#/ACC = VIL, sectors 0, 1, 268, 269 will remain protected). 2. All previously protected sectors are protected once again. Figure 2. Temporary Sector Unprotect Operation SecSi™ (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN) The 128-word SecSi sector is divided into 64 factory-lockable words that can be programmed and locked by the customer. The SecSi sector is located at addresses 000000h-00007Fh in both Persistent Pro- June 07, 2005 The customer-lockable area of the SecSi Sector (000040h-00007Eh) is shipped unprotected, which allows the customer to program and optionally lock the area as appropriate for the application. The SecSi Sector Customer-locked Indicator Bit (DQ6) is shipped as “0” and can be permanently locked to “1” by issuing the SecSi Protection Bit Program Command. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The Customer-lockable SecSi Sector area can be protected using one of the following procedures: ■ Follow the SecSi Sector protection Agorithm as shown in Figure 3. This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. Am29PDL127H 29 P R E L I M I N A R Y START SecSiTM Sector Entry Write AAh to address 555h Write 55h to address 2AAh Write 88h to address 555h SecSi Sector Entry SecSi Sector Protection Entry Write AAh to address 555h Write 55h to address 2AAh Write 60h to address 555h PLSCNT = 1 Protect SecSi Sector: write 68h to sector address with A7–A0 = 00011010 Time out 256 μs SecSi Sector Protection Verify SecSi Sector: write 48h to sector address with A7–A0 = 00011010 Increment PLSCNT Read from sector address with A7–A0 = 00011010 No No PLSCNT = 25? Data = 01h? Yes Yes SecSi Sector Protection Completed Device Failed SecSi Sector Exit Write 555h/AAh Write 2AAh/55h Write SA0+555h/90h Write XXXh/00h Figure 3. 30 SecSi Sector Exit SecSi Sector Protection Algorithm Am29PDL127H June 07, 2005 P R E L I M I N A R Y ■ To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 4. Once the SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. SecSi Sector Protection Bits The SecSi Sector Protection Bits prevent programming of the SecSi Sector memory area. Once set, the SecSi Sector memory area contents are non-modifiable. Wait 1 μs Write 60h to any address Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Figure 4. Write Pulse “Glitch” Protection Noise pulses of less than 3 ns (typical) on OE#, CE#, or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If WE# = CE# = VIL and OE# = V IH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. COMMON FLASH MEMORY INTERFACE (CFI) Remove VIH or VID from RESET# The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. Write reset command SecSi Sector Protect Verify complete SecSi Sector Protect Verify Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. June 07, 2005 When VCC is less than VLKO, the device does not accept any write cycles. This protects data during V CC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Power-Up Write Inhibit START RESET# = VIH or VID Low VCC Write Inhibit This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 9–12. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 9–12. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Am29PDL127H 31 P R E L I M I N A R Y Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of these documents. 32 Am29PDL127H June 07, 2005 P R E L I M I N A R Y Table 9. CFI Query Identification String Addresses Data Description 10h 11h 12h 0051h 0052h 0059h Query Unique ASCII string “QRY” 13h 14h 0002h 0000h Primary OEM Command Set 15h 16h 0040h 0000h Address for Primary Extended Table 17h 18h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) Table 10. System Interface String Addresses Data 1Bh 0027h VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 0036h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 0004h Typical timeout per single byte/word write 2N µs 20h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported) 21h 0009h Typical timeout per individual block erase 2N ms 22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 0005h Max. timeout for byte/word write 2N times typical 24h 0000h Max. timeout for buffer write 2N times typical 25h 0004h Max. timeout per individual block erase 2N times typical 26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) June 07, 2005 Description Am29PDL127H 33 P R E L I M I N A R Y Table 11. 34 Device Geometry Definition Addresses Data Description 27h 0018h Device Size = 2N byte 28h 29h 0001h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 0000h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 0003h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 0007h 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 00FDh 0000h 0000h 0001h Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) 35h 36h 37h 38h 0007h 0000h 0020h 0000h Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) 39h 3Ah 3Bh 3Ch 0000h 0000h 0000h 0000h Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100) Am29PDL127H June 07, 2005 P R E L I M I N A R Y Table 12. Primary Vendor-Specific Extended Query Addresses Data Description 40h 41h 42h 0050h 0052h 0049h Query-unique ASCII string “PRI” 43h 0031h Major version number, ASCII (reflects modifications to the silicon) 44h 0033h Minor version number, ASCII (reflects modifications to the CFI table) 45h 000Ch Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) 46h 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 0007h Sector Protect/Unprotect scheme 01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode 4Ah 00E7h Simultaneous Operation 00 = Not Supported, X = Number of Sectors excluding Bank 1 4Bh 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 0002h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 0085h 4Eh 0095h 4Fh 0001h 50h 0001h 57h 0004h 58h 0027h 59h 0060h 5Ah 0060h 5Bh 0027h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag June 07, 2005 00h = Uniform device, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom Program Suspend 0 = Not supported, 1 = Supported Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks Bank 1 Region Information X = Number of Sectors in Bank 1 Bank 2 Region Information X = Number of Sectors in Bank 2 Bank 3 Region Information X = Number of Sectors in Bank 3 Bank 4 Region Information X = Number of Sectors in Bank 4 Am29PDL127H 35 P R E L I M I N A R Y COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 13 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristic section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding ban k enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The AC Characteristic table provides the read parameters, and Figure 12 shows the timing diagram. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset c o m m an d re tur ns th a t ba nk to the e ra s e- s us pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without reinitiating the command sequence. Reset Command Table 13 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 4 shows the address range and bank number associated with each sector. Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. 36 Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight word electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector Am29PDL127H June 07, 2005 P R E L I M I N A R Y command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 13 shows the address and data requirements for both command sequences. See also “SecSi™ (Secured Silicon) Sector Flash Memory Region” for further information. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Word Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 13 shows the address and data requirements for the program command sequence. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to program data to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 13 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (See Table 14) Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH any operation other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and Figure 5 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 16 for timing diagrams. June 07, 2005 Am29PDL127H 37 P R E L I M I N A R Y operation is in progress. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. START Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 18 section for timing diagrams. Write Program Command Sequence Sector Erase Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Yes Increment Address No The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Last Address? Yes Programming Completed Note: See Table 13 for program command sequence. Figure 5. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 13 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written during the chip erase operation are ignored. Note that SecSi Sector, autoselect, and CFI functions are unavailable when a [program/erase] 38 Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command.Table 13 shows the address and data requirements for the sector erase command sequence. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system must rewrite the command sequence and any additional addresses and commands. Note that SecSi Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can de- Am29PDL127H June 07, 2005 P R E L I M I N A R Y termine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 18 section for timing diagrams. START Write Erase Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System No Embedded Erase algorithm in progress After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. Refer to the Autoselect Mode and Autoselect Command Sequence sections for details. Yes Erasure Completed Notes: 1. See Table 13 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Erase Operation Erase Suspend/Erase Resume Commands To resume the sector erase operation, the system must write the Erase Resume command (address bits are don’t care). The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Password Program Command The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 80 µs time-out period during the sector erase command sequence. June 07, 2005 When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase suspend command. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard Word Program operation. Refer to the Write Operation Status section for more information. Data = FFh? Figure 6. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. Four Password Program commands are required to program the password. The system must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. There are no pro- Am29PDL127H 39 P R E L I M I N A R Y visions for entering the 2-cycle unlock cycle, the password program command, and all the password data. There is no special addressing order required for programming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations to any memory location will return the programming status. Once programming is complete, the user must issue a Read/Reset command to return the device to normal operation. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-out by the Embedded Program Algorithm™ with the cell remaining as a “0”. The password is all ones when shipped from the factory. All 64-bit password combinations are valid as a password. Password Verify Command The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will always drive all F’s onto the DQ data bus. The Password Verify command is permitted if the SecSi sector is enabled. Also, the device will not operate in Simultaneous Operation when the Password Verify command is executed. Only the password is returned regardless of the bank address. The lower two address bits (A1-A0) are valid during the Password Verify. Writing the Read/Reset command returns the device back to normal operation. Password Protection Mode Locking Bit Program Command The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the Password. Once programmed, the Password Protection Mode Locking Bit cannot be erased! If the Password Protection Mode Locking Bit is verified as program without margin, the Password Protection Mode Locking Bit Program command can be executed to improve the program margin. Once the Password Protection Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. Exiting the Mode Locking Bit Program command is accomplished by writing the Read/Reset command. 40 Persistent Sector Protection Mode Locking Bit Program Command The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Command should be reissued to improve program margin. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the Read/Reset command. SecSi Sector Protection Bit Program Command The SecSi Sector Protection Bit Program Command programs the SecSi Sector Protection Bit, which prevents the SecSi sector memory from being cleared. If the SecSi Sector Protection Bit is verified as programmed without margin, the SecSi Sector Protection Bit Program Command should be reissued to improve program margin. Exiting the VCC -level SecSi Sector Protection Bit Program Command is accomplished by writing the Read/Reset command. PPB Lock Bit Set Command The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear or the Password Unlock command is executed. Upon setting the PPB Lock Bit, the PPBs are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the Read/Reset command (only in the Persistent Protection Mode). DYB Write Command The DYB Write command is used to set or clear a DYB for a given sector. The high order address bits (A22–A12) are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset.Exiting the DYB Write command is accomplished by writing the Read/Reset command. Am29PDL127H June 07, 2005 P R E L I M I N A R Y Password Unlock Command The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 µs at a time to prevent a hacker from running through all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 µ s execution window for each portion of the unlock, the command will be ignored. Once the Password Unlock command is entered, the RY/BY# indicates that the device is busy. Approximately 1 µs is required for each portion of the unlock. Once the first portion of the password unlock completes (RY/BY# is not low or DQ6 does not toggle when read), the next part of the password is written. The system must thus monitor RY/BY# or the status bits to confirm when to write the next portion of the password. Seven cycles are required to successfully clear the PPB Lock Bit. determine whether the PPB has been erased with margin. If the PPBs has been erased without margin, the erase command should be reissued to improve the program margin. It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure may occur making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. DYB Write Command The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. The bank address is latched when the command is written. PPB Program Command PPB Lock Bit Set Command The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector address (A22–A12) are written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command will not execute and the command will time-out without programming the PPB. The PPB Lock Bit set command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. The bank address is latched when the command is written. After programming a PPB, two additional cycles are needed to determine whether the PPB has been programmed with margin. If the PPB has been programmed without margin, the program command should be reissued to improve the program margin. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. PPB Status Command The PPB Program command does not follow the Embedded Program algorithm. PPB Lock Bit Status Command The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify command to the device. Sector Protection Status Command All PPB Erase Command The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase command is written all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the command will time-out without erasing the PPBs. After erasing the PPBs, two additional cycles are needed to June 07, 2005 The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the device. The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sector Protection Status command to the device. Note that there is no single command to independently verify the programming of a DYB for a given sector group. Am29PDL127H 41 P R E L I M I N A R Y Command Definitions Tables Command (Notes) Cycles Table 13. Memory Array Command Definitions Bus Cycles (Notes 1–4) Addr Data Addr Data Addr Data Addr Data Read (5) 1 RA Reset (6) 1 XXX F0 Manufacturer ID 4 555 AA 2AA 55 555 90 (BA)X00 01 Device ID (10) 6 555 AA 2AA 55 555 90 (BA)X01 7E Autoselect (Note 7) Addr Data Addr Data (BA)X0E 20 (BA)X0F 00 RD SecSi Sector Factory Protect (8) 4 555 AA 2AA 55 555 90 X03 (see note 8) Sector Group Protect Verify (9) 4 555 AAA 2AA 55 555 90 (SA)X02 XX00/ XX01 Program 4 555 AA 2AA 55 555 A0 PA PD Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 B0 PD 555 20 Program/Erase Suspend (11) 1 BA Program/Erase Resume (12) 1 BA 30 CFI Query (13) 1 55 98 Accelerated Program (15) 2 XX A0 PA Unlock Bypass Entry (15) 3 555 AA 2AA 55 Unlock Bypass Program (15) 2 XX A0 PA PD Unlock Bypass Erase (15) 2 XX 80 XX 10 Unlock Bypass CFI (13, 15) 1 XX 98 Unlock Bypass Reset (15) 2 XXX 90 XXX 00 Legend: BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determined by A22:A20, see Tables 4 and for more detail. PA = Program Address (A22:A0). Addresses latch on falling edge of WE# or CE# pulse, whichever happens later. PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first. RA = Read Address (A22:A0). RD = Read Data (DQ15:DQ0) from location RA. SA = Sector Address (A22:A12) for verifying (in autoselect mode) or erasing. WD = Write Data. See “Configuration Register” definition for specific write data. Data latched on rising edge of WE#. X = Don’t care Notes: 1. See Table 1 for description of bus operations. 8. The data is C0h for factory and customer locked and 80h for factory locked. The data is 00h for an unprotected sector group and 01h for a protected sector group. 2. All values are in hexadecimal. 3. Shaded cells in table denote read cycles. All other cycles are write operations. 9. 4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 10. Device ID must be read across cycles 4, 5, and 6. 5. No unlock or command cycles required when bank is reading array data. 6. The Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend) when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information). 7. 42 Fourth cycle of autoselect command sequence is a read cycle. System must provide bank address to obtain manufacturer ID or device ID information. See Autoselect Command Sequence section for more information. 11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode. Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address. 12. Program/Erase Resume command is valid only during Erase Suspend mode, and requires bank address. 13. Command is valid when device is ready to read array data or when device is in autoselect mode. 14. WP#/ACC must be at VID during the entire operation of command. 15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required to return to the reading array. Am29PDL127H June 07, 2005 P R E L I M I N A R Y Table 14. Sector Protection Command Definitions Cycles Bus Cycles (Notes 1-4) Command (Notes) Addr Data Addr Data Reset 1 XXX F0 SecSi Sector Entry 3 555 AA 2AA SecSi Sector Exit 4 555 AA 2AA SecSi Protection Bit Program (5, 6) 6 555 AA SecSi Protection Bit Status 5 555 Password Program (5, 7, 8) 4 Password Verify (6, 8, 9) Addr Data Addr Data Addr Data Addr Data 55 555 88 55 555 90 XX 00 2AA 55 555 60 OW 68 OW 48 OW RD(0) AA 2AA 55 555 60 OW 48 OW RD(0) 555 AA 2AA 55 555 38 XX[0-3] PD[0-3] 4 555 AA 2AA 55 555 C8 PWA[0-3] PWD[0-3] Password Unlock (7, 10, 11) 7 555 AA 2AA 55 555 28 PWA[0] PWD[0] PWA[1] PWD[1] PWA[2] PWD[2] PPB Program (5, 6, 12) 6 555 AA 2AA 55 555 60 (SA)WP 68 (SA)WP 48 (SA)WP RD(0) PPB Status 4 555 AA 2AA 55 555 90 (SA)WP RD(0) WP 60 (SA) 40 (SA)WP RD(0) PL RD(0) SL RD(0) All PPB Erase (5, 6, 13, 14) 6 555 AA 2AA 55 555 60 PPB Lock Bit Set 3 555 AA 2AA 55 555 78 PPB Lock Bit Status (15) 4 555 AA 2AA 55 555 58 SA RD(1) DYB Write (7) 4 555 AA 2AA 55 555 48 SA X1 DYB Erase (7) 4 555 AA 2AA 55 555 48 SA X0 DYB Status (6) 4 555 AA 2AA 55 555 58 SA 48 PPMLB Program (5, 6, 12) 6 555 AA 2AA 55 555 60 PL 68 PL 48 PPMLB Status (5) 5 555 AA 2AA 55 555 60 PL 48 PL RD(0) SPMLB Program (5, 6, 12) 6 555 AA 2AA 55 555 60 SL 68 SL 48 SPMLB Status (5) 5 555 AA 2AA 55 555 60 SL 48 SL RD(0) Addr Data PWA[3] PWD[3] Legend: DYB = Dynamic Protection Bit OW = Address (A7:A0) is (00011010) PD[3:0] = Password Data (1 of 4 portions) PPB = Persistent Protection Bit PWA = Password Address. A1:A0 selects portion of password. PWD = Password Data being verified. PL = Password Protection Mode Lock Address (A7:A0) is (00001010) RD(0) = Read Data DQ0 for protection indicator bit. RD(1) = Read Data DQ1 for PPB Lock status. SA = Sector Address where security command applies. Address bits A22:A12 uniquely select any sector. SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010) WP = PPB Address (A7:A0) is (00000010) (Note16) X = Don’t care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit 1. See Table 1 for description of bus operations. 9. 2. All values are in hexadecimal. 3. Shaded cells in table denote read cycles. All other cycles are write operations. 10. The password is written over four consecutive cycles, at addresses 0-3. 4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 5. The reset command returns device to reading array. 6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6, program command must be issued and verified again. 7. Data is latched on the rising edge of WE#. 8. Entire command sequence must be entered for each portion of password. June 07, 2005 Command sequence returns FFh if PPMLB is set. 11. A 2 µs timeout is required between any two portions of password. 12. A 100 µs timeout is required between cycles 4 and 5. 13. A 1.2 ms timeout is required between cycles 4 and 5. 14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB overerasure. 15. DQ1 = 1 if PPB locked, 0 if unlocked. 16. For PDL128G and PDL640G, the WP address is 0111010. The EP address (PPB Erase Address) is 1111010. Am29PDL127H 43 P R E L I M I N A R Y WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 15 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. pleted the program or erase operation and DQ7 has valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid data on DQ15–DQ0 will appear on successive read cycles. Table 15 shows the outputs for Data# Polling on DQ7. Figure 7 shows the Data# Polling algorithm. Figure 20 in the AC Characteristic section shows the Data# Polling timing diagram. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode. START Read DQ7–DQ0 Addr = VA DQ7 = Data? No No During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. 44 DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 400 µs, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ15–DQ0 on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ15–DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has com- Yes DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Am29PDL127H Figure 7. Data# Polling Algorithm June 07, 2005 P R E L I M I N A R Y RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 15 shows the outputs for Toggle Bit I on DQ6. Figure 8 shows the toggle bit algorithm. Figure 21 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. START Read Byte (DQ7–DQ0) Address =VA Table 15 shows the outputs for RY/BY#. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. Read Byte (DQ7–DQ0) Address =VA Toggle Bit = Toggle? Yes No After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 400 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. DQ5 = 1? Yes Read Byte Twice (DQ7–DQ0) Address = VA The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 8. June 07, 2005 No Am29PDL127H Toggle Bit Algorithm 45 P R E L I M I N A R Y DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 15 to compare outputs for DQ2 and DQ6. Figure 8 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 21 shows the toggle bit timing diagram. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 8 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 8). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 15 shows the status of DQ3 relative to the other status bits. 46 Am29PDL127H June 07, 2005 P R E L I M I N A R Y Table 15. Standard Mode Erase Suspend Mode Status Embedded Program Algorithm Embedded Erase Algorithm Erase Erase-Suspend- Suspended Sector Read Non-Erase Suspended Sector Erase-Suspend-Program Write Operation Status DQ7 (Note 2) DQ7# 0 DQ6 Toggle Toggle DQ5 (Note 1) 0 0 DQ3 N/A 1 DQ2 (Note 2) No toggle Toggle RY/BY# 0 0 1 No toggle 0 N/A Toggle 1 Data Data Data Data Data 1 DQ7# Toggle 0 N/A N/A 0 Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. June 07, 2005 Am29PDL127H 47 P R E L I M I N A R Y ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C 20 ns Ambient Temperature with Power Applied. . . . . . . . . . . . . . –65°C to +125°C +0.8 V Voltage with Respect to Ground –0.5 V VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . .–0.5 V to +13.0 V –2.0 V 20 ns WP#/ACC (Note 2) . . . . . . . . . . .–0.5 V to +10.5 V All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V Figure 9. Maximum Negative Overshoot Waveform Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot V SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 9. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 10. 2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5 V. During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on pin A9, OE#, and RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns. 20 ns 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns Figure 10. Maximum Positive Overshoot Waveform 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. OPERATING RANGES Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7–3.6 V Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C VIO (see Note) . . . . . . . . . . . 1.65–1.95 V or 2.7–3.6 V Note: For all AC and DC specifications, VIO = VCC; contact AMD for other VIO options. Operating ranges define those limits between which the functionality of the device is guaranteed. 48 Am29PDL127H June 07, 2005 P R E L I M I N A R Y DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ±1.0 µA ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ILIT A9, OE#, RESET# Input Load Current VCC = VCC max; VID= 12.5 V 35 µA ILR Reset Leakage Current VCC = VCC max; VID= 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, OE# = VIH VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) OE# = VIH, VCC = VCC max (Note 1) ICC2 VCC Active Write Current (Notes 2, 3) ICC3 5 MHz 20 30 10 MHz 45 55 OE# = VIH, WE# = VIL 15 25 mA VCC Standby Current (Note 2) CE#, CE2#, RESET#, WP/ACC# = VIO ± 0.3 V 1 5 µA ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 1 5 µA ICC5 Automatic Sleep Mode (Notes 2, 4) VIH = VIO ± 0.3 V; VIL = VSS ± 0.3 V 1 5 µA ICC6 VCC Active Read-While-Program Current (Notes 1, 2) OE# = VIH 21 45 mA ICC7 VCC Active Read-While-Erase Current (Notes 1, 2) OE# = VIH 21 45 mA ICC8 VCC Active Program-While-EraseSuspended Current (Notes 2, 5) OE# = VIH 17 25 mA VIL Input Low Voltage VIH Input High Voltage VHH mA VIO = 1.65–1.95 V –0.4 0.4 V VIO = 2.7–3.6 V –0.5 0.8 V VIO–0.4 VIO+0.4 V VIO = 2.7–3.6 V 2.0 VCC+0.3 V Voltage for ACC Program Acceleration VCC = 3.0 V ± 10% 8.5 9.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 V ± 10% 11.5 12.5 V VOL Output Low Voltage VOH Output High Voltage VLKO Low VCC Lock-Out Voltage (Note 5) VIO = 1.65–1.95 V IOL = 100 µA, VCC = VCC min, VIO = 1.65–1.95 V 0.1 V IOL = 2.0 mA, VCC = VCC min, VIO = 2.7–3.6 V 0.4 V IOH = –100 µA, VCC = VCC min, VIO = 1.65–1.95 V IOH = –2.0 mA, VCC = VCC min, VIO = 2.7–3.6 V V 2.4 V 2.3 Notes: 1. The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. June 07, 2005 VIO–0.1 2.5 V 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 150 ns. Typical sleep mode current is 1 μA. 5. Not 100% tested. Am29PDL127H 49 P R E L I M I N A R Y TEST CONDITIONS Table 16. 3.6 V Test Condition 2.7 kΩ Device Under Test CL Test Specifications 6.2 kΩ All Speeds Output Load 1 TTL gate Output Load Capacitance, CL (including jig capacitance) 30 pF Input Rise and Fall Times 5 ns 0.0–3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V Input Pulse Levels Note: Diodes are IN3064 or equivalent Figure 11. Unit Note: For 70 pF output load capacitance, 2 ns will be added to certain read-only operation parameters. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H 3.0 V Input Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 1.5 V Measurement Level 1.5 V Output 0.0 V Figure 12. 50 Input Waveforms and Measurement Levels Am29PDL127H June 07, 2005 P R E L I M I N A R Y AC CHARACTERISTIC Read-Only Operations Parameter Speed Options JEDEC Std. Description tAVAV tRC Read Cycle Time (Note 1) tAVQV tACC Address to Output Delay tELQV tCE Chip Enable to Output Delay Test Setup 53 63 68 88 Unit Min 55 65 65 85 ns CE#, OE# = VIL Max 55 65 65 85 ns OE# = VIL Max 60 65 70 85 ns Max 20 25 70 85 ns 20 25 30 30 ns tPACC Page Access Time tGLQV tOE Output Enable to Output Delay Max tEHQZ tDF Chip Enable to Output High Z (Note 3) Max 16 ns tGHQZ tDF Output Enable to Output High Z (Notes 1, 3) Max 16 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Notes 3) Min 5 ns Min 0 ns tOEH Read Output Enable Hold Time Toggle and (Note 1) Data# Polling Min 10 ns Notes: 1. Not 100% tested. 2. See Figure 11 and Table 16 for test specifications June 07, 2005 3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF. 4. For 70 pF output load capacitance, 2 ns will be added to tACC, tCE, tPACC, tOE values for all speed options. Am29PDL127H 51 P R E L I M I N A R Y AC CHARACTERISTICS tRC Addresses Stable Addresses tACC CE# tRH tRH tDF tOE OE# tOEH WE# tCE tOH HIGH Z Data HIGH Z Valid Data RESET# RY/BY# 0V Figure 13. Same Page A22-A3 A2-A0 Read Operation Timings Aa tACC Data Ab tPACC Qa Ad Ac tPACC Qb tPACC Qc Qd CE# OE# Figure 14. 52 Page Read Operation Timings Am29PDL127H June 07, 2005 P R E L I M I N A R Y AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std Description All Speed Options Unit tReady RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 20 µs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min 50 ns tRPD RESET# Low to Standby Mode Min 20 µs tRB RY/BY# Recovery Time Min 0 ns Note: Not 100% tested. RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#, OE# RESET# tRP Figure 15. June 07, 2005 Reset Timings Am29PDL127H 53 P R E L I M I N A R Y AC CHARACTERISTICS Erase and Program Operations Parameter Speed Options JEDEC Std Description tAVAV tWC Write Cycle Time (Note 1) Min tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tAH Address Hold Time Min tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min tDVWH tDS Data Setup Time Min tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 10 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 40 ns tWHDL tWPH Write Pulse Width High Min 20 25 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWLAX 53 63 68 88 Unit 55 65 65 85 ns 30 35 0 25 ns ns 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 6 µs tWHWH1 tWHWH1 Accelerated Programming Operation (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns Program/Erase Valid to RY/BY# Delay Max 90 ns tBUSY Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. 54 Am29PDL127H June 07, 2005 P R E L I M I N A R Y AC CHARACTERISTICS Program Command Sequence (last two cycles) tAS tWC Addresses Read Status Data (last two cycles) 555h PA PA PA tAH CE# tCH OE# tWHWH1 tWP WE# tWPH tCS tDS tDH PD A0h Data Status tBUSY DOUT tRB RY/BY# VCC tVCS Note: 1. PA = program address, PD = program data, DOUT is the true data at the program address. Figure 16. Program Operation Timings VHH WP#/ACC VIL or VIH VIL or VIH tVHH Figure 17. June 07, 2005 tVHH Accelerated Program Timing Diagram Am29PDL127H 55 P R E L I M I N A R Y AC CHARACTERISTICS Erase Command Sequence (last two cycles) tAS tWC 2AAh Addresses Read Status Data VA SA 555h for chip erase VA tAH CE# tCH OE# tWP WE# tWPH tCS tWHWH2 tDS tDH Data 55h 30h Status DOUT 10 for Chip Erase tBUSY tRB RY/BY# tVCS VCC Note: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.) Figure 18. 56 Chip/Sector Erase Operation Timings Am29PDL127H June 07, 2005 P R E L I M I N A R Y AC CHARACTERISTICS Addresses tWC tWC tRC Valid PA Valid RA tWC tAH tAS Valid PA Valid PA tAS tCPH tACC tAH tCE CE# tCP tOE OE# tOEH tGHWL tWP WE# tDF tWPH tDS tOH tDH Valid Out Valid In Data Valid In Valid In tSR/W WE# Controlled Write Cycle Read Cycle Figure 19. CE# Controlled Write Cycles Back-to-back Read/Write Cycle Timings tRC Addresses VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH DQ7 Complement Complement DQ6–DQ0 Status Data Status Data True True Valid Data Valid Data High Z High Z tBUSY RY/BY# Note: 1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 20. June 07, 2005 Data# Polling Timings (During Embedded Algorithms) Am29PDL127H 57 P R E L I M I N A R Y AC CHARACTERISTICS tAHT tAS Addresses tAHT tASO CE# tCEPH tOEH WE# tOEPH OE# tDH DQ6/DQ2 tOE Valid Data Valid Status Valid Status Valid Status (first read) (second read) (stops toggling) Valid Data RY/BY# Note: 1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Figure 21. Enter Embedded Erasing WE# Erase Suspend Erase Toggle Bit Timings (During Embedded Algorithms) Enter Erase Suspend Program Erase Suspend Program Erase Suspend Read Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Note: 1. DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. Figure 22. 58 DQ2 vs. DQ6 Am29PDL127H June 07, 2005 P R E L I M I N A R Y AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description All Speed Options Unit tVIDR VID Rise and Fall Time (See Note) Min 500 ns tVHH VHH Rise and Fall Time (See Note) Min 250 ns tRSP RESET# Setup Time for Temporary Sector Unprotect Min 4 µs tRRB RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min 4 µs Note: Not 100% tested. VID VID RESET# VIL or VIH VIL or VIH tVIDR tVIDR Program or Erase Command Sequence CE# WE# tRRB tRSP RY/BY# Figure 23. June 07, 2005 Temporary Sector Unprotect Timing Diagram Am29PDL127H 59 P R E L I M I N A R Y AC CHARACTERISTICS VID RESET# VIH SA, A6, A1, A0 Valid* Valid* Sector Group Protect/Unprotect Data 60h 60h Valid* Verify 40h Status 1 µs CE# Sector Group Protect: 150 µs Sector Group Unprotect: 15 ms WE# OE# * For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. Figure 24. Sector/Sector Block Protect and Unprotect Timing Diagram 60 Am29PDL127H June 07, 2005 P R E L I M I N A R Y AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Parameter Speed Options JEDEC Std. Description 53 63 68 88 Unit tAVAV tWC Write Cycle Time (Note 1) Min 55 65 65 85 ns tAVWL tAS Address Setup Time Min tELAX tAH Address Hold Time Min 30 35 ns tDVEH tDS Data Setup Time Min 25 30 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 35 40 ns tEHEL tCPH CE# Pulse Width High Min 20 25 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 6 µs tWHWH1 tWHWH1 Accelerated Programming Operation (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec 0 ns Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. June 07, 2005 Am29PDL127H 61 P R E L I M I N A R Y AC CHARACTERISTICS 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling Addresses PA tWC tAS tAH tWH WE# tGHEL OE# tWHWH1 or 2 tCP CE# tWS tCPH tBUSY tDS tDH DQ7# Data tRH A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. Figure 25. 62 Alternate CE# Controlled Write (Erase/Program) Operation Timings Am29PDL127H June 07, 2005 P R E L I M I N A R Y ERASE AND PROGRAMMING PERFORMANCE Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.4 5 sec Chip Erase Time 108 Excludes 00h programming prior to erasure (Note 4) sec Word Program Time 7 210 µs Accelerated Word Program Time 4 120 µs Chip Program Time (Note 3) 50 200 sec Excludes system level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. All values are subject to change. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. All values are subject to change. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables Table 13 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 13 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V –100 mA +100 mA VCC Current Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. BGA PIN CAPACITANCE Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 4.2 5.0 pF COUT Output Capacitance VOUT = 0 5.4 6.5 pF CIN2 Control Pin Capacitance VIN = 0 3.9 4.7 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Description Minimum Pattern Data Retention Time June 07, 2005 Am29PDL127H Test Conditions Min Unit 150°C 10 Years 125°C 20 Years 63 P R E L I M I N A R Y PHYSICAL DIMENSIONS VBB080—80-Ball Fine-pitch Ball Grid Array 11.5 x 9 mm package D D1 A e 0.05 C (2X) 8 e 7 6 7 SE 5 E E1 4 3 2 1 M INDEX MARK PIN A1 CORNER 6 0.05 C (2X) J H G F E D C B A A1 CORNER SD NXφb φ 0.08 M C φ 0.15 M C A B TOP VIEW BOTTOM VIEW 0.10 C A2 A A1 K 7 B 10 L C SEATING PLANE 0.08 C SIDE VIEW NOTES: PACKAGE VBB 080 JEDEC 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. N/A 2. ALL DIMENSIONS ARE IN MILLIMETERS. 11.50 mm x 9.00 mm NOM PACKAGE SYMBOL MIN NOM MAX A --- --- 1.00 A1 0.20 --- --- A2 0.62 --- 0.76 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). NOTE 4. OVERALL THICKNESS BALL HEIGHT SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. BODY THICKNESS D 11.50 BSC. BODY SIZE E 9.00 BSC. BODY SIZE D1 8.80 BSC. BALL FOOTPRINT E1 5.60 BSC. BALL FOOTPRINT MD 12 ROW MATRIX SIZE D DIRECTION ME 8 ROW MATRIX SIZE E DIRECTION N 80 TOTAL BALL COUNT φb 0.30 0.35 0.40 e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. BALL DIAMETER e 0.80 BSC. BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT (A3-A6, B3-B6, L3-L6, -M3-M6) DEPOPULATED SOLDER BALLS WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3233 \ 16-038.9h 64 Am29PDL127H June 07, 2005 P R E L I M I N A R Y REVISION SUMMARY Revision A (September 30, 2002) SecSi Sector Flash Memory Region and Enter SecSi Sector/Exit SecSi Sector Command Sequence Initial release. Distinctive Characteristics Added notes, “Note that the ACC function and unlock bypass modes are not available when the SecSi sector is enabled.” Added VIO option at 1.8 V and 3 V I/O to Enhanced VIO Control section. Sector Erase Command Sequence and Chip Erase Command Sequence Modified wording of WP#/ACC (Write Protect/Acceleration) Input. Added “Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress.” Revision A+1 (October 29, 2002) Product Selector Guide Table 13. Memory Array Command Definitions Modified the Product Selector Guide Table. Changed the first address of the unlock bypass reset command sequence from BA to XXX. Ordering Information Changed package type from TBD to VK. CMOS Compatible Added VKI to Valid combinations table. Added ILR parameter to table. Added Process Technology to Standard Product section. Deleted IACC parameter from table. Revised Order Numbers and Package Markings to reflect speed option changes. Revision A+2 (January 24, 2003) Ordering Information Global Changed 55 speed option to 53, changed 65 speed option to 63 and 68. Table 1. Am29PDL127H Device Bus Operations Added note #2. Corrected the package marking for package type PC on 83 and 88 speed options. Revision A+3 (June 20, 2003) Distinctive Characteristics Changed the active read current to 55 mA. Requirements for Reading Array Data Reworded Page Mode Read section Product Selector Guide Common Flash Memory Interface (CFI) Added row to table to expand speed options and allow for another VCC range. Changed wording in last sentence of third paragraph from, “...the autoselect mode.” to “...reading array data.” Product Selector Guide Changed CFI website address. Corrected typo in the VCC,VIO range for the 53 speed option. Command Definitions Changed wording in last sentence of first paragraph from, “...resets the device to reading array data.” to ...”may place the device to an unknown state. A reset command is then required to return the device to reading array data.” Customer Lockable: SecSi Sector NOT Programmed or Protected at the factory. Added second bullet, SecSi sector-protect verify text and figure 3. June 07, 2005 Revision A+4 (June 30, 2003) Revision A+5 (November 24, 2003) Global D eleted 64-ball For tifie d BGA pack age option (LAA064). Deleted the 83 speed option (85 ns tACC, VIO = 2.7–3.6 V). Replaced the 88 speed option (85 ns t ACC, V IO = 1.65–1.95 V) with 78 (70 ns t ACC, V IO = 1.65–1.95 V). Changed data sheet status from Advance Information to Preliminary. Am29PDL127H 65 P R E L I M I N A R Y Distinctive Characteristics Performance Characteristics: Under Power Consumption bullet, changed active read current from 55 to 45 mA; changed program/erase current from 25 to 18 mA. SecSiTM (Secured Silicon) Sector Flash Memory Region Customer-Lockable Area: Added sector protection figure and changed figure reference in this section from Figure 1 to Figure 3. DC Characteristics Changed IOL test conditions for VOL from 4.0 mA to 2.0 mA. Table 16, Test Specifications Changed CL from 70 pF to 30 pF. Added note for 70 pF load capacitance. AC Characteristics Read-only Operations table: Added note for 70 pF load capacitance. Table 16. Sector Protection Command Definitions Corrected number of cycles for SecSi Protection Bit Status, PPMLB Status, and SPMLB Status from 4 to 5 cycles. For these command sequences, inserted a cycle before the final read cycle (RD0). Revision A+6 (June 7, 2005) C over page and Title page Updated EOL disclaimers. Added notation to superseding documents. Trademarks Copyright © 2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 66 Am29PDL127H June 07, 2005