TI1 DAC70504 Quad, 16-, 14-bit, spi voltage output dacs with internal reference Datasheet

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DAC80504, DAC70504
SBAS871A – AUGUST 2017 – REVISED DECEMBER 2017
DACx0504 Quad, 16-, 14-Bit, SPI Voltage Output DACs With Internal Reference
1 Features
3 Description
•
The DACx0504 is a pin-compatible family of lowpower, four-channel, buffered voltage-output, digitalto-analog converter (DAC) with 16- and 14-bit
resolution. The DACx0504 includes a 2.5-V, 5ppm/°C internal reference, eliminating the need for an
external precision reference in most applications. A
user-selectable gain configuration provides full-scale
output voltages of 1.25 V (gain = ½), 2.5 V (gain = 1),
or 5 V (gain = 2). This device operates from a single
2.7-V to 5.5-V supply, is specified monotonic, and
provides high linearity of ±1 LSB INL.
1
•
•
•
•
•
•
•
Performance
– INL: ±1 LSB Maximum at 16-Bit Resolution
– TUE: ±0.14% of FSR Maximum
Integrated 2.5 V Precision Internal Reference
– Initial Accuracy: ±5 mV, Maximum
– Low Drift: 5 ppm/°C, Typical
High Drive Capability: 20 mA With 0.5 V From
Supply Rails
Flexible Output Configuration
– User Selectable Gain: 2, 1 or ½
– Reset to Zero Scale or Midscale
Wide Operating Range
– Power Supply: 2.7 V to 5.5 V
– Temperature: –40˚C to +125˚C
50-MHz, SPI-Compatible Serial Interface
– 4-Wire Mode, 1.7 V to 5.5 V Operation
– Daisy-Chain Operation
– CRC Error Check
Low Power: 0.7 mA/Channel at 5.5 V
Small Package: 3-mm × 3-mm, 16-Pin WQFN
Communication to the DACx0504 is performed
through a 4-wire serial interface that operates at clock
rates of up to 50 MHz. The VIO pin enables serial
interface operation from 1.7 V to 5.5 V. The
DACx0504 flexible interface enables operation with a
wide range of industry-standard microprocessors and
microcontrollers.
The DACx0504 incorporates a power-on-reset circuit
that powers up and maintains the DAC outputs at
either zero scale or midscale until a valid code is
written to the device. This device consumes low
current of 0.7 mA/channel at 5.5 V, making it suitable
for battery-operated equipment. A per-channel powerdown feature reduces the device current consumption
to 15 µA.
2 Applications
•
•
•
•
The DACx0504 is characterized for operation over
the temperature range of –40°C to +125°C, and is
available in a small, 3-mm × 3-mm, QFN package.
Optical Networking
Wireless Infrastructure
Industrial Automation
Data Acquisition Systems
Device Information(1)
PART NUMBER
DACx0504(2)
PACKAGE
WQFN (16)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
(2) DAC80504 Product Preview
Simplified Block Diagram
VIO
VDD
REFDIV
REF
GAIN
Internal
Reference
DACx0504
÷1 or ÷2
GAIN
×1 or ×2
SCLK
DAC
Buffer
CS
LDAC
Interface Logic
SDI
SDO/ALARM
DAC
Register
DAC
OUT0
BUF
Channel 0
Channel 1
OUT1
Channel 2
OUT2
Channel 3
OUT3
Power On Reset
RSTSEL
Power Down Logic
Resistive Network
GND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
DAC80504, DAC70504
SBAS871A – AUGUST 2017 – REVISED DECEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
5
5
5
6
6
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 18
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
18
18
19
23
8.5 Programming........................................................... 26
8.6 Register Map........................................................... 28
9
Application and Implementation ........................ 34
9.1 Application Information............................................ 34
9.2 Typical Application .................................................. 36
10 Power Supply Recommendations ..................... 38
11 Layout................................................................... 39
11.1 Layout Guidelines ................................................. 39
11.2 Layout Example .................................................... 39
12 Device and Documentation Support ................. 40
12.1
12.2
12.3
12.4
12.5
12.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
40
40
40
40
40
40
13 Mechanical, Packaging, and Orderable
Information ........................................................... 40
4 Revision History
Changes from Original (August 2017) to Revision A
•
2
Page
Changed from Advance Information to Mixed Status............................................................................................................. 1
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5 Device Comparison Table
(1)
DEVICE
RESOLUTION
REFERENCE
DAC80504 (1)
16-Bit
Internal (default) or External
DAC70504
14-Bit
Internal (default) or External
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6 Pin Configuration and Functions
SDI
SCLK
13
3
10
REFDIV
4
9
RSTSEL
7
8
GAIN
OUT2
14
LDAC
VDD
OUT1
SDO/ALARM
11
Thermal Pad
6
2
15
CS
GND
OUT0
VIO
12
5
1
OUT3
REF
16
RTE Package
16-Pin WQFN
Top View
Not to scale
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
REF
1
I/O
When using internal reference, this is the reference output voltage pin (default). When using an
external reference, this is the reference input pin to the device.
OUT0
2
O
Analog output voltage from DAC 0.
OUT1
3
O
Analog output voltage from DAC 1.
OUT2
4
O
Analog output voltage from DAC 2.
OUT3
5
O
Analog output voltage from DAC 3.
GND
6
GND
Ground reference point for all circuitry on the device.
VDD
7
PWR
Analog supply voltage (2.7 V to 5.5 V).
GAIN
8
I
Sets the gain configuration after a power-up or reset event. When tied to GND, the initial buffer
amplifier gain for all four channels is set to 1. When tied to VIO the initial buffer amplifier gain is 2.
Changing the state of this pin after power-up does not affect the device operation.
RSTSEL
9
I
Reset select pin. When tied to GND all four DACs reset to zero scale. When connected to VIO all four
DACs reset to midscale.
REFDIV
10
I
Sets the reference divider configuration after a power-up or reset event. When tied to GND, the
reference voltage is not divided down. When tied to VIO the reference voltage is divided by 2. Changing
the state of this pin after power-up does not affect the device operation.
LDAC
11
I
A high-to-low transition on the LDAC pin causes the DAC outputs of those channels configured in
synchronous mode to update simultaneously. The pin can be tied permanently to GND.
CS
12
I
Active low serial data enable. This input is the frame synchronization signal for the serial data. When
the signal goes low, it enables the serial interface input shift register.
SCLK
13
I
Serial interface clock.
SDI
14
I
Serial interface data input. Data are clocked into the input shift register on each falling edge of the
SCLK pin.
Serial interface data output (default). The SDO pin is in high impedance when CS pin is high. Data are
clocked out of the input shift register on either rising or falling edges of the SCLK pin as specified by
the FSDO bit. Alternatively the pin can be configured as an ALARM open-drain output to indicate a
CRC or reference alarm event. If configured as ALARM a 10 kΩ, pull-up resistor to VIO is required.
SDO/ALARM
15
O
VIO
16
PWR
IO supply voltage (1.7 V to 5.5 V). This pin sets the I/O operating voltage for the serial interface.
Thermal Pad
–
–
The thermal pad is located on the bottom-side of the QFN package. The thermal pad should be
connected to any internal PCB ground plane using multiple vias for good thermal performance.
4
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Suppy voltage
Pin voltage
Input current
Temperature
(1)
(1)
MIN
MAX
VDD to GND
–0.3
6
UNIT
VIO to GND
–0.3
6
DAC outputs to GND
–0.3
VDD + 0.3
REF to GND
–0.3
VDD + 0.3
GAIN, LDAC, REFDIV, RSTSEL, SCLK, SDI, SDO/ALARM
and CS to GND
–0.3
VIO + 0.3
Input current to any pin except supply pins
–10
10
Operating free-air, TA
–40
125
Junction, TJ
–40
150
Storage, Tstg
–60
150
V
V
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
VDD
Analog supply voltage
2.7
5.5
VIO
IO supply voltage
1.7
5.5
0
VIO
Reference divider disabled
1.2
(VDD – 0.2)/2
Reference divider enabled
2.4
VDD – 0.2
Reference divider disabled
1.2
VDD/2
Reference divider enabled
2.4
VDD
–40
125
V
DIGITAL INPUTS
Digital input voltage
V
REFERENCE INPUT
VDD = 2.7 V to 3.3 V
VREFIN
VDD = 3.3 V to 5.5 V
V
TEMPERATURE
TA
Operating free-air temperature
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7.4 Thermal Information
DACx0504
THERMAL METRIC (1)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
33.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
29.5
°C/W
RθJB
Junction-to-board thermal resistance
7.3
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
7.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
all minimum and maximum specifications at VDD= 2.7 V to 5.5 V, VIO = 1.7 V to 5.5 V, VREFIN = 1.25 V to 5.5 V, RLOAD = 2 kΩ
to GND, CLOAD = 200 pF to GND, digital inputs at VIO or GND, and TA = –40°C to +125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE (1)
DAC80504
16
DAC70504
14
Resolution
INL
DNL
Bits
DAC80504
±0.5
±1
DAC70504
±0.5
±1
DAC80504. Specified 16-bit monotonic
±0.5
±1
DAC70504. Specified 14-bit monotonic
±0.5
±1
±0.06
±0.14
±0.1
±0.2
±0.75
±1.5
mV
0.5
1.5
mV
±0.075
±0.14
±0.1
±0.22
±0.05
±0.14
Integral nonlinearity
LSB
Differential nonlinearity
LSB
Gain = 1 and Gain = 2
TUE
Total unadjusted error
%FSR
Gain = ½
Offset error
Zero-code error
DAC code = zero scale
Gain = 1 and Gain = 2
Full-scale error
% FSR
Gain = ½
Gain error
% FSR
Offset error drift
±1
Zero-code error drift
±2
µV/°C
Full-scale error drift
±2
ppm of FSR/°C
±1
ppm of FSR/°C
20
ppm of FSR
Gain error drift
Output voltage drift over time
TA = 25°C, DAC code = midscale, 1600 hours
µV/°C
OUTPUT CHARACTERISTICS
Voltage range
Gain = 2 (BUFF-GAIN = 1, REF-DIV = 0)
0
Gain = 1 (BUFF-GAIN = 1, REF-DIV = 1)
0
VREF
Gain = ½ (BUFF-GAIN = 0, REF-DIV = 1)
0
½ × VREF
to GND or VDD (unloaded)
Output voltage headroom
Short circuit current
(2)
Load regulation
Maximum capacitive load (3)
to GND or VDD (–5 mA ≤ IOUT ≤ 5 mA)
2 × VREF
0.004
0.15
V
to GND or VDD (–10 mA ≤ IOUT ≤ 10 mA)
0.3
to GND or VDD (–20 mA ≤ IOUT ≤ 20 mA)
0.5
DAC code = full scale, output shorted to GND
35
DAC code = zero scale, output shorted to VDD
30
mA
DAC code = midscale, -10 mA ≤ IOUT ≤ 10 mA
85
0
2
RLOAD = 2 kΩ
0
10
DAC code = midscale
nF
0.085
Ω
DAC code at GND or VDD
(2)
(3)
6
µV/mA
RLOAD = ∞
DC output impedance
(1)
V
15
Static performance specified with DAC outputs unloaded for all gain options, unless otherwise noted. End point fit between codes. 16bit: Code 256 to 65280, 14-bit: Code 128 to 16127
Temporary overload condition protection. Junction temperature can be exceeded during current limit. Operation above the specified
maximum junction temperature may impair device reliability.
Specified by design and characterization. Not tested during production.
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Electrical Characteristics (continued)
all minimum and maximum specifications at VDD= 2.7 V to 5.5 V, VIO = 1.7 V to 5.5 V, VREFIN = 1.25 V to 5.5 V, RLOAD = 2 kΩ
to GND, CLOAD = 200 pF to GND, digital inputs at VIO or GND, and TA = –40°C to +125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
Output voltage settling time
¼ to ¾ scale and ¾ to ¼ scale settling time to ±2
LSB, VDD = 5.5 V, VREFIN = 2.5 V, Gain = 2
Slew rate
VDD = 5.5 V, VREFIN = 2.5 V, Gain = 2
1.8
V/µs
Power-up time
DACx-PWDWN 1 to 0 transition, DAC code = full
scale, VDD = 5.5 V, VREFIN = 2.5 V, Gain = 2 (4)
12
µs
Power-up glitch magnitude
DAC code = zero scale, VDD = 5.5 V, VREFIN = 2.5 V,
Gain = 2. CLOAD = 50 pF
25
mV
Output noise
0.1 Hz to 10 Hz, DAC code = midscale, VDD = 5.5 V,
VREFIN = 2.5 V, Gain = 2
14
µVPP
1 kHz, DAC code = midscale, VDD = 5.5 V, VREFIN =
2.5 V, Gain = 2
78
10 kHz, DAC code = midscale, VDD = 5.5 V, VREFIN =
2.5 V, Gain = 2
74
1 kHz, DAC code = full scale, VDD = 5.5 V, VREFIN =
2.5 V, Gain = 1
55
10 kHz, DAC code = full scale, VDD = 5.5 V, VREFIN =
2.5 V, Gain = 1
50
AC PSRR
DAC code = midscale, frequency = 60 Hz,
amplitude = 200 mVPP superimposed on VDD
85
dB
DC PSRR
DAC code = midscale, VDD = 5 V ± 10%
10
µV/V
Code change glitch impulse
1 LSB change around major carrier
4
nV-s
Channel-to-channel ac crosstalk
DAC code = midscale. Code 32 to full-scale swing on
adjacent channel
0.2
nV-s
Measured channel at midscale. Adjacent channel at
full scale.
10
Measured channel at midscale. All other channels at
full scale.
80
DAC code = midscale. fSCLK = 1 MHz, SDO disabled
0.1
nV-s
5
µs
Output noise density
nV/√Hz
Channel-to-channel dc crosstalk
Digital feedthrough
µV
EXTERNAL REFERENCE INPUT
Reference input current
VREFIN = 2.5 V
Reference input impedance
Reference input capacitance
25
µA
100
kΩ
5
pF
INTERNAL REFERENCE
VREFOUT
Reference output voltage
TA = 25°C
2.495
Reference output drift
Reference output impedance
Reference output noise
0.1 Hz to 10 Hz
Reference output noise density
10 kHz, REFLOAD = 10 nF
Reference load current
Reference load regulation
2.505
5
8
V
ppm/°C
0.1
Ω
15
µVPP
130
nV/√Hz
±5
mA
Source and sink
100
µV/mA
20
µV/V
TA = 25°C, 1600 hours
4.8
ppm
First cycle
190
Reference line regulation
Reference output drift over time
2.5
Reference thermal hysteresis
ppm
Additional cycle
18
DIGITAL INPUTS
VIH
High-level input voltage
VIL
Low-level input voltage
0.7 × VIO
V
0.3 × VIO
Input current
Input pin capacitance
V
±2
µA
2
pF
DIGITAL OUTPUTS
VOH
High-level output voltage
ILOAD = 0.2 mA
VOL
Low-level output voltage
ILOAD = -0.2 mA
VIO – 0.4
V
0.4
Output pin capacitance
(4)
4
V
pF
Time to exit DAC power-down mode. Measured from CS rising edge to 90% of DAC final value.
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Electrical Characteristics (continued)
all minimum and maximum specifications at VDD= 2.7 V to 5.5 V, VIO = 1.7 V to 5.5 V, VREFIN = 1.25 V to 5.5 V, RLOAD = 2 kΩ
to GND, CLOAD = 200 pF to GND, digital inputs at VIO or GND, and TA = –40°C to +125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Active mode. Internal reference enabled. Gain = 1.
DAC code = full scale. Outputs unloaded. SPI static
2.8
3.6
Active mode. Internal reference disabled. Gain = 1.
DAC code = full scale. Outputs unloaded. SPI static
2.3
3
Power-down
15
30
µA
2
3
µA
POWER SUPPLY REQUIREMENTS
mA
IDD
VDD supply current
IIO
VIO supply current
8
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7.6 Typical Characteristics
1
1
0.8
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
At TA = 25°C, VDD = 5.5 V, Internal Reference = 2.5 V, Gain = 2, DAC outputs unloaded, unless otherwise noted.
0.2
0
-0.2
-0.4
0
-0.2
-0.4
OUT0
OUT1
OUT2
OUT3
-0.6
-0.8
OUT0
OUT1
OUT2
OUT3
-0.6
-0.8
-1
-1
0
2048
4096
6144
8192 10240 12288 14336 16384
Code
D001
0
Figure 1. Integral Linearity Error vs Digital Input Code
1
0.105
0.8
0.07
0.035
0
-0.035
-0.07
OUT0
OUT1
OUT2
OUT3
-0.105
2048
4096
6144
8192 10240 12288 14336 16384
Code
D002
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-1
-40
8192 10240 12288 14336 16384
Code
D003
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
D004
Figure 4. Integral Linearity Error vs Temperature
1
0.14
DNL Max
DNL Min
TUE
Total Unadjusted Error (%FSR)
0.8
DNL Error Max-Min (LSB)
6144
INL Max
INL Min
Figure 3. Total Unadjusted Error vs Digital Input Code
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-40
4096
-0.8
-0.14
0
2048
Figure 2. Differential Linearity Error vs Digital Input Code
0.14
INL Error Max-Min (LSB)
Total Unadjusted Error (%FSR)
0.2
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
0.105
0.07
0.035
0
-0.035
-0.07
-0.105
-0.14
-40
-25
-10
D005
Figure 5. Differential Linearity Error vs Temperature
5
20 35 50 65
Temperature (qC)
80
95
110 125
D006
Figure 6. Total Unadjusted Error vs Temperature
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Typical Characteristics (continued)
At TA = 25°C, VDD = 5.5 V, Internal Reference = 2.5 V, Gain = 2, DAC outputs unloaded, unless otherwise noted.
1.5
1.5
Zero Code Error (mV)
Offset Error (mV)
1
0.5
0
-0.5
1
0.5
-1
-1.5
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
0
-40
110 125
Figure 7. Offset Error vs Temperature
0.105
0.105
Full Scale Error (%FSR)
0.14
Gain Error (%FSR)
0.07
0.035
0
-0.035
-0.07
-0.105
-25
-10
5
20 35 50 65
Temperature (qC)
80
80
95
110 125
D008
0.035
0
-0.035
-0.07
95
-0.14
-40
110 125
-25
-10
5
D009
20 35 50 65
Temperature (qC)
80
95
110 125
D010
Figure 10. Full Scale Error vs Temperature
1
INL Max
INL Min
0.8
DNL Max
DNL Min
0.8
0.6
DNL Error Max-Min (LSB)
INL Error Max-Min (LSB)
20 35 50 65
Temperature (qC)
0.07
Figure 9. Gain Error vs Temperature
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
3.1
3.5
3.9
4.3
VDD (V)
4.7
5.1
5.5
-1
2.7
3.1
D011
Gain = 1
3.5
3.9
4.3
VDD (V)
4.7
5.1
5.5
D012
Gain = 1
Figure 11. Integral Linearity Error vs Supply Voltage
10
5
-0.105
1
-1
2.7
-10
Figure 8. Zero Code Error vs Temperature
0.14
-0.14
-40
-25
D007
Figure 12. Differential Linearity Error vs Supply Voltage
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Typical Characteristics (continued)
At TA = 25°C, VDD = 5.5 V, Internal Reference = 2.5 V, Gain = 2, DAC outputs unloaded, unless otherwise noted.
1.5
REF-DIV = 1
REF-DIV = 0
0.105
REF-DIV = 1
REF-DIV = 0
1
0.07
Offset Error (mV)
Total Unadjusted Error (%FSR)
0.14
0.035
0
-0.035
0.5
0
-0.5
-0.07
-1
-0.105
-0.14
2.7
3.1
3.5
3.9
4.3
VDD (V)
4.7
5.1
-1.5
2.7
5.5
Gain = 1
3.9
4.3
VDD (V)
4.7
5.1
5.5
D014
Figure 14. Offset Error vs Supply Voltage
1.5
0.14
REF-DIV = 1
REF-DIV = 0
1.25
REF-DIV = 1
REF-DIV = 0
0.105
0.07
Gain Error (%FSR)
Zero Code Error (mV)
3.5
Gain = 1
Figure 13. Total Unadjusted Error vs Supply Voltage
1
0.75
0.5
0.035
0
-0.035
-0.07
0.25
0
2.7
-0.105
3.1
3.5
3.9
4.3
VDD (V)
4.7
5.1
-0.14
2.7
5.5
3.5
3.9
4.3
VDD (V)
4.7
5.1
5.5
D016
Gain = 1
Figure 15. Zero Code Error vs Supply Voltage
Figure 16. Gain Error vs Supply Voltage
0.14
1
REF-DIV = 1
REF-DIV = 0
INL Max
INL Min
0.8
INL Error Max-Min (LSB)
0.105
0.07
0.035
0
-0.035
-0.07
-0.105
-0.14
2.7
3.1
D015
Gain = 1
Full Scale Error (%FSR)
3.1
D013
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
3.1
3.5
3.9
4.3
VDD (V)
4.7
5.1
5.5
-1
1.25
2
D017
Gain = 1
2.75
3.5
VREFIN (V)
4.25
5
5.5
D018
Gain = 1
Figure 17. Full Scale Error vs Supply Voltage
Figure 18. Integral Linearity Error vs Reference Voltage
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Typical Characteristics (continued)
At TA = 25°C, VDD = 5.5 V, Internal Reference = 2.5 V, Gain = 2, DAC outputs unloaded, unless otherwise noted.
1
0.14
DNL Error Max-Min (LSB)
Total Unadjusted Error (%FSR)
DNL Max
DNL Min
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
1.25
2
2.75
3.5
VREFIN (V)
4.25
5
0.035
0
-0.035
-0.07
-0.105
2.75
3.5
VREFIN (V)
4.25
5
5.5
D020
Gain = 1
Figure 20. Total Unadjusted Error vs Reference Voltage
1.5
1.5
REF-DIV = 0
REF-DIV = 1
1
REF-DIV = 0
REF-DIV = 1
Zero Code Error (mV)
1.25
0.5
0
-0.5
-1
1
0.75
0.5
0.25
-1.5
1.25
2
2.75
3.5
VREFIN (V)
4.25
5
0
1.25
5.5
2.75
3.5
VREFIN (V)
4.25
5
5.5
D022
Gain = 1
Figure 21. Offset Error vs Reference Voltage
Figure 22. Zero Code Error vs Reference Voltage
0.14
0.14
REF-DIV = 0
REF-DIV = 1
REF-DIV = 0
REF-DIV = 1
0.105
Full Scale Error (%FSR)
0.105
0.07
0.035
0
-0.035
-0.07
0.07
0.035
0
-0.035
-0.07
-0.105
-0.105
-0.14
1.25
2
D021
Gain = 1
Gain Error (%FSR)
2
D019
Figure 19. Differential Linearity Error vs Reference Voltage
Offset Error (mV)
0.07
-0.14
1.25
5.5
Gain = 1
2
2.75
3.5
VREFIN (V)
4.25
5
5.5
-0.14
1.25
2
D023
Gain = 1
2.75
3.5
VREFIN (V)
4.25
5
5.5
D024
Gain = 1
Figure 23. Gain Error vs Reference Voltage
12
REF-DIV = 0
REF-DIV = 1
0.105
Figure 24. Full Scale Error vs Reference Voltage
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Typical Characteristics (continued)
At TA = 25°C, VDD = 5.5 V, Internal Reference = 2.5 V, Gain = 2, DAC outputs unloaded, unless otherwise noted.
3
3
3.2
3.2
2.8
2.8
2.4
2.4
2.5
1.5
1.5
IDD, Gain = 2
IIO, Gain = 2 1
IDD, Gain = 1
IIO, Gain = 1
0.5
1
0.5
0
0
2048
4096
6144
IDD (mA)
2
IIO (PA)
2
2
0.8
0.4
0.4
1.2
0
8192 10240 12288 14336 16384
Code
D025
0
0
Gain = 1. External Reference = 2.5 V
3
4096
6144
0
8192 10240 12288 14336 16384
Code
D026
Figure 26. Supply Current with Internal Reference vs
Digital Input Code
3
3.6
3.6
3.2
3.2
2.8
2.8
2.4
2.4
2.5
1
IDD, Gain = 2
IIO, Gain = 2 1.5
IDD, Gain = 1
IIO, Gain = 1
1
0.5
0.5
1.5
0
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
IDD (mA)
2
IIO (PA)
2
2
2
0.8
IDD, Gain = 2 1.6
IIO, Gain = 2
IDD, Gain = 1 1.2
IIO, Gain = 1
0.8
0.4
0.4
1.6
1.2
0
110 125
0
-40
-25
-10
5
D027
Gain = 1. External Reference = 2.5 V
20 35 50 65
Temperature (qC)
80
95
IIO (PA)
2.5
IDD (mA)
2048
Gain = 1
Figure 25. Supply Current with External Reference vs
Digital Input Code
0
110 125
D028
Gain = 1
Figure 27. Supply Current with External Reference vs
Temperature
3
Figure 28. Supply Current with Internal Reference vs
Temperature
3
2.5
3.6
3.6
3.2
3.2
2.8
2.8
2.4
2.4
2.5
1.5
1.5
1
1
IDD
IIO
0.5
IDD (mA)
2
IIO (PA)
2
IDD (mA)
2
IDD, Gain = 2 1.6
IIO, Gain = 2
IDD, Gain = 1 1.2
IIO, Gain = 1
0.8
1.6
2
2
1.6
1.2
1.6
IDD
IIO 1.2
0.8
0.8
0.4
0.4
IIO (PA)
IDD (mA)
3.6
IIO (PA)
2.5
3.6
0.5
0
2.7
3.1
3.5
3.9
4.3
VDD (V)
4.7
5.1
0
5.5
0
2.7
3.1
D029
Gain = 1. External Reference = 2.5 V
3.5
3.9
4.3
VDD (V)
4.7
5.1
0
5.5
D030
Gain = 1
Figure 29. Supply Current with External Reference vs
Supply Voltage
Figure 30. Supply Current with Internal Reference vs
Supply Voltage
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Typical Characteristics (continued)
At TA = 25°C, VDD = 5.5 V, Internal Reference = 2.5 V, Gain = 2, DAC outputs unloaded, unless otherwise noted.
1
4
Code 0x0000
Code 0x1000
Code 0x2000
Code 0x3000
Code 0x3FFF
0.8
3
0.6
DAC Output (V)
'VOUT (V)
0.4
0.2
0
-0.2
-0.4
Sourcing 5.5V
Sourcing 2.7V
Sinking 5.5V
Sinking 2.7V
-0.6
-0.8
5
10
15
20
Load Current (mA)
25
1
0
-1
-1
0
2
-2
-60
30
-40
D033
Figure 31. Headroom/Footroom vs Load Current
-20
0
20
Load Current (mA)
40
60
D034
Figure 32. Source and Sink Capability with Gain = ½
7
4
6
0x3FFF
0x3000
2
0x2000
1
0x1000
0x0000
0
0x3FFF
5
DAC Output (V)
DAC Output (V)
3
0x3000
4
3
0x2000
2
0x1000
1
0x0000
0
-1
-1
-2
-60
-40
-20
0
20
Load Current (mA)
40
60
-2
-60
-40
D035
Figure 33. Source and Sink Capability with Gain = 1
40
60
D036
Figure 34. Source and Sink Capability with Gain = 2
Small Signal VOUT (3 LSB/div)
Large Signal VOUT (2 V/div)
CS (5 V/div)
Small Signal VOUT (3 LSB/div)
Large Signal VOUT (2 V/div)
CS (5 V/div)
Time (2 Psec/div)
Time (2 Psec/div)
D037
Gain = 1
D038
Gain = 1
Figure 35. Full-Scale Settling Time, Rising Edge
14
-20
0
20
Load Current (mA)
Figure 36. Full-Scale Settling Time, Falling Edge
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Typical Characteristics (continued)
At TA = 25°C, VDD = 5.5 V, Internal Reference = 2.5 V, Gain = 2, DAC outputs unloaded, unless otherwise noted.
VOUT (2.5 mV/div)
CS (5 V/div)
VOUT (2.5mV/div)
CS (5 V/div)
Time (0.5 Ps/div)
Time (0.5 Ps/div)
D039
Gain = 1
D040
Gain = 1
Figure 37. Glitch Impulse, Falling Edge, 1 LSB Step
Figure 38. Glitch Impulse, Rising Edge, 1 LSB Step
VDD (1.5 V/div)
VOUT (1 V/div)
VDD (1.5 V/div)
VOUT (10 mV/div)
Time (600Ps/div)
Time (600 Ps/div)
D042
D041
Gain = 1
Gain = 1
Figure 39. Power-On, Reset to Zero Scale
Figure 40. Power-On, Reset to Midscale
VDD (1.5 V/div)
VOUT (1 V/div)
VIO (1.5 V/div)
VOUT (1 V/div)
Time (600Ps/div)
Time (600Ps/div)
D044
Gain = 1. DAC code at midscale
D060
Gain = 1. DAC code at midscale
Figure 41. VDD Power-Down
Figure 42. VIO Power-Down
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Typical Characteristics (continued)
At TA = 25°C, VDD = 5.5 V, Internal Reference = 2.5 V, Gain = 2, DAC outputs unloaded, unless otherwise noted.
SCLK (5 V/div)
VOUT (1 mV/div)
VOUT (200 PV/div)
CS (5 V/div)
Time (2 Psec/div)
Time (5 Psec/div)
D045
D046
Gain = 1. Measured DAC at midscale. All other DACs switch from
code 32 to full scale
Gain = 1. DAC code at midscale
Figure 43. Channel to Channel Crosstalk
Figure 44. Clock Feedthrough with SCLK = 1 MHz
0
300
Gain = 1
Gain = 2
-10
-20
250
-30
Noise (nV/—Hz)
AC PSRR (dB)
-40
-50
-60
-70
-80
200
150
100
-90
-100
50
-110
-120
1
10
100
1000
Frequency (Hz)
10000
0
10 2030 50 100 200
100000
D047
Gain = 1. VDD = 5 V + 200 mVPP (Sinusoid). DAC code at fullscale
100000
D048
VNOISE (2 PV/div)
Figure 46. DAC Output Noise Density vs Frequency
D049
Gain = 1. External Reference = 2.5 V. DAC code at midscale
Figure 47. DAC Output Noise with External Reference
0.1 Hz to 10 Hz
16
10000
External Reference = 2.5 V. DAC code at midscale
Figure 45. DAC Output AC PSRR vs Frequency
VNOISE (2 PV/div)
5001000
Frequency (Hz)
D050
Gain = 1. DAC code at midscale
Figure 48. DAC Output Noise with Internal Reference
0.1 Hz to 10 Hz
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Typical Characteristics (continued)
2.505
2.505
2.5025
2.5025
Internal Reference (V)
Internal Reference (V)
At TA = 25°C, VDD = 5.5 V, Internal Reference = 2.5 V, Gain = 2, DAC outputs unloaded, unless otherwise noted.
2.5
2.4975
2.495
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
2.5
2.4975
2.495
2.7
110 125
3.1
3.5
3.9
4.3
VDD (V)
D051
Figure 49. Internal Reference Voltage vs Temperature
4.7
5.1
5.5
D053
Figure 50. Internal Reference Voltage vs Supply Voltage
2.505
800
2.5025
600
Noise (nV/—Hz)
Internal Reference (V)
700
2.5
2.4975
500
400
300
200
100
2.495
0
200
400
600
800 1000
Hours
1200
1400
0
10 2030 50 100 200
1600
D055
Figure 51. Internal Reference Voltage vs Time
5001000
Frequency (Hz)
10000
100000
D056
Figure 52. Internal Reference Noise Density vs Frequency
40
35
Number of Units
VNOISE (2 PV/div)
30
25
20
15
10
5
0
0
1
2
3
Temperature Drift (ppm/qC)
D057
4
5
D058
0.1 Hz to 10 Hz
Figure 53. Internal Reference Noise
Figure 54. Internal Reference Temperature Drift Histogram
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8 Detailed Description
8.1 Overview
The DACx0504 is a pin-compatible family of low-power, four-channel, buffered voltage-output digital-to-analog
converters (DACs) with 16- and 14-bit resolution. The DACx0504 includes a 2.5 V internal reference and userselectable gain configuration. providing full-scale output voltages of 1.25 V (gain = ½), 2.5 V (gain = 1), or 5 V
(gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is specified monotonic, and provides high
linearity of ±1 LSB INL.
Communication to the DACx0504 is performed through a 4-wire serial interface that supports stand-alone and
daisy-chain operation. The optional frame-error checking provides added robustness to the DACx0504 serial
interface.
The DACx0504 incorporates a power-on-reset circuit and RSTSEL pin that powers up and maintains the DAC
outputs at either zero scale or midscale until a valid code is written to the device.
8.2 Functional Block Diagram
VIO
VDD
REFDIV
REF
GAIN
Internal
Reference
DACx0504
÷1 or ÷2
GAIN
×1 or ×2
SCLK
DAC
Buffer
SDO/ALARM
CS
Interface Logic
SDI
LDAC
DAC
Register
DAC
OUT0
BUF
Channel 0
Channel 1
OUT1
Channel 2
OUT2
Channel 3
OUT3
Power On Reset
RSTSEL
Power Down Logic
Resistive Network
GND
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8.3 Feature Description
8.3.1 Digital-to-Analog Converter (DAC)
Each output channel in the DACx0504 consists of an R-2R ladder architecture followed by an output buffer
amplifier. Figure 55 shows a block diagram of the DAC architecture.
REF
2.5-V
Reference
REF Divider
(÷1 or ÷2)
Serial Interface
DAC Data Register
READ
DIV
GAIN
WRITE
DAC
Buffer
Register
DAC
Active
Register
R-2R
Gain
(×1 or ×2)
VOUT
DAC Output
(asynchronous mode)
LDAC Trigger
(synchronous mode)
GND
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Figure 55. DACx0504 DAC Block Diagram
8.3.1.1 DAC Transfer Function
The input data are written to the individual DAC data registers in straight binary format. After a power-on or a
reset event, all DAC registers are set to either zero code or midscale code, as determined by the RSTSEL pin.
The DAC transfer function is given by Equation 1.
CODE VREF
VOUT
u
u GAIN
DIV
2n
where
•
•
•
•
•
CODE = decimal equivalent of the binary code that is loaded to the DAC register. CODE ranges from 0 to 2n –
1.
VREF = DAC reference voltage. Either VREFOUT from the internal 2.5 V reference or VREFIN if using an external
one.
n = resolution in bits. Either 14 (DAC70504) or 16 (DAC80504)
DIV = 1 or 2 as set by the REFDIV pin after a reset event or by the REF-DIV bit in the GAIN register.
GAIN = 1 or 2 as set by the GAIN pin after a reset event or by the BUFF-GAIN bit for that DAC channel in the
GAIN register.
(1)
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Feature Description (continued)
8.3.1.2 Output Amplifiers
The DACx0504 output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving a
maximum output range of 0 V to VDD. Each buffer amplifier is capable of driving a load of 2 kΩ in parallel with
10 nF to GND.
The full-scale output voltage for each channel is determined by the reference voltage (VREF), the reference
divider setting (DIV), and the output buffer gain for that channel (GAIN), as shown in Table 1. After a power-up or
reset event the DIV and GAIN settings are set by the REFDIV and GAIN pins, respectively. During normal
operation the DIV and GAIN settings can be reconfigured through the REF-DIV and BUFF-GAIN bit (see
Equation 1). The GAIN setting for each output channel can be individually configured thus enabling independent
output voltage ranges for each DAC output.
Table 1. DAC Output Range Configuration
DIV SETTING
GAIN SETTING
÷2
×1
0 V to ½ × VREF
DAC OUTPUT RANGE
÷1
×1
Not recommended
÷2
×2
0 V to VREF
÷1
×2
0 V to 2 × VREF
8.3.1.3 DAC Register Structure
Data written to the DAC data registers is initially stored in the DAC buffer registers. Transfer of data from the
DAC buffer registers to the active DAC registers can be configured to happen immediately (asynchronous mode)
or initiated by an LDAC trigger (synchronous mode). Once the DAC active registers are updated, the DAC
outputs change to their new values. When the host reads from a DAC Data register, the value held in the DAC
buffer register is returned (not the value held in the DAC active register).
8.3.1.3.1 DAC Register Synchronous and Asynchronous Updates
The update mode for each DAC channel is determined by the status of its corresponding SYNC-EN bit. In
asynchronous mode, a write to the DAC data register results in an immediate update of the DAC active register
and DAC output on CS rising edge. In synchronous mode, writing to the DAC data register does not
automatically update the DAC output. Instead the update occurs only after an LDAC trigger event. An LDAC
trigger is generated either through the LDAC bit in the TRIGGER register or by the LDAC pin. The synchronous
update mode enables simultaneous update of multiple DAC outputs. In both update modes a minimum wait time
of 1 µs is required between DAC output updates.
8.3.1.3.2 Broadcast DAC Register
The DAC broadcast register enables a simultaneous update of multiple DAC outputs with the same value with a
single register write. Each DAC channel can be configured to update or remain unaffected by a broadcast
command by setting the corresponding DAC-BRDCAST-EN bit in the SYNC register. A register write to the
BRDCAST-DATA register forces those DAC channels that have been configured for broadcast operation to
update their outputs. The DAC ouputs update to the broadcast value on CS rising edge independently of their
synchronous mode configuration.
20
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8.3.2 Internal Reference
The DACx0504 includes a 2.5 V precision bandgap reference enabled by default. Operation from an external
reference is supported by disabling the internal reference in the CONFIG register. The internal reference is
externally available at the REF pin.
A minimum 150 nF capacitor is recommended between the reference output and GND for noise filtering.
8.3.2.1 Reference Divider
The reference voltage to the device, either from the internal reference or an external one can be divided by a
factor of two by tying the REFDIV pin high at power-up or by setting the REF-DIV bit in the GAIN register to 1
during normal operation. The reference voltage divider provides additional flexibility in setting the full-scale output
voltage for each DAC output and must be configured to make certain that there is sufficient headroom from VDD
to the DAC operating reference voltage (VREF/DIV). See the Recommended Operating Conditions table for more
information.
Improper configuration of the reference divider issues a reference alarm condition. In this case, the reference
buffer is shut down, and all the DAC outputs go to 0 V. The DAC data registers are unaffected by the alarm
condition thus enabling the DAC output to return to normal operation once the reference divider is configured
correctly. The reference alarm status can be read from the REF-ALM bit in the STATUS register. Additionally by
setting ALM-EN = 1 and ALM-SEL = 1 in the CONFIG register, the SDO/ALARM pin is configured as a reference
alarm pin.
8.3.2.2 Solder Heat Reflow
A known behavior of IC reference voltage circuits is the shift induced by the soldering process. Figure 56 shows
the effect of solder heat reflow for the DACx0504 internal reference.
70%
Precentage of Units
60%
Presolder Heat Reflow
Postsolder Heat Reflow
50%
40%
30%
20%
10%
0
2.4975 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010
VREFOUT (V)
D059
Figure 56. Solder Heat Reflow Reference Voltage Shift
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8.3.3 Device Reset Options
8.3.3.1 Power-on-Reset (POR)
The DACx0504 includes a power-on reset function that controls the output voltage at power up. After the VDD
and VIO supplies have been established a POR event is issued. The POR causes all registers to initialize to their
default values and communication with the device is valid only after a 250 µs power-on-reset delay. The default
value for all DACs is either zero-code or midscale-code as determined by the RSTSEL pin. Each DAC channel
remains at the power-up voltage until a valid command is written to it.
The POR circuit requires specific supply levels to discharge the internal capacitors and to reset the device on
power up, as indicated in Figure 57 and Figure 58. In order to initiate a POR event, VDD or VIO must be below
their corresponding low thresholds for at least 100 µs. If VDD and VIO remain above their specified high threshold
a POR event will not occur. When the supplies drop below their high threshold but remain over the lower one
(shown as the undefined region), the device may or may not reset under all specified temperature and powersupply conditions.
VDD (V)
VIO (V)
5.50
5.50
No Power-On Reset
Specified Supply
Voltage Range
No Power-On Reset
Specified Supply
Voltage Range
2.70
2.20
Undefined
1.70
1.50
1.20
Undefined
0.70
Power-On Reset
Power-On Reset
0.00
0.00
Figure 57. Threshold Levels for VDD POR Circuit
Figure 58. Threshold Levels for VIO POR Circuit
8.3.3.2 Software Reset
A device software reset event is initiated by writing the reserved code 0x1010 to SOFT-RESET in the TRIGGER
register. The software reset command is triggered on the CS rising edge of the instruction. A software reset
initiates a POR event.
22
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8.4 Device Functional Modes
8.4.1 Stand-Alone Operation
A serial interface access cycle is initiated by asserting the CS pin low. The serial clock SCLK can be a
continuous or gated clock. SDI data are clocked on SCLK falling edges. A regular serial interface access cycle is
24 bits long with error checking disabled and 32 bits long with error checking enabled, thus the CS pin must stay
low for at least 24 or 32 SCLK falling edges. The access cycle ends when the CS pin is de-asserted high. If the
access cycle contains less than the minimum clock edges, the communication is ignored. If the access cycle
contains more than the minimum clock edges are present, only the last 24 or 32 bits are used by the device.
When CS is high, the SCLK and SDI signals are blocked and the SDO pin is in a Hi-Z state.
In an error checking disabled access cycle (24-bits long) the first byte input to SDI is the instruction cycle which
identifies the request as a read or write command and the 4-bit address to be accessed. The following bits in the
cycle form the data cycle, as shown in Table 2.
Table 2. Serial Interface Access Cycle
BIT
FIELD
23
RW
22:20
Reserved
19:16
A[3:0]
15:0
DI[15:0]
DESCRIPTION
Identifies the communication as a read or write command to the addressed register. R/W = 0 sets a
write operation. R/W = 1 sets a read operation.
Reserved bits. Must be filled with zeros.
Register address. Specifies the register to be accessed during the read or write operation.
Data cycle bits. If a write command, the data cycle bits are the values to be written to the register with
address A[3:0]. If a read command, the data cycle bits are don’t care values.
A read operation is initiated by issuing a read command access cycle. After the read command, a second access
cycle must be issued to get the requested data, as shown in Table 3. Data are clocked out on SDO pin either on
the falling edge or rising edge of SCLK according to the FSDO bit in the CONFIG register.
Table 3. SDO Output Access Cycle
BIT
FIELD
23
RW
22:20
Reserved
19:16
A[3:0]
15:0
DO[15:0]
DESCRIPTION
Echo RW from previous access cycle.
Echo bits 22:20 from previous access cycle (all zeros).
Echo address from previous access cycle.
Readback data requested on previous access cycle.
8.4.2 Daisy-Chain Operation
For systems that contain more than one DACx0504 devices, the SDO pin can be used to daisy-chain them
together. Daisy-chain operation is useful in reducing the number of serial interface lines.
The first falling edge on the CS pin starts the operation cycle. If more than 24 SCLK pulses are applied while the
CS pin is kept low, the data ripples out of the shift register and is clocked out on the SDO pin either on the falling
edge or rising edge of SCLK according to the FSDO bit. By connecting the SDO output of the first device to the
SDI input of the next device in the chain, a multiple-device interface is constructed. Each device in the system
requires 24 clock pulses. As a result the total number of clock cycles must be equal to 24 × N, where N is the
total number of DACx0504 devices in the daisy chain. When the serial transfer to all devices is complete the CS
signal is taken high. This action transfers the data from the serial peripheral interface (SPI) shift registers to the
internal registers of each device in the daisy chain and prevents any further data from being clocked into the
input shift register.
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C
B
DACx0504
DACx0504
DACx0504
SDO
SDI
A
SDI
SDO
SDI
SCLK
SCLK
SCLK
CS
CS
CS
SDO
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Figure 59. Daisy-Chain Layout
8.4.3 Frame Error Checking
If the DACx0504 is used in a noisy environment, error checking can be used to check the integrity of SPI data
communication between the device and the host processor. This feature can be enabled by setting the CRC-EN
bit in the CONFIG register.
The error checking scheme is based on the CRC-8-ATM (HEC) polynomial x8 + x2 + x + 1 (that is, 100000111).
When error checking is enabled, the serial interface access cycle width is 32 bits. The normal 24-bit SPI data are
appended with an 8-bit CRC polynomial by the host processor before feeding it to the device, as shown in
Table 4. In all serial interface readback operations the CRC polynomial is output on the SDO pin as part of the
32-bit cycle.
Table 4. Error Checking Serial Interface Access Cycle
BIT
FIELD
31
RW
30
CRC-ERROR
29:28
Reserved
27:24
A[3:0]
23:8
DI[15:0]
7:0
CRC
DESCRIPTION
Identifies the communication as a read or write command to the addressed register. R/W = 0 sets a
write operation. R/W = 1 sets a read operation.
Reserved bit. Set to zero.
Reserved bits. Must be filled with zeros.
Register address. Specifies the register to be accessed during the read or write operation.
Data cycle bits. If a write command, the data cycle bits are the values to be written to the register with
address A[3:0]. If a read command, the data cycle bits are don’t care values.
8-bit CRC polynomial.
The DACx0504 decodes the 32-bit access cycle to compute the CRC remainder on CS rising edges. If no error
exists, the CRC remainder is zero and data are accepted by the device.
A write operation failing the CRC check causes the data to be ignored by the device. After the write command, a
second access cycle can be issued to determine the error checking result (CRC-ERROR bit) on the SDO pin, as
shown in Table 5. Additionally, by setting ALM-EN = 1 and ALM-SEL = 0 in the CONFIG register, the
SDO/ALARM pin is configured as a CRC alarm pin.
Table 5. Write Operation Error Checking Cycle
BIT
24
FIELD
DESCRIPTION
31
RW
30
CRC-ERROR
Echo RW from previous access cycle (RW = 0).
Returns a 1 when a CRC error is detected, 0 otherwise.
29:28
Reserved
Echo bits 29:28 from previous access cycle (all zeros).
27:24
A[3:0]
23:8
DO[15:0]
7:0
CRC
Echo address from previous access cycle.
Echo data from previous access cycle.
Calculated CRC value of bits 31:8.
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A read operation must be followed by a second access cycle to get the requested data on the SDO pin. The
error check result (CRC-ERROR bit) from the read command is output on the SDO pin, as shown in Table 6. As
in the case of a write operation failing the CRC check, the SDO/ALARM pin if configured as a CRC alarm pin can
be used to indicate a read command CRC failure.
Table 6. Read Operation Error Checking Cycle
BIT
FIELD
31
RW
DESCRIPTION
30
CRC-ERROR
Returns a 1 when a CRC error is detected, 0 otherwise.
29:28
Reserved
Echo bits 29:28 from previous access cycle (all zeros).
27:24
A[3:0]
23:8
DO[15:0]
7:0
CRC
Echo RW from previous access cycle (RW = 1).
Echo address from previous access cycle.
Readback data requested on previous access cycle.
Calculated CRC value of bits 31:8.
8.4.4 Power-Down Mode
The DACx0504 DAC output amplifiers and internal reference can be independently powered down through the
CONFIG register. At power-up all output channels and the device internal referece are active by defaul. A DAC
output channel in power-down mode is connected internally to GND through a 1-kΩ resistor.
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8.5 Programming
The DACx0504 is controlled through a flexible four-wire serial interface that is compatible with SPI type
interfaces used on many microcontrollers and DSP controllers. The interface provides read and write access to
all DACx0504 registers and can also be configured to daisy-chain multiple devices for write operations. The
DACx0504 incorporates an optional error checking mode to validate SPI data communication integrity in noisy
environments. Table 7 shows the SPI timing requirements. Figure 60 and Figure 61 show the SPI write and read
timing diagrams, respectively. Figure 62 shows the digital logic timing diagram.
Table 7. Programming Timing Requirements (1)
VIO = 1.7 V to 2.7 V
MIN
NOM
VIO = 2.7 V to 5.5 V
MAX
MIN
NOM
MAX
UNIT
SERIAL INTERFACE – WRITE OPERATION
fSCLK
SCLK frequency
tSCLKHIGH
SCLK high time
9
50
9
50
MHz
ns
tSCLKLOW
SCLK low time
9
9
ns
tSDIS
SDI setup
5
5
ns
tSDIH
SDI hold
10
10
ns
tCSS
CS to SCLK falling edge setup
13
13
ns
tCSH
SCLK falling edge to CS rising edge
10
10
ns
tCSHIGH
CS high time
15
15
ns
tCSIGNORE
SCLK falling edge to CS ignore
7
7
ns
SERIAL INTERFACE – READ AND DAISY CHAIN OPERATION, FSDO = 0
fSCLK
SCLK frequency
tSCLKHIGH
SCLK high time
35
12
25
18
ns
tSCLKLOW
SCLK low time
35
25
ns
tSDIS
SDI setup
5
5
ns
tSDIH
SDI hold
10
10
ns
tCSS
CS to SCLK falling edge setup
32
20
ns
tCSH
SCLK falling edge to CS rising edge
10
10
ns
tCSHIGH
CS high time
15
tSDODLY
SDO output delay from SCLK rising edge
3.5
33.5
3.5
23
ns
tSDODZ
SDO driven to tri-state
0
30
0
25
ns
tCSIGNORE
SCLK falling edge to CS ignore
7
15
MHz
ns
7
ns
SERIAL INTERFACE – READ AND DAISY CHAIN OPERATION, FSDO = 1
fSCLK
SCLK frequency
tSCLKHIGH
SCLK high time
22
20
18
25
ns
tSCLKLOW
SCLK low time
22
18
ns
tSDIS
SDI setup
5
5
ns
tSDIH
SDI hold
10
10
ns
tCSS
CS to SCLK falling edge setup
32
20
ns
tCSH
SCLK falling edge to CS rising edge
10
10
ns
tCSHIGH
CS high time
15
15
ns
tSDODLY
SDO output delay from SCLK falling edge
3.5
45
3.5
32
ns
tSDODZ
SDO driven to tri-state
0
30
0
25
ns
tCSIGNORE
SCLK falling edge to CS ignore
7
7
MHz
ns
DIGITAL LOGIC
tRSTDLYPOR
POR reset delay
tDACWAIT
Sequential DAC output updates
(1)
26
170
1
250
170
1
250
µs
µs
All input signals are specified at tR = tF = 1 ns/V (10% to 90% of VIO), timed from a voltage level of (VIL + VIH) / 2, VDD = 2.7 V to 5.5 V,
VIO = 1.7 V to 5.5 V, VREFIN = 1.25 V to 5.5 V, SDO loaded with 20 pF, and TA = –40°C to +125°C (unless otherwise noted)
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tCSHIGH
tCSS
tCSH
CS
tCSIGNORE
tSCLKLOW
SCLK
tSCLKHIGH
SDI
Bit 23
Bit 1
Bit 0
tSDIH
tSDIS
Figure 60. Serial Interface Write Timing Diagram
tCSHIGH
tCSS
tCSH
CS
tCSIGNORE
tSCLKLOW
SCLK
tSCLKHIGH
FIRST READ COMMAND
SDI
Bit 23
tSDIS
Bit 22
ANY COMMAND
Bit 0
Bit 23
Bit 1
Bit 0
Bit 23
Bit 1
Bit 0
tSDIH
SDO
FSDO = 0
tSDODZ
tSDODLY
DATA FROM FIRST READ COMMAND
SDO
FSDO = 1
Bit 23
Bit 1
Bit 0
X
tSDODZ
tSDODLY
DATA FROM FIRST READ COMMAND
Figure 61. Serial Interface Read Timing Diagram
tLDACS
tLDACH
CS
LDAC
Figure 62. Digital Logic Timing Diagram
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8.6 Register Map
Table 8. Register Map
ADDRESS BITS
REGISTER
NOP
28
TYPE
W
DATA BITS
RESET
A3
A2
A1
A0
0000
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NOP
DEVICE ID
R
—
0
0
0
1
SYNC
R/W
FF00
0
0
1
0
DEVICEID
CONFIG
R/W
0000
0
0
1
1
GAIN
R/W
0000
0
1
0
0
TRIGGER
W
0000
0
1
0
1
BRDCAST
R/W
0000
0
1
1
0
STATUS
R/W
0000
0
1
1
1
DAC0
R/W
0000
1
0
0
0
DAC0-DATA[15:0]
DAC1
R/W
0000
1
0
0
1
DAC1-DATA[15:0]
DAC2
R/W
0000
1
0
1
0
DAC2-DATA[15:0]
DAC3
R/W
0000
1
0
1
1
DAC3-DATA[15:0]
All Others
—
—
—
—
—
—
RESERVED
RESERVED
RESERVED
ALM
SEL
VERSIONID
DACx-BRDCAST-EN
ALM
EN
CRC
EN
F
SDO
D
SDO
RESERVED
RESERVED
DACx-SYNC-EN
REF
PWD
WN
RESERVED
DACx-PWDWN
REF
DIVEN
RESERVED
BUFFx-GAIN
L
DAC
RESERVED
SOFT-RESET[3:0]
BRDCAST-DATA[15:0]
REF
ALM
RESERVED
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8.6.1 NOP Register (address = 0x00) [reset = 0x0000]
Figure 63. NOP Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOP
W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. NOP Register Field Descriptions
Bit
Field
Type
Reset
Description
15:0
NOP
W
0x0000
No operation. Write 0000h for proper no-operation command
8.6.2 DEVICE ID Register (address = 0x01) [reset = 0x---]
Figure 64. DEVICE ID Register
15
14
13
12
11
10
9
8
DEVICEID
R
7
6
5
4
3
2
1
0
VERSIONID
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. DEVICE ID Field Descriptions
Bit
Field
Type
Reset
Description
15:2
DEVICEID
R
----
Device ID:
D15 Reserved - 0
D14:12 Resolution - 000 (16-bit); 001 (14-bit)
D11:4 Channels - 0100 (4 channels)
D7 Reset - Determined by RSTSEL pin. 0 (reset to zero); 1
(reset to midscale)
D6:2 Reserved - 00101
1:0
VERSIONID
R
10
Version ID. Subject to change
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8.6.3 SYNC Register (address = 0x2) [reset = 0xFF00]
Figure 65. SYNC Register
15
14
13
12
11
DAC3BRDCAST-EN
R/W
10
DAC2BRDCAST-EN
R/W
9
DAC1BRDCAST-EN
R/W
8
DAC0BRDCAST-EN
R/W
5
4
3
DAC3-SYNCEN
R/W
2
DAC2-SYNCEN
R/W
1
DAC1-SYNCEN
R/W
0
DAC0-SYNCEN
R/W
Reserved
—
7
6
Reserved
—
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. SYNC Register Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
—
1111
Reserved for factory use
11
DAC3-BRDCAST-EN
R/W
1
10
DAC2-BRDCAST-EN
R/W
1
9
DAC1-BRDCAST-EN
R/W
1
8
DAC0-BRDCAST-EN
R/W
1
When set to 1 the corresponding DAC is set to update its output
after a serial interface write to the BRDCAST register.
When cleared to 0 the corresponding DAC output remains
unaffected after a serial interface write to the BRDCAST
register.
15:12
7:4
30
Reserved
—
0000
Reserved for factory use
3
DAC3-SYNC-EN
R/W
0
2
DAC2-SYNC-EN
R/W
0
1
DAC1-SYNC-EN
R/W
0
When set to 1 the corresponding DAC output is set to update in
response to an LDAC trigger (synchronous mode).
When cleared to 0 the corresponding DAC output is set to
update immediately on a CS rising edge (asynchronous mode).
0
DAC0-SYNC-EN
R/W
0
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8.6.4 CONFIG Register (address = 0x3) [reset = 0x0000]
Figure 66. CONFIG Register
15
14
Reserved
—
7
13
ALM-SEL
R/W
12
ALM-EN
R/W
5
4
6
11
CRC-EN
R/W
10
FSDO
R/W
9
DSDO
R/W
8
REF-PWDWN
R/W
3
2
1
0
DAC3-PWDWN DAC2-PWDWN DAC1-PWDWN DAC0-PWDWN
R/W
R/W
R/W
R/W
Reserved
—
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15:14
Reserved
—
00
Reserved for factory use
13
ALM-SEL
R/W
0
ALARM select.
0: ALARM pin is CRC-ERROR
1: ALARM pin is REF-ALARM
12
ALM-EN
R/W
0
Configure SDO/ALARM pin. When 1: SDO/ALARM pin is an
active-low, open-drain, alarm pin. An external 10 kΩ pullup
resistor to VIO is required. FSDO and DSDO bits are ignored.
When 0: SDO/ALARM pin is a serial interface, push-pull, SDO
pin
11
CRC-EN
R/W
0
CRC enable bit. Set to 1 to enable CRC. Set to 0 to disable
10
FSDO
R/W
0
Fast SDO bit (half-cycle speedup). When 0, SDO updates on an
SCLK rising edge. When 1, SDO updates a half-cycle earlier,
during an SCLK falling edge.
9
DSDO
R/W
0
Disable SDO bit. When 1, SDO is always tri-stated. When 0,
SDO is driven while CS is low, and tri-stated while CS is high
8
REF-PWDWN
R/W
0
When set to 1 disables the device internal reference
Reserved
—
0000
Reserved for factory use
3
DAC3-PWDWN
R/W
0
2
DAC2-PWDWN
R/W
0
When set to 1 the corresponding DAC is set in power-down
mode and its output is connected to GND through a 1 kΩ
internal resistor.
1
DAC1-PWDWN
R/W
0
0
DAC0-PWDWN
R/W
0
7:4
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8.6.5 GAIN Register (address = 0x04) [reset = 0x---]
Figure 67. GAIN Register
15
14
7
6
13
12
Reserved
—
11
10
9
8
REFDIV-EN
R/W
5
4
3
BUFF3-GAIN
R/W
2
BUFF2-GAIN
R/W
1
BUFF1-GAIN
R/W
0
BUFF0-GAIN
R/W
Reserved
—
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. GAIN Register Field Descriptions
Bit
15:9
8
7:4
Field
Type
Reset
Description
Reserved
—
0
Reserved for factory use.
REFDIV-EN
R/W
0/1
When set to 1 the reference voltage is internally divided by a
factor of 2.
When cleared to 0 the reference voltage is unaffected.
Default value is determined by the REFDIV pin.
Reserved
—
0000
Reserved for factory use
3
BUFF3-GAIN
R/W
0/1
2
BUFF2-GAIN
R/W
0/1
1
BUFF1-GAIN
R/W
0/1
0
BUFF0-GAIN
R/W
0/1
When set to 1 the buffer amplifier for corresponding DAC has a
gain of 2.
When cleared to 0 the buffer amplifier for corresponding DAC
has a gain of 1.
Default value is determined by the GAIN pin.
8.6.6 TRIGGER Register (address = 0x05) [reset = 0x0000]
Figure 68. TRIGGER Register
15
14
13
12
11
10
Reserved
—
9
8
7
6
5
4
LDAC
W
3
2
1
SOFT-RESET[3:0]
W
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. TRIGGER Register Field Descriptions
Bit
15:5
4
3:0
32
Field
Type
Reset
Description
Reserved
—
0
Reserved for factory use.
LDAC
W
0
Set this bit to 1 to synchronously load those DACs that have
been set in synchronous mode in the SYNC register.
SOFT-RESET[3:0]
W
0x0
When set to the reserved code 1010 resets the device to its
default state.
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8.6.7 BRDCAST Register (address = 0x6) [reset = 0x0000]
Figure 69. BRDCAST Register
15
14
13
12
11
10
9
8
7
6
BRDCAST-DATA[15:0]
R/W
5
4
3
2
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. BRDCAST Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
BRDCAST-DATA[15:0]
R/W
0x0000
Writing to the BRDCAST register forces those DAC channels
that have been set to broadcast in the SYNC register to update
their active data register with the BRDCAST-DATA value.
Data are MSB aligned in straight binary format and follows the
format below:
DAC80504: { DATA[15:0] }
DAC70504: { DATA[13:0], x, x }
x – Don’t care bits
8.6.8 STATUS Register (address = 0x7) [reset = 0x0000]
Figure 70. STATUS Register
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
—
0
REFALM
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. STATUS Register Field Descriptions
Field
Type
Reset
Description
15:1
Bit
Reserved
—
0
Reserved for factory use.
0
REF-ALM
R
0
Reference alarm bit. Reads 1 when the difference between
VREF/DIV and VDD is below the required minimum analog
threshold. Reads 0 otherwise.
8.6.9 DACx Register (address = 0x8 to 0xF) [reset = 0x0000 or 0x8000]
Figure 71. DACx Register
15
14
13
12
11
10
9
8
7
DACx-DATA[15:0]
R/W
6
5
4
3
2
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. DACx Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
DACx-DATA[15:0]
R/W
0x0000 or
0x8000
Stores the 16- or 14-bit data to be loaded to DACx in MSB
aligned straight binary format. The default value is determined
by the RSTSEL pin.
Data follows the format below:
DAC80504: { DATA[15:0] }
DAC70504: { DATA[13:0], x, x }
x – Don’t care bits
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The high linearity, small package size and wide temperature range make the DACx0504 suitable in applications
such as optical networking, wireless infrastructure, industrial automation and data acquisition systems. The
device incorporates a 2.5 V internal reference with an internal reference divider circuit that enables full-scale
DAC output voltages of 1.25 V, 2.5 V, or 5 V.
9.1.1 Interfacing to a Microcontroller
Figure 72 displays a typical serial interface that may be observed when connecting the DACx0504 SPI serial
interface to a (master) microcontroller type platform. The setup for the interface is as follows: the microcontroller
output SPI CLK drives the SCLK pin of the DACx0504, while the DACx0504 SDI pin is driven by the MOSI pin of
the microcontroller. The CS pin of the DACx0504 can be asserted from a general program input/output pin of the
microcontroller. When data are to be transmitted to the DACx0504, the CS pin is taken low. The data from the
microcontroller is then transmitted to the DACx0504, totaling 24 bits latched into the DACx0504 device through
the falling edge of SCLK. CS is then brought high after the completed write. The DACx0504 requires data with
the MSB as the first bit received.
Microcontroller
CS
DACx0504
CS
SCLK
SCLK
MOSI
SDI
MISO
SDO
Copyright © 2017, Texas Instruments Incorporated
Figure 72. Typical Serial Interface
34
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Application Information (continued)
9.1.2 Programmable Current Source Circuit
The DACx0504 can be integrated into the circuit in Figure 73 to implement an improved Howland current pump
for precise voltage to current conversions. Bidirectional current flow and high voltage compliance are two
features of the circuit. With a matched resistor network, the load current of the circuit is shown by Equation 2.
R2 R3 / R1
CODE
u VREF u
IL
R3
(2)
2n
The value of R3 in Equation 2 can be reduced to increase the output current drive of U3. U3 can drive ±20 mV in
both directions with voltage compliance limited up to 15 V by the U3 voltage supply. Elimination of the circuit
compensation capacitor C1 in the circuit is not suggested as a result of the change in the output impedance ZO,
according to Equation 3.
R1' R3 R1 R2
ZO
R1 R2'
R3'
R1' R2 R3
(3)
As shown in Equation 3, with matched resistors, ZO is infinite and the circuit is optimum for use as a current
source. However, if unmatched resistors are used, ZO is positive or negative with negative output impedance
being a potential cause of oscillation. Therefore, by incorporating C1 into the circuit, possible oscillation problems
are eliminated. The value of C1 can be determined for critical applications; for most applications, however, a
value of several pF is suggested.
R2'
15 k
VDD
REF
VDD
VREF
C1
10 pF
VDAC
R1'
150 k
DACx0504
R3'
50
U3
OPA277
GND
VOUT
R3
50
GND
R1
150 k
R2
15 k
IL
LOAD
Copyright © 2017, Texas Instruments Incorporated
Figure 73. Programmable Bidirectional Current Source Circuit
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9.2 Typical Application
The DACx0504 is designed for single-supply operation; however, a bipolar output is also possible using the
circuit shown in Figure 74.
GND
15 V
DACx0504
VDAC
R2
REF
OPA192
VOUT
VREF
±15 V
R1
R3
VREF
Copyright © 2017, Texas Instruments Incorporated
Figure 74. Bipolar Operation Using the DACx0504
9.2.1 Design Requirements
The circuit shown in Figure 74 gives a bipolar output voltage at VOUT. When GAIN = 1, VOUT can be calculated
using Equation 4:
ª§
R3 · º
CODE · § R3 R3 · §
u
VOUT CODE Ǭ VREF u
1
V
¨
¸
¨
¸»
REF
¸
R1 ¹ »¼
2n ¹ © R2 R1 ¹ ©
«¬©
where
•
•
•
•
VOUT(CODE) = output voltage versus code
CODE = 0 to 2n – 1. This is the digital code loaded to the DAC
VREF = reference voltage applied to the DACx0504
n = resolution in bits
(4)
Table 18. Design Parameters
PARAMETER
VALUE
VOUT
±10 V
VREF
2.5 V
n
12
9.2.2 Detailed Design Procedure
The bipolar output span can be calculated through Equation 4 by defining a few parameters, the first being the
value for the reference voltage. Once a reference voltage is chosen, the gain resistors can be set accordingly by
determining the desired VOUT at code 0 and code 2n. For a VREF of 2.5 V and a desired output voltage range of
±10 V the calculation is as follows.
CODE = 0:
VOUT 0
§
R3 ·
¨ VREF u
¸
R1 ¹
©
§
R3 ·
¨ 2.5V u
¸
R1 ¹
©
(5)
Setting the equation to minimum output span, VOUT(0) = –10 V, will reduce the equation to: R3/R1 = 4:
CODE = 4096:
Setting the equation to maximum output scan, VOUT(4096) = 10 V, and R3/R1 = 4 will reduce the equation to:
R3/R2 = 3
It is important to note that the maximum code of a 12-bit DAC is 4095; code 4096 was used to simplify the
equation above. For practical use, the true output span will encompass a range of –10 V to (10 V – 1 LSB),
which in this case is –10 V to 9.995 V.
36
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9.2.3 Application Curve
The ±10 V output span with a reference voltage of 2.5 V can be achieved by using values of 30 kΩ, 10 kΩ, and
7.5 kΩ for R3, R2, and R1, respectively. A curve to illustrate this output span is shown in Figure 75. For this
example, 1% tolerance resistors were used in evaluating bipolar operation.
10
Output Voltage (V)
5
0
-5
-10
0
512
1024
1536 2048 2560
DAC Code
3072
3584
4096
D001
Figure 75. Bipolar Operation
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10 Power Supply Recommendations
The DACx0504 operates within the specified VDD supply range of 2.7 V to 5.5 V, and VIO supply range of 1.7 V to
5.5 V. The DACx0504 does not require specific supply sequencing.
The VDD supply must be well-regulated and low-noise. Switching power supplies and dc-dc converters often have
high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar
high-frequency spikes. This noise can easily couple into the DAC output voltage through various paths between
the power connections and analog output. In order to further minimize noise from the power supply, include a 1μF to 10-μF capacitor and 0.1-μF bypass capacitor. The current consumption on the VDD pin, the short-circuit
current limit, and the load current for the device is listed in the Electrical Characteristics. The power supply must
meet the aforementioned current requirements.
38
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11 Layout
11.1 Layout Guidelines
A precision analog component requires careful layout, the list below provides some insight into good layout
practices.
• Bypass all power supply pins to ground with a low-ESR ceramic bypass capacitor. The typical recommended
bypass capacitance is 0.1-µF to 0.22-µF ceramic with a X7R or NP0 dielectric.
• Place power supplies and REF bypass capacitors close to the pins to minimize inductance and optimize
performance.
• Use a high-quality ceramic type NP0 or X7R for its optimal performance across temperature, and very low
dissipation factor.
• The digital and analog sections must have proper placement with respect to the digital pins and analog pins
of the DACx0504 device. The separation of analog and digital blocks minimizes coupling into neighboring
blocks, as well as interaction between analog and digital return currents.
11.2 Layout Example
ANALOG SIDE
GND POUR
BYPASS CAPACITOR
4
BYPASS CAPACITORS
3
2
1
16
5
6
15
7
14
8
13
9
10
11 12
GND POUR
DIGITAL SIDE
Figure 76. DACx0504 Layout Example
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 19. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DAC80504
Click here
Click here
Click here
Click here
Click here
DAC70504
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
40
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC70504RTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
70504
DAC70504RTET
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
70504
XDAC80504RTET
ACTIVE
WQFN
RTE
16
250
TBD
Call TI
Call TI
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DAC70504RTER
WQFN
RTE
16
3000
180.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
DAC70504RTET
WQFN
RTE
16
250
180.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC70504RTER
WQFN
RTE
16
3000
195.0
200.0
45.0
DAC70504RTET
WQFN
RTE
16
250
195.0
200.0
45.0
Pack Materials-Page 2
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