xDSL line driver that features full ADSL central office (CO) Performance on ±12 V supplies Low power operation ±5 V to ±12 V voltage supply 12.5 mA/amp (typical) total supply current Power reduced keep alive current of 4.5 mA/amp High output voltage and current drive IOUT = 600 mA 40 V p-p differential output voltage RL = 50 Ω, VS = ±12 V Low single-tone distortion –75 dBc @ 1 MHz SFDR, RL = 100 Ω, VOUT = 2 V p-p MTPR = –75 dBc, 26 kHz to 1.1 MHz, ZLINE = 100 Ω, PLINE = 20.4 dBm High Speed 78 MHz bandwidth (–3 dB), G = +5 40 MHz gain flatness 1000 V/μs slew rate PIN CONFIGURATIONS +V1 1 24 VOUT1 2 23 VOUT2 VINN1 3 22 VINN2 VINP1 4 21 VINP2 AGND 5 20 AGND – + + – AD8016 AGND 6 +V2 AGND TOP VIEW (Not to Scale) 18 AGND 17 AGND AGND 7 AGND 8 19 PWDN0 9 16 PWDN1 DGND 10 15 BIAS –V1 11 14 –V2 NC 12 13 NC NC = NO CONNECT 01019-002 FEATURES Figure 1. 24-Lead SOIC_W_BAT (RB-24) NC 1 28 NC NC 2 27 NC NC 3 26 NC +VIN2 4 25 NC –VIN2 5 24 PWDN1 VOUT2 6 23 BIAS +V2 7 AD8016ARE 22 –V2 +V1 8 TOP VIEW (Not to Scale) 21 –V1 VOUT1 9 20 DGND –VIN1 10 19 NC +VIN1 11 18 PWDN0 NC 12 17 NC NC 13 16 NC NC 14 15 NC NOTES 1. THE EXPOSED PADDLE IS FLOATING, NOT ELECTRICALLY CONNECTED INTERNALLY. 2. NC = NO CONNECT. 01019-003 Data Sheet Low Power, High Output Current xDSL Line Driver AD8016 Figure 2. 28-Lead TSSOP_EP (RE-28-1) GENERAL DESCRIPTION The AD8016 high output current dual amplifier is designed for the line drive interface in Digital Subscriber Line systems such as ADSL, HDSL2, and proprietary xDSL systems. The drivers are capable, in full-bias operation, of providing 24.4 dBm output power into low resistance loads, enough to power a 20.4 dBm line, including hybrid insertion loss. the xDSL hybrid in Figure 35 and Figure 36. Two digital bits (PWDN0, PWDN1) allow the driver to be capable of full performance, an output keep-alive state, or two intermediate bias states. The keep-alive state biases the output transistors enough to provide a low impedance at the amplifier outputs for back termination. The AD8016 is available in a low cost 24-lead SOIC_W_BAT and a 28-lead TSSOP_EP with an exposed lead frame (ePAD). Operating from ±12 V supplies, the AD8016 requires only 1.5 W of total power dissipation (refer to the Power Dissipation section for details) while driving 20.4 dBm of power downstream using The low power dissipation, high output current, high output voltage swing, flexible power-down, and robust thermal packaging enable the AD8016 to be used as the central office (CO) terminal driver in ADSL, HDSL2, VDSL, and proprietary xDSL systems. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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AD8016 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Feedback Resistor Selection ...................................................... 14 Pin Configurations ........................................................................... 1 Bias Pin and PWDN Features ................................................... 14 General Description ......................................................................... 1 Thermal Shutdown .................................................................... 15 Revision History ............................................................................... 2 Applications Information .............................................................. 16 Specifications..................................................................................... 3 Multitone Power Ratio (MTPR) ............................................... 16 Logic Inputs (CMOS Compatible Logic) .................................. 4 Generating DMT ........................................................................ 17 Absolute Maximum Ratings ............................................................ 5 Power Dissipation....................................................................... 17 Maximum Power Dissipation ..................................................... 5 Thermal Enhancements and PCB Layout ............................... 18 ESD Caution .................................................................................. 5 Thermal Testing.......................................................................... 18 Pin Configurations and Function Descriptions ........................... 6 Air Flow Test Conditions .......................................................... 18 Typical Performance Characteristics ............................................. 7 Experimental Results ................................................................. 19 Test Circuts ...................................................................................... 13 Outline Dimensions ....................................................................... 20 Theory of Operation ...................................................................... 14 Ordering Guide .......................................................................... 20 Power Supply and Decoupling .................................................. 14 REVISION HISTORY 3/12—Rev. B to Rev. C Updated Format .................................................................. Universal Deleted PSOP Package and Evaluation Boards (Throughout) ... 1 Added Pin Configurations and Function Descriptions Sections .. 7 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 19 11/03—Rev. A to Rev. B Changes to Ordering Guide ............................................................ 4 Changes to TPC 21 ........................................................................... 8 Updated Outline Dimensions ..................................................19-20 Rev. C | Page 2 of 20 Data Sheet AD8016 SPECIFICATIONS @ 25°C, VS = ±12 V, RL = 100 Ω, PWDN0, PWDN1 = (1, 1), TMIN = −40°C, TMAX = +85°C, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Large Signal Bandwidth Peaking Slew Rate Rise and Fall Time Settling Time Input Overdrive Recovery Time NOISE/DISTORTION PERFORMANCE Distortion, Single-Ended Second Harmonic Third Harmonic Multitone Power Ratio 1 IMD IP3 Voltage Noise (RTI) Input Current Noise INPUT CHARACTERISTICS RTI Offset Voltage +Input Bias Current –Input Bias Current Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Recovery Time Shutdown Current Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE 1 Test Conditions/Comments G = +1, RF = 1.5 kΩ, VOUT = 0.2 V p-p G = +5, RF = 499 Ω, VOUT < 0.5 V p-p G = +5, RF = 499 Ω, VOUT = 0.2 V p-p VOUT = 4 V p-p VOUT = 0.2 V p-p < 50 MHz VOUT = 4 V p-p, G = +2 VOUT = 2 V p-p 0.1%, VOUT = 2 V p-p VOUT = 12.5 V p-p VOUT = 2 V p-p, G = +5, RF = 499 Ω fC = 1 MHz, RL = 100 Ω/25 Ω fC = 1 MHz, RL = 100 Ω/25 Ω 26 kHz to 1.1 MHz, ZLINE = 100 Ω, PLINE = 20.4 dBm 500 kHz, Δf = 10 kHz, RL = 100 Ω/25 Ω 500 kHz, RL = 100 Ω/25 Ω f = 10 kHz f = 10 kHz Min 69 16 −75/−62 −88/−74 −84/−80 42/40 −3.0 −45 −75 −10 58 Single-ended, RL = 100 Ω G = 5, RL = 10 Ω, f1 = 100 kHz, −60 dBc SFDR −11 400 Typ See Figure 48, R20, R21 = 0 Ω, R1 = open. Rev. C | Page 3 of 20 63 −40 Unit 380 78 38 90 0.1 1000 2 23 350 MHz MHz MHz MHz dB V/μs ns ns ns −77/−64 −93/−76 –75 −88/−85 43/41 2.6 18 dBc dBc dBc dBc dBm nV/√Hz pA√Hz 1.0 4 400 2 4.5 21 +3.0 +45 +75 +10 64 12.5 8 5 4 25 1.5 75 mV μA μA kΩ pF V dB +11 V mA mA pF ±13 13.2 10 8 6 V mA/Amp mA/Amp mA/Amp mA/Amp μs mA/Amp dB °C 600 2000 80 ±3 PWDN1, PWDN0 = (1, 1) PWDN1, PWDN0 = (1, 0) PWDN1, PWDN0 = (0, 1) PWDN1, PWDN0 = (0, 0) To 95% of IQ 250 μA out of bias pin ΔVS = ±1 V Max 4.0 +85 AD8016 Data Sheet @ 25°C, VS = ±6 V, RL = 100 Ω, PWDN0, PWDN1 = (1, 1), TMIN = –40°C, TMAX = +85°C, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth Test Conditions/Comments Bandwidth for 0.1 dB Flatness Large Signal Bandwidth Peaking Slew Rate Rise and Fall Time Settling Time Input Overdrive Recovery Time NOISE/DISTORTION PERFORMANCE Distortion, Single-Ended Second Harmonic Third Harmonic Multitone Power Ratio 1 IMD IP3 Voltage Noise (RTI) Input Current Noise INPUT CHARACTERISTICS RTI Offset Voltage +Input Bias Current −Input Bias Current Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Quiescent Current Recovery Time Shutdown Current Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE Min G = +1, RF = 1.5 kΩ, VOUT = 0.2 V p-p G = +5, RF = 499 Ω, VOUT < 0.5 V p-p G = +5, RF = 499 Ω, VOUT = 0.2 V p-p VOUT = 1 V rms VOUT = 0.2 V p-p < 50 MHz VOUT = 4 V p-p, G = +2 VOUT = 2 V p-p 0.1%, VOUT = 2 V p-p VOUT = 6.5 V p-p 70 10 G = +5, VOUT = 2 V p-p, RF = 499 Ω fC = 1 MHz, RL = 100 Ω/25 Ω fC = 1 MHz, RL = 100 Ω/25 Ω 26 kHz to 138 kHz, ZLINE = 100 Ω, PLINE = 13 dBm 500 kHz, Δf = 110 kHz, RL = 100 Ω/25 Ω 500 kHz f = 10 kHz f = 10 kHz −73/61 −80/−68 −87/−82 42/39 −3.0 −25 −30 −4 60 Single-Ended, RL = 100 Ω G = +5, RL = 5 Ω, f = 100 kHz, −60 dBc SFDR −5 300 Typ 320 71 15 80 0.7 300 2 39 350 −75/−63 −82/−70 −68 −88/−83 42/39 4 17 +4 66 RS = 10 Ω PWDN1, PWDN0 = (1, 1) PWDN1, PWDN0 = (1, 0) PWDN1, PWDN0 = (0, 1) PWDN1, PWDN0 = (0, 0) To 95% of IQ 250 μA out of bias pin ΔVS = ±1 V 8 6 4 3 23 1.0 80 PWDN0, PWDN1, VCC = ±12 V or ±6 V; full temperature range. Table 3. Typ Max VCC 0.8 Rev. C | Page 4 of 20 Unit V V mV μA μA kΩ pF V dB V mA mA pF 9.7 6.9 5.0 4.1 mA/Amp mA/Amp mA/Amp mA/Amp μs mA/Amp dB °C +85 LOGIC INPUTS (CMOS COMPATIBLE LOGIC) dBc dBc dBc dBc dBm nV/√Hz pA√Hz +5 2.0 See Figure 48, R20, R21 = 0 Ω, R1 = open. Min 2.2 0 1.0 MHz MHz MHz MHz dB V/μs ns ns ns +3.0 +25 +30 1 Parameter Logic 1 Voltage Logic 0 Voltage Unit 5 20 0.2 10 10 400 2 420 830 50 63 −40 Max Data Sheet AD8016 ABSOLUTE MAXIMUM RATINGS Storage Temperature Range Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Rating 26.4 V 1.4 W 1.4 W ±VS ±VS Observe power derating curves −65°C to +125°C −40°C to +85°C 300°C 1 Specification is for device on a 4-layer board with 10 inches2 of 1 oz copper at 85°C 24-lead SOIC_W_BAT package: θJA = 28°C/W. 2 Specification is for device on a 4-layer board with 9 inches2 of 1 oz copper at 85°C 28-lead (TSSOP_EP) package: θJA = 29°C/W. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 8 7 6 5 4 SOIC_W_BAT 3 TSSOP-EP 2 1 0 0 10 20 30 40 50 60 AMBIENT TEMPERATURE (°C) 70 80 90 01019-005 Parameter Supply Voltage Internal Power Dissipation SOIC_W_BAT Package1 TSSOP_EP Package2 Input Voltage (Common-Mode) Differential Input Voltage Output Short-Circuit Duration The output stage of the AD8016 is designed for maximum load current capability. As a result, shorting the output to common can cause the AD8016 to source or sink 2000 mA. To ensure proper operation, it is necessary to observe the maximum power derating curves. Direct connection of the output to either power supply rail can destroy the device. MAXIMUM POWER DISSIPATION (W) Table 4. Figure 3. Maximum Power Dissipation vs. Temperature for AD8016 for TJ = 125 °C ESD CAUTION MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8016 is limited by the associated rise in junction temperature. The maximum safe junction temperature for a plastic encapsulated device is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Rev. C | Page 5 of 20 AD8016 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NC 1 24 +V2 VOUT1 2 23 VOUT2 VINN1 3 – + + – VINP1 4 21 AGND 5 AGND 7 AGND 8 AD8016 VINN2 VINP2 25 NC –VIN2 5 24 PWDN1 23 BIAS +V2 7 AD8016ARE 22 –V2 +V1 8 TOP VIEW (Not to Scale) 21 –V1 20 AGND 19 AGND –VIN1 10 19 NC +VIN1 11 18 16 PWDN1 DGND 10 15 BIAS –V1 11 14 –V2 NC 12 13 NC NC = NO CONNECT +VIN2 4 VOUT1 9 TOP VIEW (Not to Scale) 18 AGND 17 AGND PWDN0 9 26 NC VOUT2 6 20 DGND PWDN0 NC 12 17 NC NC 13 16 NC NC 14 15 NC NOTES 1. THE EXPOSED PADDLE IS FLOATING, NOT ELECTRICALLY CONNECTED INTERNALLY. 2. NC = NO CONNECT. 01019-002 AGND 6 22 27 NC NC 3 Figure 4. 24-Lead SOIC_W_BAT (RB-24) 01019-003 +V1 1 28 NC NC 2 Figure 5. 28-Lead TSSOP_EP (RE-28-1) Table 5. Pin Function Descriptions SOIC_W_BAT 1 2 3 4 5 to 8, 17 to 20 9 10 11 12, 13 14 15 16 21 22 23 24 Pin No. TSSOP_EP 8 9 18 20 21 1 to 3, 12 to 17, 19, 25 to 28 22 23 24 6 7 4 5 10 11 EP Mnemonic +V1 VOUT1 VINN1 VINP1 AGND PWDN0 DGND −V1 NC Description Positive Power Supply, Amp 1. Output Signal, Amp 1. Negative Input Signal, Amp 1. Positive Input Signal, Amp1. Analog Ground. Power-Down Input 0. Digital Ground. Negative Power Supply, Amp1. This pin is not connected internally (see Figure 4 and Figure 5). −V2 BIAS PWDN1 VINP2 VINN2 VOUT2 +V2 +VIN2 −VIN2 −VIN1 +VIN1 EPAD −V Power Supply, Amp 2. Quiescent Current Adjust. Power-Down Input 1. Positive Input Signal, Amp 2. Negative Input Signal, Amp 2. Output Signal, Amp 2. Positive Power Supply, Amp 2. Positive Input Signal, Amp 2. Negative Input Signal, Amp 2. Negative Input Signal, Amp 1. Positive Input Signal, Amp 1. Exposed Pad. The exposed paddle is floating, not electrically connected internally. Rev. C | Page 6 of 20 Data Sheet AD8016 TYPICAL PERFORMANCE CHARACTERISTICS 549.3 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3 FREQUENCY (kHz) TIME (100ns/DIV) Figure 6. Multitone Power Ratio; VS = ±12 V, 20.4 dBm Output Power into 100 Ω, Downstream Figure 9. 100 mV Step Response; G = +5, VS = ±12 V, RL = 25 Ω, Single-Ended VOLTS VOUT = 4V VIN = 20mV 01019-011 VIN = 800mV 01019-008 VOLTS VOUT = 100mV TIME (100ns/DIV) VIN = 20mV 01019-010 VOLTS –75dBc 01019-004 10dB/DIV VOUT = 100mV TIME (100ns/DIV) Figure 7. 100 mV Step Response; G = +5, VS = ±6 V, RL = 25 Ω, Single-Ended Figure 10. 4 V Step Response; G = +5, VS = ±12 V, RL = 25 Ω, Single-Ended –30 RF = 499Ω G = +10 –40 VOUT = 4V p-p VOUT = 5V (0,0) VOLTS DISTORTION (dBc) –50 VIN = 800mV (0,1) (1,0) –60 –70 –80 PWDN1, PWDN0 = (1,1) –90 –110 0.01 Figure 8. 4 V Step Response; G = +5, VS = ±6 V, RL = 25 Ω, Single-Ended 0.1 1 FREQUENCY (MHz) 10 20 01019-012 01019-009 TIME (100ns/DIV) –100 Figure 11. Distortion vs. Frequency; Second Harmonic, VS = ±12 V, RL = 50 Ω, Differential Rev. C | Page 7 of 20 AD8016 Data Sheet –30 (0,0) RF = 499Ω G = +10 V –40 OUT = 4V p-p (0,1) –50 DISTORTION (dBc) (1,0) –60 –70 –80 PWDN1, PWDN0 = (1,1) –100 10 20 Figure 12. Distortion vs. Frequency; Second Harmonic, VS = ±6 V, RL = 50 Ω –30 –110 0.01 –30 10 20 RF = 499Ω G = +5 (1,0) (0,0) –45 DISTORTION (dBc) –50 –55 (0,0) (0,1) (1,0) –60 –65 –70 –50 (0,1) –60 –70 –80 0 100 300 400 500 600 200 PEAK OUTPUT CURRENT (mA) 700 800 01019-014 PWDN1, PWDN0 = (1,1) –75 Figure 13. Distortion vs. Peak Output Current; Second Harmonic, VS = ±12 V, RL = 10 Ω, f = 100 kHz, Single-Ended –30 –90 0 100 300 400 500 200 PEAK OUTPUT CURRENT (mA) 600 700 Figure 16. Distortion vs. Peak Output Current, Third Harmonic; VS = ±12 V, RL = 10 Ω, G = +5, f = 100 kHz, Single-Ended –30 (0,0) RF = 499Ω G = +10 –40 VOUT = 4V p-p PWDN1, PWDN0 = (1,1) 01019-017 DISTORTION (dBc) 1 FREQUENCY (MHz) –40 –40 –80 0.1 Figure 15. Distortion vs. Frequency; Third Harmonic, VS = ±6 V, RL = 50 Ω, Differential RF = 499Ω G = +5 –35 PWDN1, PWDN0 = (1,1) –80 –100 1 FREQUENCY (MHz) (1,0) –70 –90 0.1 (0,1) –60 –90 –110 0.01 (0,0) –50 01019-013 DISTORTION (dBc) RF = 499Ω G = +10 –40 VOUT = 4V p-p 01019-016 –30 RF = 499Ω G = +5 –35 (0,1) –40 –60 DISTORTION (dBc) DISTORTION (dBc) –50 (1,0) –70 PWDN1, PWDN0 = (1,1) –80 –45 (0,0) –50 (0,1) –55 (1,0) –60 –65 –90 –70 0.1 1 FREQUENCY (MHz) 10 20 –80 01019-015 –110 0.01 –75 Figure 14. Distortion vs. Frequency; Third Harmonic, VS = ±12 V, RL = 50 Ω, Differential PWDN1, PWDN0 = (1,1) 0 100 200 300 400 PEAK OUTPUT CURRENT (mA) 500 600 01019-018 –100 Figure 17. Distortion vs. Peak Output Current; Second Harmonic, VS = ±6 V, RL = 5 Ω, f = 100 kHz, Single-Ended Rev. C | Page 8 of 20 AD8016 –30 –30 –40 –40 –50 –50 DISTORTION (dBc) (0,0) –60 (0,1) –70 (1,0) (0,0) (0,1) –60 (1,0) –70 –80 –80 PWDN1, PWDN0 = (1,1) 0 5 15 20 25 30 10 DIFFERENTIAL OUTPUT (V p-p) 35 –100 01019-020 –100 PWDN1, PWDN0 = (1,1) –90 –90 40 0 5 10 15 20 25 30 DIFFERENTIAL OUTPUT (V p-p) 35 01019-023 DISTORTION (dBc) Data Sheet 40 Figure 21. Distortion vs. Output Voltage; Third Harmonic, VS = ±12 V, G = +10, f = 1 MHz, RL = 50 Ω, Differential Figure 18. Distortion vs. Output Voltage; Second Harmonic, VS = ±12 V, G = +10, f = 1 MHz, RL = 50 Ω, Differential –30 –30 –40 –40 DISTORTION (dBc) DISTORTION (dBc) (0,0) –50 –60 (0,0) (0,1) –70 –50 (0,1) –60 (1,0) –70 (1,0) 10 15 5 DIFFERENTIAL OUTPUT (V p-p) 0 20 –90 Figure 19. Distortion vs. Output Voltage; Second Harmonic, VS = ±6 V, G = +10, f = 1 MHz, RL = 50 Ω, Differential 20 3 –40 –45 –50 (0,0) –55 (0,1) –60 (1,0) –65 –70 –75 0 100 300 400 200 PEAK OUTPUT CURRENT (mA) 500 600 Figure 20. Distortion vs. Peak Output Current; Third Harmonic, VS = ±6 V, G = +5, RL = 5 Ω, f = 100 kHz, Single-Ended –3 (1,1) –6 (1,0) –9 –12 (0,1) –15 –18 (0,0) –21 VIN = 40mV p-p G = +5 RL = 100Ω –24 –27 01019-022 PWDN1, PWDN0 = (1,1) 0 1 10 FREQUENCY (MHz) 100 500 01019-025 NORMALIZED FREQUENCY RESPONSE (dB) –35 DISTORTION (dBc) 5 10 15 DIFFERENTIAL OUTPUT (V p-p) Figure 22. Distortion vs. Output Voltage, Third Harmonic, VS = ±6 V, G = +10, f = 1 MHz, RL = 50 Ω, Differential –30 –80 0 01019-024 PWDN1, PWDN0 = (1,1) 01019-021 –90 PWDN1, PWDN0 = (1,1) –80 –80 Figure 23. Frequency Response; VS = ±12 V, @ PWDN1, PWDN0 Codes Rev. C | Page 9 of 20 AD8016 11 Data Sheet 11 G = +5 RL = 100Ω RF = 499Ω 8 –1 –4 –7 –10 2 –1 –4 –7 –10 –13 –13 –16 –16 1 10 FREQUENCY (MHz) 100 500 –19 10 FREQUENCY (MHz) 1 Figure 24. Output Voltage vs. Frequency; VS = ±12 V 20 10 500 Figure 27. Output Voltage vs. Frequency; VS = ±6 V –10 VIN = 2V rms RF = 602Ω RF = 499Ω –20 (1,1) 0 100 01019-029 OUTPUT VOLTAGE (dBV) 5 2 01019-026 OUTPUT VOLTAGE (dBV) 5 –19 G = +5 RL = 100Ω RF = 499Ω 8 (1,0) –30 +PSRR –20 –30 PSRR (dB) CMRR (dB) –10 (0,1) –40 –40 –50 –PSRR –60 (0,0) –50 –70 –60 100 500 –90 0.01 10 1 FREQUENCY (MHz) 100 500 Figure 28. PSRR vs. Frequency; VS = ±12 V Figure 25. CMRR vs. Frequency; VS = ±12 V @ PWDN1, PWDN0 Codes 180 90 3 160 80 140 70 120 60 100 50 80 40 + INPUT CURRENT NOISE (pA/ Hz) 6 0 (1,1) –3 –6 (1,0) –9 –12 (0,1) –15 –18 –21 VIN = 40mV p-p G = +5 RL = 100Ω –24 1 (0,0) 60 30 +INOISE 40 20 VIN NOISE 10 20 10 FREQUENCY (MHz) 100 500 01019-028 NORMALIZED FREQUENCY RESPONSE (dB) 0.1 Figure 26. Frequency Response; VS = ±6 V, @ PWDN1, PWDN0 Codes Rev. C | Page 10 of 20 0 10 INPUT VOLTAGE NOISE (nV/ Hz) 10 1 FREQUENCY (MHz) 100 100k 1k 10k FREQUENCY (MHz) Figure 29. Noise vs. Frequency 1M 0 10M 01019-031 0.1 01019-027 –80 0.03 01019-030 –80 –70 G = +2 RF = 1kΩ VOUT = 2VSTEP RL = 100Ω +2mV (–0.1%) 0 –2mV (–0.1%) VOUT VIN –5 0 5 10 VOUT – VIN 15 20 25 30 35 40 G = +2 RF = 1kΩ VOUT = 2VSTEP RL = 100Ω +2mV (–0.1%) 0 –2mV (–0.1%) 45 TIME (ns) VIN VOUT –5 0 10 5 15 20 25 30 35 40 45 TIME (ns) Figure 30. Settling Time 0.1%; VS = ±12 V Figure 33. Settling Time 0.1%; VS = ±6 V 1000 –20 VOUT = 2V p-p RF = 499Ω G = +5 –30 R = 100Ω L OUTPUT IMPEDANCE (Ω) 100 –40 CROSSTALK (dB) VOUT – VIN 01019-035 OUTPUT VOLTAGE ERROR (2mV/DIV (0.1%/DIV)) AD8016 01019-032 OUTPUT VOLTAGE ERROR (2mV/DIV (0.1%/DIV)) Data Sheet –50 –60 –70 (0,0) (0,1) 10 (1,0) 1 (1,1) 0.1 0.1 1 10 FREQUENCY (MHz) 100 500 0.01 0.03 01019-033 –90 0.03 Figure 31. Output Crosstalk vs. Frequency 0.1 1 10 FREQUENCY (MHz) 100 01019-036 –80 500 Figure 34. Output Impedance vs. Frequency @ PWDN1, PWDN0 Codes 1M 360 100k 320 10k 280 VIN = 2V/DIV VOUT = 5V/DIV 240 100 200 TRANSIMPEDANCE 10 160 120 1 0.1 80 0.01 40 PHASE (Degrees) PHASE 1k 0V VIN 0.001 0.0001 0.001 0.01 0.1 1 10 FREQUENCY (MHz) 100 1k 0 10k Figure 32. Open-Loop Transimpedance and Phase vs. Frequency –100 0 100 200 300 400 500 TIME (ns) 600 700 800 900 01019-037 0V 01019-034 TRANSIMPEDANCE (k Ω) VOUT Figure 35. Positive Overdrive Recovery; VS = ±12 V, G = +5, RL = 100 Ω Rev. C | Page 11 of 20 AD8016 Data Sheet 18 VIN = 2V/DIV VOUT = 5V/DIV 16 PWDN1, PWDN0 = (1,1) 14 0V VOUT 12 IQ (mA) (1,0) 0V 10 (0,1) 8 (0,0) VIN 6 4 100 200 300 400 500 TIME (ns) 600 700 800 900 0 0 50 100 IBIAS (µA) 150 200 01019-040 0 01019-038 2 –100 Figure 38. IQ vs. IBIAS Current; VS = ±6 V Figure 36. Negative Overdrive Recovery; VS = ±12 V, G = +5, RL = 100 Ω 12 25 +VOUT, VS = ±12V PWDN1, PWDN0 = (1,1) 8 20 OUTPUT SWING (V) +VOUT, VS = ±6V (1,0) IQ (mA) 15 (0,1) 10 4 0 –4 (0,0) –VOUT, VS = ±6V 5 –8 50 100 IBIAS (µA) 150 200 Figure 37. IQ vs. IBIAS Current; VS = ±12 V –12 10 100 1k RLOAD (Ω) Figure 39. Output Voltage vs. RLOAD Rev. C | Page 12 of 20 10k 01019-041 0 01019-039 –VOUT, VS = ±12V 0 Data Sheet AD8016 TEST CIRCUTS 10µF +VS 124Ω 499Ω + 0.1µF +VIN VOUT +VO 49.9Ω RL 499Ω 111Ω VIN 49.9Ω 499Ω RL +VS 0.1µF + 10µF 0.1µF + 10µF 0.1µF –VIN –VO –VS Figure 40. Single-Ended Test Circuit; G = +5 10µF + Figure 41. Differential Test Circuit; G = +10 Rev. C | Page 13 of 20 01019-007 –VS 01019-006 49.9Ω AD8016 Data Sheet THEORY OF OPERATION The AD8016 is a current feedback amplifier with high (500 mA) output current capability. With a current feedback amplifier, the current into the inverting input is the feedback signal and the open-loop behavior is that of a transimpedance, dVOUT/dIIN or TZ. The open-loop transimpedance is analogous to the open-loop voltage gain of a voltage feedback amplifier. Figure 42 shows a simplified model of a current feedback amplifier. Because RIN is proportional to 1/gm, the equivalent voltage gain is just TZ × gm, where gm is the transconductance of the input stage. Basic analysis of the follower with gain circuit yields TZ (S) VOUT =G× TZ (S) + G × RIN + RF VIN RIN = RF RG 1 ≈ 25 Ω gm Recognizing that G × RIN << RF for low gains, the familiar result of constant bandwidth with gain for current feedback amplifiers is evident, the 3 dB point being set when |TZ| = RF. Of course, for a real amplifier there are additional poles that contribute excess phase and there is a value for RF below which the amplifier is unstable. Tolerance for peaking and desired flatness determines the optimum RF in each application. RF RG – RIN IIN VOUT + VIN In current feedback amplifiers, selection of feedback and gain resistors has an impact on the MTPR performance, bandwidth, and gain flatness. Take care in selecting these resistors so that optimum performance is achieved. Table 6 below shows the recommended resistor values for use in a variety of gain settings. These values are suggested as a good starting point when designing for any application. Table 6. Resistor Selection Guide Gain +1 −1 +2 +5 +10 RF (Ω) 1000 500 650 750 1000 RG (Ω) ∞ 500 650 187 111 BIAS PIN AND PWDN FEATURES 01019-042 RN + TZ The AD8016 should be powered with a good quality (that is, low noise) dual supply of ±12 V for the best distortion and multitone power ratio (MTPR) performance. Careful attention must be paid to decoupling the power supply pins. A 10 μF capacitor located in near proximity to the AD8016 is required to provide good decoupling for lower frequency signals. In addition, 0.1 μF decoupling capacitors should be located as close to each of the four power supply pins as is physically possible. All ground pins should be connected to a common low impedance ground plane. FEEDBACK RESISTOR SELECTION where: G =1+ POWER SUPPLY AND DECOUPLING Figure 42. Simplified Block Diagram The AD8016 is the first current feedback amplifier capable of delivering 400 mA of output current while swinging to within 2 V of either power supply rail. This enables full CO ADSL performance on only 12 V rails, an immediate 20% power saving. The AD8016 is also unique in that it has a power management system included on-chip. It features four user programmable power levels (all of which provide a low output impedance of the driver), as well as the provision for complete shutdown (high impedance state). Also featured is a thermal shutdown with alarm signal. The AD8016 is designed to cover both central office (CO) and customer premise equipment (CPE) ends of an xDSL application. It offers full versatility in setting quiescent bias levels for the particular application from full on to reduced bias (in three steps) to full off (via BIAS pin). This versatility gives the modem designer the flexibility to maximize efficiency while maintaining reasonable levels of MTPR performance. Optimizing driver efficiency while delivering the required DMT power is accomplished with the AD8016 through the use of onchip power management features. Two digitally programmable logic pins, PWDN1 and PWDN0, may be used to select four different bias levels: 100%, 60%, 40%, and 25% of full quiescent power (see Table 7). Table 7. PWDN Code Selection Guide PWDN1 Code 1 1 0 0 X Rev. C | Page 14 of 20 PWDN0 Code 1 0 1 0 X Quiescent Bias Level 100% (full on) 60% 40% 25% (low ZOUT but not off) Full off (high ZOUT via 250 μA pulled out of BIAS pin) Data Sheet AD8016 The BIAS control pin by itself is a means to continuously adjust the AD8016 internal biasing and, thus, quiescent current IQ. By pulling out a current of 0 μA (or open) to approximately200 μA, the quiescent current can be adjusted from 100% (full on) to a full off condition. The full off condition yields a high output impedance. Because of an on-chip resistor variation of up to ±20%, the actual amount of current required to fully shut down the AD8016 can vary. To institute a full chip shutdown, a pulldown current of 250 μA is recommended. See Figure 43 for the logic drive circuit for complete amplifier shutdown. Figure 37 and Figure 38 show the relationship between current pulled out of the BIAS pin (IBIAS) and the supply current (IQ). A typical shutdown IQ is less than 1 mA total. Alternatively, an external pull-down resistor to ground or a current sink attached to the BIAS pin can be used to set IQ to lower levels (see Figure 44). The BIAS pin may be used in combination with the PWDN1 and PWDN0 pins; however, diminished MTPR performance may result when IQ is lowered too much. Current pulled away from the BIAS pin shunts away a portion of the internal bias current. Setting PWDN1 or PWDN0 to Logic 0 also shunts away a portion of the internal bias current. The reduction of quiescent bias levels due to the use of PWDN1 and PWDN0 is consistent with the percentages established in Table 7. When PWDN0 alone is set to Logic 0, and no other means of reducing the internal bias currents is used, full-rate ADSL signals may be driven while maintaining reasonable levels of MTPR. R2 50kΩ R1* The AD8016 ARB is designed to incorporate shutdown protection against accidental thermal overload. In the event of thermal overload, the AD8016 was designed to shut down at a junction temperature of 165°C and return to normal operation at a junction temperature 140°C. The AD8016 continues to operate, cycling on and off, as long as the thermal overload condition remains. The frequency of the protection cycle depends on the ambient environment, severity of the thermal overload condition, the power being dissipated, and the thermal mass of the PCB beneath the AD8016. When the AD8016 begins to cycle due to thermal stress, the internal shutdown circuitry draws current out of the node connected in common with the BIAS pin, while the voltage at the BIAS pin goes to the negative rail. When the junction temperature returns to 140°C, current is no longer drawn from this node, and the BIAS pin voltage returns to the positive rail. Under these circumstances, the BIAS pin can be used to trip an alarm indicating the presence of a thermal overload condition. Figure 44 also shows three circuits for converting this signal to a standard logic level. VCC V = VCC – 0.2V 10kΩ BIAS SHUTDOWN BIAS PWDN0 OR 0µA – 200µA VEE PWDN1 5V VCC 10kΩ 5V BIAS 10kΩ ALARM OR BIAS 1MΩ 100kΩ 1/4 HCF 40109B SGS–THOMSON Figure 44. Shutdown and Alarm Circuit BIAS 2N3904 *R1 = 47kΩ FOR ±12V S OR +12VS, R1 = 22kΩ FOR ±6VS. AD8016 200µA 01019-043 3.3V LOGIC THERMAL SHUTDOWN Figure 43. Logic Drive of BIAS Pin for Complete Amplifier Shutdown Rev. C | Page 15 of 20 ALARM MIN β 350 01019-044 The bias level can be controlled with TTL logic levels (high = 1) applied to the PWDN1 and PWDN0 pins alone or in combination with the BIAS control pin. The DGND or digital ground pin is the logic ground reference for the PWDN1 and PWDN0 pins. In typical ADSL applications where ±12 V or ±6 V supplies (also single supplies) are used, the DGND pin is connected to analog ground. AD8016 Data Sheet APPLICATIONS INFORMATION ADSL systems rely on discrete multitone modulation to carry digital data over phone lines. DMT modulation appears in the frequency domain as power contained in several individual frequency subbands, sometimes referred to as tones or bins, each of which is uniformly separated in frequency. (See Figure 6 for an example of downstream DMT signals used in evaluating MTPR performance.) A uniquely encoded, quadrature amplitude modulation (QAM) signal occurs at the center frequency of each subband or tone. Difficulties arise when decoding these subbands if a QAM signal from one subband is corrupted by the QAM signal(s) from other subbands, regardless of whether the corruption comes from an adjacent subband or harmonics of other subbands. Conventional methods of expressing the output signal integrity of line drivers, such as spurious-free dynamic range (SFDR), single-tone harmonic distortion or THD, twotone intermodulation distortion (IMD), and third-order intercept (IP3) become significantly less meaningful when amplifiers are required to drive DMT and other heavily modulated waveforms. A typical xDSL downstream DMT signal may contain as many as 256 carriers (subbands or tones) of QAM signals. MTPR is the relative difference between the measured power in a typical subband (at one tone or carrier) vs. the power at another subband specifically selected to contain no QAM data. In other words, a selected subband (or tone) remains open or void of intentional power (without a QAM signal), yielding an empty frequency bin. MTPR, sometimes referred to as the empty bin test, is typically expressed in dBc, similar to expressing the relative difference between single-tone fundamentals and second or third harmonic distortion components. Z′ ≡ Z2 (2 × N )2 where: Z' is the primary side impedance as seen by the differential driver. Z2 is the line impedance. N is the transformer turns ratio. Figure 45 shows the dynamic headroom in each subband of a downstream DMT waveform vs. turns ratio running at 100% and 60% of the quiescent power while maintaining −65 dBc of MTPR at VS = ±12 V. 4 VS = ±12V PWDN1, PWDN0 = (1,1) 3 VS = ±11.4V PWDN1, PWDN0 = (1,1) 2 VS = ±12V PWDN1, PWDN0 = (1,0) 1 0 VS = ±11.4V PWDN1, PWDN0 = (1,0) –1 –2 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 DOWNSTREAM TURNS RATIO 1.8 1.9 2.0 Figure 45. Dynamic Headroom vs. XFMR Turns Ratio, VS = ±12 V Rev. C | Page 16 of 20 01019-045 MULTITONE POWER RATIO (MTPR) See Figure 6 for a sample of the ADSL downstream spectrum showing MTPR results while driving 20.4 dBm of power onto a 100 Ω line. Measurements of MTPR are typically made at the output (line side) of ADSL hybrid circuits. MTPR can be affected by the components contained in the hybrid circuit, including the quality of the capacitor dielectrics, voltage ratings, and the turns ratio of the selected transformers. Other components aside, an ADSL driver hybrid containing the AD8016 can be optimized for the best MTPR performance by selecting the turns ratio of the transformers. The voltage and current demands from the differential driver changes, depending on the transformer turns ratio. The point on the curve indicating maximum dynamic headroom is achieved when the differential driver delivers both the maximum voltage and current while maintaining the lowest possible distortion. Below this point, the driver has reserve current-driving capability and experiences voltage clipping. Above this point, the amplifier runs out of current drive capability before the maximum voltage drive capability is reached. Because a transformer reflects the secondary load impedance back to the primary side by the square of the turns ratio, varying the turns ratio changes the load across the differential driver. The following equation may be used to calculate the load impedance across the output of the differential driver, reflected by the transformers, from the line side of the xDSL driver hybrid. DYNAMIC HEADROOM (dB) The AD8016 dual amplifier forms an integrated single-channel ADSL line driver. The AD8016 may be applied in driving modulated signals including discrete multitone (DMT) in either direction; upstream from CPE to the CO and downstream from CO to CPE. The most significant thermal management challenge lies in driving downstream information from CO sites to the CPE. Driving xDSL information downstream suggests the need to locate many xDSL modems in a single CO site. The implication is that several modems will be placed onto a single printed circuit board residing in a card cage located in a variety of ambient conditions. Environmental conditioners such as fans or air conditioning may or may not be available, depending on the density of modems and the facilities contained at the CO site. To achieve long-term reliability and consistent modem performance, designers of CO solutions must consider the wide array of ambient conditions that exist within various CO sites. Data Sheet AD8016 Once an optimum turns ratio is determined, the amplifier has an MTPR performance for each setting of the power-down pins. Table 8 demonstrates the effects of reducing the total power dissipated by using the PWDN pins on MTPR performance when driving 20.4 dBm downstream onto the line with a transformer turns ratio of 1:1.4. Table 8. Dynamic Power Dissipation of Downstream Transmission 1 PWDN0 1 0 1 0 PD (W) 1.454 1.262 1.142 0.120 POUT = 23.4 dBm = 220 mW VOUT @ 50 Ω = 3.31 V rms VOUT = 2.354 V at each amplifier output, which yields a PD of 1.81 W. MTPR −78 dBc −75.3 dBc −57.2 dBc N/A Through measurement, a DMT signal of 23.4 dBm requires 1.47 W of power to be dissipated by the AD8016. Figure 46 shows the results of calculation and actual measurements detailing the relationship between the power dissipated by the AD8016 vs. the total output power delivered to the back termination resistors and the load combined. A 1:2 transformer turns ratio was used in the calculations and measurements. This mode is quiescent power dissipation. GENERATING DMT At this time, DMT modulated waveforms are not typically menu selectable items contained within arbitrary waveform generators. Even using AWG software to generate DMT signals, AWGs that are available today may not deliver DMT signals sufficient in performance with regard to MTPR due to limitations in the DAC and output drivers used by AWG manufacturers. Similar to evaluating single-tone distortion performance of an amplifier, MTPR evaluation requires a DMT signal generator capable of delivering MTPR performance better than that of the driver under evaluation. 2.5 2.0 CALCULATED POWER DISSIPATION PWDN1 1 1 0 01 The situation is more complicated with a complex modulated signal. In the case of a DMT signal, taking the equivalent sine wave power overestimates the power dissipation by ~23%. For example: 1.5 MEASURED SINE MEASURED DMT 1.0 0.5 To properly size the heat sinking area for the user’s application, it is important to consider the total power dissipation of the AD8016. The dc power dissipation for VIN = 0 V is IQ (VCC − VEE), or 2 × IQ × VS. For the AD8016 powered on +12 V and −12 V supplies (±VS), the number is 0.6 W. In a differential driver circuit (Figure 41), one can use symmetry to simplify the computation for a dc input signal. PD = 2 × IQ × VS + 4 × (VS − VOUT ) VOUT RL where: VOUT is the peak output voltage of an amplifier. This formula is slightly pessimistic due to the fact that some of the quiescent supply current is commutated during sourcing or sinking current into the load. For a sine wave source, integration over a half cycle yields 4V V V 2 PD = 2 × IQ × VS + 2 OUT S − OUT πR RL L Rev. C | Page 17 of 20 0 0 100 200 OUTPUT POWER (mW) 300 Figure 46. Power Dissipation vs. Output Power (Including Back Terminations), See Figure 9 for Test Circuit 01019-046 POWER DISSIPATION AD8016 Data Sheet THERMAL ENHANCEMENTS AND PCB LAYOUT AIR FLOW TEST CONDITIONS There are several ways to enhance the thermal capacity of the CO solution. Additional thermal capacity can be created using enhanced PCB layout techniques such as interlacing (sometimes referred to as stitching or interconnection) of the layers immediately beneath the line driver. This technique serves to increase the thermal mass or capacity of the PCB immediately beneath the driver. The AD8016 in a TSSOP_EP (ARE model) package can be designed to operate in the CO solution using prudent measures to manage the power dissipation through careful PCB design. The ARE package is available for use in designing the highest density CO solutions. Maximum heat transfer to the PCB can be accomplished using the ARE package when the thermal slug is soldered to an exposed copper pad directly beneath the AD8016. Optimum thermal performance can be achieved in the ARE package only when the back of the package is soldered to a PCB designed for maximum thermal capacity (see Figure 48). Thermal experiments with the ARE package were conducted without soldering the heat slug to the PCB. Heat transfer was through physical contact only. The following offers some insight into the AD8016 power dissipation and relative junction temperature, as well as the effects of PCB size and composition on the junction-to-air thermal resistance or θJA. DUT Power THERMAL TESTING A wind tunnel study was conducted to determine the relationship between thermal capacity (that is, printed circuit board copper area), air flow, and junction temperature. Junction-toambient thermal resistance, θJA, was also calculated for the AD8016 ARE and AD8016 ARB packages. The AD8016 was operated in a noninverting differential driver configuration, typical of an xDSL application yet isolated from any other modem components. Testing was conducted using a 1 oz. copper board in an ambient temperature of ~24°C over air flows of 200, 150, 100, and 50 linear feet per minute (LFM) (0.200 and 400 for AD8016 ARE) and for the ARB packages as well as in still air. The 4-layer PCB was designed to maximize the area of copper on the outer two layers of the board, while the inner layers were used to configure the AD8016 in a differential driver circuit. The PCB measured 3 inches × 4 inches in the beginning of the study and was progressively reduced in size to approximately 2 inches × 2 inches. The testing was performed in a wind tunnel to control airflow in units of LFM. The tunnel is approximately 11 inches in diameter. A typical DSL DMT signal produces about 1.5 W of power dissipation in the AD8016 package. The fully biased (PWDN0 and PWDN1 = Logic 1) quiescent current of the AD8016 is ~25 mA. A 1 MHz differential sine wave at an amplitude of 8 V p-p/amplifier into an RLOAD of 100 Ω differential (50 Ω per side) produces the 1.5 W of power typical in the AD8016 device. (See the Power Dissipation section for details.) Thermal Resistance The junction-to-case thermal resistance (θJC) of the AD8016 ARB or SOIC_W_BAT package is 8.6°C/W and for the AD8016 ARE or TSSOP_EP it is 5.6°C/W. These package specifications were used in this study to determine junction temperature based on the measured case temperature. PCB Dimensions of a Differential Driver Circuit Several components are required to support the AD8016 in a differential driver circuit. The PCB area necessary for these components (that is, feedback and gain resistors, ac-coupling and decoupling capacitors, termination and load resistors) dictated the area of the smallest PCB in this study, 4.7 square inches. Further reduction in PCB area, although possible, has consequences in terms of the maximum operating junction temperature method of thermal enhancement.) A cooling fan that draws moving air over the PCB and xDSL drivers, while not always required, may be useful in reducing the operating temperature. Rev. C | Page 18 of 20 Data Sheet AD8016 35 EXPERIMENTAL RESULTS ARB 0 LFM The experimental data suggests that for both packages, and a PCB as small as 4.7 square inches, reasonable junction temperatures can be maintained even in the absence of air flow. The graph in Figure 47 shows junction temperature vs. airflow for various dimensions of 1 oz. copper PCBs at an ambient temperature of 24°C in the ARB package. For the worst-case package, the AD8016 ARB and the worst-case PCB at 4.7 square inches, the extrapolated junction temperature for an ambient environment of 85°C would be approximately 132°C with 0 LFM of airflow. If the target maximum junction temperature of the AD8016 ARB is 125°C, a 4-layer PCB with 1 oz. copper covering the outer layers and measuring 9 square inches is required with 0 LFM of air flow. 75 +24°C AMBIENT ARB 4.7 SQ-IN θJA (°C/W) ARB 200 LFM 01019-048 7 PCB AREA (SQ-IN) 4 10 50 45 40 35 ARE 0 LFM 30 ARE 200 LFM 25 ARE 400 LFM 20 ARB 9 SQ-IN 10 55 0 1 2 3 4 5 6 PCB AREA (SQ-IN) 7 8 9 10 01019-049 15 ARB 7.125 SQ-IN 60 Figure 49. Junction-to-Ambient Thermal Resistance vs. PCB Area 50 45 0 50 100 AIR FLOW (LFM) 150 200 01019-047 JUNCTION TEMPERATURE (°C) ARB 150 LFM 20 Figure 48. Junction-to-Ambient Thermal Resistance vs. PCB Area 65 40 25 10 ARB 6 SQ-IN 70 ARB 100 LFM 15 θJA (°C/W) Note that the AD8016 ARE is targeted at xDSL applications other than full-rate CO ADSL. The AD8016 ARE is targeted at g.lite and other xDSL applications where reduced power dissipation can be achieved through a reduction in output power. Extreme temperatures associated with full-rate ADSL using the AD8016 ARE should be avoided whenever possible. ARB 50 LFM 30 Figure 47. Junction Temperature vs. Air Flow Rev. C | Page 19 of 20 AD8016 Data Sheet OUTLINE DIMENSIONS 15.60 15.20 24 13 7.60 7.40 1 10.65 10.00 12 PIN 1 0.75 45° 0.25 2.65 2.35 0.30 0.10 1.27 BSC 0.51 0.33 SEATING PLANE 0.32 0.23 8° 0° 1.27 0.40 COMPLIANT WITH JEDEC STANDARDS MS-013-AD Figure 50. 24-Lead Batwing SOIC, Thermally Enhanced w/Fused Leads [SOIC_W_BAT] (RB-24) Dimensions shown in millimeters 9.80 9.70 9.60 3.55 3.50 3.45 15 28 4.50 4.40 4.30 1 14 BOTTOM VIEW 1.05 1.00 0.80 1.20 MAX SEATING PLANE COPLANARITY 0.10 0.65 BSC 0.30 0.19 8° 0° 0.20 0.09 0.75 0.60 0.45 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-153-AET 02-23-2012-A TOP VIEW 0.15 0.05 3.05 3.00 2.95 EXPOSED PAD (Pins Up) 6.40 BSC Figure 51. 28-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP] (RE-28-1) Dimensions shown in millimeters ORDERING GUIDE Model1 AD8016ARBZ AD8016ARBZ-REEL AD8016AREZ AD8016AREZ-REEL AD8016AREZ-REEL7 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 24-Lead SOIC_W_BAT 24-Lead SOIC_W_BAT 28-Lead TSSOP_EP 28-Lead TSSOP_EP 28-Lead TSSOP_EP Z = RoHS Compliant Part. ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01019-0-3/12(C) Rev. C | Page 20 of 20 Package Option RB-24 RB-24 RE-28-1 RE-28-1 RE-28-1