Cypress CY8C20110 Capsense express button capacitive controller Datasheet

CY8C20110/CY8C20180/CY8C20160
CY8C20140/CY8C20142
CapSense® Express™ Button
Capacitive Controllers
Features
■
■
■
10/8/6/4 Capacitive Button Input
❐ Robust sensing algorithm
❐ High sensitivity, low noise
❐ Immunity to RF and AC noise
❐ Low radiated EMC noise
❐ Supports wide range of input capacitance, sensor shapes,
and sizes
Target Applications
❐ Printers
❐ Cellular handsets
❐ LCD monitors
❐ Portable DVD players
Low Operating Current
❐ Active current: continuous sensor scan: 1.5 mA
❐ Deep sleep current: 4 uA
■
Industry's Best Configurability
❐ Custom sensor tuning, one optional capacitor
❐ Output supports strong drive for LED
2
❐ Output state can be controlled through I C or directly from
®
CapSense input state
2
❐ Run time re-configurable over I C
Advanced Features
❐ All GPIOs support LED dimming with configurable delay
option in CY8C21110
❐ Interrupt outputs
❐ User defined Inputs
❐ Wake on interrupt input
❐ Sleep control pin
❐ Nonvolatile storage of custom settings
❐ Easy integration into existing products – configure output to
match system
❐ No external components required
❐ World class free configuration tool
Cypress Semiconductor Corporation
Document Number: 001-54606 Rev. **
I2C Communication
❐ Supported from 1.8V
❐ Internal pull up resistor support option
❐ Data rate up to 400 kbps
2
❐ Configurable I C addressing
■
Industrial temperature range: –40°C to +85°C.
■
Available in16-pin COL, 8-pin, and 16-pin SOIC Packages
Overview
■
■
■
Wide Range of Operating Voltages
❐ 2.4V to 2.9V
❐ 3.10V to 3.6V
❐ 4.75V to 5.25V
•
These CapSense Express™ controllers support 4 to 10 capacitive sensing (CapSense buttons). The device functionality is
configured through an I2C port and can be stored in onboard
nonvolatile memory for automatic loading at power on. The
CY8C20110 is optimized for dimming LEDs in 15 selectable duty
cycles for back light applications. The device can be configured
to have up to 10 GPIOs connected to the PWM output. The PWM
duty cycle is programmable for variable LED intensities.
The four key blocks that make up these devices are: a robust
capacitive sensing core with high immunity against radiated and
conductive noise, control registers with nonvolatile storage,
configurable outputs, and I2C communications. The user can
configure registers with parameters needed to adjust the
operation and sensitivity of the CapSense buttons and outputs
and permanently store the settings. The standard I2C serial
communication interface enables the host to configure the
device and read sensor information in real time. The I2C address
is fully configurable without any external hardware strapping.
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 12, 2009
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Pinouts
Figure 1. Pin Diagram - 16 COL- CY8C20110 (10 Buttons)/CY8C20180 (8 Buttons)
CY8C20160 (6 Buttons)/CY8C20140 (4 Buttons)
Table 1. Pin Definitions – 16 COL- CY8C20110 (10 Buttons)/CY8C20180 (8 Buttons)
CY8C20160 (6 Buttons)/CY8C20140 (4 Buttons)[1]
Pin No.
Pin Name
1
GP0[0]
Description
Configurable as CapSense or GPIO
2
GP0[1]
Configurable as CapSense or GPIO
3
I2C SCL
I2C Clock
4
I2C SDA
I2C Data
5
GP1[0]
6
GP1[1]
7
VSS
8
GP1[2]
Configurable as CapSense or GPIO
9
GP1[3]
Configurable as CapSense or GPIO
10
GP1[4]
Configurable as CapSense or GPIO
11
XRES
Active high external reset with internal pull up
12
GP0[2]
13
VDD
14
GP0[3]
15
CSInt
16
GP0[4]
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Ground Connection
Configurable as CapSense or GPIO
Supply voltage
Configurable as CapSense or GPIO
Integrating Capacitor Input. The external capacitance is required
only if 5:1 SNR cannot be achieved. Typical range is 1 nF to 4.7 nF
Configurable as CapSense or GPIO
Note
1. 8/6/4 available configurable IOs can be configured to any of the 10 IOs of the package. After any of the 8/6/4 IOs are chosen, the remaining 2/4/6 IOs of the package
are not available for any functionality.
Document Number: 001-54606 Rev. **
Page 2 of 29
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Figure 2. Pin Diagram – 16 SOIC– CY8C20110 (10 Buttons)/CY8C20180 (8 Buttons)
CY8C20160 (6 Buttons)/CY8C20140 (4 Buttons)
Table 2. Pin Definitions – 16 SOIC– CY8C20110 (10 Buttons)/CY8C20180 (8 Buttons)
CY8C20160 (6 Buttons)/CY8C20140 (4 Buttons)1]
Pin No
Name
Description
1
GP0[3]
2
CSint
3
GP0[4]
Configurable as CapSense or GPIO
4
GP0[0]
Configurable as CapSense or GPIO
5
GP0[1]
Configurable as CapSense or GPIO
6
I2C
I2C Clock
7
I2C SDA
8
GP1[0]
Configurable as CapSense or GPIO
9
GP1[1]
Configurable as CapSense or GPIO
SCL
Configurable as CapSense or GPIO
Integrating Capacitor Input. The external capacitance is required only if 5:1 SNR
cannot be achieved. Typical range is 1 nF to 4.7 nF
I2C Data
10
VSS
11
GP1[2]
Configurable as CapSense or GPIO
Ground Connection
12
GP1[3]
Configurable as CapSense or GPIO
13
GP1[4]
Configurable as CapSense or GPIO
14
XRES
Active high external reset with internal pull up
15
GP0[2]
Configurable as CapSense or GPIO
16
VDD
Document Number: 001-54606 Rev. **
Supply voltage
Page 3 of 29
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Figure 3. Pin Diagram - 8-Pin SOIC- CY8C20142 (4 Button)
Table 3. Pin Definitions - 8-Pin SOIC - CY8C20142 (4 Button)
Pin No
Name
Description
1
VSS
2
I2C SCL
I2C Clock
3
I2C SDA
I2C Data
4
GP1[0]
Configurable as CapSense or GPIO
5
GP1[1]
Configurable as CapSense or GPIO
6
GP0[0]
Configurable as CapSense or GPIO
7
GP0[1]
Configurable as CapSense or GPIO
8
VDD
Document Number: 001-54606 Rev. **
Ground
Supply voltage
Page 4 of 29
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Typical Circuits
Circuit-1: Five Button and Five LED with I2C Interface
Circuit 2 - Two Buttons and Two LEDs with I2C Interface
Document Number: 001-54606 Rev. **
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Circuit 3 - Compatibility with 1.8V I2C Signaling
Note 1.8V ≤ VDD_I2C ≤ VDD_CE and 2.4V ≤ VDD_CE ≤ 5.25V
Circuit 4 - Powering Down CapSense Express Device for Low Power Requirements
Output
enable
LDO
Output
VDD
LED
Master
Or
Host
CapSense Express
I2C Pull
UPs
SDA
I2C
BUS
SCL
For low power requirements, if Vdd is to be turned off, this concept can be used. The requirement is that the Vdds of CapSense
Express, I2C pull ups, and LEDs should be from the same source such that turning off the Vdd ensures that no signal is applied to
the device while it is unpowered. The I2C signals should not be driven high by the master in this situation. If a port pin or group of port
pins of the master can cater to the power supply requirements of the circuit, the LDO can be avoided.
Document Number: 001-54606 Rev. **
Page 6 of 29
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I2C Interface
The CapSense Express devices support the industry standard I2C protocol, which can be used for:
■
Configuring the device
■
Reading the status and data registers of the device
■
Controlling device operation
■
Executing commands
The I2C address can be modified during configuration.
2
I C Device Addressing
The device uses a seven bit addressing protocol. The I2C data transfer is always initiated by the master sending a one byte address:
the first 7 bits contain the address and the LSB indicates the data transfer direction. Zero in the LSB bit indicates the write transaction
from master and one indicates read transfer by the master. The following table shows examples for different I2C addresses.
Table 4. I2C Address Examples
7 Bit Slave
Address
D7
D6
D5
D4
D3
D2
D1
D0
8 Bit Slave Address
1
0
0
0
0
0
0
1
0(W)
02
1
0
0
0
0
0
0
1
1(R)
03
75
1
0
0
1
0
1
1
0(W)
96
75
1
0
0
1
0
1
1
1(W)
97
I2C Clock Stretching
I2C
‘Clock stretching’ or ‘bus stalling’ in
communication protocol
is a state in which the slave holds the SCL line low to indicate
that it is busy. In this condition, the master is expected to wait till
the SCL is released by the slave.
When an I2C master communicates with the CapSense Express
device, the CapSense Express stalls the I2C bus after the
reception of each byte (that is, just before the ACK/NAK bit) until
processing of the byte is complete and critical internal functions
are executed. Use a fully I2C compliant master to communicate
with the CapSense Express device.
Document Number: 001-54606 Rev. **
If the I2C master does not support clock stretching (a bit banged
software I2C Master), the master must wait for a specific amount
of time (as specified in “Format for Register Write and Read” on
page 8) for each register write and read operation before the next
bit is transmitted. The I2C master must check the SCL status (it
should be high) before the I2C master initiates any data transfer
with CapSense Express. If the master fails to do so and
continues to communicate, the communication is erroneous.
The following diagrams represent the ACK time delays shown in
“Format for Register Write and Read” on page 8 for write and
read.
Page 7 of 29
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Figure 4. Write ACK Time Representation[2]
Figure 5. Read ACK Time Representation[3]
Format for Register Write and Read
Register write format
Start
Slave Addr + W
A
Reg Addr
A
Data
Register read format
Start
Slave Addr + W
Start
Slave Addr + R
A
A
Reg Addr
Data
A
A
Stop
Data
Legends:
Master
Slave
A
Data
A
.....
A
.....
Data
Data
N
A
Stop
Stop
A - ACK
N- NAK
Notes
2. Time to process the received data
3. Time taken for the device to send next byte
Document Number: 001-54606 Rev. **
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Operating Modes of I2C Commands
Normal Mode
In normal mode of operation, the acknowledgment time is
optimized. The timings remain approximately the same for
different configurations of the slave. To reduce the acknowledgment times in normal mode, the registers 0x06-0x09, 0x0C,
0x0D, 0x10-0x17, 0x50, 0x51, 0x57-0x60, 0x7E are given only
read access. Write to these registers can be done only in setup
mode.
Setup Mode
All registers have read and write access (except those which are
read only) in this mode. The acknowledgment times are longer
compared to normal mode. When CapSense scanning is
disabled (command code 0x0A in command register 0xA0), the
acknowledgment times can be improved to values similar to the
normal mode of operation.
Device Operation Modes
CapSense Express devices are configured to operate in any of
the following three modes to meet different power consumption
requirements:
Deep Sleep Mode
Deep sleep mode provides the lowest power consumption
because there is no operation running. All CapSense scanning
is disabled during this mode. In this mode, the device wakes up
only using an external GPIO interrupt. A sleep timer interrupt
cannot wake up a device from deep sleep mode. This is treated
as a continuous sleep mode without periodic wakeups. Refer to
the application note CapSense Express Power and Sleep
Considerations - AN44209 for details on different sleep modes.
To get the lowest power during this mode the sleep timer
frequency should be set to 1 Hz.
Sleep Control Pin
The devices require a dedicated sleep control pin to enable
reliable I2C communication in case any sleep mode is enabled.
This is achieved by pulling the sleep control pin low to wake up
the device and start I2C communication. The sleep control pin
can be configured on any GPIO.
Interrupt Pin to Master
■
Active Mode
To inform the master of any button press a GPIO can be
configured as interrupt output and all CapSense buttons can be
connected to this GPIO with an OR logic operator. This can be
configured using the software tool.
■
Periodic Sleep Mode
LED Dimming
■
Deep Sleep Mode
Active Mode
In the active mode, all the device blocks including the CapSense
sub system are powered. Typical active current consumption of
the device across the operating voltage range is 1.5 mA.
Periodic Sleep Mode
Sleep mode provides an intermediate power operation mode. It
is enabled by configuring the corresponding device registers
(0x7E, 0x7F). The device goes into sleep after there is no event
for stay awake counter (Reg 0x80) number of sleep intervals.
The device wakes up on sleep interval and It scans the capacitive sensors before going back to sleep again. If any sensor is
active, then the device wakes up. The device can also wake up
from sleep mode with a GPIO interrupt. The following sleep
intervals are supported in CapSense Express. The sleep interval
is configured through registers.
■
1.95 ms (512 Hz)
■
15.6 ms (64 Hz)
■
125 ms (8 Hz)
■
1s (1 Hz)
Document Number: 001-54606 Rev. **
To change the brightness and intensity of the LEDs, the host
master (MCU, MPU, DSP, and so on) must send I2C commands
and program the PWM registers to enable output pins, set duty
cycle, and mode configuration. The single PWM source is
connected to all GPIO pins and has a common user defined duty
cycle. Each PWM enabled pin has two possible outputs: PWM
and 0/1 (depending on the configuration). Four different modes
of LED dimming are possible, as shown in “LED Dimming Mode
1: Change Intensity on ON/OFF Button Status” on page 10 to
“LED Dimming Mode 4: Toggle Intensity on ON/OFF or OFF/ON
Button Transitions” on page 11. The operation mode and duty
cycle of the PWM enabled pins is common. This means that one
pin cannot behave as in Mode1 and another pin as in Mode 2.
Page 9 of 29
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LED Dimming Mode 1: Change Intensity on ON/OFF Button Status
LED Dimming Mode 2: Flash Intensity on ON Button Status
Document Number: 001-54606 Rev. **
Page 10 of 29
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LED Dimming Mode 3: Hold Intensity After ON/OFF Button Transition
LED Dimming Mode 4: Toggle Intensity on ON/OFF or OFF/ON Button Transitions
Note LED DIMMING is available only in CY8C20110.
Document Number: 001-54606 Rev. **
Page 11 of 29
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Register Map
Name
Register
Address
(in Hex)
Access
INPUT_PORT0
INPUT_PORT1
STATUS_POR0
STATUS_POR1
OUTPUT_PORT0
OUTPUT_PORT1
CS_ENABL0
CS_ENABLE
GPIO_ENABLE0
GPIO_ENABLE1
INVERSION_MASK0
INVERSION_MASK1
INT_MASK0
INT_MASK1
STATUS_HOLD_MSK0
STATUS_HOLD_MSK1
DM_PULL_UP0
DM_STRONG0
DM_HIGHZ0
DM_OD_LOW0
DM_PULL_UP1
DM_STRONG1
DM_HIGHZ1
DM_OD_LOW1
PWM_ENABLE0[8]
PWM_ENABLE1[8]
PWM_MODE_DC[8]
PWM_DELAY[8]
OP_SEL_00
OPR1_PRT0_00
OPR1_PRT1_00
OPR2_PRT0_00
OPR2_PRT1_00
OP_SEL_01
OPR1_PRT0_01
OPR1_PRT1_01
OPR2_PRT0_01
OPR2_PRT1_01
OP_SEL_02
OPR1_PRT0_02
OPR1_PRT1_02
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
R
R
R
R
W
W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Document Number: 001-54606 Rev. **
Writable Only in
SETUP Mode[4]
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Factory Default Values
I2C Max ACK Time in I2C Max ACK Time
of Registers
Normal Mode (ms) in Setup Mode (ms)
(in Hex)
00
00
00
00
00
00
00
00
00
00
00
00
00
00
03/1F[5]
03/1F[5]
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0.1
0.1
0.1
0.1
0.1
0.1
11
11
11
11
0.11
0.11
11
11
0.11
0.11
11
11
11
11
11
11
11
11
0.1
0.1
0.1
0.1
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
11
11
11
11
11
11
11
11
11
11
11
11
11
Page 12 of 29
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Register Map (continued)
Name
OPR2_PRT0_02
OPR2_PRT1_02
OP_SEL_03
OPR1_PRT0_03
OPR1_PRT1_03
OPR2_PRT0_03
OPR2_PRT1_03
OP_SEL_04
OPR1_PRT0_04
OPR1_PRT1_04
OPR2_PRT0_04
OPR2_PRT1_04
OP_SEL_10
OPR1_PRT0_10
OPR1_PRT1_10
OPR2_PRT0_10
OPR2_PRT1_10
OP_SEL_11
OPR1_PRT0_11
OPR1_PRT1_11
OPR2_PRT0_11
OPR2_PRT1_11
OP_SEL_12
OPR1_PRT0_12
OPR1_PRT1_12
OPR2_PRT0_12
OPR2_PRT1_12
OP_SEL_13
OPR1_PRT0_13
OPR1_PRT1_13
OPR2_PRT0_13
OPR2_PRT1_13
OP_SEL_14
OPR1_PRT0_14
OPR1_PRT1_14
OPR2_PRT0_14
OPR2_PRT1_14
CS_NOISE_TH
CS_BL_UPD_TH
CS_SETL_TIME
CS_OTH_SET
CS_HYSTERISIS
Register
Address
(in Hex)
Access
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Document Number: 001-54606 Rev. **
Writable Only in
SETUP Mode[4]
YES
YES
Factory Default Values
I2C Max ACK Time in I2C Max ACK Time
of Registers
Normal Mode (ms) in Setup Mode (ms)
(in Hex)
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
28
64
A0
00
0A
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.11
0.11
0.11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
35
35
11
Page 13 of 29
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Register Map (continued)
Name
CS_DEBOUNCE
CS_NEG_NOISE_TH
CS_LOW_BL_RST
CS_FILTERING
CS_SCAN_POS_00
CS_SCAN_POS_01
CS_SCAN_POS_02
CS_SCAN_POS_03
CS_SCAN_POS_04
CS_SCAN_POS_10
CS_SCAN_POS_11
CS_SCAN_POS_12
CS_SCAN_POS_13
CS_SCAN_POS_14
CS_FINGER_TH_00
CS_FINGER_TH_01
CS_FINGER_TH_02
CS_FINGER_TH_03
CS_FINGER_TH_04
CS_FINGER_TH_10
CS_FINGER_TH_11
CS_FINGER_TH_12
CS_FINGER_TH_13
CS_FINGER_TH_14
CS_IDAC_00
CS_IDAC_01
CS_IDAC_02
CS_IDAC_03
CS_IDAC_04
CS_IDAC_10
CS_IDAC_11
CS_IDAC_12
CS_IDAC_13
CS_IDAC_14
I2C_ADDR_LOCK
DEVICE_ID
DEVICE_STATUS
I2C_ADDR_DM
Register
Address
(in Hex)
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75[6]
76[6]
77[6]
78[6]
79
7A
7B
7C
Document Number: 001-54606 Rev. **
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
RW
Writable Only in
SETUP Mode[4]
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Factory Default Values
I2C Max ACK Time in I2C Max ACK Time
of Registers
Normal Mode (ms) in Setup Mode (ms)
(in Hex)
03
14
14
20
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
64
64
64
64
64
64
64
64
64
64
0A
0A
0A
0A
0A
0A
0A
0A
0A
0A
0.11
0.11
0.11
0.11
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
01
42/40/60/80/10[7]
03
00
0.11
0.11
0.11
0.11
11
11
11
11
Page 14 of 29
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CY8C20140/CY8C20142
Register Map (continued)
Name
SLEEP_PIN
SLEEP_CTRL
SLEEP_SA_CNTR
CS_READ_BUTTON
CS_READ_BLM
CS_READ_BLL
CS_READ_DIFFM
CS_READ_DIFFL
CS_READ_RAWM
CS_READ_RAWL
CS_READ_STATUSM
CS_READ_STATUSL
COMMAND_REG
Register
Address
(in Hex)
Access
7D[6]
7E
7F
80
81
82
83
84
85
86
87
88
89
8A[6]
8B[6]
8C[6]
8D[6]
A0
RW
RW
RW
RW
R
R
R
R
R
R
R
R
W
Writable Only in
SETUP Mode[4]
YES
Factory Default Values
I2C Max ACK Time in I2C Max ACK Time
of Registers
Normal Mode (ms) in Setup Mode (ms)
(in Hex)
00
00
00
00
00
00
00
00
00
00
00
00
0.1
0.1
0.1
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
11
11
11
11
11
11
11
11
11
11
11
11
00
0.1
11
Table 5. Device IDs
Part Number
Device ID
CY8C 20142
42
CY8C 20140
40
CY8C 20160
60
CY8C 20180
80
CY8C 20110
10
Note All the Ack times specified are maximum values with all buttons enabled and filer enabled with maximum order.
Notes
4. These registers are writable only after entering into setup mode. All the other registers available for read and write in Normal as well as in Setup mode.
5. The factory defaults of Reg 0x0E and 0x0F is 0x03 for 20142 device and 0x1F for 20140/60/80/10 devices.
6. The register 0x75- 0x78, 0x7D and 0x8A-0x8D are reserved.
7. The Device ID for different devices are tabulated in Table 5.
8. These registers are available only in CY8C20110.
Document Number: 001-54606 Rev. **
Page 15 of 29
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CapSense Express Commands
Command[9]
Executable
Mode
Description
Duration the Device is not
accessible after ACK (in ms)
W 00 A0 00
Get firmware revision
Setup/Normal
0
W 00 A0 01
Store current configuration to NVM
Setup/Normal
120
W 00 A0 02
Restore factory configuration
Setup/Normal
120
W 00 A0 03
Write NVM POR defaults
Setup/Normal
120
W 00 A0 04
Read NVM POR defaults
Setup/Normal
5
W 00 A0 05
Read current configurations (RAM)
Setup/Normal
5
W 00 A0 06
Reconfigure device (POR)
Setup
5
W 00 A0 07
Set Normal mode of operation
Setup/Normal
0
W 00 A0 08
Set Setup mode of operation
Setup/Normal
0
W 00 A0 09
Start scan
Setup/Normal
10
W 00 A0 0A
Stop scan
Setup/Normal
5
W 00 A0 0B
Get CapSense scan status
Setup/Normal
0
Register Conventions
This table lists the register conventions that are specific to this section.
Convention
RW
R
Description
Register has both read and write access
Register has only read access
Note
9. The ‘W’ indicates the write transfer. The next byte of data represents the 7 bit I2C address.
Document Number: 001-54606 Rev. **
Page 16 of 29
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Layout Guidelines and Best Practices
CapSense Button Shapes
Button Layout Design
X: Button to ground clearance (Refer to Table 6 on page 18)
Y: Button to button clearance (Refer to Table 6 on page 18)
Recommended via Hole Placement
Document Number: 001-54606 Rev. **
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Table 6. Recommended Layout Guidelines and Best Practices
Sl
Category
Min
1
Button Shape
2
Button Size
5 mm
3
Button-Button Spacing
= Button
Ground
Clearance
4
Button Ground Clearance
0.5 mm
5
Ground Flood - Top Layer
6
Ground Flood - Bottom Layer
7
Trace Length from Sensor to
PSoC - Buttons
Max
Recommendations/Remarks
Solid round pattern, round with LED hole, rectangle with
round corners
15 mm
10 mm
8 mm [X]
2 mm
Button ground clearance = Overlay Thickness [Y]
Hatched ground 7 mil trace and 45 mil grid (15% filling)
Hatched ground 7 mil trace and 70 mil grid (10% filling)
200 mm
8
Trace Width
9
Trace Routing
Traces should be routed on the non sensor side. If any non
CapSense trace crosses CapSense trace, ensure that intersection is orthogonal.
10
Via Position for the Sensors
Via should be placed near the edge of the button/slider to
reduce trace length thereby increasing sensitivity.
11
Via Hole Size for Sensor Traces
10 mil
12
Number of Vias on Sensor
Trace
13
CapSense Series Resistor
Placement
14
Distance between any
CapSense Trace to Ground
Flood
15
Device Placement
Mount the device on the layer opposite to sensor. The
CapSense trace length between the device and sensors
should be minimum
16
Placement of Components in 2
Layer PCB
Top layer - sensor pads and bottom layer - PSoC, other
components, and traces.
17
Placement of Components in 4
Layer PCB
Top layer - sensor pads, second layer - CapSense traces,
third layer - hatched ground, bottom layer - PSoC, other
components, and non CapSense traces
18
Overlay Thickness - Buttons
19
Overlay Material
Should to be non conductive material. Glass, ABS Plastic,
Formica
20
Overlay Adhesives
Adhesive should be non conductive and dielectrically homogenous. 467MP and 468MP adhesives made by 3M are
recommended.
21
LED Back Lighting
Cut a hole in the sensor pad and use rear mountable LEDs.
Refer the PCB layout below.
22
Board Thickness
Standard board thickness for CapSense FR4 based designs
is 1.6 mm.
Document Number: 001-54606 Rev. **
0.17 mm
1
10 mil
0 mm
0.20 mm
<100 mm.
0.17 mm (7 mil)
2
1
10 mm
Place CapSense series resistors close to PSoC for noise
suppression.CapSense resistors have highest priority place
them first.
20 mil
20 mil
2 mm
1 mm
Page 18 of 29
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Example PCB Layout Design with Two CapSense Buttons and Two LEDs
Figure 6. Top Layer
Figure 7. Bottom Layer
Document Number: 001-54606 Rev. **
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Operating Voltages
For details on I2C 1x ACK time, refer to “Register Map” on page 12 and “CapSense Express Commands” on page 16. I2C 4x ACK
time is approximately four times the values mentioned in these tables.
CapSense Constraints
Parameter
Min
Typ
Parasitic Capacitance (CP) of the
CapSense Sensor
Overlay Thickness
Supply Voltage Variation (VDD)
Document Number: 001-54606 Rev. **
0
1
Max
Units
30
pF
2
mm
Notes
All layout best practices followed, properly
tuned, and noise free condition.
± 5%
Page 20 of 29
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Electrical Specifications
Absolute Maximum Ratings
Parameter
Description
Min
Typ
Max
Unit
Notes
Higher storage temperatures reduce data
retention time. Recommended storage
temperature is +25°C ± 25°C (0°C to 50°C).
Extended duration storage temperatures
above 65°C degrade reliability
TSTG
Storage temperature
–55
25
+100
°C
TA
Ambient temperature with power
applied
–40
–
+85
°C
VDD
Supply voltage on VDD relative to VSS
–0.5
–
+6.0
V
VIO
DC input voltage
VSS – 0.5
–
VDD + 0.5
V
VIOZ
DC voltage applied to tristate
VSS – 0.5
–
VDD + 0.5
V
IMIO
Maximum current into any GPIO pin
–25
–
+50
mA
ESD
Electro static discharge voltage
2000
–
–
V
LU
Latch up current
–
–
200
mA
Min
Typ
Max
Unit
Human body model ESD
Operating Temperature
Parameter
Description
TA
Ambient temperature
–40
–
+85
°C
TJ
Junction temperature
–40
–
+100
°C
Min
Typ
Max
Unit
Notes
DC Electrical Characteristics
DC Chip Level Specifications
Parameter
Description
Notes
VDD
Supply voltage
2.40
–
5.25
V
IDD
Supply current
–
1.5
2.5
mA
Conditions are VDD = 3.10V, TA = 25°C
ISB
Deep Sleep mode current with POR
and LVD active
–
2.6
4
µA
VDD = 2.55V, 0°C < TA < 40°C
ISB
Deep Sleep mode current with POR
and LVD active
–
2.8
5
µA
VDD = 3.3V, –40°C < TA < 85°C
ISB
Deep Sleep mode current with POR
and LVD active
–
5.2
6.4
µA
VDD = 5.25V, –40°C < TA < 85°C
5V and 3.3V DC General Purpose I/O Specifications
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
-40°C<TA<85°C, 3.10V to 3.6V -40°C<TA<85°C. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only.
Min
Typ
Max
Unit
VOH1
Parameter
High output voltage on Port 0 pins
Description
VDD – 0.2
–
–
V
IOH < 10 µA, VDD > 3.10V, maximum of
20 mA source current in all I/Os.
VOH2
High output voltage on Port 0 pins
VDD – 0.9
–
–
V
IOH = 1 mA, VDD > 3.10V, maximum of
20 mA source current in all I/Os.
VOH3
High output voltage on Port 1 pins
VDD – 0.2
–
–
V
IOH < 10 µA, VDD > 3.10V, maximum of
20 mA source current in all I/Os.
VOH4
High output voltage on Port 1 pins
VDD – 0.9
–
–
V
IOH = 5 mA, VDD > 3.10V, maximum of
20 mA source current in all I/Os.
Document Number: 001-54606 Rev. **
Notes
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5V and 3.3V DC General Purpose I/O Specifications (continued)
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
-40°C<TA<85°C, 3.10V to 3.6V -40°C<TA<85°C. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only.
Parameter
Description
Min
Typ
Max
Unit
Notes
VOL
Low output voltage
–
–
0.75
V
IOL = 20 mA/pin, VDD > 3.10, maximum of
40/60 mA sink current on even port pins and
of 40/60 mA sink current on odd port
pins.[10]
VIL
Input low voltage
–
–
0.75
V
VDD = 3.10V to 3.6V.
VIH
Input high voltage
1.6
–
–
V
VDD = 3.10V to 3.6V.
VIL
Input low voltage
–
–
0.8
V
VDD = 4.75V to 5.25V.
VIH
Input high voltage
2.0
–
–
V
VDD = 4.75V to 5.25V.
VH
Input hysteresis voltage
–
140
–
mV
IIL
Input leakage
–
1
–
nA
Gross tested to 1 µA.
CIN
Capacitive load on pins as input
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25°C.
COUT
Capacitive load on pins as output
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25°C.
2.7 DC General Purpose IO Specifications
Min
Typ
Max
Unit
VOH1
Parameter
High output voltage on Port 0 pins
Description
VDD – 0.2
–
–
V
IOH <10 µA, maximum of 10 mA source
current in all IOs.
Notes
VOH2
High output voltage on Port 0 pins
VDD – 0.5
–
–
V
IOH = 0.2 mA, maximum of 10 mA
source current in all IOs.
VOH3
High output voltage on Port 1 pins
VDD – 0.2
–
–
V
IOH <10 µA, maximum of 10 mA source
current in all IOs.
VOH4
High output voltage on Port 1 pins
VDD – 0.5
–
–
V
IOH = 2 mA, maximum of 10 mA
source current in all IOs.
VOL1
Low output voltage
–
–
0.75
V
IOL = 10 mA/pin, VDD > 3.10, maximum of
20/30 mA sink current on even port pins and
of 20/30mA sink current on odd port pins.[11]
VIL
Input low voltage
–
–
0.75
V
VDD = 2.4 to 2.90V and 3.10V to 3.6V.
VIH1
Input High voltage
1.4
–
–
V
VDD = 2.4 to 2.7V.
VIH2
Input High voltage
1.6
–
–
V
VDD = 2.7 to 2.90V and 3.10V to 3.6V.
VH
Input hysteresis voltage
–
60
–
mV
IIL
Input leakage
–
1
–
nA
Gross tested to 1 µA.
CIN
Capacitive load on pins as input
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25°C.
COUT
Capacitive load on pins as output
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25°C
Notes
10. The maximum sink current is 40 mA for 20140 and 20142 devices and for all other devices the maximum sink current is 60 mA
11. The maximum sink current per port is 20 mA for 20140 and 20142 devices and for all other devices the maximum sink current is 30 mA.
Document Number: 001-54606 Rev. **
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2.7V DC Spec for I2C Line with 1.8V External Pull Up
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 2.9V and 3.10V to
3.60V, and -40°C<TA <85°C, respectively. Typical parameters apply to 2.7V at 25°C. The I2C lines drive mode must be set to open
drain and pulled up to 1.8V externally.
Parameter
Description
Min
Typ
Max
Unit
Notes
VOLP
Low output voltage
–
–
0.4
V
IOL=5 mA/pin
VIL
Input low voltage
–
–
0.75
V
VDD = 2.4 to 3.6V.
VIH
Input high voltage
1.4
–
–
V
VDD = 2.4 to 3.6V.
CI2C
Capacitive load on I2C pins
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25°C.
RPU
Pull up resistor
4
5.6
8
kΩ
Min
Typ
Max
Unit
–
–
2.36
2.60
2.40
2.65
V
V
2.39
2.75
3.98
2.45
2.92
4.05
2.51
2.99
4.12
V
V
V
DC POR and LVD Specifications
Parameter
VPPOR0
VPPOR1
VLVD0
VLVD2
VLVD6
Description
VDD Value for PPOR Trip
VDD= 2.7V
VDD= 3.3V, 5V
VDD Value for LVD Trip
VDD= 2.7V
VDD= 3.3V
VDD= 5V
Notes
VDD must be greater than or equal to 2.5V
during startup or internal reset.
DC Flash Write Specifications
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
-40°C<TA<85°C, 3.10V to 3.6V and -40°C<TA<85°C or 2.4V to 2.90V and -40°C<TA<85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C. These are for design guidance only. Flash Endurance and Retention specifications are valid only within the
range: 25°C±20°C during the Flash Write operation. It is at the user’s own risk to operate out of this temperature range. If Flash writing
is done out of this temperature range, the endurance and data retention reduces.
Symbol
VddIWRITE
IDDP
FlashENPB
FlashDR
Description
Supply Voltage for Flash Write Operations
Supply Current for Flash Write Operations
Flash Endurance
Flash Data Retention
Min
2.7
–
50,000[12]
10
Typ
–
5
–
–
Max
–
25
–
–
Units
V
mA
–
Years
Notes
Erase/write cycles
CapSense Electrical Characteristics
Max (V)
Typ (V)
Min (V)
Conditions for Supply
Voltage
3.6
3.3
3.1
<2.9
The device automatically reconfigures itself to work in
2.7V mode of operation.
>2.9 or <3.10
This range is not recommended for CapSense usage.
2.90
5.25
2.7
5.0
2.45
4.75
<2.45V
Result
The scanning for CapSense parameters shuts down
until the voltage returns to over 2.45V.
>3.10
The device automatically reconfigures itself to work in
3.3V mode of operation.
<2.4V
The device goes into reset.
<4.73V
The scanning for CapSense parameters shuts down
until the voltage returns to over 4.73V.
Note
12. Commands involving Flash Writes (0x01, 0x02, 0x03) must be executed only within the same VCC voltage range detected at POR (power on, or command 0x06) and
above 2.7V.
Document Number: 001-54606 Rev. **
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AC Electrical Specifications
5V and 3.3V AC General Purpose I/O Specifications
Parameter
Description
Min
Max
Unit
Notes
TRise0
Rise time, strong mode,
Cload = 50 pF, Port 0
15
80
ns
VDD = 3.10V to 3.6V and 4.75V to
5.25V, 10% - 90%
TRise1
Rise time, strong mode,
Cload = 50 pF, Port 1
15
50
ns
VDD = 3.10V to 3.6V, 10% - 90%
TFall
Fall time, strong mode,
Cload = 50 pF, all ports
10
50
ns
VDD = 3.10V to 3.6V and 4.75V to
5.25V, 10% - 90%
2.7V AC General Purpose I/O Specifications
Min
Max
Unit
TRise0
Parameter
Rise time, strong mode,
Cload = 50 pF, Port 0
Description
15
100
ns
VDD = 2.4V to 2.90V, 10% - 90%
Notes
TRise1
Rise time, strong mode,
Cload = 50 pF, Port 1
15
70
ns
VDD = 2.4V to 2.90V, 10% - 90%
TFall
Fall time, strong mode,
Cload = 50 pF
10
70
ns
VDD = 2.4V to 2.90V, 10% - 90%
AC I2C Specifications
Parameter
FSCLI2C
Description
Standard Fast Mode
Mode
Min
SCL clock frequency
Units
0
100
0
400
kbps
THDSTAI2C Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
4.0
–
0.6
–
µs
TLOWI2C
LOW period of the SCL clock
4.7
–
1.3
–
µs
I2C
HIGH period of the SCL clock
4.0
–
0.6
–
µs
TSUSTAI2C Setup time for a repeated START condition 4.7
–
0.6
–
µs
THDDATI2C Data hold time
0
–
0
–
µs
250
–
100
–
ns
THIGH
TSUDATI2C
TSUSTOI2C
TBUFI2C
TSPI2C
Data setup time
Setup time for STOP condition
4.0
–
0.6
–
µs
BUS free time between a STOP and START
condition
4.7
–
1.3
–
µs
–
–
0
50
ns
Pulse width of spikes suppressed by the
input filter
Document Number: 001-54606 Rev. **
Notes
Max Min Max
Fast mode not supported for
VDD < 3.0V
Page 24 of 29
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Figure 8. Definition of Timing for Fast/Standard Mode on the I2C Bus
Appendix- Examples of Frequently Used I2C Commands
Sl
No.
Requirement
I2C commands[13]
Comment
1
Enter into setup mode
W 00 A0 08
2
Enter into normal mode
W 00 A0 07
3
Load factory defaults to RAM
registers
W 00 A0 02
4
Do a software reset
W 00 A0 08
W 00 A0 06
5
Save current configuration to Flash
W 00 A0 01
6
Load factory defaults to RAM
registers and save as user configuration
W 00 A0 08
W 00 A0 02
W 00 A0 01
W 00 A0 06
Enter into setup mode
Load factory defaults to SRAM
Save the configuration to flash. Wait for time specified in
“CapSense Express Commands” on page 16.
Do software reset
7
Enable GP00 as CapSense button
W 00 A0 08
W 00 06 01
W 00 A0 01
W 00 A0 06
Enter into setup mode
Configuring CapSense buttons
Save the configuration to flash. Wait for time specified in
“CapSense Express Commands” on page 16.
Do software reset
8
Read CapSense button(GP00)
scan results
W 00 81 01
W 00 82
R 00 RD. RD. RD.
Select CapSense button for reading scan result
Set the read point to 82h
Consecutive 6 reads get baseline, difference count and
raw count (all two byte each)
9
Read CapSense button status
register
W 00 88
R 00 RD
Set the read pointer to 88
Reading a byte gets status CapSense inputs
Enter into setup mode
Do software reset
Note
13. The ‘W’ indicates the write transfer and the next byte of data represents the 7-bit I2C address. The I2C address is assumed to be ‘0’ in the above examples.
Similarly ‘R’ indicates the read transfer followed by 7-bit address and data byte read operations.
Document Number: 001-54606 Rev. **
Page 25 of 29
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CY8C20110/CY8C20180/CY8C20160
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Ordering Information
Ordering Code
Package
Diagram
Package Type
Operating
Temperature
CapSense
Block
CY8C20110-LDX2I
001-09116
16 COL[14]
Industrial
Yes
10
Yes
CY8C20110-SX2I
51-85068
16 SOIC
Industrial
Yes
10
Yes
CY8C20180-LDX2I
001-09116
16 COL[14]
Industrial
Yes
08
Yes
CY8C20180-SX2I
51-85068
16 SOIC
Industrial
Yes
08
Yes
CY8C20160-LDX2I
001-09116
16 COL[14]
Industrial
Yes
06
Yes
CY8C20160-SX2I
51-85068
16 SOIC
Industrial
Yes
06
Yes
CY8C20140-LDX2I
001-09116
16 COL[14]
Industrial
Yes
04
Yes
CY8C20140-SX2I
51-85068
16 SOIC
Industrial
Yes
04
Yes
CY8C20142-SX1I
51-85066
8 SOIC
Industrial
Yes
04
No
GPIOs
XRES Pin
Note For die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Ordering Code Definition
Table 7. Thermal Impedances by Package
Package
Typical θJA[15]
16 COL[1]
46 °C/W
16 SOIC
79.96 °C/W
8 SOIC
127.22 °C/W
Table 8. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature[16]
Maximum Peak Temperature
16 COL[1]
240 °C
260 °C
16 SOIC
240 °C
260 °C
8 SOIC
240 °C
260 °C
Notes
14. Earlier termed as QFN package.
15. TJ = TA + Power x θJA.
16. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5°C with Sn-Pb or 245 ± 5°C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
Document Number: 001-54606 Rev. **
Page 26 of 29
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CY8C20110/CY8C20180/CY8C20160
CY8C20140/CY8C20142
Package Diagrams
Figure 9. 16-Pin Chip On Lead 3 X 3 mm (Sawn) (001-09116)
Figure 10. 16-Pin (150-Mil) SOIC (51-85068)
Document Number: 001-54606 Rev. **
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CY8C20110/CY8C20180/CY8C20160
CY8C20140/CY8C20142
Figure 11. 8-Pin (150-Mil) SOIC (51-85066)
Document Number: 001-54606 Rev. **
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CY8C20110/CY8C20180/CY8C20160
CY8C20140/CY8C20142
Document History Page
Document Title: CY8C20110/CY8C20180/CY8C20160/CY8C20140/CY8C20142 CapSense® Express™ - Button Capacitive
Controllers
Document Number: 001-54606
Rev.
ECN.
Orig. of
Change
**
2741726
SLAN/FSU
Submission
Date
Description of Change
07/21/2009 New Data sheet
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© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
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Document Number: 001-54606 Rev. **
Revised July 12, 2009
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CapSense Express™ and PSoC Designer™ are trademarks and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks
referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C
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