APPLICATIONS Medical instrumentation Precision data acquisition Transducer interface Differential drive for High resolution input ADCs Remote sensors OUT1 OUT2 –VS FUNCTIONAL BLOCK DIAGRAM +VS 16 15 14 13 AD8224 –IN1 1 12 –IN2 RG1 2 11 RG2 RG1 3 10 RG2 +IN1 4 9 +IN2 7 8 06286-001 6 –VS 5 REF2 Two channels in a small 4 mm × 4 mm LFCSP Low input currents 10 pA maximum input bias current (B grade) 0.6 pA maximum input offset current (B grade) High CMRR 100 dB CMRR (minimum), G = 10 (B grade) 80 dB CMRR (minimum) to 5 kHz, G = 1 (B grade) Excellent ac specifications and low power 1.5 MHz bandwidth (G = 1) 14 nV/√Hz input noise (1 kHz) Slew rate 2 V/μs 750 μA quiescent supply current per amplifier (maximum) Versatility Rail-to-rail output Input voltage range to below negative supply rail 4 kV ESD protection 4.5 V to 36 V single supply ±2.25 V to ±18 V dual supply Gain set with single resistor (G = 1 to 1000) +VS FEATURES REF1 Preliminary Technical Data Precision, Dual-Channel, JFET Input Rail-to-Rail Instrumentation Amplifier AD8224 Figure 1. 4mm × 4 mm LFCSP Table 1. In Amps and Difference Amplifiers by Category High Perform. AD82201 AD8221 AD8222 AD82241 1 Low Cost AD85531 AD6231 High Volt. AD628 AD629 Mil Grade AD620 AD621 AD524 AD526 AD624 Low Power AD6271 Digital Gain AD85551 AD85561 AD85571 Rail-to-rail output. GENERAL DESCRIPTION The AD8224 is the first single-supply junction field effect transistor (JFET) input instrumentation amplifier available in the space-saving 16-lead, 4 mm×4 mm LFCSP. It requires the same board area as a typical single instrumentation amplifier, yet doubles the channel density and offers a lower cost per channel without compromising performance. Designed to meet the needs of high performance, portable instrumentation, the AD8224 has a minimum common-mode rejection ratio (CMRR) of 86 dB at dc and a minimum CMRR of 80 dB at 5 kHz for G = 1. Maximum input bias current is 10 pA and typically remains below 300 pA over the entire industrial temperature range. Despite the JFET inputs, the AD8224 typically has a noise corner of only 10 Hz. With the proliferation of mixed-signal processing, the number of power supplies required in each system has grown. Designed to alleviate this problem, the AD8224 can operate on a ±18 V dual supply, as well as on a single +5 V supply. The device’s rail-to-rail output stage maximizes dynamic range on the low voltage supplies common in portable applications. Its ability to run on a single 5 V supply eliminates the need for higher voltage, dual supplies. The AD8224 draws a maximum of 750 μA of quiescent current per amplifier, making it ideal for battery-powered devices. In addition, the AD8224 can be configured as a single-channel, differential output instrumentation amplifier. Differential outputs provide high noise immunity, which can be useful when the output signal must travel through a noisy environment, such as with remote sensors. The configuration can also be used to drive differential input ADCs. For a single-channel version, use the AD8220 device. Rev. PrB Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by AnalogDevices for its use,nor for any infringements of patents or other rightsof third parties that mayresult from its use. Specifications subject to change withoutnotice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registeredtrademarks arethe property oftheir respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD8224 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Layout .......................................................................................... 21 Applications....................................................................................... 1 Solder Wash................................................................................. 22 Functional Block Diagram .............................................................. 1 Input Bias Current Return Path ............................................... 22 General Description ......................................................................... 1 Input Protection ......................................................................... 22 Revision History .......................... Error! Bookmark not defined. RF Interference ........................................................................... 22 Specifications..................................................................................... 3 Common-Mode Input Voltage Range ..................................... 23 Absolute Maximum Ratings............................................................ 9 Applications..................................................................................... 24 Thermal Resistance ...................................................................... 9 Driving an Analog-to-Digital Converter ................................ 24 ESD Caution.................................................................................. 9 Differential Output .................................................................... 24 Pin Configuration and Function Descriptions........................... 10 Driving a Differential Input ADC............................................ 25 Typical Performance Characteristics ........................................... 11 Driving Cabling .......................................................................... 25 Theory of Operation ...................................................................... 20 Outline Dimensions ....................................................................... 26 Gain Selection ............................................................................. 20 Ordering Guide .......................................................................... 26 Reference Terminal .................................................................... 21 Rev. PrB | Page 2 of 27 Preliminary Technical Data AD8224 SPECIFICATIONS VS+ = +15 V, VS− = −15 V, VREF = 0 V, TA = +25°C, G = 1, RL = 2 kΩ, unless otherwise noted. Table 2. Single-Ended and Differential1 Output Configuration A Grade Parameter Test Conditions Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with 1 kΩ Source Imbalance VCM = ±10 V G=1 78 G = 10 94 dB G = 100 94 dB 94 dB G=1 74 dB G = 10 84 dB G = 100 84 dB 84 dB G = 1000 CMRR at 5 kHz VCM = ±10 V G = 1000 NOISE dB RTI noise = √(eni2 + (eno/G)2) Voltage Noise, 1 kHz Input Voltage Noise, eni VIN+, VIN− = 0 V 14 nV√Hz Output Voltage Noise, eno VIN+, VIN− = 0 V 90 nV√Hz 5 μV p-p RTI, 0.1 Hz to 10 Hz G=1 G = 1000 Current Noise VOLTAGE OFFSET f = 1 kHz 0.8 μV p-p 1 fA/√Hz RTI VOS = (VOSI) + (VOSO/G) Input Offset, VOSI Average TC 250 T = −40°C to +85°C Output Offset, VOSO Average TC Offset RTI vs. Supply (PSR) T = −40°C to +85°C μV 10 μV/°C 750 μV 10 μV/°C G=1 86 G = 10 96 dB dB G = 100 96 dB G = 1000 96 dB INPUT CURRENT (PER CHANNEL) Input Bias Current Over Temperature2 Input Offset Current Over Temperature2 GAIN 25 T = −40°C to +85°C 300 T = −40°C to +85°C G = 1 + (49.4 kΩ/RG) 5 pA pA 2 pA pA 1000 V/V G=1 0.06 % G = 10 0.3 % G = 100 0.3 % G = 1000 0.3 % Gain Range Gain Error Gain Nonlinearity 1 VOUT = ±10 V VOUT = −10 V to +10 V G=1 RL = 10 kΩ 10 15 ppm G = 10 RL = 10 kΩ 5 10 ppm G = 100 RL = 10 kΩ 30 60 ppm Rev. PrB | Page 3 of 27 AD8224 Preliminary Technical Data A Grade Parameter Typ Max G = 1000 RL = 10 kΩ Test Conditions Min 400 500 Unit ppm G=1 RL = 2 kΩ 10 15 ppm G = 10 RL = 2 kΩ 10 15 ppm G = 100 RL = 2 kΩ 50 75 ppm 3 10 ppm/°C −50 ppm/°C Gain vs. Temperature G=1 G > 10 INPUT Impedance (Pin to Ground)3 Input Operating Voltage Range Over Temperature 104||5 4 GΩ||pF VS = ±2.25 V to ±18 V for dual supplies −VS − 0.1 +VS − 2 V T = −40°C to +85°C −VS − 0.1 +VS − 2.1 V RL = 2 kΩ −14.3 +14.3 V OUTPUT Output Swing Over Temperature Output Swing Over Temperature T = −40°C to +85°C −14.3 +14.1 V RL = 10 kΩ −14.7 +14.7 V T = −40°C to +85°C −14.6 +14.6 V Short-Circuit Current 15 mA REFERENCE INPUT RIN IIN 40 VIN+, VIN− = 0 V Voltage Range kΩ 70 −VS Gain to Output +VS 1 ± 0.0001 μA V V/V POWER SUPPLY (PER AMPLIFIER) ±2.255 Operating Range Quiescent Current Over Temperature T = −40°C to +85°C ±18 V 750 μA 850 μA TEMPERATURE RANGE For Specified Performance −40 +85 °C Operational6 −40 +125 °C 1 Refers to differential configuration shown in Figure 64. Please refer to Figure 16 and Figure 17 for the relationship between input current and temperature. Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2. 4 The AD8224 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum allowable voltage where the input bias current is within the specification. 5 At this supply voltage, ensure that the input common-mode voltage is within the input voltage range specification. 6 The AD8224 is characterized from −40°C to +125°C. See the Typical Performance Characteristics section for expected operation in this temperature range. 2 3 Rev. PrB | Page 4 of 27 Preliminary Technical Data AD8224 VS+ = +15 V, VS− = −15 V, VREF = 0 V, TA = +25°C, G = 1, RL = 2 kΩ, unless otherwise noted. Table 3. Single-Ended Output Configuration—Dynamic Performance (Both Amplifiers) Parameter DYNAMIC RESPONSE Small Signal Bandwidth −3 dB G=1 G = 10 G = 100 G =1000 Settling Time 0.01% G=1 G = 10 G = 100 G =1000 Settling Time 0.001% G=1 G = 10 G = 100 G =1000 Slew Rate G = 1 to 100 Conditions Min A Grade Typ Max Unit TBD TBD TBD TBD kHz kHz kHz kHz TBD TBD TBD TBD μs μs μs μs TBD TBD TBD TBD μs μs μs μs 10 V step 10 V step TBD V/μs Please fill in TBDs if you can. VS+ = +15 V, VS− = −15 V, VREF = 0 V, TA = +25°C, G = 1, RL = 2 kΩ, unless otherwise noted. Table 4. Differential Output Configuration1—Dynamic Performance Parameter DYNAMIC RESPONSE Small Signal Bandwidth−3 dB G=1 G = 10 G = 100 G =1000 Settling Time 0.01% G=1 G = 10 G = 100 G =1000 Settling Time 0.001% G=1 G = 10 G = 100 G =1000 Slew Rate G = 1 to 100 1 Conditions Min A Grade Typ Max Unit TBD TBD TBD TBD kHz kHz kHz kHz TBD TBD TBD TBD μs μs μs μs TBD TBD TBD TBD μs μs μs μs 10 V step 10 V step TBD Refers to differential configuration shown in Figure 64. Rev. PrB | Page 5 of 27 V/μs AD8224 Preliminary Technical Data VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = +25°C, G = 1, RL = 2 kΩ, unless otherwise noted. Table 5. Single-Ended and Differential1 Output Configuration Parameter Test Conditions Min A Grade Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with 1 kΩ Source Imbalance G=1 VCM = 0 to 2.5 V G = 10 G = 100 G = 1000 CMRR at 5 kHz G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz Input Voltage Noise, eni Output Voltage Noise, eno RTI, 0.1 Hz to 10 Hz G=1 G = 1000 Current Noise VOLTAGE OFFSET Input Offset, VOSI Average TC Output Offset, VOSO Average TC Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT (PER CHANNEL) Input Bias Current Over Temperature2 Input Offset Current Over Temperature2 GAIN Gain Range Gain Error 78 dB 94 94 dB dB 94 dB 74 84 dB dB 84 84 dB dB RTI noise = √(eni2 + (eno/G)2) VIN+, VIN− = 0 V, VREF = 0 V VIN+, VIN− = 0 V, VREF = 0 V 14 90 nV√Hz nV√Hz f = 1 kHz 5 0.8 1 μV p-p μV p-p fA/√Hz RTI VOS = (VOSI) + (VOSO/G) T = −40°C to +85°C 300 10 800 μV μV/°C μV T = −40°C to +85°C 10 μV/°C 86 96 96 96 dB dB dB dB 25 T = −40°C to +85°C 300 T = −40°C to +85°C G = 1 + (49.4 kΩ/RG) 5 2 1 pA pA pA pA 1000 V/V 0.06 % 0.3 0.3 0.3 % % % 50 50 75 ppm ppm ppm VOUT = 0.3 V to 2.9 V for G = 1 VOUT = 0.3 V to 3.8 V for G > 1 G=1 G = 10 G = 100 G = 1000 Nonlinearity G=1 G = 10 G = 100 VOUT = 0.3 V to 2.9 V for G = 1 VOUT = 0.3 V to 3.8 V for G > 1 RL = 10 kΩ RL = 10 kΩ RL = 10 kΩ Rev. PrB | Page 6 of 27 35 35 50 Preliminary Technical Data Parameter AD8224 Test Conditions G = 1000 Min RL = 10 kΩ RL = 2 kΩ RL = 2 kΩ RL = 2 kΩ G=1 G = 10 G = 100 Gain vs. Temperature G=1 G > 10 INPUT Impedance (Pin to Ground)3 Input Voltage Range Over Temperature Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT RIN IIN Voltage Range Gain to Output POWER SUPPLY (PER AMPLIFIER) Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE For Specified Performance Operational5 Max Unit 650 750 ppm 35 35 50 50 ppm ppm 50 75 ppm 3 10 −50 ppm/°C ppm/°C 104||6 4 OUTPUT Output Swing Over Temperature A Grade Typ T = −40°C to +85°C RL = 2 kΩ T = −40°C to +85°C RL = 10 kΩ T = −40°C to +85°C GΩ||pF −0.1 −0.1 +VS − 2 V +VS − 2. V 0.25 0.3 4.75 4.70 V V 0.15 0.2 4.85 4.80 V V mA 15 40 70 +VS kΩ μA V V/V +4.5 +36 750 850 V μA μA −40 −40 +85 +125 °C °C VIN+, VIN− = 0 V −VS 1 ± 0.0001 T = −40°C to +85°C 1 Refers to differential configuration shown in Figure 64. Refer to Figure 16 and Figure 17 for the relationship between input current and temperature. 3 Differential and common-mode impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2. 4 The AD8224 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum allowable voltage where the input bias current is within the specification. 5 The AD8224 is characterized from −40°C to +125°C. See the Typical Performance Characteristics section for expected operation in that temperature range. 2 Rev. PrB | Page 7 of 27 AD8224 Preliminary Technical Data VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = +25°C, G = 1, RL = 2 kΩ, unless otherwise noted. Table 6. Single-Ended Output Configuration—Dynamic Performance (Both Amplifiers) Parameter DYNAMIC RESPONSE Small Signal Bandwidth −3 dB G=1 G = 10 G = 100 G =1000 Settling Time 0.01% G=1 G = 10 G = 100 G =1000 Settling Time 0.001% G=1 G = 10 G = 100 G =1000 Slew Rate G = 1 to 100 Conditions Min A Grade Typ Max TBD TBD TBD TBD 3 V Step 4 V Step 4 V Step 4 V Step TBD TBD TBD TBD 3 V Step 4 V Step 4 V Step 4 V Step TBD TBD TBD TBD TBD VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = +25°C, G = 1, RL = 2 kΩ, unless otherwise noted. Table 7. Differential Output Configuration1—Dynamic Performance Parameter DYNAMIC RESPONSE Small Signal Bandwidth −3 dB G=1 G = 10 G = 100 G =1000 Settling Time 0.01% G=1 G = 10 G = 100 G =1000 Settling Time 0.001% G=1 G = 10 G = 100 G =1000 Slew Rate G = 1 to 100 1 Conditions Min A Grade Typ Max Unit TBD TBD TBD TBD kHz kHz kHz kHz 3 V Step 4 V Step 4 V Step 4 V Step TBD TBD TBD TBD μs μs μs μs 3 V Step 4 V Step 4 V Step 4 V Step TBD TBD TBD TBD μs μs μs μs TBD Refers to differential configuration shown in Figure 64. Rev. PrB | Page 8 of 27 V/μs Preliminary Technical Data AD8224 ABSOLUTE MAXIMUM RATINGS Maximum Power Dissipation Table 8. Parameter Supply Voltage Power Dissipation Output Short Circuit Current Input Voltage (Common Mode) Differential Input Voltage Storage Temperature Operating Temperature Range2 Lead Temperature Range (Soldering 10 sec) Junction Temperature Rating ±18 V See Figure 2 Indefinite1 ±Vs ±Vs −65°C to +130°C −40°C to +125°C 300°C 130°C Package Glass Transition Temperature ESD (Human Body Model) ESD (Charge Device Model) ESD (Machine Model) 130°C 4 kV 1 kV 0.4 kV The maximum safe power dissipation for the AD8224 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 130°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the amplifiers. Exceeding a temperature of 130°C for an extended period can result in a loss of functionality. Figure 2 shows the maximum safe power dissipation in the package vs. the ambient temperature for the LFCSP on a 4-layer JEDEC standard board. 4.0 3.5 1 3.0 MAX POWER (W) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. 2.5 2.0 1.5 1.0 0.5 THERMAL RESISTANCE θJA = 86°C/W WHEN THERMAL PAD IS NOT SOLDERED TO BOARD 0 –60 Table 9. Thermal Pad Soldered to Board Not Soldered to Board θJA = 48°C/W WHEN THERMAL PAD IS SOLDERED TO BOARD θJA 48 86 –40 –20 0 20 40 60 80 AMBIENT TEMPERATURE (°C) Unit °C/W °C/W Figure 2. Maximum Power Dissipation ESD CAUTION The θJA values in Table 9 assume a 4-layer JEDEC standard board. If the thermal pad is soldered to the board, then it is also assumed it is connected to a plane. θJC at the exposed pad is 4.4°C/W. Rev. PrB | Page 9 of 27 100 120 140 06286-002 Assumes the load is referenced to mid-supply. Temperature for specified performance is −40°C to +85°C. For performance to +125°C, see the Typical Performance Characteristics section. 2 AD8224 Preliminary Technical Data 11 RG2 10 RG2 9 +IN2 –VS 8 TOP VIEW +VS 5 +IN1 4 AD8224 REF1 6 REF2 7 RG1 3 12 –IN2 06286-003 PIN 1 INDICATOR –IN1 1 RG1 2 15 OUT1 14 OUT2 13 –VS 16 +VS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 10. Pin Function Descriptions Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic −IN1 RG1 RG1 +IN1 +VS REF1 REF2 −VS +IN2 RG2 RG2 −IN2 −VS OUT2 OUT1 +VS Description Negative Input In-Amp 1. Gain Resistor In-Amp 1. Gain Resistor In-Amp 1. Positive Input In-Amp 1. Positive Supply. Reference Adjust In-Amp 1. Reference Adjust In-Amp 2. Negative Supply. Positive Input In-Amp 2. Gain Resistor In-Amp 2. Gain Resistor In-Amp 2. Negative Input In-Amp 2. Negative Supply. Output In-Amp 2. Output In-Amp 1. Positive Supply. Rev. PrB | Page 10 of 27 Preliminary Technical Data AD8224 TYPICAL PERFORMANCE CHARACTERISTICS Figure 4. Typical Distribution of CMRR (G = 1) Figure 7. Typical Distribution of Input Bias Current Figure 5. Typical Distribution of Input Offset Voltage Figure 8. Typical Distribution of Input Offset Current 1000 GAIN = +100 BANDWIDTH ROLL-OFF 100 (nV/ Hz) GAIN = +1 GAIN = +10 GAIN = 100/GAIN = +1000 10 1 1 10 100 1k 10k FREQUENCY (Hz) Figure 9. Voltage Spectral Density vs. Frequency Figure 6. Typical Distribution of Output Offset Voltage Rev. PrB | Page 11 of 27 100k 06286-009 GAIN = +1000 BANDWIDTH ROLL-OFF AD8224 Preliminary Technical Data XX 150 GAIN = +1000 130 PSRR (dB) XXX (X) BANDWIDTH LIMITED GAIN = +100 110 GAIN = +10 90 GAIN = +1 70 50 30 XX XX XX XXX (X) 10 10 1 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 10. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1) 06286-013 1s/DIV 06286-010 5µV/DIV Figure 13. Positive PSRR vs. Frequency, RTI XX 150 130 XXX (X) PSRR (dB) 110 GAIN = +1000 90 GAIN = +1 70 GAIN = +10 50 GAIN = +100 30 XX XXX (X) 10 10 1 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000) Figure 14. Negative PSRR vs. Frequency, RTI 8 0.3 INPUT BIAS CURRENT (pA) 5 4 3 2 0.2 INPUT OFFSET CURRENT ±5 0.1 7 0 5 –15.1V –0.1 –0.2 3 –5.1V INPUT BIAS CURRENT ±15 INPUT BIAS CURRENT ±5 1 –0.3 1 1 10 100 TIME (s) 1k –1 –16 –12 –8 –4 0 4 8 12 16 COMMON-MODE VOLTAGE (V) Figure 15. Input Current vs. Common-Mode Voltage Figure 12. Change in Input Offset Voltage vs. Warmup Time Rev. PrB | Page 12 of 27 –0.5 06286-015 –0.4 06286-012 Δ VOSI (µV) 6 INPUT OFFSET CURRENT ±15 INPUT OFFSET CURRENT (pA) 9 7 0 0.1 06286-014 1s/DIV 06286-011 1µV/DIV XX XX Preliminary Technical Data AD8224 160 140 1n IBIAS 100p 10p GAIN = +100 100 BANDWIDTH LIMITED GAIN = +1 GAIN = +10 80 IOS 1p GAIN = +1000 120 CMRR (dB) 0 25 50 75 100 125 150 TEMPERATURE (°C) 40 10 1 100 1k 10k 100k 06286-019 –25 06286-016 –50 130 06286-020 60 0.1p 10M 06286-021 INPUT BIAS CURRENT (A) 10n FREQUENCY (Hz) Figure 16. Input Bias Current and Offset Current Temperature, VS = ±15 V, VREF = 0 V Figure 19. CMRR vs. Frequency, 1 kΩ Source Imbalance 10 8 10n 6 4 IBIAS Δ CMRR (μV/V) CURRENT (A) 1n 100p 10p IOS 1p 2 0 –2 –4 –6 0.1p –8 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) –10 –50 06286-017 –50 30 50 70 90 110 70 60 GAIN = +1000 GAIN = +1000 50 40 GAIN = +100 GAIN = +100 GAIN = +10 GAIN (dB) 30 BANDWIDTH LIMITED 100 GAIN = +1 20 GAIN = +10 10 0 80 GAIN = +1 –10 –20 60 –30 40 10 100 1k 10k FREQUENCY (Hz) 100k 06286-018 CMRR (dB) 10 Figure 20. Change in CMRR vs. Temperature, G = 1 160 120 –10 TEMPERATURE (°C) Figure 17. Input Bias Current and Offset Current vs. Temperature, VS = +5 V, VREF = 2.5 V 140 –30 Figure 18. CMRR vs. Frequency –40 100 1k 10k 100k FREQUENCY (Hz) Figure 21. Gain vs. Frequency Rev. PrB | Page 13 of 27 1M VS = ±15V –10 –8 –6 RLOAD = 10kΩ –4 –2 0 2 4 6 8 06286-025 XXX RLOAD = 10kΩ NONLINEARITY (500ppm/DIV) RLOAD = 2kΩ RLOAD = 2kΩ 06286-022 XXX Preliminary Technical Data NONLINEARITY (5ppm/DIV) AD8224 VS = ±15V 10 –10 –8 –6 –4 VIN (V) –2 0 2 4 6 8 10 OUTPUT VOLTAGE (V) Figure 22. Gain Nonlinearity, G = 1 Figure 25. Gain Nonlinearity, G = 1000 RLOAD = 10kΩ VS = ±15V –10 –8 –6 –4 –2 0 2 4 6 8 +13V 12 6 0 –14.8V, +5.5V +14.9V, +5.5V +3V –4.8V, +0.6V +4.95V, +0.6V ±5V SUPPLIES –4.8V, –3.3V –6 +4.95V, –3.3V –14.8V, –8.3V +14.9V, –8.3V –5.3V –12 –18 –16 10 ±15V SUPPLIES –15.3V –12 –8 –4 0 4 8 12 16 OUTPUT VOLTAGE (V) VIN (V) 06286-026 INPUT COMMON-MODE VOLTAGE (V) RLOAD = 2kΩ 06286-023 XXX NONLINEARITY (5ppm/DIV) 18 Figure 26. Input Common-Mode Voltage Range vs. Output Voltage, G = 1, VREF = 0 V Figure 23. Gain Nonlinearity, G = 10 RLOAD = 10kΩ VS = ±15V –10 –8 –6 –4 –2 0 2 4 6 8 +0.1V, +1.7V +4.9V, +1.7V +5V SINGLE SUPPLY, VREF = +2.5V 1 +0.1V, +0.5V +4.9V, +0.5V 0 –0.3V 0 1 2 3 4 5 6 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 24. Gain Nonlinearity, G = 100 2 –1 –1 10 +3V 3 Figure 27. Input Common-Mode Voltage Range vs. Output Voltage, G = 1, VS = +5 V, VREF = 2.5 V Rev. PrB | Page 14 of 27 06286-027 INPUT COMMON-MODE VOLTAGE (V) RLOAD = 2kΩ 06286-024 XXX NONLINEARITY (50ppm/DIV) 4 Preliminary Technical Data AD8224 VS+ –1 +13V ±15V SUPPLIES 6 +3V –14.9V, +5.4V +14.9V, +5.4V –4.9V, +0.4V 0 +4.9V, +0.5V ±5V SUPPLIES –4.9V, –4.1V +4.9V, –4.1V –6 –5.3V –14.8V, –9V +14.9V, –9V +125°C –4 +4 +3 –8 –4 0 4 8 12 16 VS – Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, G = 100, VREF = 0 V 2 4 6 8 10 +85°C 12 +25°C 14 –40°C 16 18 DUAL SUPPLY VOLTAGE (±V) 06286-031 –12 +1 OUTPUT VOLTAGE (V) Figure 31. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ, G = 10, VREF = 0 V 4 VS+ –0.2 +3V 2 +4.9V, +1.7V +5V SINGLE SUPPLY, VREF = +2.5V 0 +0.4 +0.1V, –0.5V –1 –1 0 1 +4.9V, –0.5V –0.3V 2 3 4 +85°C +25°C –40°C +125°C +85°C +25°C –40°C +0.2 5 6 VS – OUTPUT VOLTAGE (V) Figure 29. Input Common-Mode Voltage Range vs. Output Voltage, G = 100, VS = +5 V, VREF = 2.5 V 2 4 6 8 10 12 14 16 18 DUAL SUPPLY VOLTAGE (±V) 06286-032 +0.1V, +1.7V 1 +125°C –0.4 OUTPUT SWING (V) 3 06286-029 Figure 32. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ, G = 10, VREF = 0 V VS+ 15 –1 –40°C +125°C 10 VOLTAGE SWING (V) –2 +25°C +85°C NOTES 1. THE AD8224 CAN OPERATE UP TO A VBE BELOW THE NEGATIVE SUPPLY, BUT THE BIAS CURRENT WILL INCREASE SHARPLY. +1 –40°C +25°C +85°C 6 8 10 +125°C 0 +125°C –5 –10 12 14 16 18 VOLTAGE SUPPLY (V) Figure 30. Input Voltage Limit vs. Supply Voltage, G = 1, VREF =0 V –15 100 06286-030 4 +85°C 5 +85°C +125°C VS– 2 –40°C +25°C +25°C –40°C 1k RLOAD (Ω) 10k 06286-033 INPUT COMMON-MODE VOLTAGE (V) –3 +125°C –15.3V –1 +85°C +25°C +2 –12 –18 –16 INPUT VOLTAGE (V) –40°C –2 OUTPUT SWING (V) 12 06286-028 INPUT COMMON-MODE VOLTAGE (V) 18 Figure 33. Output Voltage Swing vs. Load Resistance VS = ±15 V, VREF = 0 V Rev. PrB | Page 15 of 27 AD8224 Preliminary Technical Data 5 XX –40°C +25°C NO LOAD +85°C 47pF 100pF +125°C 3 XXX (X) VOLTAGE SWING (V) 4 2 +125°C 1 +25°C +85°C –40°C RLOAD (Ω) 20mV/DIV XX XX Figure 34. Output Voltage Swing vs. Load Resistance VS = +5 V, VREF = 2.5 V XX XXX (X) Figure 37. Small Signal Pulse Response for Various Capacitive Loads, VS = ±15 V, VREF = 0 V VS+ XX –40°C –1 +125°C –2 47pF 100pF NO LOAD +85°C +25°C –3 –4 XXX (X) OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES 5µs/DIV 06286-037 10k 1k 06286-034 0 100 +4 +3 +2 +125°C +85°C +25°C +1 2 4 6 8 10 12 14 16 IOUT (mA) 20mV/DIV XX XX Figure 35. Output Voltage Swing vs. Output Current, VS = ±15 V, VREF = 0 V Figure 38. Small Signal Pulse Response for Various Capacitive Loads, VS = +5 V, VREF = 2.5 V +85°C +25°C +125°C –2 +2 +125°C +1 +85°C +25°C –40°C 0 2 4 6 8 IOUT (mA) 10 12 14 16 Figure 36. Output Voltage Swing vs. Output Current, VS = +5 V, VREF = 2.5 V 30 25 GAIN = +10, +100, +1000 GAIN = +1 20 15 10 5 0 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 06286-039 –1 OUTPUT VOLTAGE SWING (V p-p) 35 06286-036 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES XX XXX (X) VS+ VS – 5µs/DIV 06286-038 –40°C 0 06286-035 VS – Figure 39. Output Voltage Swing vs. Large Signal Frequency Response Rev. PrB | Page 16 of 27 Preliminary Technical Data AD8224 XX XX 5V/DIV XXX (X) XXX (X) 5V/DIV 5µs TO 0.01% 6µs TO 0.001% 0.002%/DIV 58μs TO 0.01% 74μs TO 0.001% 200µs/DIV 20µs/DIV XX XXX (X) XX XX 06286-040 XX XX 06286-043 0.002%/DIV XX XXX (X) Figure 40. Large Signal Pulse Response and Settle Time, G = 1, RL = 10 kΩ, VS = ±15 V, VREF = 0 V Figure 43. Large Signal Pulse Response and Settle Time, G = 1000, RL = 10 kΩ, VS = ±15 V, VREF = 0 V XX XXX XXX (X) 5V/DIV 0.002%/DIV 4.3μs TO 0.01% 4.6μs TO 0.001% 20mV/DIV 4µs/DIV 06286-041 XX XXX (X) XXX 06286-044 20µs/DIV XX XX Figure 44. Small Signal Pulse Response, G = 1, RL = 2 kΩ, CL = 100 pF, VS = ±15 V, VREF = 0 V Figure 41. Large Signal Pulse Response and Settle Time, G = 10, RL = 10 kΩ, VS = ±15 V, VREF = 0 V XX XXX XXX (X) 5V/DIV 0.002%/DIV 8.1μs TO 0.01% 9.6μs TO 0.001% 20mV/DIV Figure 42. Large Signal Pulse Response and Settle Time, G = 100, RL = 10 kΩ, VS = ±15 V, VREF = 0 V 4µs/DIV 06286-042 XX XXX (X) XXX 06286-045 20µs/DIV XX XX Figure 45. Small Signal Pulse Response, G = 10, RL = 2 kΩ, CL = 100 pF, VS = ±15 V, VREF = 0 V. Rev. PrB | Page 17 of 27 XXX Preliminary Technical Data XXX AD8224 4µs/DIV 4µs/DIV Figure 46. Small Signal Pulse Response, G = 100, RL = 2 kΩ, C L= 100 pF, VS = ±15 V, VREF =0 V Figure 49. Small Signal Pulse Response, G = 10, RL = 2 kΩ, CL = 100 pF, VS = +5 V, VREF = 2.5 V XXX XXX XXX XXX 06286-049 20mV/DIV 06286-046 20mV/DIV 20mV/DIV Figure 50. Small Signal Pulse Response, G = 100, RL = 2 kΩ, CL = 100 pF, VS = +5 V, VREF = 2.5 V XXX XXX Figure 47. Small Signal Pulse Response, G = 1000, RL = 2 kΩ, CL = 100 pF, VS = ±15 V, VREF = 0 V 4µs/DIV XXX 06286-050 40µs/DIV XXX 06286-047 20mV/DIV 20mV/DIV Figure 48. Small Signal Pulse Response, G = 1, RL = 2 kΩ, CL = 100 pF, VS = +5 V, VREF = 2.5 V 40µs/DIV XXX 06286-051 4µs/DIV XXX 06286-048 20mV/DIV Figure 51. Small Signal Pulse Response, G = 1000,RL = 2 kΩ, CL = 100 pF, VS = +5 V, VREF = 2.5 V Rev. PrB | Page 18 of 27 Preliminary Technical Data AD8224 15 60 GAIN = +1000 GAIN = +100 10 GAIN (dB) SETTLING TIME (µs) 40 SETTLED TO 0.001% 20 GAIN = +10 0 SETTLED TO 0.01% 5 GAIN = +1 0 5 10 20 15 –40 100 06286-052 0 OUTPUT VOLTAGE STEP SIZE (V) 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 52. Settling Time vs. Step Size (G = 1) ±15 V, VREF = 0 V 06286-055 –20 Figure 55. Differential Output Configuration: Gain vs. Frequency 100 100 CMROUT = 20 log 90 VDIFF_OUT VCM_OUT 70 SETTLED TO 0.001% CMROUT (dB) SETTLING TIME (µs) 80 10 SETTLED TO 0.01% LIMITED BY MEASUREMENT SYSTEM 60 50 40 30 20 10 100 1000 GAIN (V/V) Figure 53. Settling Time vs. Gain for a 10 V Step, VS = ±15 V, VREF = 0 V Figure 54 Channel Separation vs. Frequency, RL = 2 kΩ, Source Channel at G = 1 Rev. PrB | Page 19 of 27 0 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 56. Differential Output Configuration: Common-Mode Output vs. Frequency 1M 06286-056 1 06286-053 10 1 AD8224 Preliminary Technical Data THEORY OF OPERATION +VS +VS NODE A R1 24.7kΩ +VS +VS NODE B RG –VS 20kΩ R2 24.7kΩ –VS NODE F +VS 20kΩ OUTPUT 20kΩ +VS +VS NODE C J1 Q1 +IN –VS A3 VPINCH NODE E NODE D C1 C2 A1 A2 Q2 –IN J2 VPINCH +VS –VS REF 20kΩ –VS –VS VB I 06286-057 I –VS Figure 57. Simplified Schematic The AD8224 is a JFET input, monolithic instrumentation amplifier based on the classic three op amp topology (see Figure 57). Input Transistor J1 and Input Transistor J2 are biased at a fixed current so that any input signal forces the output voltages of A1 and A2 to change accordingly. The input signal creates a current through RG that flows in R1 and R2 such that the outputs of A1 and A2 provide the correct, gained signal. Topologically, J1, A1, R1 and J2, A2, R2 can be viewed as precision current feedback amplifiers with a gain bandwidth of 1.5 MHz. The common-mode voltage and amplified differential signal from A1 and A2 are applied to a difference amplifier that rejects the common-mode voltage but amplifies the differential signal. The difference amplifier employs 20 kΩ laser trimmed resistors that result in an in-amp with gain error less than 0.04%. New trim techniques were developed to ensure that CMRR exceeds 86 dB (G = 1). Using JFET transistors, the AD8224 offers extremely high input impedance, extremely low bias currents of 10 pA maximum, low offset current of 0.6 pA maximum, and no input bias current noise. In addition, input offset is less than 125 μV and drift is less than 5 μV/°C. Ease of use and robustness were considered. A common problem for instrumentation amplifiers is that at high gains, when the input is overdriven, an excessive milliampere input bias current can result and the output can undergo phase reversal. Overdriving the input at high gains refers to when the input signal is within the supply voltages but the amplifier cannot output the gained signal. For example, at a gain of 100, driving the amplifier with 10 V on ±15 V constitutes overdriving the inputs since the amplifier cannot output 100 V. The AD8224 has none of these problems; its input bias current is limited to less than 10 μA and the output does not phase reverse under overdrive fault conditions. The AD8224 has extremely low load induced nonlinearity. All amplifiers that comprise the AD8224 have rail-to-rail output capability for enhanced dynamic range. The input of the AD8224 can amplify signals with wide common-mode voltages even slightly lower than the negative supply rail. The AD8224 operates over a wide supply voltage range. It can operate from either a single +4.5 V to +36 V supply or a dual ±2.25 V to ±18 V. The transfer function of the AD8224 is G =1+ 49.4 kΩ RG Users can easily and accurately set the gain using a single, standard resistor. Since the input amplifiers employ a current feedback architecture, the AD8224 gain bandwidth product increases with gain, resulting in a system that does not experience as much bandwidth loss as voltage feedback architectures at higher gains. GAIN SELECTION Placing a resistor across the RG terminals sets the gain of the AD8224. This is calculated by referring to Table 11 or by using the following gain equation. Rev. PrB | Page 20 of 27 RG = 49.4 kΩ G −1 Preliminary Technical Data AD8224 LAYOUT Table 11. Gains Achieved Using 1% Resistors 1% Standard Table Value of RG (Ω) 49.9 k 12.4 k 5.49 k 2.61 k 1.00 k 499 249 100 49.9 The AD8224 is a high precision device. To ensure optimum performance at the PC board level, care must be taken in the design of the board layout. The AD8224 pinout is arranged in a logical manner to aid in this task. Calculated Gain 1.990 4.984 9.998 19.93 50.40 100.0 199.4 495.0 991.0 Package Considerations The AD8224 is available in a 16-lead, 4 mm × 4 mm LFCSP. Blindly copying the footprint from another 4 mm × 4 mm LFCSP part is not recommended; it may not have the same thermal pad size and leads. Refer to the Outline Dimensions section to verify that the PCB symbol has the correct dimensions. Space between the leads and thermal pad should be kept as wide as possible for the best bias current performance. The AD8224 defaults to G = 1 when no gain resistor is used. The tolerance and gain drift of the RG resistor should be added to the AD8224’s specifications to determine the total gain accuracy of the system. When the gain resistor is not used, gain error and gain drift are kept to a minimum. Thermal Pad The AD8224’s 4 mm × 4 mm LFCSP comes with a thermal pad. This pad is connected internally to +VS. The pad can either be left unconnected or connected to the positive supply rail. REFERENCE TERMINAL The output voltage of the AD8224 is developed with respect to the potential on the reference terminal. This is useful when the output signal needs to be offset to a precise midsupply level. For example, a voltage source can be tied to the REF1 or REF2 pin to level-shift the output so that the AD8224 can drive a singlesupply ADC. Pin REFx is protected with ESD diodes and should not exceed either +VS or −VS by more than 0.5 V. For best performance, source impedance to the REF terminal should be kept below 1 Ω. As shown in Figure 57 the reference terminal, REF, is at one end of a 20 kΩ resistor. Additional impedance at the REF terminal adds to this 20 kΩ resistor and results in amplification of the signal connected to the positive input. The amplification from the additional RREF can be computed by The AD8224 has a higher CMRR over frequency than typical in-amps, which gives it greater immunity to disturbances, such as line noise and its associated harmonics. A well-implemented layout is required to maintain this high performance. Input source impedances should be matched closely. Source resistance should be placed close to the inputs so that it interacts with as little parasitic capacitance as possible. Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades the amplifier’s CMRR. CORRECT AD8224 CORRECT AD8224 VREF Because the AD8224 dissipates little power, heat dissipation is rarely an issue. If improved heat dissipation is desired (for example, when driving heavy loads), connect the thermal pad to the positive supply rail. For the best heat dissipation performance, the positive supply rail should be a plane in the board. See the section for thermal coefficients with and without the pad soldered. Common-Mode Rejection over Frequency 2 (20 kΩ + RREF ) 40 kΩ + RREF INCORRECT To preserve maximum pin compatibility with future dual instrumentation amplifiers, leave the pad unconnected. This can be done by not soldering the paddle at all or by soldering the part to a landing that is a not connected to any other net. For high vibration applications, a landing is recommended. Parasitics at the RGx pins can also affect CMRR over frequency. The PCB should be laid out so that the parasitic capacitances at each pin match. Traces from the gain setting resistor to the RGx pins should be kept short to minimize parasitic inductance. AD8224 VREF VREF + OP2177 AD8224 – – 06286-058 Reference + Errors introduced at the reference terminal feed directly to the output. Take care to tie the REFx pins to the appropriate local ground. Figure 58. Driving the Reference Pin Rev. PrB | Page 21 of 27 AD8224 Preliminary Technical Data Power Supplies INPUT BIAS CURRENT RETURN PATH A stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. The input bias current of the AD8224 must have a return path to common. When the source, such as a transformer, cannot provide a return current path, one should be created, as shown in Figure 60. The AD8224 has two positive supply pins (Pin 5 and Pin 16) and two negative supply pins (Pin 8 and Pin 13). While the part functions with only one pin from each supply pair connected, both pins should be connected for specified performance and optimum reliability. The AD8224 should be decoupled with 0.1 μF bypass capacitors, one for each supply. The positive supply decoupling capacitor should be placed near Pin 16, and the negative supply decoupling capacitor should be placed near Pin 8. Each supply should also be decoupled with a 10 μF tantalum capacitor. The tantalum capacitor can be placed further away from the AD8224 and can generally be shared by other precision integrated circuits. Figure 59 shows an example layout. INPUT PROTECTION All terminals of the AD8224 are protected against ESD. ESD protection is guaranteed to 4 kV (human body model).In addition, the input structure allows for dc overload conditions a diode drop above the positive supply and a diode drop below the negative supply. Voltages beyond a diode drop of the supplies cause the ESD diodes to conduct and enable current to flow through the diode. Therefore, an external resistor should be used in series with each of the inputs to limit current for voltages above +Vs. In either scenario, the AD8224 safely handles a continuous 6 mA current at room temperature. For applications where the AD8224 encounters extreme overload voltages, as in cardiac defibrillators, external series resistors and low leakage diode clamps, such as BAV199L, FJH1100, or SP720, should be used. 0.1µF INCORRECT CORRECT +VS 15 14 13 AD8224 AD8224 1 12 2 11 3 10 4 9 RG RG 5 6 7 AD8224 REF REF –VS –VS TRANSFORMER TRANSFORMER +VS +VS C 8 C R 1 fHIGH-PASS = 2πRC AD8224 C REF AD8224 C REF R 0.1µF –VS 06286-059 –VS CAPACITIVELY COUPLED CAPACITIVELY COUPLED Figure 60. Creating an IBIAS Path Figure 59. Example Layout RF INTERFERENCE SOLDER WASH The solder process can leave flux and other contaminants on the board. When these contaminants are between the AD8224 leads and thermal pad, they can create leakage paths that are larger than the AD8224’s bias currents. A thorough washing process removes these contaminants and restores the device’s excellent bias current performance. RF rectification is often a problem in applications where there are large RF signals. The problem appears as a small dc offset voltage. The AD8224 by its nature has a 5 pF gate capacitance (CG) at its inputs. Matched series resistors form a natural low-pass filter that reduces rectification at high frequency (see Figure 61). The relationship between external, matched series resistors and the internal gate capacitance is expressed as follows: Rev. PrB | Page 22 of 27 06286-060 16 +VS Preliminary Technical Data FilterFreq DIFF = 1 2πRCG FilterFreqCM = 1 2πRCG AD8224 FilterFreqCM = Mismatched CC capacitors result in mismatched low-pass filters. The imbalance causes the AD8224 to treat what would have been a common-mode signal as a differential signal. To reduce the effect of mismatched external CC capacitors, select a value of CD greater than 10 times CC. This sets the differential filter frequency lower than the common-mode frequency. +15V +15V 10µF + 0.1µF CC +IN 4.02kΩ +IN CD CG R –IN CG –VS VOUT AD8224 10nF R VOUT AD8224 –VS + 1nF R R 10µF REF –IN 4.02kΩ CC 1nF REF 0.1µF 10µF + –15V 10µF Figure 62. RFI Suppression + –15V 06286-061 0.1µF COMMON-MODE INPUT VOLTAGE RANGE Figure 61. RFI Filtering Without External Capacitors To eliminate high frequency common-mode signals while using smaller source resistors, a low-pass R-C network can be placed at the input of the instrumentation amplifier (see Figure 62). The filter limits the input signal bandwidth according to the following relationship: FilterFreq DIFF = 06286-062 0.1µF 1 2πR(CC + CG ) 1 2πR(2 CD + CC + CG ) The three op amp architecture of the AD8224 applies gain and then removes the common-mode voltage. Therefore, internal nodes in the AD8224 experience a combination of both the gained signal and the common-mode signal. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. Figure 26, Figure 27, Figure 28, and Figure 29 show the allowable common-mode input voltage ranges for various output voltages, supply voltages, and gains. Rev. PrB | Page 23 of 27 AD8224 Preliminary Technical Data APPLICATIONS +IN An instrumentation amplifier is often used in front of an analog-todigital converter to provide CMRR and additional conditioning such as a voltage level shift and gain (see Figure 63). In this example, a 2.7 nF capacitor and a 500 Ω resistor create an anti aliasing filter for the AD7685. The 2.7 nF capacitor also serves to store and deliver necessary charge to the switched capacitor input of the ADC. The 500 Ω series resistor reduces the burden of the 2.7 nF load from the amplifier. However, large source impedance in front of the ADC can degrade total harmonic distortion (THD). ADR435 4.7µF +IN ±50mV REF 2.7nF AD7685 –IN 06286-063 +2.5V Figure 63. Driving an ADC in a Low Frequency Application REF2 –OUT Figure 64. Differential Circuit Schematic Setting the Common-Mode Voltage The output common-mode voltage is set by the average of +IN2 and REF2. The transfer function is VCM_OUT = (V+OUT + V−OUT)/2 = (V+IN2 + VREF2)/2 The differential configuration of the AD8224 has the same excellent dc precision specifications as the single-ended output configuration and is recommended for applications in the frequency range of dc to 100 kHz. The circuit configuration, outlined in Table 7, refers to the configuration shown in Figure 64 only. The circuit includes an RC filter that maintains the stability of the loop. The transfer function for the differential output is: VDIFF_OUT = V+OUT − V−OUT = (V+IN − V−IN) × G A common application sets the common-mode output voltage to the midscale of a differential ADC. In this case, the ADC reference voltage is sent to the +IN2 terminal, and ground is connected to the REF2 terminal. This produces a commonmode output voltage of half the ADC reference voltage. 2-Channel Differential Output Using a Dual Op Amp DIFFERENTIAL OUTPUT Another differential output topology is shown in Figure 65. Instead of a second in-amp, ½ of a dual OP2177 op amp creates the inverted output. Because the OP2177 comes in an MSOP, this configuration allows the creation of a dual channel, precision differential output in-amp with little board area. Errors from the op amp are common to both outputs and are thus common mode. Errors from mismatched resistors also create a common-mode dc offset. Because these errors are common mode, they are likely to be rejected by the next device in the signal chain. where: G =1+ +IN2 500Ω AD8224 1.07kΩ 33pF +IN2 and REF2 have different properties that allow the reference voltage to be easily set for a wide variety of applications. +IN2 has high impedance but cannot swing to the supply rails of the part. REF2 must be driven with a low impedance, but can go 300 mV beyond the supply rails. 0.1µF +5V AD8224 +IN AD8224 49.4 kΩ +OUT –IN RG REF 4.99kΩ 4.99kΩ VREF + – OP2177 –OUT Figure 65. Differential Output Using Op Amp Rev. PrB | Page 24 of 27 06286-065 10µF +OUT 20kΩ – + +5V + –IN + AD8224 – For applications where THD performance is critical, the series resistor needs to be small. At worst, a small series resistor can load the AD8224, potentially causing the output to overshoot or ring. In such cases, a buffer amplifier, such as the AD8615, should be used after the AD8224 to drive the ADC. RG 06286-064 DRIVING AN ANALOG-TO-DIGITAL CONVERTER Preliminary Technical Data AD8224 +12V 10µF + 0.1µF +5V 100pF NPO 1kΩ 5% +IN 0.1µF +OUT 1000pF AD8224 (DIFF OUT) 1kΩ –IN +IN2 100pF NPO 5% 806Ω –OUT REF2 IN– 2.7nF 2.7nF + AD7688 GND REF 10µF X5R +12V +5V REF 10µF VDD IN+ 806Ω 0.1µF 0.1µF VIN –12V +5V REF VOUT 0.1µF ADR435 06286-066 GND Figure 66. Driving a Differential ADC DRIVING A DIFFERENTIAL INPUT ADC Reference The AD8224 can be configured in differential output mode to drive a differential analog-to-digital converter. Figure 66 illustrates several of the concepts. The ADR435 supplies a reference voltage to both the ADC and the AD8224. Because REF2 on the AD8224 is grounded, the common-mode output voltage is precisely half the reference voltage, exactly where it needs to be for the ADC. The 1 kΩ resistor, 1000 pF capacitor, and 100 pF capacitors in front of the in-amp form a 76 kHz filter. This is the first of two antialiasing filters in the circuit and helps to reduce the noise of the system. The 100 pF capacitors protect against commonmode RFI signals. Note that they are 5% COG/NPO types. These capacitors match well over time and temperature, which keeps the system’s CMRR high over frequency. Second Antialiasing Filter An 806 Ω resistor and 2.7 nF capacitor are located between each AD8224 output and ADC input. They create a 73 kHz low-pass filter for another stage of antialiasing protection. DRIVING CABLING All cables have a certain capacitance per unit length, which varies widely with cable type. The capacitive load from the cable may cause peaking in the AD8224 output response. To reduce peaking, use a resistor between the AD8224 and the cable. Because cable capacitance and desired output response vary widely, this resistor is best determined empirically. A good starting point is 50 Ω. The AD8224 operates at a low enough frequency that transmission line effects are rarely an issue; therefore, the resistor need not match the characteristic impedance of the cable. These four elements also isolate the ADC from loading the AD8224. The 806 Ω resistor shields the AD8224 from the ADC’s switched capacitor input which looks like a time varying load. The 2.7 nF capacitor provides charge to the switched capacitor front end of the ADC. If the application requires a lower frequency antialiasing filter, increase the value of the capacitor rather than the resistor. The 1 kΩ resistors can also protect an ADC from overvoltages. Because the AD8224 runs on wider supply voltages than a typical ADC, there is a possibility of overdriving the ADC. This is not an issue with a PulSAR® converter, such as the AD7688. Its input can handle a 130 mA overdrive, which is much higher than the short-circuit limit of the AD8224. However, other converters have less robust inputs and may need the added protection. Rev. PrB | Page 25 of 27 AD8224 (DIFF OUT) AD8224 (SINGLE OUT) 06286-067 First Antialiasing Filter Figure 67. Driving a Cable AD8224 Preliminary Technical Data OUTLINE DIMENSIONS 4.00 BSC SQ 0.60 MAX 12 13 3.75 BSC SQ TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING 0.30 PLANE 0.23 0.18 1 16 EXPOSED PAD 0.65 BSC 4 9 8 PIN 1 INDICATOR 2.65 2.50 SQ 2.35 5 0.25 MIN 1.95 BCS 0.80 MAX 0.65 TYP BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.20 REF 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGC. 031006-A PIN 1 INDICATOR 0.50 0.40 0.30 Figure 68. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-13) Dimensions are shown in millimeters ORDERING GUIDE Model AD8224ACPZ-R71 AD8224ACPZ-RL1 AD8224ACPZ-WP1 AD8224BCPZ-R71 AD8224BCPZ-RL1 AD8224BCPZ-WP1 AD8224-EVALZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Product Description 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ Evaluation Board Z = Pb-free part. Rev. PrB | Page 26 of 27 Package Option CP-16-13 CP-16-13 CP-16-13 CP-16-13 CP-16-13 CP-16-13 Preliminary Technical Data AD8224 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06286-0-12/06(PrB) Rev. PrB | Page 27 of 27