TI1 DAC2904 Dual, 14-bit, 125msps digital-to-analog converter Datasheet

DA
C
290
4
DAC2904
www.ti.com.............................................................................................................................................. SBAS198C – AUGUST 2001 – REVISED OCTOBER 2009
Dual, 14-Bit, 125MSPS
DIGITAL-TO-ANALOG CONVERTER
Check for Samples: DAC2904
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
1
2
125MSPS UPDATE RATE
SINGLE SUPPLY: +3.3V or +5V
HIGH SFDR: 78dB at fOUT = 10MHz
LOW GLITCH: 2pV-s
LOW POWER: 310mW
INTERNAL REFERENCE
POWER-DOWN MODE: 23mW
DESCRIPTION
The DAC2904 is a monolithic, 14-bit, dual-channel,
high-speed Digital-to-Analog Converter (DAC), and is
optimized to provide high dynamic performance while
dissipating only 310mW.
Operating with high update rates of up to 125MSPS,
the
DAC2904
offers
exceptional
dynamic
performance, and enables the generation of very-high
output frequencies suitable for “Direct IF”
applications. The DAC2904 has been optimized for
communications applications in which separate I and
Q data are processed while maintaining tight-gain
and offset matching.
Each DAC has a high-impedance differential-current
output, suitable for single-ended or differential
analog-output configurations.
COMMUNICATIONS:
– Base Stations, WLL, WLAN
– Baseband I/Q Modulation
• MEDICAL/TEST INSTRUMENTATION
• ARBITRARY WAVEFORM GENERATORS
(ARB)
• DIRECT DIGITAL SYNTHESIS (DDS)
space
space
The DAC2904 combines high dynamic performance
with a high update rate to create a cost-effective
solution for a wide variety of waveform-synthesis
applications:
• Pin compatibility between family members
provides 10-bit (DAC2900), 12-bit (DAC2902),
and 14-bit (DAC2904) resolution.
• Pin compatible to the AD9767 dual DAC.
• Gain matching is typically 0.5% of full-scale, and
offset matching is specified at 0.02% max.
• The DAC2904 utilizes an advanced CMOS
process; the segmented architecture minimizes
output-glitch energy, and maximizes the dynamic
performance.
• All digital inputs are +3.3V and +5V logic
compatible. The DAC2904 has an internal
reference circuit, and allows use in a multiplying
configuration.
The DAC2904 is available in a TQFP-48 package,
and is specified over the extended industrial
temperature range of –40°C to +85°C.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2009, Texas Instruments Incorporated
DAC2904
SBAS198C – AUGUST 2001 – REVISED OCTOBER 2009.............................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
(1)
(2)
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
DAC2904Y
TQFP-48
PFB
–40°C to +85°C
DAC2904Y
ORDERING
NUMBER (2)
TRANSPORT
MEDIA,
QUANTITY
DAC2904Y/250
Tape and Reel, 250
DAC2904Y/1K
Tape and Reel, 1k
DAC2904IPFB
Tray, 250
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Models with a slash (/) are available only in tape and reel media in the quantities indicated (for example, /1K indicates 1000 devices per
reel). Ordering 1000 pieces of DAC2904Y/1K will get a single 1000-piece tape and reel.
ABSOLUTE MAXIMUM RATINGS (1)
DAC2904
UNIT
+VA to AGND
–0.3 to +6
V
+VD to DGND
–0.3 to +6
V
–0.3 to +0.3
V
–6 to +6
V
CLK, PD to DGND
–0.3 to VD +0.3
V
D0–D9 to DGND
–0.3 to VD +0.3
V
IOUT, I OUT to AGND
–1 to VA + 0.3
V
BW, BYP to AGND
–0.3 to VA + 0.3
V
REFIN, FSA to AGND
–0.3 to VA + 0.3
V
INT/EXT to AGND
–0.3 to VA + 0.3
V
Junction Temperature
+150
°C
Case Temperature
+100
°C
Storage Temperature
+125
°C
AGND to DGND
+VA to +VD
(1)
2
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
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ELECTRICAL CHARACTERISTICS
TMIN to TMAX, +VA = +5V, +VD = +3.3V, differential transformer coupled output, and 50Ω doubly-terminated, unless otherwise
noted. Independent Gain Mode.
DAC2904
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
Resolution
Output Update Rate (fCLOCK)
14
Bits
125
MSPS
STATIC ACCURACY (1)
Differential Nonlinearity (DNL)
TA = +25°C
±4.0
LSB
Integral Nonlinearity (INL)
TA = +25°C
±5.0
LSB
DYNAMIC PERFORMANCE
Spurious-Free Dynamic Range (SFDR)
To Nyquist
82
dBc
fOUT = 1MHz, fCLOCK = 50MSPS
–6dBFS Output
77
dBc
–12dBFS Output
72
dBc
fOUT = 1MHz, fCLOCK = 26MSPS
82
dBc
fOUT = 2.18MHz, fCLOCK = 52MSPS
81
dBc
fOUT = 5.24MHz, fCLOCK = 52MSPS
81
dBc
fOUT = 10.4MHz, fCLOCK = 78MSPS
78
dBc
fOUT = 15.7MHz, fCLOCK = 78MSPS
72
dBc
fOUT = 5.04MHz, fCLOCK = 100MSPS
80
dBc
fOUT = 20.2MHz, fCLOCK = 100MSPS
69
dBc
fOUT = 20.1MHz, fCLOCK = 125MSPS
69
dBc
fOUT = 40.2MHz, fCLOCK = 125MSPS
64
dBc
0dBFS Output
71
Spurious-Free Dynamic Range within a
Window
fOUT = 1MHz, fCLOCK = 50MSPS
2MHz span
90
dBc
fOUT = 5.24MHz, fCLOCK = 52MSPS
10MHz span
80
88
dBc
fOUT = 5.26MHz, fCLOCK = 78MSPS
10MHz span
88
dBc
fOUT = 5.04MHz, fCLOCK = 125MSPS
10MHz span
88
dBc
Total Harmonic Distortion (THD)
dBc
fOUT = 1MHz, fCLOCK = 50MSPS
–79
fOUT = 5.24MHz, fCLOCK = 52MSPS
–77
dBc
fOUT = 5.26MHz, fCLOCK = 78MSPS
–76
dBc
fOUT = 5.04MHz, fCLOCK = 125MSPS
–75
dBc
0dBFS output
80
dBc
0dBFS output
68
dBc
0dBFS output
67
dBc
fOUT = 1MHz, fCLOCK = 52MSPS
85
dBc
fOUT = 20MHz, fCLOCK = 125MSPS
77
dBc
Multitone Power Ratio
fOUT = 2.0MHz to 2.99MHz, fCLOCK =
65MSPS
–70
dBc
Eight tone with 110kHz spacing
Signal-to-Noise Ratio (SNR)
fOUT = 5.02MHz, fCLOCK = 50MHz
Signal-to-Noise and Distortion (SINAD)
fOUT = 5.02MHz, fCLOCK = 50MHz
Channel Isolation
(1)
At output lOUT, while driving a virtual ground.
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ELECTRICAL CHARACTERISTICS (continued)
TMIN to TMAX, +VA = +5V, +VD = +3.3V, differential transformer coupled output, and 50Ω doubly-terminated, unless otherwise
noted. Independent Gain Mode.
DAC2904
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE, continued
Output Settling Time (2)
Output Rise Time
(2)
Output Fall Time (2)
To 0.1%
30
ns
10% to 90%
2
ns
10% to 90%
2
ns
2
pV-s
Glitch Impulse
DC ACCURACY
Full-Scale Output Range (3)(FSR)
All Bits HIGH, IOUT
2
20
–1.0
+1.25
mA
Output Compliance Range
With internal reference
Gain Error—Full-Scale
With internal reference
–5
±1
+5
%FSR
Gain Error
With internal reference
–2.5
±1
+2.5
%FSR
Gain Matching
With internal reference
–2.0
0.5
+2.0
Gain Drift
With internal reference
Offset Error
With internal reference
Offset Drift
With internal reference
Power-Supply Rejection, +VA
+5V, ±10%
Power-Supply Rejection, +VD
+3.3V, ±10%
Output Noise
+0.02
%FSR
ppmFSR/°
C
±0.2
–0.2
+0.2
%FSR/V
–0.025
+0.025
%FSR/V
IOUT = 20mA, RLOAD = 50Ω
IOUT = 2mA
Output Resistance
Output Capacitance
%FSR
ppmFSR/°
C
±50
–0.02
V
IOUT, I OUT to ground
50
pA/√Hz
30
pA/√Hz
200
kΩ
6
pF
REFERENCE/CONTROL AMP
Reference Voltage
+1.18
+1.25
+1.31
V
ppmFSR/°
C
Reference Voltage Drift
±50
Reference Output Current
100
nA
Reference Multiplying Bandwidth
0.3
MHz
Input Compliance Range
+0.5
+1.25
V
DIGITAL INPUTS
Logic Coding
Straight Binary
Logic High Voltage, VIH
+VD = 5V
3.5
5
Logic Low Voltage, VIL
+VD = 5V
Logic High Voltage, VIH
+VD = 3.3V
Logic Low Voltage, VIL
+VD = 3.3V
0
+VD = 3.3V
±10
μA
+VD = 3.3V
±10
μA
5
pF
Logic High Current, IIH
(4)
Logic Low Current
Input Capacitance
(2)
(3)
(4)
4
0
V
2
1.2
3
V
V
0.8
V
Measured single-ended into 50Ω load.
Nominal full-scale output current is 32 ×IREF; see Applicationxx section for details.
Typically 45μA for the PD pin, which has an internal pull-down resistor.
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ELECTRICAL CHARACTERISTICS (continued)
TMIN to TMAX, +VA = +5V, +VD = +3.3V, differential transformer coupled output, and 50Ω doubly-terminated, unless otherwise
noted. Independent Gain Mode.
DAC2904
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
Supply Voltages
+VA
+3.0
+5
+5.5
V
+VD
+3.0
+3.3
+5.5
V
Supply Current
IVA
(5)
+VA = +5V, lOUT = 20mA
58
65
mA
IVA
(5)
Power-Down mode
1.7
3
mA
IVD
(5)
4.2
7
mA
IVD
(6)
17
19.5
mA
Power Dissipation (5)
+VA = +5V, +VD = 3.3V, lOUT = 20mA
310
350
mW
Power Dissipation (6)
+VA = +5V, +VD = 3.3V, lOUT = 20mA
348
390
mW
Power Dissipation (5)
+VA = +5V, +VD = 3.3V, lOUT = 2mA
130
Power-Down mode
23
Power Dissipation
mW
38
mW
Thermal Resistance, TQFP-48
θJA
60
°C/W
θJC
13
°C/W
TEMPERATURE RANGE
Specified
Ambient
–40
+85
°C
Operating
Ambient
–40
+85
°C
(5)
(6)
Measured at fCLOCK = 25MSPS and fOUT = 1MHz.
Measured at fCLOCK = 100MSPS and fOUT = 40MHz.
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DAC2904
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DEVICE INFORMATION
NC
+VA
lOUT1
IOUT 1
FSA1
REFIN
GSET
FSA2
IOUT 2
lOUT2
AGND
PD
PFB PACKAGE
TQFP-48
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
37
1
36 D0-2
D12_1 2
35 D1-2
D11_1 3
34 D2_2
D10_1 4
33 D3_2
D9_1 5
32 D4_2
D13_1 (MSB)
D8_1 6
31 D5_2
DAC2904
13
14
15
16
17
18
19
20
21
22
23
24
D12_2
25 D11_2
D13_2 (MSB)
D2_1 12
+VD
26 D10_2
DGND
D3_1 11
WRT2
27 D9_2
CLK2
D4_1 10
CLK1
28 D8_2
WRT1
D5_1 9
+VD
29 D7_2
DGND
D6_1 8
D0-1
30 D6_2
D1-1
D7_1 7
TERMINAL FUNCTIONS
TERMINAL
6
NAME
NO.
D[13:0]_1
1–14
Data port DAC1, data bit 13 (MSB) to bit 0 (LSB)
DESCRIPTION
DGND
15, 21
Digital ground
+VD
16, 22
Digital supply, +3.0V to +5.5V
WRT1
17
DAC1 input latches write signal
CLK1
18
Clock input DAC1
CLK2
19
Clock input DAC2
WRT2
20
DAC2 input latches write signal
D[13:0]_2
23–36
PD
37
Power-down function control input. H = DAC in power-down mode; L = DAC in normal operation (internal pull-down for default L).
AGND
38
Analog ground
IOUT2
39
Current output DAC2. Full-scale with all bits of data port 2 high.
I OUT 2
40
Complementary current output DAC2. Full-scale with all bits of data port 2 low.
FSA2
41
Full-scale adjust, DAC2. Connect external RSET resistor.
GSET
42
Gain-setting mode (H = one resistor, L = two resistors)
REFIN
43
Internal reference voltage output; external reference voltage input. Bypass with 0.1μF capacitor to AGND for internal reference operation.
FSA1
44
Full-scale adjust, DAC1. Connect external RSET resistor.
I OUT 1
45
Complementary current output DAC1. Full-scale with all bits of data port 1 low.
IOUT1
46
Current output DAC1. Full-scale with all bits of data port 1 high.
+VA
47
Analog supply, +3.0V to +5.5V
NC
48
No connection
Data port DAC2, data bit 13 (MSB) to bit 0 (LSB).
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tS
DATA IN
tH
D[13:0](n)
D[13:0](n + 1)
tLPW
WRT1
WRT2
tCPW
CLK1
CLK2
tSET
IOUT1
50%
IOUT
(n)
IOUT
(n + 1)
IOUT2
tPD
TIMING REQUIREMENTS
PARAMETER
MIN
tS
Input setup time
tH
Input hold time
1.5
tLPW, tCPW
Latch/Clock pulse width
3.5
tCW
Delay rising CLK edge to rising WRT edge
tPD
Propagation delay
tSET
Settling time (0.1%)
TYP
MAX
UNIT
2
ns
ns
4
0
ns
tPW – 2
ns
1
ns
30
ns
DIGITAL INPUTS AND TIMING
The data input ports of the DAC2904 accept a standard positive coding with data bit D13 being the most
significant bit (MSB). The converter outputs support a clock rate of up to 125MSPS. The best performance will
typically be achieved with a symmetric duty cycle for write and clock; however, the duty cycle may vary as long
as the timing specifications are met. Also, the set-up and hold times may be chosen within their specified limits.
All digital inputs of the DAC2904 are CMOS compatible. The logic thresholds depend on the applied digital
supply voltages, such that they are set to approximately half the supply voltage; Vth = +VD/2 (±20% tolerance).
The DAC2904 is designed to operate with a digital supply (+VD) of +3.0V to +5.5V.
The two converter channels within the DAC2904 consist of two independent, 14-bit, parallel data ports. Each
DAC channel is controlled by its own set of write (WRT1, WRT2) and clock (CLK1, CLK2) inputs. Here, the WRT
lines control the channel input latches and the CLK lines control the DAC latches. The data is first loaded into the
input latch by a rising edge of the WRT line. This data is presented to the DAC latch on the following falling edge
of the WRT signal. On the next rising edge of the CLK line, the DAC is updated with the new data and the analog
output signal will change accordingly. The double latch architecture of the DAC2904 results in a defined
sequence for the WRT and CLK signals, expressed by parameter tCW . A correct timing is observed when the
rising edge of CLK occurs at the same time, or before, the rising edge of the WRT signal. This condition can
simply be met by connecting the WRT and CLK lines together. Note that all specifications were measured with
the WRT and CLK lines connected together.
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DAC2904
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TYPICAL CHARACTERISTICS
At TA = +25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50Ω double terminated load, and
SFDR up to Nyquist, unless otherwise noted.
TYPICAL DNL
TYPICAL INL
4
6
3
5
4
2
INL (LBS)
DNL (LBS)
3
1
0
-1
2
1
0
-1
-2
-2
-3
-3
-4
-4
0
2k
4k
6k
8k
10k
12k
14k
16k
0
2k
4k
6k
8k
Code
Figure 1.
SFDR vs fOUT AT 26MSPS
16k
SFDR vs fOUT AT 52MSPS
85
0dBFS
-6dBFS
-6dBFS
80
SFDR (dBc)
SFDR (dBc)
14k
90
85
75
70
0dBFS
80
75
70
-12dBFS
-12dBFS
65
65
60
60
0
2
4
6
8
10
12
0
5
10
fOUT (MHz)
15
20
25
fOUT (MHz)
Figure 3.
Figure 4.
SFDR vs fOUT AT 78MSPS
SFDR vs fOUT AT 100MSPS
85
85
0dBFS
80
80
-6dBFS
-6dBFS
75
75
SFDR (dBc)
SFDR (dBc)
12k
Figure 2.
90
70
-12dBFS
65
70
-12dBFS
65
0dBFS
60
60
55
55
50
0
5
10
15
20
25
30
35
0
fOUT (MHz)
5
10
15
20
25
30
35
40
45
fOUT (MHz)
Figure 5.
8
10k
Code
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50Ω double terminated load, and
SFDR up to Nyquist, unless otherwise noted.
SFDR vs fOUT AT 125MHz
SFDR vs IOUTFS AND fOUT AT 78MSPS
85
82
80
80
20mA
78
75
76
SFDR (dBc)
SFDR (dBc)
10mA
-6dBFS
-12dBFS
70
65
0dBFS
74
72
5mA
70
68
60
66
55
64
50
0dBFs
62
0
10
20
30
40
50
60
0
5
10
Figure 7.
SFDR AT 125MSPS vs TEMPERATURE
85
0.6
0.003
Gain Error (% FS)
10MHz
75
20MHz
40MHz
60
55
Offset Error
0.4
0.002
0.2
0.001
0
0
-0.2
-0.001
Gain Error
-0.4
-0.002
-0.6
-0.003
-0.8
0
-20
20
40
60
80
-0.004
-40
100
Offset Error (% FS)
SFDR (dBc)
0.004
2MHz
80
50
-40
25
GAIN AND OFFSET DRIFT
0.8
65
20
Figure 8.
90
70
15
fOUT (MHz)
fOUT (MHz)
0
-20
20
40
Temperature (°C)
60
80 85
Temperature (°C)
Figure 9.
Figure 10.
IVD vs RATIO AT +VD = +3.3V
IVA vs IOUTFS
60
25
125MSPS
55
100MSPS
20
50
IVA (mA)
IVD (mA)
45
78MSPS
15
52MSPS
10
40
35
30
25
26MSPS
20
5
15
0
0.00
10
0.05
0.10
0.15 0.20
0.25
0.30 0.35 0.40
0.45
0
Ratio (fOUT/fCLK)
5
10
15
20
25
IOUTFS (mA)
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50Ω double terminated load, and
SFDR up to Nyquist, unless otherwise noted.
SINGLE-TONE SFDR
SINGLE-TONE SFDR
10
10
fCLOCK = 52MSPS
fOUT = 5.23MHz
Amplitude = 0dBFS
0
-10
-20
Magnitude (dBm)
Magnitude (dBm)
-10
fCLOCK = 100MSPS
fOUT = 20.2MHz
Amplitude = 0dBFS
0
-30
-40
-50
-60
-20
-30
-40
-50
-60
-70
-70
-80
-80
-90
-90
0
5.2
10.4
15.6
Frequency (MHz)
20.8
26
0
10
20
Figure 13.
40
50
Figure 14.
DUAL-TONE SFDR
10
FOUR-TONE SFDR
10
fCLOCK = 78MSPS
fOUT1 = 9.44MHz
fOUT2 = 10.44MHz
Amplitude = 0dBFS
-10
-20
fCLOCK = 50MSPS
fOUT1 = 6.25MHz
fOUT2 = 6.75MHz
fOUT3 = 7.25MHz
fOUT4 = 7.75MHz
Amplitude = 0dBFS
0
-10
Magnitude (dBm)
0
Magnitude (dBm)
30
Frequency (MHz)
-30
-40
-50
-60
-20
-30
-40
-50
-60
-70
-70
-80
-80
-90
-90
0
7.8
15.6
23.4
Frequency (MHz)
31.2
39
0
5
Figure 15.
10
15
Frequency (MHz)
20
25
Figure 16.
WCDMA—ACPR
-30
fCLOCK = 61.44MSPS
PCHANNEL = -13dBm
ACPR = -69.2dB
-40
Magnitude (dBm)
-50
-60
-70
-80
-90
-100
-110
-120
-130
Center: 15.36MHz; Span: 14MHz
Figure 17.
10
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APPLICATION INFORMATION
THEORY OF OPERATION
DAC TRANSFER FUNCTION
The architecture of the DAC2904 uses the current
steering technique to enable fast switching and a high
update rate. The core element within the monolithic
DAC is an array of segmented current sources that
are designed to deliver a full-scale output current of
up to 20mA, as shown in Figure 18. An internal
decoder addresses the differential current switches
each time the DAC is updated and a corresponding
output current is formed by steering all currents to
either output summing node, IOUT or I OUT . The
complementary outputs deliver a differential output
signal, which improves the dynamic performance
through reduction of even-order harmonics,
common-mode signals (noise), and double the
peak-to-peak output signal swing by a factor of two,
compared to single-ended operation.
Each of the DACs in the DAC2904 has a set of
complementary current output, IOUT and I OUT . The
full-scale output current, IOUTFS, is the summation of
the two complementary output currents:
IOUTFS = IOUT + I OUT
(1)
The segmented architecture results in a significant
reduction of the glitch energy, improves the dynamic
performance (SFDR), and DNL. The current outputs
maintain a very high output impedance of greater
than 200kΩ.
The individual output currents depend on the DAC
code and can be expressed as:
Code
IOUT = IOUTFS ´
16,384
(2)
IOUT = IOUTFS ´ (16,383 -
Code
)
16,384
(3)
where Code is the decimal representation of the DAC
data input word. Additionally, IOUTFS is a function of
the reference current IREF, which is determined by the
reference voltage and the external setting resistor,
RSET.
V
IOUTFS = 32 ´ IREF = 32 ´ REF
RSET
(4)
The full-scale output current is determined by the
ratio of the internal reference voltage (1.25V) and an
external resistor, RSET. The resulting IREF is internally
multiplied by a factor of 32 to produce an effective
DAC output current that can range from 2mA to
20mA, depending on the value of RSET.
In most cases the complementary outputs will drive
resistive loads or a terminated transformer. A signal
voltage will develop at each output according to:
VOUT = IOUT ´ RLOAD
(5)
The DAC2904 is split into a digital and an analog
portion, each of which is powered through its own
supply pin. The digital section includes edge-triggered
input latches and the decoder logic, while the analog
section comprises the current source array with its
associated switches, and the reference circuitry.
The value of the load resistance is limited by the
output compliance specification of the DAC2904. To
maintain specified linearity performance, the voltage
for IOUT and I OUT should not exceed the maximum
allowable compliance range.
VOUT = I OUT ´ RLOAD
(6)
The two single-ended output voltages can be
combined to find the total differential output swing:
VOUTDIFF = VOUT - VOUT =
(2 ´ Code - 16,383)
´ IOUTFS ´ RLOAD
16,384
(7)
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Data Input
Port 1
D[13:0]_1
+VD
+VD
Input
Latch 1
DAC
Latch 1
+VA
DAC1
Segmented Switches
Current Sources
IOUT 1
REFIN
WRT1
CLK1
DAC2904
Reference
Control Amplifier
FSA1
FSA2
GSET
CLK2
PD
WRT2
Data Input
Port 2
D[13:0]_2
lOUT1
Input
Latch 2
DAC
Latch 2
DGND
DAC2
Segmented Switches
Current Sources
DGND
lOUT2
IOUT 2
AGND
Figure 18. Block Diagram of the DAC2904
ANALOG OUTPUTS
The DAC2904 provides two complementary current
outputs, IOUT and I OUT . The simplified circuit of the
analog output stage representing the differential
topology is shown in Figure 19. The output
impedance of IOUT and I OUT results from the parallel
combination of the differential switches, along with
the current sources and associated parasitic
capacitances.
+VA
DAC2904
IOUT
IOUT
RL
RL
Figure 19. Equivalent Analog Output
The signal voltage swing that may develop at the two
outputs, IOUT and I OUT , is limited by a negative and
positive compliance. The negative limit of –1V is
12
given by the breakdown voltage of the CMOS
process, and exceeding it will compromise the
reliability of the DAC2904, or even cause permanent
damage. With the full-scale output set to 20mA, the
positive compliance equals 1.25V, operating with an
analog supply of +VA = 5V. Note that the compliance
range decreases to about 1V for a selected output
current of IOUTFS = 2mA. Care should be taken that
the configuration of DAC2904 does not exceed the
compliance range to avoid degradation of the
distortion performance and integral linearity.
Best distortion performance is typically achieved with
the maximum full-scale output signal limited to
approximately 0.5VPP. This is the case for a 50Ω
doubly terminated load and a 20mA full-scale output
current. A variety of loads can be adapted to the
output of the DAC2904 by selecting a suitable
transformer while maintaining optimum voltage levels
at IOUT and I OUT . Furthermore, using the differential
output configuration in combination with a transformer
will be instrumental for achieving excellent distortion
performance. Common-mode errors, such as
even-order harmonics or noise, can be substantially
reduced. This is particularly the case with high output
frequencies.
For those applications requiring the optimum
distortion and noise performance, it is recommended
to select a full-scale output of 20mA. A lower
full-scale range down to 2mA may be considered for
applications that require a low power consumption,
but can tolerate a slightly reduced performance level.
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OUTPUT CONFIGURATIONS
DIFFERENTIAL WITH TRANSFORMER
The current outputs of the DAC2904 allow for a
variety of configurations, some of which are illustrated
in Table 1. As mentioned previously, utilizing the
converter differential outputs will yield the best
dynamic performance. Such a differential output
circuit may consist of an RF transformer or a
differential amplifier configuration. The transformer
configuration is ideal for most applications with ac
coupling, while op amps will be suitable for a
dc-coupled configuration.
Using an RF transformer provides a convenient way
of converting the differential output signal into a
single-ended signal while achieving excellent
dynamic performance (see Figure 20). The
appropriate transformer should be carefully selected
based on the output frequency spectrum and
impedance requirements. The differential transformer
configuration has the benefit of significantly reducing
common-mode signals, thus improving the dynamic
performance over a wide range of frequencies.
Furthermore, by selecting a suitable impedance ratio
(winding ratio), the transformer can be used to
provide optimum impedance matching while
controlling the compliance voltage for the converter
outputs. The model shown, ADTT1-1 (by
Mini-Circuits), has a 1:1 ratio and may be used to
interface the DAC2904 to a 50Ω load. This results in
a 25Ω load for each of the outputs, IOUT and I OUT .
The output signals are ac-coupled and inherently
isolated because of its magnetic coupling.
Table 1. Input Coding vs Analog Output Current
INPUT CODE (D13 - D0)
IOUT
11 1111 1111 1111
20mA
I OUT
0mA
10 0000 0000 0000
10mA
10mA
00 0000 0000 0000
0mA
20mA
The single-ended configuration may be considered
for applications requiring a unipolar output voltage.
Connecting a resistor from either one of the outputs
to ground will convert the output current into a
ground-referenced voltage signal. To improve on the
dc linearity by maintaining a virtual ground, an I-to-V
or op amp configuration may be considered.
space
space
space
space
space
As shown in Figure 20, the transformer center tap is
connected to ground. This forces the voltage swing
on IOUT and I OUT to be centered at 0V. In this case
the two resistors, RL, may be replaced with one,
RDIFF, or omitted altogether. This approach should
only be used if all components are close to each
other, and if the VSWR is not important. A complete
power transfer from the DAC output to the load can
be realized, but the output compliance range should
be observed. Alternatively, if the center tap is not
connected, the signal swing will be centered at (RL ×
IOUTFS/2). However, in this case, the two load
resistors, RL, must be used to enable the necessary
dc-current flow for both outputs.
ADTT1-1
(Mini-Circuits)
1:1
IOUT
RDIFF
100W
DAC2904
RL
50W
RS
50W
IOUT
RL
50W
Figure 20. Differential Output Configuration Using an RF Transformer
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DIFFERENTIAL CONFIGURATION USING AN
OP AMP
If the application requires a dc-coupled output, a
difference amplifier may be considered, as shown in
Figure 21. Four external resistors are needed to
configure the voltage-feedback op amp OPA690 as a
difference amplifier performing the differential to
single-ended conversion. Under the configuration
shown, the DAC2904 generates a differential output
signal of 0.5VPP at the load resistors, RL. The resistor
values shown were selected to result in a symmetric
25Ω loading for each of the current outputs since the
input impedance of the difference amplifier is in
parallel to resistors RL, and should be considered.
R2
402W
R1
200W
slew-limitations or into an overload condition; both
would cause excessive distortion. The difference
amplifier can easily be modified to add a level shift for
applications requiring the single-ended output voltage
to be unipolar; that is, swing between 0V and +2V.
DUAL TRANSIMPEDANCE OUTPUT
CONFIGURATION
The circuit example of Figure 22 shows the signal
output currents connected into the summing junctions
of the dual voltage-feedback op amp OPA2690 that is
set up as a transimpedance stage, or -to-V converter.
With this circuit, the DAC output will be kept at a
virtual ground, minimizing the effects of output
impedance variations, which results in the best dc
linearity (INL). As mentioned previously, care should
be taken not to drive the amplifier into slew-rate
limitations, and produce unwanted distortion.
IOUT
+5V
DAC2904
IOUT
OPA690
COPT
RL
26.1W
R3
200W
RL
28.7W
VOUT
50W
1/2
OPA2690
R4
402W
RF1
DAC2904
IOUT
CD1
Figure 21. Difference Amplifier Provides
Differential to Single-Ended Conversion and
DC-Coupling
The OPA690 is configured for a gain of two.
Therefore, operating the DAC2904 with a 20mA
full-scale output will produce a voltage output of ±1V.
This requires the amplifier to operate off of a dual
power supply (±5V). The tolerance of the resistors
typically sets the limit for the achievable
common-mode rejection. An improvement can be
obtained by fine-tuning resistor R4.
This configuration typically delivers a lower level of ac
performance
than
the
previously
discussed
transformer solution because the amplifier introduces
another source of distortion. Suitable amplifiers
should be selected based on the slew rate, harmonic
distortion, and output swing capabilities. High-speed
amplifiers like the OPA690 or OPA687 may be
considered. The ac performance of this circuit may be
improved by adding a small capacitor, CDIFF, between
the outputs IOUT and I OUT (see Figure 21). This will
introduce a real pole to create a low-pass filter in
order to slew-limit the DAC fast output signal steps,
which otherwise could drive the amplifier into
14
-VOUT = IOUT · RF1
-5V +5V
CF1
RF2
IOUT
CD2
CF2
1/2
OPA2690
-V OUT = IOUT · RF2
50W
-5V
Figure 22. Dual, Voltage-Feedback Amplifier
OPA2690 Forms Differential Transimpedance
Amplifier
The dc gain for this circuit is equal to feedback
resistor RF. At high frequencies, the DAC output
impedance (CD1, CD2) will produce a zero in the noise
gain for the OPA2690 that may cause peaking in the
closed-loop frequency response.
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CF is added across RF to compensate for this noise
gain peaking. To achieve a flat transimpedance
frequency response, the pole in each feedback
network should be set to:
1
GBP
=
2pRFCF 4pRFCD
(8)
with GBP = Gain Bandwidth Product of the OPA
which will give
approximately:
f-3dB =
a
corner
frequency
f–3dB
GBP
2pRFCD
of
(9)
The full-scale output voltage is simply defined by the
product of IOUTFS × RF, and has a negative unipolar
excursion. To improve on the ac performance of this
circuit, adjustment of RF and/or IOUTFS should be
considered. Further extensions of this application
example may include adding a differential filter at the
OPA2690 output followed by a transformer, in order
to convert to a single-ended signal.
INTERFACING ANALOG QUADRATURE
MODULATORS
One of the main applications for the dual-channel
DAC is baseband I- and Q-channel transmission for
digital communications. In this application, the DAC is
followed by an analog quadrature modulator,
modulating an IF carrier with the baseband data, as
shown in Figure 25. Often, the input stages of these
quadrate modulators consist of npn-type transistors
that require a dc bias (base) voltage greater than
0.8V. The wide output compliance range (–10V to
+1.25V) allows for a direct dc-coupling between the
DAC2904 and the quadrature modulator.
Figure 24 shows an example of a dc-coupled
interface with dc level-shifting, using a precision
resistor network. An ac-coupled interface (see
Figure 26) has the advantage that the common-mode
levels at the input of the modulator can be set
independently of those at the output of the DAC.
Furthermore, no voltage loss is obtained in this setup.
VDC
SINGLE-ENDED CONFIGURATION
Using a single load resistor connected to one of the
DAC outputs, a simple current-to-voltage conversion
can be accomplished. The circuit in Figure 23 shows
a 50Ω resistor connected to IOUT, providing the
termination of the further connected 50Ω cable.
Therefore, with a nominal output current of 20mA, the
DAC produces a total signal swing of 0V to 0.5V into
the 25Ω load.
R3
VOUT1
V OUT 1
R4
IOUT1
DAC2904
IOUT1
IOUT 1
IOUTFS = 20mA
IOUT 1
VOUT = 0V to +0.5V
IOUT
R5
DAC2904
IOUT
50W
50W
25W
Figure 24. DC-Coupled Interface to Quadrature
Modulator Applying Level Shifting
Figure 23. Driving a Doubly-Terminated 50Ω
Cable Directly
Different load resistor values may be selected as long
as the output compliance range is not exceeded.
Additionally, the output current, IOUTFS, and the load
resistor may be mutually adjusted to provide the
desired output signal swing and performance.
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VOUT ~ 0VP to 1.20VP
VIN ~ 0.6VP to 1.8VP
IIN
IREF
IIN
DAC2904
IOUT1
IREF
IOUT 1
Signal
Conditioning
S
RF
QIN
IOUT2
QREF
IOUT 2
Quadrature Modulator
Signal conditioning (level-shifting) may be required to ensure correct dc common-mode levels at the input of the quadrature modulator.
Figure 25. Generic Interface to a Quadrature Modulator
INTERNAL REFERENCE OPERATION
The DAC2904 has an on-chip reference circuit which
consists of a 1.25V bandgap reference and two
control amplifiers, one for each DAC. The full-scale
output current, IOUTFS, of the DAC2904 is determined
by the reference voltage, VREF, and the value of
resistor RSET. IOUTFS can be calculated by:
V
IOUTFS = 32 ´ IREF = 32 ´ REF
RSET
(10)
As shown in Figure 27, the external resistor RSET
connects to the FSA pin (Full-Scale Adjust). The
reference control amplifier operates as a V-to-I
converter producing a reference current, IREF, which
is determined by the ratio of VREF and RSET (see
Equation 10). The full-scale output current, IOUTFS,
results from multiplying IREF by a fixed factor of 32.
Using the internal reference, a 2kΩ resistor value
results in a full-scale output of approximately 20mA.
Resistors with a tolerance of 1% or better should be
considered. Selecting higher values, the output
current can be adjusted from 20mA down to 2mA.
Operating the DAC2904 at lower than 20mA output
currents may be desirable for reasons of reducing the
total power consumption, improving the distortion
performance, or observing the output compliance
voltage limitations for a given load condition.
It is recommended to bypass the REFIN pin with a
ceramic chip capacitor of 0.1μF or more. The control
amplifier is internally compensated, and its
small-signal bandwidth is approximately 0.3MHz.
16
VDC
R1
IOUT1
DAC2904
0.01mF
VOUT1
IOUT1
V OUT 1
IOUT 1
0.01mF
IOUT 1
50W
RLOAD
50W
R2
Figure 26. AC-Coupled Interface to Quadrature
Modulator Applying Level Shifting
+5V
+VA
DAC2904
IREF =
VREF
RSET
FSA
REFIN
RSET
2kW
Ref
Control
Amp
Current
Sources
0.1mF
+1.25V Ref.
Figure 27. Internal Reference Configuration
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GAIN SETTING OPTIONS
+5V
The full-scale output current on the DAC2904 can be
set two ways: either for each of the two DAC
channels independently or for both channels
simultaneously. For the independent gain set mode,
the GSET pin (pin 42) must be low (that is, connected
to AGND). In this mode, two external resistors are
required—one RSET connected to the FSA1 pin (pin
44) and the other to the FSA2 pin (pin 41). In this
configuration, the user has the flexibility to set and
adjust the full-scale output current for each DAC
independently, allowing for the compensation of
possible gain mismatches elsewhere within the
transmit signal path.
Alternatively, bringing the GSET pin high (that is,
connected to +VA), the DAC2904 will switch into the
simultaneous gain set mode. Now the full-scale
output current of both DAC channels is determined by
only one external RSET resistor connected to the
FSA1 pin. The resistor at the FSA2 pin may be
removed; however, this is not required because this
pin is not functional in this mode and the resistor has
no effect on the gain equation. The formula for
deriving the correct RSET remains unchanged; for
example, RSET = 2kΩ will result in a 20mA output for
both DACs.
EXTERNAL REFERENCE OPERATION
The internal reference can be disabled by simply
applying an external reference voltage into the REFIN
pin, which in this case functions as an input, as
shown in Figure 28. The use of an external reference
may be considered for applications that require higher
accuracy and drift performance, or to add the ability
of dynamic gain control.
While a 0.1μF capacitor is recommended to be used
with the internal reference, it is optional for the
external reference operation. The reference input,
REFIN, has a high input impedance (1MΩ) and can
easily be driven by various sources. Note that the
voltage range of the external reference should stay
within the compliance range of the reference input.
POWER-DOWN MODE
The DAC2904 features a power-down function which
can be used to reduce the total supply current to less
than 6mA over the specified supply range of 3.0V to
5.5V. Applying a logic high to the PD pin will initiate
the power-down mode, while a logic low enables
normal operation. When left unconnected, an internal
active pulldown circuit will enable the normal
operation of the converter.
+VA
DAC2904
IREF =
VREF
RSET
FSA
REFIN
External
Reference
Ref
Control
Amp
Current
Sources
RSET
+1.25V Ref.
Figure 28. External Reference Configuration
GROUNDING, DECOUPLING AND LAYOUT
INFORMATION
Proper grounding and bypassing, short lead lengths,
and the use of ground planes are particularly
important for high-frequency designs. Multilayer
printed circuit boards (PCBs) are recommended for
best performance because they offer distinct
advantages such as minimization of ground
impedance, separation of signal layers by ground
layers, etc.
The DAC2904 uses separate pins for its analog and
digital supply and ground connections. The
placement of the decoupling capacitor should be such
that the analog supply (+VA) is bypassed to the
analog ground (AGND), and the digital supply
bypassed to the digital ground (DGND). In most
cases 0.1μF ceramic chip capacitors at each supply
pin are adequate to provide a low impedance
decoupling path. Keep in mind that the effectiveness
of these capacitors largely depends on the proximity
to the individual supply and ground pins. Therefore,
they should be located as close as physically
possible to those device leads. Whenever possible,
the capacitors should be located immediately under
each pair of supply/ground pins on the reverse side of
the PCB. This layout approach will minimize the
parasitic inductance of component leads and PCB
runs.
Further supply decoupling with surface-mount
tantalum capacitors (1μF to 4.7μF) may be added as
needed in proximity of the converter.
Low noise is required for all supply and ground
connections to the DAC2904. It is recommended to
use a multilayer PCB utilizing separate power and
ground planes. Mixed signal designs require
particular attention to the routing of the different
supply currents and signal traces. Generally, analog
supply and ground planes should only extend into
analog signal areas, such as the DAC output signal
and the reference signal. Digital supply and ground
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planes must be confined to areas covering digital
circuitry, including the digital input lines connecting to
the converter, as well as the clock signal. The analog
and digital ground planes should be joined together at
one point underneath the DAC. This can be realized
with a short track of approximately 1/8 inch (3,0 mm).
The power to the DAC2904 should be provided
through the use of wide PCB runs or planes. Wide
runs will present a lower trace impedance, further
optimizing the supply decoupling. The analog and
digital supplies for the converter should only be
18
connected together at the supply connector of the
PCB. In the case of only one supply voltage being
available to power the DAC, ferrite beads along with
bypass capacitors may be used to create an LC filter.
This will generate a low-noise analog supply voltage,
which can then be connected to the +VA supply pin of
the DAC2904.
While designing the layout, it is important to keep the
analog signal traces separated from any digital line,
in order to prevent noise coupling onto the analog
signal path.
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November, 2003) to Revision C .......................................................................................... Page
•
Updated document format to current standards ................................................................................................................... 1
•
Added DAC2904IPFB orderable to Package/Ordering Information table ............................................................................. 2
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PACKAGE OPTION ADDENDUM
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21-May-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
DAC2904IPFB
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
DAC2904Y/1K
ACTIVE
TQFP
PFB
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
DAC2904Y/1KG4
ACTIVE
TQFP
PFB
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
DAC2904Y/250
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
DAC2904Y/250G4
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-May-2010
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DAC2904Y/1K
TQFP
PFB
48
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
DAC2904Y/250
TQFP
PFB
48
250
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC2904Y/1K
TQFP
PFB
48
1000
367.0
367.0
38.0
DAC2904Y/250
TQFP
PFB
48
250
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
0°– 7°
1,05
0,95
Seating Plane
0,75
0,45
0,08
1,20 MAX
4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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