AD ADSP-BF592KCPZ Blackfin embedded processor Datasheet

Blackfin
Embedded Processor
ADSP-BF592
FEATURES
PERIPHERALS
Up to 400 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Accepts a wide range of supply voltages for internal and I/O
operations, see Operating Conditions on Page 16
Off-chip voltage regulator interface
64-lead (9 mm × 9 mm) LFCSP package
Four 32-bit timers/counters, three with PWM support
2 dual-channel, full-duplex synchronous serial ports (SPORT),
supporting eight stereo I2S channels
2 serial peripheral interface (SPI) compatible ports
1 UART with IrDA support
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
2-wire interface (TWI) controller
9 peripheral DMAs
2 memory-to-memory DMA channels
Event handler with 28 interrupt inputs
32 general-purpose I/Os (GPIOs), with programmable
hysteresis
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
MEMORY
68K bytes of core-accessible memory
(See Table 1 on Page 3 for L1 and L3 memory size details)
64K byte L1 instruction ROM
Flexible booting options from internal L1 ROM and SPI memory or from host devices including SPI, PPI, and UART
Memory management unit providing memory protection
WATCHDOG TIMER
SPORT1
VOLTAGE REGULATOR INTERFACE
PORT F
JTAG TEST AND EMULATION
SPI0
PERIPHERAL
TIMER2–0
ACCESS BUS
B
L1 INSTRUCTION
ROM
L1 INSTRUCTION
SRAM
UART
INTERRUPT
CONTROLLER
L1 DATA
SRAM
GPIO
PPI
SPORT0
DMA
CONTROLLER
DCB
PORT G
DMA
ACCESS
BUS
SPI1
TWI
DEB
BOOT
ROM
Figure 1. Processor Block Diagram
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Rev. B
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ADSP-BF592
TABLE OF CONTENTS
Features ................................................................. 1
Related Signal Chains ........................................... 13
Memory ................................................................ 1
Signal Descriptions ................................................. 14
Peripherals ............................................................. 1
Specifications ........................................................ 16
General Description ................................................. 3
Operating Conditions ........................................... 16
Portable Low Power Architecture ............................. 3
Electrical Characteristics ....................................... 18
System Integration ................................................ 3
Absolute Maximum Ratings ................................... 20
Blackfin Processor Core .......................................... 3
ESD Sensitivity ................................................... 20
Memory Architecture ............................................ 5
Package Information ............................................ 21
Event Handling .................................................... 5
Timing Specifications ........................................... 22
DMA Controllers .................................................. 6
Output Drive Currents ......................................... 36
Processor Peripherals ............................................. 6
Test Conditions .................................................. 37
Dynamic Power Management .................................. 8
Environmental Conditions .................................... 40
Voltage Regulation ................................................ 9
64-Lead LFCSP Lead Assignment ............................... 41
Clock Signals ....................................................... 9
Outline Dimensions ................................................ 43
Booting Modes ................................................... 11
Automotive Products .............................................. 44
Instruction Set Description ................................... 12
Ordering Guide ..................................................... 44
Development Tools ............................................. 12
Additional Information ........................................ 13
REVISION HISTORY
7/13—Rev. A to Rev. B
Corrected Processor Block Diagram ............................. 1
Updated Development Tools .................................... 12
Updated text in Signal Descriptions ............................ 14
Corrected VDDINT rating in Table 14,
Absolute Maximum Ratings ..................................... 20
Rev. B
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ADSP-BF592
GENERAL DESCRIPTION
The ADSP-BF592 processor is a member of the Blackfin® family
of products, incorporating the Analog Devices/Intel Micro
Signal Architecture (MSA). Blackfin processors combine a dualMAC state-of-the-art signal processing engine, the advantages
of a clean, orthogonal RISC-like microprocessor instruction set,
and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.
The ADSP-BF592 processor is completely code compatible with
other Blackfin processors. The ADSP-BF592 processor offers
performance up to 400 MHz and reduced static power consumption. The processor features are shown in Table 1.
Table 1. Processor Features
Memory (bytes)
Feature
Timer/Counters with PWM
SPORTs
SPIs
UART
Parallel Peripheral Interface
TWI
GPIOs
L1 Instruction SRAM
L1 Instruction ROM
L1 Data SRAM
L1 Scratchpad SRAM
L3 Boot ROM
Maximum Instruction Rate1
Maximum System Clock Speed
Package Options
1
ADSP-BF592
3
2
2
1
1
1
32
32K
64K
32K
4K
4K
400 MHz
100 MHz
64-Lead LFCSP
The ADSP-BF592 processor is a highly integrated system-on-achip solution for the next generation of digital communication
and consumer multimedia applications. By combining industry
standard interfaces with a high performance signal processing
core, cost-effective applications can be developed quickly, without the need for costly external components. The system
peripherals include a watchdog timer; three 32-bit timers/counters with PWM support; two dual-channel, full-duplex
synchronous serial ports (SPORTs); two serial peripheral interface (SPI) compatible ports; one UART® with IrDA support; a
parallel peripheral interface (PPI); and a 2-wire interface (TWI)
controller.
BLACKFIN PROCESSOR CORE
As shown in Figure 2, the Blackfin processor core contains two
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
four video ALUs, and a 40-bit shifter. The computation units
process 8-, 16-, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.
Maximum instruction rate is not available with every possible SCLK selection.
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like programmability, multimedia support, and leading-edge signal
processing in one integrated package.
PORTABLE LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. They are produced with a low power and low
voltage design methodology and feature on-chip dynamic
power management, which provides the ability to vary both the
voltage and frequency of operation to significantly lower overall
power consumption. This capability can result in a substantial
reduction in power consumption, compared with just varying
the frequency of operation. This allows longer battery life for
portable appliances.
Rev. B
SYSTEM INTEGRATION
|
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions includes byte alignment and packing operations,
16-bit and 8-bit adds with clipping, 8-bit average operations,
and 8-bit subtract/absolute value/accumulate (SAA) operations.
The compare/select and vector search instructions are also
provided.
For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction) and
subroutine calls. Hardware is provided to support zero over
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ADSP-BF592
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering) and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. Data memory holds data, and
a dedicated scratchpad data memory stores stack and local variable information.
The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
Multiple L1 memory blocks are provided. The memory
management unit (MMU) provides memory protection for
individual tasks that may be operating on the core and can
protect system registers from unintended access.
ADDRESS ARITHMETIC UNIT
L3
B3
M3
I2
L2
B2
M2
I1
L1
B1
M1
I0
L0
B0
M0
SP
FP
P5
DAG1
P4
P3
DAG0
P2
32
32
P1
P0
TO MEMORY
DA1
DA0
I3
32
PREG
32
RAB
SD
LD1
LD0
32
32
32
ASTAT
32
32
SEQUENCER
R7.H
R6.H
R7.L
R6.L
R5.H
R5.L
R4.H
R4.L
R3.H
R3.L
R2.H
R2.L
R1.H
R1.L
R0.H
R0.L
16
ALIGN
16
8
8
8
8
DECODE
BARREL
SHIFTER
40
40
A0
32
40
40
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
Rev. B
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A1
LOOP BUFFER
CONTROL
UNIT
ADSP-BF592
MEMORY ARCHITECTURE
Custom ROM (Optional)
The Blackfin processor views memory as a single unified
4G byte address space, using 32-bit addresses. All resources,
including internal memory and I/O control registers, occupy
separate sections of this common address space. See Figure 3.
The on-chip L1 Instruction ROM on the ADSP-BF592 may be
customized to contain user code with the following features:
• 64K bytes of L1 Instruction ROM available for custom code
The core-accessible L1 memory system is high performance
internal memory that operates at the core clock frequency. The
external bus interface unit (EBIU) provides access to the boot
ROM.
The memory DMA controller provides high bandwidth datamovement capability. It can perform block transfers of code or
data between the L1 Instruction SRAM and L1 Data SRAM
memory spaces.
0xFFFF FFFF
CORE MEMORY MAPPED REGISTERS (2M BYTES)
0xFFE0 0000
SYSTEM MEMORY MAPPED REGISTERS (2M BYTES)
0xFFC0 0000
RESERVED
0xFFB0 1000
L1 SCRATCHPAD RAM (4K BYTES)
0xFFB0 0000
RESERVED
0xFFA2 0000
L1 INSTRUCTION ROM (64K BYTES)
0xFFA1 0000
RESERVED
• Ability to restrict access to all or specific segments of the
on-chip ROM
Customers wishing to customize the on-chip ROM for their
own application needs should contact ADI sales for more information on terms and conditions and details on the technical
implementation.
I/O Memory Space
The processor does not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped into
memory-mapped registers (MMRs) at addresses near the top of
the 4G byte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core functions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The MMRs are accessible only in supervisor mode and appear
as reserved space to on-chip peripherals.
Booting from ROM
0xFFA0 8000
L1 INSTRUCTION BANK B SRAM (16K BYTES)
The processor contains a small on-chip boot kernel, which configures the appropriate peripheral for booting. If the processor is
configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more
information, see Booting Modes on Page 11.
0xFFA0 4000
L1 INSTRUCTION BANK A SRAM (16K BYTES)
0xFFA0 0000
RESERVED
0xFF80 8000
DATA SRAM (32K BYTES)
0xFF80 0000
RESERVED
0xEF00 1000
BOOT ROM (4K BYTES)
EVENT HANDLING
0xEF00 0000
RESERVED
0x0000 0000
Figure 3. Internal/External Memory Map
Internal (Core-Accessible) Memory
The processor has three blocks of core-accessible memory, providing high bandwidth access to the core.
The first block is the L1 instruction memory, consisting of
32K bytes SRAM. This memory is accessed at full processor
speed.
The second core-accessible memory block is the L1 data memory, consisting of 32K bytes. This memory block is accessed at
full processor speed.
The third memory block is a 4K byte L1 scratchpad SRAM,
which runs at the same speed as the other L1 memories.
L1 Utility ROM
The event controller on the processor handles all asynchronous
and synchronous events to the processor. The processor
provides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be
active simultaneously. Prioritization ensures that servicing of a
higher-priority event takes precedence over servicing of a lowerpriority event. The controller provides support for five different
types of events:
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• RESET – This event resets the processor.
• Nonmaskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shutdown of the system.
The L1 instruction ROM contains utility ROM code. This
includes the TMK (VDK core), C run-time libraries, and DSP
libraries. See the VisualDSP++ documentation for more
information.
Rev. B
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ADSP-BF592
• Exceptions – Events that occur synchronously to program
flow (in other words, the exception is taken before the
instruction is allowed to complete). Conditions such as
data alignment violations and undefined instructions cause
exceptions.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input signals, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The processor event controller consists of two stages: the core
event controller (CEC) and the system interrupt controller
(SIC). The core event controller works with the system interrupt
controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC and are
then routed directly into the general-purpose interrupts of the
CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority
interrupts (IVG15–14) are recommended to be reserved for
software interrupt handlers, leaving seven prioritized interrupt
inputs to support the peripherals of the processor. The inputs to
the CEC, their names in the event vector table (EVT), and their
priorities are described in the ADSP-BF59x Blackfin Processor
Hardware Reference, “System Interrupts” chapter.
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the processor provides a default mapping, the user
can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment
registers (SIC_IARx). The inputs into the SIC and the default
mappings into the CEC are described in the ADSP-BF59x Blackfin Processor Hardware Reference, “System Interrupts” chapter.
The SIC allows further control of event processing by providing
three pairs of 32-bit interrupt control and status registers. Each
register contains a bit, corresponding to each peripheral interrupt event. For more information, see the ADSP-BF59x Blackfin
Processor Hardware Reference, “System Interrupts” chapter.
DMA CONTROLLERS
The processor has multiple, independent DMA channels that
support automated data transfers with minimal overhead for
the processor core. DMA transfers can occur between the processor’s internal memories and any of its DMA-capable
peripherals. DMA-capable peripherals include the SPORTs, SPI
ports, UART, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel.
Rev. B
The processor DMA controller supports both one-dimensional
(1-D) and two-dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets
of parameters called descriptor blocks.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be deinterleaved on the fly.
Examples of DMA types supported by the processor DMA controller include:
• A single, linear buffer that stops upon completion
• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels, which are provided for transfers
between the various memories of the processor system with
minimal processor intervention. Memory DMA transfers can be
controlled by a very flexible descriptor-based methodology or
by a standard register-based autobuffer mechanism.
PROCESSOR PERIPHERALS
The ADSP-BF592 processor contains a rich set of peripherals
connected to the core via several high bandwidth buses, providing flexibility in system configuration, as well as excellent
overall system performance (see Figure 1). The processor also
contains dedicated communication modules and high speed
serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or external
sources, and power management control functions to tailor the
performance and power characteristics of the processor and system to many application scenarios.
The SPORTs, SPIs, UART, and PPI peripherals are supported
by a flexible DMA structure. There are also separate memory
DMA channels dedicated to data transfers between the processor’s various memory spaces, including boot ROM. Multiple
on-chip buses running at up to 100 MHz provide enough bandwidth to keep the processor core running along with activity on
all of the on-chip and external peripherals.
The ADSP-BF592 processor includes an interface to an off-chip
voltage regulator in support of the processor’s dynamic power
management capability.
Watchdog Timer
The processor includes a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can
improve system availability by forcing the processor to a known
state through generation of a hardware reset, nonmaskable
interrupt (NMI), or general-purpose interrupt, if the timer
expires before being reset by software. The programmer
| Page 6 of 44 | July 2013
ADSP-BF592
initializes the count value of the timer, enables the appropriate
interrupt, then enables the timer. Thereafter, the software must
reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an
unknown state where software, which would normally reset the
timer, has stopped running due to an external noise condition
or software error.
Serial Peripheral Interface (SPI) Ports
The processor has two SPI-compatible ports that enable the
processor to communicate with multiple SPI-compatible
devices.
The timer is clocked by the system clock (SCLK) at a maximum
frequency of fSCLK.
The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSI, and Master InputSlave Output, MISO) and a clock pin (serial clock, SCK). An SPI
chip select input pin (SPIx_SS) lets other SPI devices select the
processor, and many SPI chip select output pins (SPIx_SEL7–1)
let the processor select other SPI devices. The SPI select pins are
reconfigured general-purpose I/O pins. Using these pins, the
SPI port provides a full-duplex, synchronous serial interface,
which supports both master/slave modes and multimaster
environments.
Timers
UART Port
There are four general-purpose programmable timer units in
the processor. Three timers have an external pin that can be
configured either as a pulse width modulator (PWM) or timer
output, as an input to clock the timer, or as a mechanism for
measuring pulse widths and periods of external events. These
timers can be synchronized to an external clock input to the several other associated PF pins, to an external clock input to the
PPI_CLK input pin, or to the internal SCLK.
The ADSP-BF592 processor provides a full-duplex universal
asynchronous receiver/transmitter (UART) port, which is fully
compatible with PC-standard UARTs. The UART port provides
a simplified UART interface to other peripherals or hosts,
supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART port includes support for five to
eight data bits, one or two stop bits, and none, even, or odd parity. The UART port supports two modes of operation:
The timer units can be used in conjunction with the UART to
measure the width of the pulses in the data stream to provide a
software auto-baud detect function for the respective serial
channels.
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O mapped UART registers.
The data is double-buffered on both transmit and receive.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the processor peripherals. After a reset,
software can determine whether the watchdog was the source of
the hardware reset by interrogating a status bit in the watchdog
timer control register.
The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the three general-purpose programmable timers,
a fourth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
Serial Ports
The ADSP-BF592 processor incorporates two dual-channel
synchronous serial ports (SPORT0 and SPORT1) for serial and
multiprocessor communications. The SPORTs support the following features:
Serial port data can be automatically transferred to and from
on-chip memory/external memory via dedicated DMA channels. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. In this configuration, one SPORT provides two transmit signals while the other
SPORT provides the two receive signals. The frame sync and
clock are shared.
Serial ports operate in five modes:
• Standard DSP serial mode
• Multichannel (TDM) mode
• DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
Parallel Peripheral Interface (PPI)
The processor provides a parallel peripheral interface (PPI) that
can connect directly to parallel analog-to-digital and digital-toanalog converters, video encoders and decoders, and other general-purpose peripherals. The PPI consists of a dedicated input
clock pin, up to three frame synchronization pins, and up to 16
data pins. The input clock supports parallel data rates up to half
the system clock rate, and the synchronization signals can be
configured as either inputs or outputs.
The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
half-duplex, bidirectional data transfer with up to 16 bits of
data. Up to three frame synchronization signals are also provided. In ITU-R 656 mode, the PPI provides half-duplex
bidirectional transfer of 8- or 10-bit video data. Additionally,
on-chip decode of embedded start-of-line (SOL) and start-offield (SOF) preamble packets is supported.
• I2S mode
• Packed I2S mode
• Left-justified mode
Rev. B
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ADSP-BF592
General-Purpose Mode Descriptions
DYNAMIC POWER MANAGEMENT
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications.
Three distinct submodes are supported:
The processor provides five operating modes, each with a different performance/power profile. In addition, dynamic power
management provides the control functions to dynamically alter
the processor core supply voltage, further reducing power dissipation. When configured for a 0 V core supply voltage, the
processor enters the hibernate state. Control of clocking to each
of the processor peripherals also reduces power consumption.
See Table 2 for a summary of the power settings for each mode.
• Input mode – Frame syncs and data are inputs into the PPI.
Input mode is intended for ADC applications, as well as
video communication with hardware signaling.
• Frame capture mode – Frame syncs are outputs from the
PPI, but data are inputs. This mode allows the video
source(s) to act as a slave (for frame capture for example).
• Output mode – Frame syncs and data are outputs from the
PPI. Output mode is used for transmitting video or other
data with up to three output frame syncs.
ITU-R 656 Mode Descriptions
The ITU-R 656 modes of the PPI are intended to suit a wide
variety of video capture, processing, and transmission applications. Three distinct submodes are supported:
• Active video only mode – Active video only mode is used
when only the active video portion of a field is of interest
and not any of the blanking intervals.
• Vertical blanking only mode – In this mode, the PPI only
transfers vertical blanking interval (VBI) data.
• Entire field mode – In this mode, the entire incoming bit
stream is read in through the PPI.
TWI Controller Interface
The processor includes a 2-wire interface (TWI) module for
providing a simple exchange method of control data between
multiple devices. The TWI is functionally compatible with the
widely used I2C® bus standard. The TWI module offers the
capabilities of simultaneous master and slave operation and
support for both 7-bit addressing and multimedia data arbitration. The TWI interface utilizes two pins for transferring clock
(SCL) and data (SDA) and supports the protocol at speeds up to
400K bits/sec.
The TWI module is compatible with serial camera control bus
(SCCB) functionality for easier control of various CMOS camera sensor devices.
Ports
The processor groups the many peripheral signals to two
ports—Port F and Port G. Most of the associated pins are shared
by multiple signals. The ports function as multiplexer controls.
General-Purpose I/O (GPIO)
The processor has 32 bidirectional, general-purpose I/O (GPIO)
pins allocated across two separate GPIO modules—PORTFIO
and PORTGIO, associated with Port F and Port G respectively.
Each GPIO-capable pin shares functionality with other processor peripherals via a multiplexing scheme; however, the GPIO
functionality is the default state of the device upon power-up.
Neither GPIO output nor input drivers are active by default.
Each general-purpose port pin can be individually controlled by
manipulation of the port control, status, and interrupt registers.
Rev. B
Table 2. Power Settings
PLL
Mode/State PLL
Bypassed
Full On
Enabled No
Active
Enabled/ Yes
Disabled
Sleep
Enabled —
Deep Sleep Disabled —
Hibernate
Disabled —
Core
Clock
(CCLK)
Enabled
Enabled
System
Clock
(SCLK)
Enabled
Enabled
Core
Power
On
On
Disabled Enabled On
Disabled Disabled On
Disabled Disabled Off
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Dynamic Power
Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. DMA
access is available to appropriately configured L1 memories.
For more information about PLL controls, see the “Dynamic
Power Management” chapter in the ADSP-BF59x Blackfin Processor Hardware Reference.
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typically, an external event wakes up the processor.
System DMA access to L1 memory is not supported in
sleep mode.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals
may still be running but cannot access internal resources or
external memory. This powered-down mode can only be exited
by assertion of the reset interrupt (RESET) or by an asynchronous interrupt generated by a GPIO pin.
| Page 8 of 44 | July 2013
ADSP-BF592
Note that when a GPIO pin is used to trigger wake from deep
sleep, the programmed wake level must linger for at least 10ns
to guarantee detection.
Power Savings Factor
f CCLKRED  V DDINTRED  2  T RED 
= -------------------  ------------------------  -----------f CCLKNOM  V DDINTNOM  T NOM 
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
clocks to the processor core (CCLK) and to all of the peripherals
(SCLK), as well as signaling an external voltage regulator that
VDDINT can be shut off. Any critical information stored internally (for example, memory contents, register contents, and
other information) must be written to a nonvolatile storage
device prior to removing power if the processor state is to be
preserved. Writing b#0 to the HIBERNATE bit causes
EXT_WAKE to transition low, which can be used to signal an
external voltage regulator to shut down.
Since VDDEXT can still be supplied in this mode, all of the external pins three-state, unless otherwise specified. This allows
other devices that may be connected to the processor to still
have power applied without drawing unwanted current.
As long as VDDEXT is applied, the VR_CTL register maintains its
state during hibernation. All other internal registers and memories, however, lose their content in the hibernate state.
Power Savings
As shown in Table 3, the processor supports two different
power domains, which maximizes flexibility while maintaining
compliance with industry standards and conventions. By isolating the internal logic of the processor into its own power
domain, separate from other I/O, the processor can take advantage of dynamic power management without affecting the other
I/O devices. There are no sequencing requirements for the
various power domains, but all domains must be powered
according to the appropriate Specifications table for processor
operating conditions, even if the feature/peripheral is not used.
Table 3. Power Domains
Power Domain
All internal logic and memories
All other I/O
VDD Range
VDDINT
VDDEXT
% Power Savings =  1 – Power Savings Factor   100%
where:
fCCLKNOM is the nominal core clock frequency
fCCLKRED is the reduced core clock frequency
VDDINTNOM is the nominal internal supply voltage
VDDINTRED is the reduced internal supply voltage
TNOM is the duration running at fCCLKNOM
TRED is the duration running at fCCLKRED
VOLTAGE REGULATION
The ADSP-BF592 processor requires an external voltage regulator to power the VDDINT domain. To reduce standby power
consumption, the external voltage regulator can be signaled
through EXT_WAKE to remove power from the processor core.
This signal is high-true for power-up and may be connected
directly to the low-true shut-down input of many common
regulators.
While in the hibernate state, the external supply, VDDEXT, can
still be applied, eliminating the need for external buffers. The
external voltage regulator can be activated from this powerdown state by asserting the RESET pin, which then initiates a
boot sequence. EXT_WAKE indicates a wakeup to the external
voltage regulator.
The power good (PG) input signal allows the processor to start
only after the internal voltage has reached a chosen level. In this
way, the startup time of the external regulator is detected after
hibernation. For a complete description of the power-good
functionality, refer to the ADSP-BF59x Blackfin Processor Hardware Reference.
CLOCK SIGNALS
The dynamic power management feature of the processor
allows both the processor’s input voltage (VDDINT) and clock frequency (fCCLK) to be dynamically controlled.
The processor can be clocked by an external crystal, a sine wave
input, or a buffered, shaped clock derived from an external
clock oscillator.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation, while reducing the
voltage by 25% reduces dynamic power dissipation by more
than 40%. Further, these power savings are additive, in that if
the clock frequency and supply voltage are both reduced, the
power savings can be dramatic, as shown in the following
equations.
If an external clock is used, it should be a TTL-compatible signal
and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Rev. B
|
Alternatively, because the processor includes an on-chip oscillator circuit, an external crystal may be used. For fundamental
frequency operation, use the circuit shown in Figure 4. A
parallel-resonant, fundamental frequency, microprocessorgrade crystal is connected across the CLKIN and XTAL pins.
The on-chip resistance between CLKIN and the XTAL pin is in
the 500 kΩ range. Further parallel resistors are typically not
Page 9 of 44 | July 2013
ADSP-BF592
recommended. The two capacitors and the series resistor shown
in Figure 4 fine tune phase and amplitude of the sine frequency.
The capacitor and resistor values shown in Figure 4 are typical
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations on multiple
devices over temperature range.
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
CLKIN
PLL
5u to 64u
“COARSE” ADJUSTMENT
ON-THE-FLY
÷ 1, 2, 4, 8
CCLK
÷ 1 to 15
SCLK
VCO
SCLK d CCLK
BLACKFIN
Figure 5. Frequency Modification Methods
CLKOUT (SCLK)
CLKBUF
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 4 illustrates typical system clock ratios.
TO PLL CIRCUITRY
EN
EN
SELECT
560 ⍀
EXTCLK
XTAL
CLKIN
330 ⍀*
18 pF *
Table 4. Example System Clock Ratios
FOR OVERTONE
OPERATION ONLY:
18 pF *
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR
FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE
OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED
RESISTOR VALUE SHOULD BE REDUCED TO 0 ⍀.
Figure 4. External Crystal Connections
A third-overtone crystal can be used for frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in Figure 4. A design procedure for third-overtone operation is discussed in detail in (EE-168) Using Third Overtone
Crystals with the ADSP-218x DSP on the Analog Devices website (www.analog.com)—use site search on “EE-168.”
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 5, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a programmable 5× to 64× multiplication
factor (bounded by specified minimum and maximum VCO
frequencies). The default multiplier is 6×, but it can be modified
by a software instruction sequence.
On-the-fly frequency changes can be effected by simply writing
to the PLL_DIV register. The maximum allowed CCLK and
SCLK rates depend on the applied voltages VDDINT and VDDEXT;
the VCO is always permitted to run up to the frequency specified by the part’s instruction rate. The EXTCLK pin can be
configured to output either the SCLK frequency or the input
buffered CLKIN frequency, called CLKBUF. When configured
to output SCLK (CLKOUT), the EXTCLK pin acts as a reference signal in many timing specifications. While three-stated by
default, it can be enabled using the VRCTL register.
Rev. B
Signal Name
SSEL3–0
0010
0110
1010
Divider Ratio
VCO/SCLK
2:1
6:1
10:1
Example Frequency Ratios
(MHz)
VCO
SCLK
100
50
300
50
400
40
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of fSCLK. The SSEL value can be
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 5. This programmable core clock capability is useful for
fast core frequency modifications.
Table 5. Core Clock Ratios
Signal Name
CSEL1–0
00
01
10
11
Example Frequency Ratios
(MHz)
Divider Ratio
VCO/CCLK
VCO
CCLK
1:1
300
300
2:1
300
150
4:1
400
100
8:1
200
25
The maximum CCLK frequency both depends on the part’s
instruction rate (see Ordering Guide) and depends on the
applied VDDINT voltage. See Table 8 for details. The maximal system clock rate (SCLK) depends on the chip package and the
applied VDDINT and VDDEXT voltages (see Table 10).
| Page 10 of 44 |
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ADSP-BF592
BOOTING MODES
• SPI0 master boot from flash (BMODE = 0x4) — In this
mode SPI0 is configured to operate in master mode and to
connect to 8-, 16-, 24-, or 32-bit addressable devices. The
processor uses the PF8/SPI0_SSEL2 to select a single SPI
EEPROM/flash device, submits a read command and successive address bytes (0×00) until a valid 8-, 16-, 24-, or 32bit addressable device is detected, and begins clocking data
into the processor. Pull-up resistors are required on the
SSEL and MISO pins. By default, a value of 0×85 is written
to the SPI_BAUD register.
The processor has several mechanisms (listed in Table 6) for
automatically loading internal and external memory after a
reset. The boot mode is defined by the BMODE input pins dedicated to this purpose. There are two categories of boot modes.
In master boot modes, the processor actively loads data from
parallel or serial memories. In slave boot modes, the processor
receives data from external host devices.
Table 6. Booting Modes
BMODE2–0
000
001
010
011
100
101
110
111
• Boot from PPI host device (BMODE = 0x5) — The processor operates in PPI slave mode and is configured to receive
the bytes of the LDR file from a PPI host (master) agent.
Description
Idle/No Boot
Reserved
SPI1 master boot from Flash, using SPI1_SSEL5 on PG11
SPI1 slave boot from external master
SPI0 master boot from Flash, using SPI0_SSEL2 on PF8
Boot from PPI port
Boot from UART host device
Execute from Internal L1 ROM
• Boot from UART host device (BMODE = 0x6) — In this
mode UART0 is used as the booting source. Using an autobaud handshake sequence, a boot-stream formatted
program is downloaded by the host. The host selects a bit
rate within the UART clocking capabilities. When performing the autobaud, the UART expects a “@” (0×40)
character (eight bits data, one start bit, one stop bit, no parity bit) on the RXD pin to determine the bit rate. The
UART then replies with an acknowledgment which is composed of 4 bytes (0xBF—the value of UART_DLL) and
(0×00—the value of UART_DLH). The host can then
download the boot stream. To hold off the host the processor signals the host with the boot host wait (HWAIT)
signal. Therefore, the host must monitor the HWAIT, (on
PG4), before every transmitted byte.
The boot modes listed in Table 6 provide a number of mechanisms for automatically loading the processor’s internal and
external memories after a reset. By default, all boot modes use
the slowest meaningful configuration settings. Default settings
can be altered via the initialization code feature at boot time.
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, implement the modes shown in Table 6.
• IDLE State/No Boot (BMODE - 0x0) — In this mode, the
boot kernel transitions the processor into Idle state. The
processor can then be controlled through JTAG for recovery, debug, or other functions.
• SPI1 master boot from flash (BMODE = 0x2) — In this
mode, SPI1 is configured to operate in master mode and to
connect to 8-, 16-, 24-, or 32-bit addressable devices. The
processor uses the PG11/SPI1_SSEL5 to select a single SPI
EEPROM/flash device, submits a read command and successive address bytes (0×00) until a valid 8-, 16-, 24-, or 32bit addressable device is detected, and begins clocking data
into the processor. Pull-up resistors are required on the
SSEL and MISO pins. By default, a value of 0×85 is written
to the SPI_BAUD register.
• SPI1 slave boot from external master (BMODE = 0x3) — In
this mode, SPI1 is configured to operate in slave mode and
to receive the bytes of the .LDR file from a SPI host (master) agent. To hold off the host device from transmitting
while the boot ROM is busy, the Blackfin processor asserts
a GPIO pin, called host wait (HWAIT), to signal to the host
device not to send any more bytes until the pin is deasserted. The host must interrogate the HWAIT signal,
available on PG4, before transmitting every data unit to the
processor. A pull-up resistor is required on the SPI1_SS
input. A pull-down on the serial clock may improve signal
quality and booting robustness.
Rev. B
• Execute from internal L1 ROM (BMODE = 0x7) — In this
mode the processor begins execution from the on-chip 64k
byte L1 instruction ROM starting at address 0xFFA1 0000.
For each of the boot modes (except Execute from internal L1
ROM), a 16 byte header is first brought in from an external
device. The header specifies the number of bytes to be transferred and the memory destination address. Multiple memory
blocks may be loaded by any boot sequence. Once all blocks are
loaded, program execution commences from the start of L1
instruction SRAM.
The boot kernel differentiates between a regular hardware reset
and a wakeup-from-hibernate event to speed up booting in the
latter case. Bits 7–4 in the system reset configuration (SYSCR)
register can be used to bypass the boot kernel or simulate a
wakeup-from-hibernate boot in case of a software reset.
The boot process can be further customized by “initialization
code.” This is a piece of code that is loaded and executed prior to
the regular application boot. Typically, this is used to speed up
booting by managing the PLL, clock frequencies, or serial bit
rates.
The boot ROM also features C-callable functions that can be
called by the user application at run time. This enables second
stage boot or boot management schemes to be implemented
with ease.
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ADSP-BF592
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core
processor resources.
The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified programming model.
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded
in 16 bits.
The other Analog Devices IDE, VisualDSP++, supports processor families introduced prior to the release of CrossCore
Embedded Studio. This IDE includes the Analog Devices VDK
real time operating system and an open source TCP/IP stack.
For more information visit www.analog.com/visualdsp. Note
that VisualDSP++ will not support future Analog Devices
processors.
EZ-KIT Lite Evaluation Board
For processor evaluation, Analog Devices provides wide range
of EZ-KIT Lite® evaluation boards. Including the processor and
key peripherals, the evaluation board also supports on-chip
emulation capabilities and other evaluation and development
features. Also available are various EZ-Extenders®, which are
daughter cards delivering additional specialized functionality,
including audio and video processing. For more information
visit www.analog.com and search on “ezkit” or “ezextender”.
EZ-KIT Lite Evaluation Kits
For a cost-effective way to learn more about developing with
Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Lite evaluation board, directions for downloading an evaluation
version of the available IDE(s), a USB cable, and a power supply.
The USB controller on the EZ-KIT Lite board connects to the
USB port of the user’s PC, enabling the chosen IDE evaluation
suite to emulate the on-board processor in-circuit. This permits
the customer to download, execute, and debug programs for the
EZ-KIT Lite system. It also supports in-circuit programming of
the on-board Flash device to store user-specific boot code,
enabling standalone operation. With the full version of CrossCore Embedded Studio or VisualDSP++ installed (sold
separately), engineers can develop software for supported EZKITs or any custom system utilizing supported Analog Devices
processors.
Software Add-Ins for CrossCore Embedded Studio
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including integrated
development environments (which include CrossCore® Embedded Studio and/or VisualDSP++®), evaluation products,
emulators, and a wide variety of software add-ins.
Integrated Development Environments (IDEs)
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers two IDEs.
The newest IDE, CrossCore Embedded Studio, is based on the
EclipseTM framework. Supporting most Analog Devices processor families, it is the IDE of choice for future processors,
including multicore devices. CrossCore Embedded Studio
seamlessly integrates available software add-ins to support real
time operating systems, file systems, TCP/IP stacks, USB stacks,
algorithmic software modules, and evaluation hardware board
support packages. For more information, visit
www.analog.com/cces.
Rev. B
Analog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend its capabilities
and reduce development time. Add-ins include board support
packages for evaluation hardware, various middleware packages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
add-ins are viewable through the CrossCore Embedded Studio
IDE once the add-in is installed.
Board Support Packages for Evaluation Hardware
Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add-ins called
Board Support Packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
located on the web page for the associated EZ-KIT or EZExtender product. The link is found in the Product Download
area of the product web page.
| Page 12 of 44 |
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ADSP-BF592
Middleware Packages
Analog Devices separately offers middleware add-ins such as
real time operating systems, file systems, USB stacks, and
TCP/IP stacks. For more information see the following web
pages:
• www.analog.com/ucos3
• www.analog.com/ucfs
• www.analog.com/ucusbd
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the “signal chain” entry in the
Glossary of EE Terms on the Analog Devices website.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
The Circuits from the LabTM site (www.analog.com\circuits)
provides:
• www.analog.com/lwip
Algorithmic Modules
To speed development, Analog Devices offers add-ins that perform popular audio and video processing algorithms. These are
available for use with both CrossCore Embedded Studio and
VisualDSP++. For more information visit www.analog.com and
search on “Blackfin software modules” or “SHARC software
modules”.
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques
Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The emulator accesses the processor’s internal features via the
processor’s TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers. The
processor must be halted to send data and commands, but once
an operation is completed by the emulator, the DSP system is set
to run at full speed with no impact on system timing. The emulators require the target board to include a header that supports
connection of the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the Engineer-to-Engineer
Note “Analog Devices JTAG Emulation Technical Reference”
(EE-68) on the Analog Devices website (www.analog.com)—use
site search on “EE-68.” This document is updated regularly to
keep pace with improvements to emulator support.
ADDITIONAL INFORMATION
The following publications that describe the ADSP-BF592 processor (and related processors) can be ordered from any Analog
Devices sales office or accessed electronically on our website:
• Getting Started With Blackfin Processors
• ADSP-BF59x Blackfin Processor Hardware Reference
• Blackfin Processor Programming Reference
• ADSP-BF592 Blackfin Processor Anomaly List
RELATED SIGNAL CHAINS
A signal chain is a series of signal conditioning electronic components that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
Rev. B
| Page 13 of 44 |
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ADSP-BF592
SIGNAL DESCRIPTIONS
Signal definitions for the ADSP-BF592 processor are listed in
Table 7. In order to maintain maximum function and reduce
package size and pin count, some pins have dual, multiplexed
functions. In cases where pin function is reconfigurable, the
default state is shown in plain text, while the alternate function
is shown in italics.
create a crystal oscillator circuit. During hibernate, all signals
are three-stated with the following exceptions: EXT_WAKE is
driven low and XTAL is driven to a solid logic level.
During and immediately after reset, all processor signals are
three-stated with the following exceptions: EXT_WAKE is
driven high and XTAL is driven in conjunction with CLKIN to
Adding a parallel termination to EXTCLK may prove useful in
further enhancing signal integrity. Be sure to verify overshoot/undershoot and signal integrity specifications on actual
hardware.
During and immediately after reset, all I/O pins have their input
buffers disabled with the exception of the pins that need pullups or pull-downs, as noted in Table 7.
Table 7. Signal Descriptions
Signal Name
Port F: GPIO and Multiplexed Peripherals
PF0–GPIO/DR1SEC/PPI_D8/WAKEN1
PF1–GPIO/DR1PRI/PPI_D9
PF2–GPIO/RSCLK1/PPI_D10
PF3–GPIO/RFS1/PPI_D11
PF4–GPIO/DT1SEC/PPI_D12
PF5–GPIO/DT1PRI/PPI_D13
PF6–GPIO/TSCLK1/PPI_D14
PF7–GPIO/TFS1/PPI_D15
PF8–GPIO/TMR2/SPI0_SSEL2/WAKEN0
PF9–GPIO/TMR0/PPI_FS1/SPI0_SSEL3
PF10–GPIO/TMR1/PPI_FS2
PF11–GPIO/UA_TX/SPI0_SSEL4
PF12–GPIO/UA_RX/SPI0_SSEL7/TACI2–0
PF13–GPIO/SPI0_MOSI/SPI1_SSEL3
PF14–GPIO/SPI0_MISO/SPI1_SSEL4
PF15–GPIO/SPI0_SCK/SPI1_SSEL5
Port G: GPIO and Multiplexed Peripherals
PG0–GPIO/DR0SEC/SPI0_SSEL1/SPI0_SS
PG1–GPIO/DR0PRI/SPI1_SSEL1/WAKEN3
PG2–GPIO/RSCLK0/SPI0_SSEL5
PG3–GPIO/RFS0/PPI_FS3
PG4–GPIO(HWAIT)/DT0SEC/SPI0_SSEL6
PG5–GPIO/DT0PRI/SPI1_SSEL6
PG6–GPIO/TSCLK0
PG7–GPIO/TFS0/SPI1_SSEL7
PG8–GPIO/SPI1_SCK/PPI_D0
PG9–GPIO/SPI1_MOSI/PPI_D1
Driver
Type
Type Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/SPORT1 Receive Data Secondary/PPI Data 8/Wake Enable 1
GPIO/SPORT1 Receive Data Primary/PPI Data 9
GPIO/SPORT1 Receive Serial Clock/PPI Data 10
GPIO/SPORT1 Receive Frame Sync/PPI Data 11
GPIO/SPORT1 Transmit Data Secondary/PPI Data 12
GPIO/SPORT1 Transmit Data Primary/PPI Data 13
GPIO/SPORT1 Transmit Serial Clock/PPI Data 14
GPIO/SPORT1 Transmit Frame Sync/PPI Data 15
GPIO/Timer 2/SPI0 Slave Select Enable 2/Wake Enable 0
GPIO/Timer 0/PPI Frame Sync 1/SPI0 Slave Select Enable 3
GPIO/Timer 1/PPI Frame Sync 2
GPIO/UART Transmit/SPI0 Slave Select Enable 4
GPIO/UART Receive/SPI0 Slave Select Enable 7/Timers 2–0 Alternate Input
Capture
I/O GPIO/SPI0 Master Out Slave In/SPI1 Slave Select Enable 3
I/O GPIO/SPI0 Master In Slave Out/SPI1 Slave Select Enable 4
(This pin should always be pulled high through a 4.7 kΩ resistor,
if booting via the SPI port.)
I/O GPIO/SPI0 Clock/SPI1 Slave Select Enable 5
A
A
A
A
A
A
A
A
A
A
A
A
A
I/O GPIO/SPORT0 Receive Data Secondary/SPI0 Slave Select Enable 1/SPI0 Slave
Select Input
I/O GPIO/SPORT0 Receive Data Primary/SPI1 Slave Select Enable 1/Wake Enable 3
I/O GPIO/SPORT0 Receive Serial Clock/SPI0 Slave Select Enable 5
I/O GPIO/SPORT0 Receive Frame Sync/PPI Frame Sync 3
I/O GPIO (HWAIT output for Slave Boot Modes)/SPORT0 Transmit Data
Secondary/SPI0 Slave Select Enable 6
I/O GPIO/SPORT0 Transmit Data Primary/SPI1 Slave Select Enable 6
I/O GPIO/SPORT0 Transmit Serial Clock
I/O GPIO/SPORT0 Transmit Frame Sync/SPI1 Slave Select Enable 7
I/O GPIO/SPI1 Clock/PPI Data 0
I/O GPIO/SPI1 Master Out Slave In/PPI Data 1
A
Rev. B
| Page 14 of 44 |
July 2013
A
A
A
A
A
A
A
A
A
A
A
A
ADSP-BF592
Table 7. Signal Descriptions (Continued)
Signal Name
PG10–GPIO/SPI1_MISO/PPI_D2
PG11–GPIO/SPI1_SSEL5/PPI_D3
PG12–GPIO/SPI1_SSEL2/PPI_D4/WAKEN2
PG13–GPIO/SPI1_SSEL1/SPI1_SS/PPI_D5
PG14–GPIO/SPI1_SSEL4/PPI_D6/TACLK1
PG15–GPIO/SPI1_SSEL6/PPI_D7/TACLK2
TWI
SCL
SDA
JTAG Port
TCK
TDO
TDI
TMS
TRST
EMU
Clock
CLKIN
XTAL
EXTCLK
Mode Controls
RESET
NMI
BMODE2–0
PPI_CLK
External Regulator Control
PG
EXT_WAKE
Power Supplies
VDDEXT
VDDINT
GND
Driver
Type Function
Type
I/O GPIO/SPI1 Master In Slave Out/PPI Data 2
A
(This pin should always be pulled high through a 4.7 kΩ resistor if booting via
the SPI port.)
I/O GPIO/SPI1 Slave Select Enable 5/PPI Data 3
A
I/O GPIO/SPI1 Slave Select Enable 2 Output/PPI Data 4/Wake Enable 2
A
I/O GPIO/SPI1 Slave Select Enable 1 Output/PPI Data 5/SPI1 Slave Select Input
A
I/O GPIO/SPI1 Slave Select Enable 4/PPI Data 6/Timer 1 Auxiliary Clock Input
A
I/O GPIO/SPI1 Slave Select Enable 6/PPI Data 7/Timer 2 Auxiliary Clock Input
A
I/O TWI Serial Clock (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I2C specification for the proper resistor
value.)
I/O TWI Serial Data (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I2C specification for the proper resistor
value.)
I
O
I
I
I
B
B
O
JTAG CLK
JTAG Serial Data Out
JTAG Serial Data In
JTAG Mode Select
JTAG Reset
(This lead should be pulled low if the JTAG port is not used.)
Emulation Output
A
I
O
O
CLK/Crystal In
Crystal Output
External Clock Output pin/System Clock Output
C
I
I
Reset
Nonmaskable Interrupt
(This lead should be pulled high when not used.)
Boot Mode Strap 2–0
PPI Clock Input
I
I
I
O
P
P
G
Power Good indication
Wake up Indication
ALL SUPPLIES MUST BE POWERED
See Operating Conditions on Page 16.
I/O Power Supply
Internal Power Supply
Ground for All Supplies (Back Side of LFCSP Package.)
Rev. B
| Page 15 of 44 |
July 2013
A
A
ADSP-BF592
SPECIFICATIONS
Specifications are subject to change without notice.
OPERATING CONDITIONS
Parameter
VDDINT Internal Supply Voltage
Internal Supply Voltage
VDDEXT External Supply Voltage
External Supply Voltage
VIH
High Level Input Voltage1, 2
VIHCLKIN High Level Input Voltage1, 2
VIH
High Level Input Voltage1, 2
VIH
High Level Input Voltage1, 2
VIHCLKIN High Level Input Voltage1, 2
High Level Input Voltage3
VIHTWI
VIL
Low Level Input Voltage1, 2
VIL
Low Level Input Voltage1, 2
VIL
Low Level Input Voltage1, 2
VILTWI
Low Level Input Voltage3
TJ
Junction Temperature
Junction Temperature
TJ
TJ
Junction Temperature
Conditions
Non-Automotive Models
Automotive Models
Non-Automotive Models
Automotive Models
VDDEXT = 1.9 V
VDDEXT = 1.9 V
VDDEXT = 2.75 V
VDDEXT = 3.6 V
VDDEXT = 3.6 V
VDDEXT = 1.90 V/2.75 V/3.6 V
VDDEXT = 1.7 V
VDDEXT = 2.25 V
VDDEXT = 3.0 V
VDDEXT = Minimum
64-Lead LFCSP @ TAMBIENT = 0°C to +70°C
64-Lead LFCSP @ TAMBIENT = –40°C to +85°C
64-Lead LFCSP @ TAMBIENT = –40°C to +105°C
1
Min
1.1
1.33
1.7
2.7
1.1
1.2
1.7
2.0
2.2
0.7 × VDDEXT
0
–40
–40
Nominal
1.8/2.5/3.3
Max
1.47
1.47
3.6
3.6
3.6
0.6
0.7
0.8
0.3 × VDDEXT
80
+95
+115
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
Bidirectional leads (PF15–0, PG15–0) and input leads (TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE2–0) of the ADSP-BF592 processor are 3.3 V tolerant
(always accept up to 3.6 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage.
Parameter value applies to all input and bidirectional leads, except SDA and SCL.
3
Parameter applies to SDA and SCL.
2
Rev. B
| Page 16 of 44 |
July 2013
ADSP-BF592
ADSP-BF592 Clock Related Operating Conditions
Table 8 describes the core clock timing requirements for the
ADSP-BF592 processor. Take care in selecting MSEL, SSEL, and
CSEL ratios so as not to exceed the maximum core clock and
system clock (see Table 10). Table 9 describes phase-locked loop
operating conditions.
Table 8. Core Clock (CCLK) Requirements
Parameter
fCCLK
1
Core Clock Frequency (All Models)
Core Clock Frequency (Industrial/Commercial Models)
Core Clock Frequency (Industrial/Commercial Models)
Min VDDINT
1.33 V
1.16 V
1.10 V
Nom VDDINT
1.400 V
1.225 V
1.150 V
Max CCLK
Frequency
400
300
2501
Unit
MHz
MHz
MHz
See the Ordering Guide on Page 44.
Table 9. Phase-Locked Loop Operating Conditions
Parameter
fVCO
1
Voltage Controlled Oscillator (VCO) Frequency
(Non-Automotive Models)
Voltage Controlled Oscillator (VCO) Frequency
(Automotive Models)
Min
72
Max
Instruction Rate1
Unit
MHz
84
Instruction Rate1
MHz
See the Ordering Guide on Page 44.
Table 10. Maximum SCLK Conditions
Parameter1
fSCLK
1
VDDEXT 1.8 V/2.5 V/3.3 V Nominal
Unit
CLKOUT/SCLK Frequency (VDDINT 1.16 V )
100
MHz
CLKOUT/SCLK Frequency (VDDINT <1.16 V )
80
MHz
fSCLK must be less than or equal to fCCLK.
Rev. B
| Page 17 of 44 |
July 2013
ADSP-BF592
ELECTRICAL CHARACTERISTICS
Parameter
VOH
VOH
VOH
VOL
High Level Output Voltage
High Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
VOLTWI
Low Level Output Voltage
IIH
IIL
IIHP
IOZH
IOZHTWI
IOZL
CIN
IDDDEEPSLEEP7
High Level Input Current1
Low Level Input Current1
High Level Input Current JTAG2
Three-State Leakage Current3
Three-State Leakage Current4
Three-State Leakage Current3
Input Capacitance5
VDDINT Current in Deep Sleep Mode
IDDSLEEP
VDDINT Current in Sleep Mode
IDD-IDLE
VDDINT Current in Idle
IDD-TYP
VDDINT Current
IDD-TYP
VDDINT Current
IDD-TYP
VDDINT Current
IDDHIBERNATE7
Hibernate State Current
IDDDEEPSLEEP7
IDDINT8
VDDINT Current in Deep Sleep Mode
VDDINT Current
Test Conditions
VDDEXT = 1.7 V, IOH = –0.5 mA
VDDEXT = 2.25 V, IOH = –0.5 mA
VDDEXT = 3.0 V, IOH = –0.5 mA
VDDEXT = 1.7 V/2.25 V/3.0 V,
IOL = 2.0 mA
VDDEXT = 1.7 V/2.25 V/3.0 V,
IOL = 2.0 mA
Min
1.35
2.0
2.4
VDDEXT =3.6 V, VIN = 3.6 V
VDDEXT =3.6 V, VIN = 0 V
VDDEXT = 3.6 V, VIN = 3.6 V
10
VDDEXT = 3.6 V, VIN = 3.6 V
VDDEXT =3.0 V, VIN = 3.6 V
VDDEXT = 3.6 V, VIN = 0 V
fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V
VDDINT = 1.2 V, fCCLK = 0 MHz,
fSCLK = 0 MHz, TJ = 25°C, ASF = 0.00
VDDINT = 1.2 V, fSCLK = 25 MHz,
TJ = 25°C
VDDINT = 1.2 V, fCCLK = 50 MHz,
TJ = 25°C, ASF = 0.35
VDDINT = 1.3 V, fCCLK = 200 MHz,
TJ = 25°C, ASF = 1.00
VDDINT = 1.3 V, fCCLK = 300 MHz,
TJ = 25°C, ASF = 1.00
VDDINT = 1.4 V, fCCLK = 400 MHz,
TJ = 25°C, ASF = 1.00
VDDEXT =3.3 V, TJ = 25°C,
CLKIN = 0 MHz with voltage
regulator off (VDDINT = 0 V)
fCCLK = 0 MHz, fSCLK = 0 MHz
fCCLK 0 MHz, fSCLK  0 MHz
1
Typical
0.4
0.4
4
0.8
Rev. B
| Page 18 of 44 |
July 2013
10
10
50
10
10
10
86
Unit
V
V
V
V
V
V
μA
μA
μA
μA
μA
μA
pF
mA
4
mA
6
mA
40
mA
66
mA
91
mA
20
μA
Applies to input pins.
Applies to JTAG input pins (TCK, TDI, TMS, TRST).
3
Applies to three-statable pins.
4
Applies to bidirectional pins SCL and SDA.
5
Applies to all signal pins.
6
Guaranteed, but not tested.
7
See the ADSP-BF59x Blackfin Processor Hardware Reference Manual for definitions of sleep, deep sleep, and hibernate operating modes.
8
See Table 11 for the list of IDDINT power vectors covered.
2
Max
Table 12
mA
Table 12 +
mA
(Table 13 × ASF)
ADSP-BF592
Total Power Dissipation
The ASF is combined with the CCLK frequency and VDDINT
dependent data in Table 13 to calculate this part. The second
part is due to transistor switching in the system clock (SCLK)
domain, which is included in the IDDINT specification equation.
Total power dissipation has two components:
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and processor activity. Electrical Characteristics on Page 18 shows the
current dissipation for internal circuitry (VDDINT). IDDDEEPSLEEP
specifies static power dissipation as a function of voltage
(VDDINT) and temperature (see Table 12), and IDDINT specifies the
total power specification for the listed test conditions, including
the dynamic component as a function of voltage (VDDINT) and
frequency (Table 13).
Table 11. Activity Scaling Factors (ASF)1
IDDINT Power Vector
IDD-PEAK
IDD-HIGH
IDD-TYP
IDD-APP
IDD-NOP
IDD-IDLE
There are two parts to the dynamic component. The first part is
due to transistor switching in the core clock (CCLK) domain.
This part is subject to an Activity Scaling Factor (ASF), which
represents application code running on the processor core and
L1 memories (Table 11).
1
Activity Scaling Factor (ASF)
1.29
1.26
1.00
0.83
0.66
0.33
See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors
(EE-297). The power vector information also applies to the ADSP-BF592
processor.
Table 12. Static Current - IDD-DEEPSLEEP (mA)
1
TJ (°C)
25
40
55
70
85
100
115
1
1.15 V
0.85
1.57
2.57
4.04
6.52
9.67
14.18
1.20 V
0.98
1.8
2.88
4.45
7.12
10.51
15.29
1.25 V
1.13
2.01
3.2
4.86
7.73
11.37
16.45
Voltage (VDDINT)1
1.30 V
1.35 V
1.29
1.46
2.16
2.51
3.5
3.84
5.3
5.81
8.36
9.09
12.24
13.21
17.71
19.05
1.40 V
1.62
2.74
4.22
6.31
9.86
14.26
20.45
1.45 V
1.85
3.05
4.63
6.87
10.67
15.37
21.96
1.50 V
2.07
3.36
5.05
7.45
11.54
16.55
23.56
1.40 V
88.96
78.70
69.02
58.17
47.85
26.64
1.45 V
92.81
82.07
71.93
60.69
49.97
27.92
1.50 V
96.63
85.46
75.05
63.23
52.09
29.98
Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 16.
Table 13. Dynamic Current in CCLK Domain (mA, with ASF = 1.0)1
fCCLK
(MHz)2
400
350
300
250
200
100
1
2
1.15 V
N/A
N/A
N/A
46.10
37.86
21.45
1.20 V
N/A
N/A
57.52
48.43
39.80
22.56
1.25 V
N/A
N/A
60.38
50.76
41.76
23.78
Voltage (VDDINT)2
1.30 V
1.35 V
N/A
85.31
72.08
75.41
63.22
66.14
53.19
55.68
43.79
45.81
24.98
25.97
The values are not guaranteed as stand-alone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 18.
Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 16 and Table 8 on Page 17.
Rev. B
| Page 19 of 44 |
July 2013
ADSP-BF592
ABSOLUTE MAXIMUM RATINGS
Characteristics table.
Stresses greater than those listed in Table 14 may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Table 16. Total Current Pin Groups–VDDEXT Groups
Table 14. Absolute Maximum Ratings
Parameter
Internal Supply Voltage (VDDINT)
External (I/O) Supply Voltage (VDDEXT)
Input Voltage1, 2
Output Voltage Swing
IOH/IOL Current per Pin Group
IOH/IOL Current per Individual Pin
Storage Temperature Range
Junction Temperature While Biased
(Non-Automotive Models)
Junction Temperature While Biased
(Automotive Models)
1
2
Rating
–0.3 V to +1.50 V
–0.3 V to +3.8 V
–0.5 V to +3.6 V
–0.5 V to VDDEXT +0.5 V
55 mA (Max)
25 mA (Max)
–65°C to +150°C
+110°C
Group
1
2
3
4
5
6
7
8
9
10
11
12
Pins in Group
PF0, PF1, PF2, PF3
PF4, PF5, PF6, PF7
PF8, PF9, PF10, PF11
PF12, PF13, PF14, PF15
PG3, PG2, PG1, PG0
PG7, PG6, PG5, PG4
PG11, PG10, PG9, PG8
PG15, PG14, PG13, PG12
TDI, TDO, EMU, TCK, TRST, TMS
BMODE2, BMODE1, BMODE0
EXT_WAKE, PG, RESET, NMI, PPI_CLK, EXTCLK
SDA, SCL, CLKIN, XTAL
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary circuitry, damage may occur
on devices subjected to high energy ESD. Therefore,
proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
+115°C
Applies to 100% transient duty cycle. For other duty cycles see Table 15.
Applies only when VDDEXT is within specifications. When VDDEXT is outside specifications, the range is VDDEXT ± 0.2 Volts.
Table 15. Maximum Duty Cycle for Input Transient Voltage1
VIN Min (V)2
–0.5
–0.7
–0.8
–0.9
–1.0
VIN Max (V)2
+3.8
+4.0
+4.1
+4.2
+4.3
Maximum Duty Cycle3
100%
40%
25%
15%
10%
1
Applies to all signal pins with the exception of CLKIN, XTAL, EXT_WAKE.
The individual values cannot be combined for analysis of a single instance of
overshoot or undershoot. The worst case observed value must fall within one of
the voltages specified, and the total duration of the overshoot or undershoot
(exceeding the 100% case) must be less than or equal to the corresponding duty
cycle.
3
Duty cycle refers to the percentage of time the signal exceeds the value for the
100% case. The is equivalent to the measured duration of a single instance of
overshoot or undershoot as a percentage of the period of occurrence.
2
Table 14 specifies the maximum total source/sink (IOH/IOL) current for a group of pins and for individual pins. Permanent
damage can occur if this value is exceeded. To understand this
specification, if pins PF0 and PF1 from Group 1 in Table 16
were sourcing or sinking 10 mA each, the total current for those
pins would be 20 mA. This would allow up to 35 mA total that
could be sourced or sunk by the remaining pins in the group
without damaging the device. It should also be noted that the
maximum source or sink current for an individual pin cannot
exceed 25 mA. The list of all groups and their pins are shown in
Table 16. Note that the VOH and VOL specifications have separate
per-pin maximum current requirements, see the Electrical
Rev. B
| Page 20 of 44 |
July 2013
ADSP-BF592
PACKAGE INFORMATION
The information presented in Figure 6 and Table 17 provides
details about the package branding for the ADSP-BF592 processor. For a complete listing of product availability, see Ordering
Guide on Page 44.
a
ADSP-BF592
tppZccc
vvvvvv.x n.n
#yyww country_of_origin
B
Figure 6. Product Information on Package
Table 17. Package Brand Information
Brand Key
ADSP-BF592
t
pp
Z
ccc
vvvvvv.x
n.n
#
yyww
Field Description
Product Name
Temperature Range
Package Type
RoHS Compliant Designation
See Ordering Guide
Assembly Lot Code
Silicon Revision
RoHS Compliance Designator
Date Code
Rev. B
| Page 21 of 44 |
July 2013
ADSP-BF592
TIMING SPECIFICATIONS
Specifications are subject to change without notice.
Clock and Reset Timing
Table 18 and Figure 7 describe clock and reset operations. Per
the CCLK and SCLK timing specifications in Table 8 to
Table 10, combinations of CLKIN and clock multipliers must
not select core/peripheral clocks in excess of the processor’s
instruction rate.
Table 18. Clock and Reset Timing
Parameter
Timing Requirements
fCKIN
CLKIN Period1, 2, 3, 4
tCKINL
CLKIN Low Pulse1
tCKINH
CLKIN High Pulse1
tWRST
RESET Asserted Pulse Width Low5
Switching Characteristic
tBUFDLAY
CLKIN to CLKBUF6 Delay
Min
VDDEXT 1.8 V Nominal
Max
12
10
10
11 × tCKIN
50
11
VDDEXT 2.5 V/3.3 V Nominal
Min
Max
Unit
12
10
10
11 × tCKIN
50
MHz
ns
ns
ns
10
ns
1
Applies to PLL bypass mode and PLL non bypass mode.
2
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 8 on Page 17 through Table 10
on Page 17.
3
The tCKIN period (see Figure 7) equals 1/fCKIN.
4
If the DF bit in the PLL_CTL register is set, the minimum fCKIN specification is 24 MHz.
5
Applies after power-up sequence is complete. See Table 19 and Figure 8 for power-up reset timing.
6
The ADSP-BF592 processor does not have a dedicated CLKBUF pin. Rather, the EXTCLK pin may be programmed to serve as CLKBUF or CLKOUT. This parameter applies
when EXTCLK is programmed to output CLKBUF.
tCKIN
CLKIN
tCKINL
tBUFDLAY
tCKINH
CLKBUF
tWRST
RESET
Figure 7. Clock and Reset Timing
Rev. B
| Page 22 of 44 |
July 2013
tBUFDLAY
ADSP-BF592
Table 19. Power-Up Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tRST_IN_PWR
RESET Deasserted after the VDDINT, VDDEXT, and CLKIN Pins are Stable and within 3500 × tCKIN
Specification
tRST_IN_PWR
RESET
CLKIN
V
DD_SUPPLIES
Figure 8. Power-Up Reset Timing
Rev. B
| Page 23 of 44 |
July 2013
μs
ADSP-BF592
Parallel Peripheral Interface Timing
Table 20 and Figure 9 through Figure 13 describe parallel
peripheral interface operations.
Table 20. Parallel Peripheral Interface Timing
VDDEXT = 1.8 V
Max
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
tSCLK –1.5
2 × tSCLK –1.5
tSCLK –1.5
2 × tSCLK –1.5
ns
ns
4 × tPCLK
6.7
4 × tPCLK
6.7
ns
ns
1.8
4.1
2
1.6
3.5
1.6
ns
ns
ns
Min
Parameter
Timing Requirements
tPCLKW
PPI_CLK Width1
tPCLK
PPI_CLK Period1
Timing Requirements—GP Input and Frame Capture Modes
External Frame Sync Startup Delay2
tPSUD
tSFSPE
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
tHFSPE
External Frame Sync Hold After PPI_CLK
tSDRPE
Receive Data Setup Before PPI_CLK
tHDRPE
Receive Data Hold After PPI_CLK
Switching Characteristics—GP Output and Frame Capture Modes
tDFSPE
Internal Frame Sync Delay After PPI_CLK
tHOFSPE
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
tDDTPE
tHDTPE
Transmit Data Hold After PPI_CLK
9.0
1.7
8.0
1.7
8.7
2.3
8.0
1.9
1
ns
ns
ns
ns
PPI_CLK frequency cannot exceed fSCLK/2.
2
The PPI port is fully enabled 4 PPI clock cycles after the PAB write to the PPI port enable bit. Only after the PPI port is fully enabled are external frame syncs and data words
guaranteed to be received correctly by the PPI peripheral.
PPI_CLK
tPSUD
PPI_FS1/2
Figure 9. PPI with External Frame Sync Timing
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
PPI_CLK
tSFSPE
tPCLKW
tHFSPE
tPCLK
PPI_FS1/2
tSDRPE
tHDRPE
PPI_DATA
Figure 10. PPI GP Rx Mode with External Frame Sync Timing
Rev. B
| Page 24 of 44 |
July 2013
ADSP-BF592
DATA DRIVEN /
FRAME SYNC SAMPLED
PPI_CLK
tSFSPE
tHFSPE
tPCLKW
tPCLK
PPI_FS1/2
tDDTPE
tHDTPE
PPI_DATA
Figure 11. PPI GP Tx Mode with External Frame Sync Timing
FRAME SYNC
DRIVEN
DATA
SAMPLED
PPI_CLK
tHOFSPE
tDFSPE
tPCLKW
tPCLK
PPI_FS1/2
tSDRPE
tHDRPE
PPI_DATA
Figure 12. PPI GP Rx Mode with Internal Frame Sync Timing
FRAME SYNC
DRIVEN
DATA
DRIVEN
tPCLK
PPI_CLK
tHOFSPE
tDFSPE
tPCLKW
PPI_FS1/2
tDDTPE
tHDTPE
PPI_DATA
Figure 13. PPI GP Tx Mode with Internal Frame Sync Timing
Rev. B
| Page 25 of 44 |
July 2013
DATA
DRIVEN
ADSP-BF592
Serial Ports
Table 21 through Table 25 and Figure 14 through Figure 18
describe serial port operations.
Table 21. Serial Ports—External Clock
Parameter
Timing Requirements
tSFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx1
tHFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx1
tSDRE
Receive Data Setup Before RSCLKx1
tHDRE
Receive Data Hold After RSCLKx1
tSCLKEW
TSCLKx/RSCLKx Width
TSCLKx/RSCLKx Period
tSCLKE
tSUDTE
Start-Up Delay From SPORT Enable To First External TFSx2
tSUDRE
Start-Up Delay From SPORT Enable To First External RFSx2
Switching Characteristics
tDFSE
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)3
tHOFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)1
tDDTE
Transmit Data Delay After TSCLKx1
tHDTE
Transmit Data Hold After TSCLKx1
Min
VDDEXT
1.8V Nominal
Max
3
3
3
3.5
4.5
2 × tSCLK
4 × tTSCLKE
4 × tRSCLKE
VDDEXT
2.5 V/3.3V Nominal
Min
Max
Unit
3
3
3
3
4.5
2 × tSCLK
4 × tTSCLKE
4 × tRSCLKE
ns
ns
ns
ns
ns
ns
ns
ns
10
0
10
0
11
ns
ns
0
ns
ns
VDDEXT
2.5 V/3.3V Nominal
Min
Max
Unit
11.5
–1.5
11.5
–1.5
9.6
–1.5
11.3
–1.5
ns
ns
ns
ns
7
8
ns
ns
0
10
1
Referenced to sample edge.
Verified in design but untested.
3
Referenced to drive edge.
2
Table 22. Serial Ports—Internal Clock
Parameter
Timing Requirements
tSFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx1
tHFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx1
tSDRI
Receive Data Setup Before RSCLKx1
tHDRI
Receive Data Hold After RSCLKx1
Switching Characteristics
TSCLKx/RSCLKx Width
tSCLKIW
tDFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)2
tHOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)1
tDDTI
Transmit Data Delay After TSCLKx1
tHDTI
Transmit Data Hold After TSCLKx1
1
2
Min
VDDEXT
1.8V Nominal
Max
4
–2
–2
4
–1.8
Referenced to sample edge.
Referenced to drive edge.
Rev. B
3
| Page 26 of 44 |
July 2013
ns
3
–1.5
ns
ns
ADSP-BF592
DATA RECEIVE—INTERNAL CLOCK
DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE
DRIVE EDGE
SAMPLE EDGE
SAMPLE EDGE
tSCLKE
tSCLKEW
tSCLKIW
RSCLKx
RSCLKx
tDFSE
tDFSI
tHOFSI
tHOFSE
RFSx
(OUTPUT)
RFSx
(OUTPUT)
tSFSI
tHFSI
RFSx
(INPUT)
tSFSE
tHFSE
tSDRE
tHDRE
RFSx
(INPUT)
tSDRI
tHDRI
DRx
DRx
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
DATA TRANSMIT—EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE
tSCLKIW
SAMPLE EDGE
t SCLKEW
TSCLKx
tSCLKE
TSCLKx
tD FSI
tDFSE
tHOFSI
tHOFSE
TFSx
(OUTPUT)
TFSx
(OUTPUT)
tSFSI
tHFSI
tSFSE
TFSx
(INPUT)
TFSx
(INPUT)
tDDTI
tDDTE
tHDTI
tHDTE
DTx
DTx
Figure 14. Serial Ports
TSCLKx
(INPUT)
tSUDTE
TFSx
(INPUT)
RSCLKx
(INPUT)
tSUDRE
RFSx
(INPUT)
FIRST
TSCLKx/RSCLKx
EDGE AFTER
SPORT ENABLED
Figure 15. Serial Port Start Up with External Clock and Frame Sync
Rev. B
| Page 27 of 44 |
July 2013
tHFSE
ADSP-BF592
Table 23. Serial Ports—Enable and Three-State
Min
Parameter
Switching Characteristics
tDTENE
Data Enable Delay from External TSCLKx1
tDDTTE
Data Disable Delay from External TSCLKx1
tDTENI
Data Enable Delay from Internal TSCLKx1
Data Disable Delay from Internal TSCLKx1
tDDTTI
1
VDDEXT
1.8V Nominal
Max
0
0
tSCLK + 1
–2
DRIVE EDGE
DRIVE EDGE
TSCLKx
tDTENE/I
tDDTTE/I
DTx
Figure 16. Serial Ports — Enable and Three-State
| Page 28 of 44 |
tSCLK + 1
–2
tSCLK + 1
Referenced to drive edge.
Rev. B
VDDEXT
2.5 V/3.3V Nominal
Min
Max
July 2013
tSCLK + 1
Unit
ns
ns
ns
ns
ADSP-BF592
Table 24. Serial Ports—External Late Frame Sync
Min
Parameter
Switching Characteristics
tDDTLFSE
Data Delay from Late External TFSx
or External RFSx in multi-channel mode with MFD = 01, 2
tDTENLFSE
Data Enable from External RFSx in multi-channel mode with 0
MFD = 01, 2
1
2
VDDEXT
1.8V Nominal
Max
12
When in multi-channel mode, TFSx enable and TFSx valid follow tDTENLFSE and tDDTLFSE.
If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2 then tDDTTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFSE apply.
EXTERNAL RFSx IN MULTI-CHANNEL MODE
SAMPLE
DRIVE
EDGE
EDGE
DRIVE
EDGE
RSCLKx
RFSx
tDDTLFSE
tDTENLFSE
1ST BIT
DTx
LATE EXTERNAL TFSx
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
TSCLKx
TFSx
tDDTLFSE
1ST BIT
DTx
Figure 17. Serial Ports — External Late Frame Sync
Rev. B
| Page 29 of 44 |
July 2013
VDDEXT
2.5 V/3.3V Nominal
Min
Max
10
0
Unit
ns
ns
ADSP-BF592
Table 25. Serial Ports—Gated Clock Mode
Parameter
Timing Requirements
tSDRI
Receive Data Setup Before TSCLKx
tHDRI
Receive Hold After TSCLKx
Switching Characteristics
Transmit Data Delay After TSCLKx
tDDTI
tHDTI
Transmit Data Hold After TSCLKx
tDFTSCLKCNV
First TSCLKx edge delay after TFSx/TMR1 Low
tDCNVLTSCLK
TFSx/TMR1 High Delay After Last TSCLKx Edge
Min
VDDEXT
1.8V Nominal
Max
11.3
0
Unit
8.7
0
ns
ns
3
3
–1.8
0.5 × tTSCLK – 3
tTSCLK – 3
–1.8
0.5 × tTSCLK – 3
tTSCLK – 3
GATED CLOCK MODE DATA RECEIVE
TSCLKx
(OUT)
tSDRI
tHDRI
DRx
DELAY TIME DATA TRANSMIT
TFS/TMR
(OUT)
tDFTSCLKCNV
tDCNVLTSCLK
tDFTSCLKCNV
tDCNVLTSCLK
TSCLKx
(OUT)
TSCLKx
(OUT)
tDDTI
tHDTI
DTx
Figure 18. Serial Ports Gated Clock Mode
Rev. B
VDDEXT
2.5 V/3.3 V Nominal
Min
Max
| Page 30 of 44 |
July 2013
ns
ns
ns
ns
ADSP-BF592
Serial Peripheral Interface (SPI) Port—Master Timing
Table 26 and Figure 19 describe SPI port master operations.
Table 26. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
tSSPIDM
Data Input Valid to SCK Edge (Data Input Setup)
tHSPIDM
SCK Sampling Edge to Data Input Invalid
Switching Characteristics
SPI_SELx low to First SCK Edge
tSDSCIM
tSPICHM
Serial Clock High Period
tSPICLM
Serial Clock Low Period
tSPICLK
Serial Clock Period
tHDSM
Last SCK Edge to SPI_SELx High
tSPITDM
Sequential Transfer Delay
SCK Edge to Data Out Valid (Data Out Delay)
tDDSPIDM
tHDSPIDM
SCK Edge to Data Out Invalid (Data Out Hold)
VDDEXT
2.5 V/3.3V Nominal
Min
Max
Unit
11.6
–1.5
9.6
–1.5
ns
ns
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
4 × tSCLK – 1.5
2 × tSCLK – 2
2 × tSCLK – 1.5
0
6
–1
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
4 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
0
6
–1
ns
ns
ns
ns
ns
ns
ns
ns
Min
VDDEXT
1.8V Nominal
Max
SPIxSELy
(OUTPUT)
tSDSCIM
tSPICLM
tSPICHM
tSPICLK
tHDSM
SPIxSCK
(OUTPUT)
tHDSPIDM
tDDSPIDM
SPIxMOSI
(OUTPUT)
tSSPIDM
CPHA = 1
tHSPIDM
SPIxMISO
(INPUT)
tDDSPIDM
tHDSPIDM
SPIxMOSI
(OUTPUT)
CPHA = 0
tSSPIDM
tHSPIDM
SPIxMISO
(INPUT)
Figure 19. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. B
| Page 31 of 44 |
July 2013
tSPITDM
ADSP-BF592
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 27 and Figure 20 describe SPI port slave operations.
Table 27. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
tSPICHS
Serial Clock High Period
tSPICLS
Serial Clock Low Period
tSPICLK
Serial Clock Period
Last SCK Edge to SPI_SS Not Asserted
tHDS
tSPITDS
Sequential Transfer Delay
tSDSCI
SPI_SS Assertion to First SCK Edge
tSSPID
Data Input Valid to SCK Edge (Data Input Setup)
tHSPID
SCK Sampling Edge to Data Input Invalid
Switching Characteristics
tDSOE
SPI_SS Assertion to Data Out Active
tDSDHI
SPI_SS Deassertion to Data High Impedance
tDDSPID
SCK Edge to Data Out Valid (Data Out Delay)
tHDSPID
SCK Edge to Data Out Invalid (Data Out Hold)
Min
VDDEXT
1.8V Nominal
Max
2 × tSCLK – 1.5
2 × tSCLK – 1.5
4 × tSCLK
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
1.6
2
0
0
12
11
10
VDDEXT
2.5 V/3.3V Nominal
Min
Max
Unit
2 × tSCLK – 1.5
2 × tSCLK – 1.5
4 × tSCLK
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
1.6
1.6
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
10.3
9
10
0
SPIxSS
(INPUT)
tSDSCI
tSPICLS
tSPICHS
tHDS
tSPICLK
SPIxSCK
(INPUT)
tDSOE
tDDSPID
tDDSPID
tHDSPID
tDSDHI
SPIxMISO
(OUTPUT)
CPHA = 1
tSSPID
tHSPID
SPIxMOSI
(INPUT)
tDSOE
tHDSPID
tDDSPID
tDSDHI
SPIxMISO
(OUTPUT)
CPHA = 0
tSSPID
SPIxMOSI
(INPUT)
Figure 20. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. B
| Page 32 of 44 |
July 2013
tHSPID
tSPITDS
ns
ns
ns
ns
ADSP-BF592
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
The UART ports receive and transmit operations are described
in the ADSP-BF59x Hardware Reference Manual.
General-Purpose Port Timing
Table 28 and Figure 21 describe general-purpose
port operations.
Table 28. General-Purpose Port Timing
VDDEXT 1.8V/2.5 V/3.3V Nominal
Min
Max
Unit
Parameter
Timing Requirement
tWFI
General-Purpose Port Pin Input Pulse Width
Switching Characteristic
tGPOD
General-Purpose Port Pin Output Delay from CLKOUT Low
tSCLK + 1
0
CLKOUT
tGPOD
GPIO OUTPUT
tWFI
GPIO INPUT
Figure 21. General-Purpose Port Timing
Rev. B
| Page 33 of 44 |
July 2013
ns
11
ns
ADSP-BF592
Timer Cycle Timing
Table 29 and Figure 22 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input frequency of (fSCLK/2) MHz.
Table 29. Timer Cycle Timing
VDDEXT
2.5 V/3.3V Nominal
Min
Max
Unit
1 × tSCLK
1 × tSCLK
ns
1 × tSCLK
1 × tSCLK
ns
10
–2
8
–2
ns
ns
VDDEXT
1.8V Nominal
Max
Min
Parameter
Timing Requirements
tWL
Timer Pulse Width Input Low
(Measured In SCLK Cycles)1
tWH
Timer Pulse Width Input High
(Measured In SCLK Cycles)1
tTIS
Timer Input Setup Time Before CLKOUT Low2
tTIH
Timer Input Hold Time After CLKOUT Low2
Switching Characteristics
tHTO
Timer Pulse Width Output
(Measured In SCLK Cycles)
tTOD
Timer Output Update Delay After CLKOUT High
(232 – 1) × tSCLK
1 × tSCLK – 2
tSCLK – 1.5
6
(232 – 1) × tSCLK
ns
6
ns
1
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PG0 or PPI_CLK signals in PWM output mode.
2
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
CLKOUT
tTOD
TMRx OUTPUT
tTIS
tTIH
tHTO
TMRx INPUT
tWH,tWL
Figure 22. Timer Cycle Timing
Timer Clock Timing
Table 30 and Figure 23 describe timer clock timing.
Table 30. Timer Clock Timing
Parameter
Switching Characteristic
tTODP
Timer Output Update Delay After PPI_CLK High
Min
VDDEXT = 1.8 V
Max
12.64
PPI_CLK
tTODP
TMRx OUTPUT
Figure 23. Timer Clock Timing
Rev. B
| Page 34 of 44 |
July 2013
Min
VDDEXT = 2.5V/3.3 V
Max
12.64
Unit
ns
ADSP-BF592
JTAG Test And Emulation Port Timing
Table 31 and Figure 24 describe JTAG port operations.
Table 31. JTAG Port Timing
Parameter
Timing Requirements
tTCK
TCK Period
tSTAP
TDI, TMS Setup Before TCK High
tHTAP
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High1
tSSYS
tHSYS
System Inputs Hold After TCK High1
tTRSTW
TRST Pulse Width2 (measured in TCK cycles)
Switching Characteristics
tDTDO
TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low3
Min
VDDEXT
1.8V Nominal
Max
20
4
4
4
5
4
10
13
1
System inputs = SCL, SDA, PF15–0, PG15–0, PH2–0, TCK, NMI, BMODE3–0, PG.
50 MHz maximum.
3
System outputs = CLKOUT, SCL, SDA, PF15–0, PG15–0, PH2–0, TDO, EMU, EXT_WAKE.
2
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 24. JTAG Port Timing
Rev. B
| Page 35 of 44 |
July 2013
VDDEXT
2.5 V/3.3V Nominal
Min
Max
Unit
20
4
4
5
5
4
ns
ns
ns
ns
ns
TCK
10
13
ns
ns
ADSP-BF592
OUTPUT DRIVE CURRENTS
Figure 25 through Figure 33 show typical current-voltage characteristics for the output drivers of the ADSP-BF592 processor.
40
VDDEXT = 1.9V @ – 40°C
VDDEXT = 3.0V @ – 40°C
100
VDDEXT = 3.3V @ 25°C
80
VDDEXT = 3.6V @ 105°C
SOURCE CURRENT (mA)
60
40
VOH
20
20
VOH
SOURCE CURRENT (mA)
120
VDDEXT = 1.8V @ 25°C
VDDEXT = 1.7V @ 105°C
30
The curves represent the current drive capability of the output
drivers. See Table 7 on Page 14 for information about which
driver type corresponds to a particular pin.
10
0
–10
VOL
–20
–30
0
–40
–20
0
0.5
1.0
–40
1.5
SOURCE VOLTAGE (V)
–60
VOL
–80
Figure 27. Driver Type A Current (1.8V VDDEXT)
–100
0
0.5
1.0
1.5
2.0
2.5
3.0
120
3.5
VDDEXT = 3.6V @ – 40°C
100
SOURCE VOLTAGE (V)
VDDEXT = 3.3V @ 25°C
80
Figure 25. Driver Type A Current (3.3V VDDEXT)
VDDEXT = 2.75V @ – 40°C
VDDEXT = 2.5V @ 25°C
VDDEXT = 2.25V @ 105°C
20
40
20
0
–20
–40
–60
VOL
–80
VOH
–100
0
–120
0
–20
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
–40
Figure 28. Driver Type B Current (3.3V VDDEXT)
VOL
–60
80
–80
0
0.5
1.0
1.5
2.0
VDDEXT = 2.75V @ – 40°C
2.5
VDDEXT = 2.5V @ 25°C
60
SOURCE VOLTAGE (V)
VDDEXT = 2.25V @ 105°C
40
Figure 26. Drive Type A Current (2.5V VDDEXT)
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
40
SOURCE CURRENT (mA)
80
60
VDDEXT = 3.0V @ 105°C
60
20
0
–20
–40
VOL
–60
–80
0
0.5
1.0
1.5
2.0
SOURCE VOLTAGE (V)
Figure 29. Driver Type B Current (2.5V VDDEXT)
Rev. B
| Page 36 of 44 |
July 2013
2.5
ADSP-BF592
60
50
VDDEXT = 1.9V @ – 40°C
40
VDDEXT = 1.8V @ 25°C
30
VDDEXT = 1.7V @ 105°C
20
10
0
–10
–20
VOL
–30
VDDEXT = 1.8V @ 25°C
VDDEXT = 1.7V @ 105°C
40
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
VDDEXT = 1.9V @ – 40°C
20
VOH
0
–20
VOL
–40
–40
–60
–50
0
0.5
1.0
0
1.5
0.5
1.0
1.5
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 33. Driver Type C Current (1.8V VDDEXT)
Figure 30. Driver Type B Current (1.8V VDDEXT)
TEST CONDITIONS
150
SOURCE CURRENT (mA)
VDDEXT = 3.6V @ – 40°C
120
VDDEXT = 3.3V @ 25°C
90
VDDEXT = 3.0V @ 105°C
60
VOH
30
All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 34
shows the measurement point for ac measurements (except output enable/disable). The measurement point VMEAS is VDDEXT/2
for VDDEXT (nominal) = 1.8 V/2.5 V/3.3 V.
0
– 30
INPUT
OR
OUTPUT
– 60
VOL
– 90
– 120
Figure 34. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
– 150
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Output Enable Time Measurement
SOURCE VOLTAGE (V)
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving.
Figure 31. Driver Type C Current (3.3V VDDEXT)
100
VDDEXT = 2.75V @ – 40°C
75
VDDEXT = 2.5V @ 25°C
VDDEXT = 2.25V @ 105°C
50
SOURCE CURRENT (mA)
VMEAS
VMEAS
25
The output enable time tENA is the interval from the point when
a reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of
Figure 35.
VOH
0
REFERENCE
SIGNAL
– 25
– 50
VOL
tDIS_MEASURED
– 75
tDIS
– 100
0
0.5
1.0
1.5
2.0
2.5
VOH
(MEASURED)
SOURCE VOLTAGE (V)
VOL
(MEASURED)
Figure 32. Driver Type C Current (2.5V VDDEXT)
tENA_MEASURED
tENA
VOH (MEASURED) ⴚ ⌬V
VOH(MEASURED)
VTRIP(HIGH)
VOL (MEASURED) + ⌬V
VTRIP(LOW)
VOL (MEASURED)
tDECAY
OUTPUT STOPS DRIVING
tTRIP
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
Figure 35. Output Enable/Disable
Rev. B
| Page 37 of 44 |
July 2013
ADSP-BF592
The time tENA_MEASURED is the interval from when the reference
signal switches to when the output voltage reaches VTRIP(high)
or VTRIP(low) and is shown below.
• VDDEXT (nominal) = 1.8 V, VTRIP (high) is 1.05 V, VTRIP
(low) is 0.75 V
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 36). VLOAD is equal
to (VDDEXT)/2.
• VDDEXT (nominal) = 2.5 V, VTRIP (high) is 1.5 V, VTRIP (low)
is 1.0 V
TESTER PIN ELECTRONICS
50:
VLOAD
• VDDEXT (nominal) = 3.3 V, VTRIP (high) is 1.9 V, VTRIP (low)
is 1.4 V
T1
DUT
OUTPUT
45:
70:
Time tTRIP is the interval from when the output starts driving to
when the output reaches the VTRIP(high) or VTRIP(low) trip
voltage.
ZO = 50:(impedance)
TD = 4.04 r 1.18 ns
50:
0.5pF
4pF
Time tENA is calculated as shown in the equation:
2pF
400:
t ENA = t ENA_MEASURED – t TRIP
If multiple pins are enabled, the measurement value is that of
the first lead to start driving.
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
Output Disable Time Measurement
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time tDIS is the
difference between tDIS_MEASURED and tDECAY as shown on the left
side of Figure 35.
t DIS = t DIS_MEASURED – t DECAY
The time for the voltage on the bus to decay by ΔV is dependent
on the capacitive load CL and the load current IL. This decay
time can be approximated by the equation:
t DECAY =  C L V   I L
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
Figure 36. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
The graphs of Figure 37 through Figure 42 show how output
rise time varies with capacitance. The delay and hold specifications given should be derated by a factor derived from these
figures. The graphs in these figures may not be linear outside the
ranges shown.
The time tDECAY is calculated with test loads CL and IL, and with
ΔV equal to 0.25 V for VDDEXT (nominal) = 2.5 V/3.3 V and
0.15 V for VDDEXT (nominal) = 1.8V.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ΔV
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. CL is
the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be
tDECAY plus the various output disable times as specified in the
Timing Specifications on Page 22.
Rev. B
tFALL
16
RISE AND FALL TIME (ns)
The time tDIS_MEASURED is the interval from when the reference
signal switches to when the output voltage decays ΔV from the
measured output high or output low voltage.
20
18
| Page 38 of 44 |
14
tRISE
12
10
8
6
4
tFALL = 1.8V @ 25°C
2
tRISE = 1.8V @ 25°C
0
0
50
100
150
200
LOAD CAPACITANCE (pF)
Figure 37. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V VDDEXT)
July 2013
250
ADSP-BF592
18
9
16
8
tFALL
tFALL
7
RISE AND FALL TIME (ns)
RISE AND FALL TIME (ns)
14
tRISE
12
10
8
6
4
tFALL = 2.5V @ 25°C
2
6
tRISE
5
4
3
2
tFALL = 2.5V @ 25°C
1
tRISE = 2.5V @ 25°C
tRISE = 2.5V @ 25°C
0
0
0
50
100
150
200
250
0
50
LOAD CAPACITANCE (pF)
Figure 38. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (2.5V VDDEXT)
150
250
7
14
tFALL
6
tFALL
12
RISE AND FALL TIME (ns)
tRISE
10
8
6
4
2
5
tRISE
4
3
2
1
tFALL = 3.3V @ 25°C
tFALL = 3.3V @ 25°C
tRISE = 3.3V @ 25°C
tRISE = 3.3V @ 25°C
0
0
50
100
200
150
250
0
0
LOAD CAPACITANCE (pF)
tFALL
10
8
tRISE
6
4
tFALL = 1.8V @ 25°C
tRISE = 1.8V @ 25°C
0
0
50
100
150
100
150
200
Figure 42. Driver Type C Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (3.3V VDDEXT)
12
2
50
LOAD CAPACITANCE (pF)
Figure 39. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (3.3V VDDEXT)
RISE AND FALL TIME (ns)
200
Figure 41. Driver Type C Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (2.5V VDDEXT)
16
RISE AND FALL TIME (ns)
100
LOAD CAPACITANCE (pF)
200
250
LOAD CAPACITANCE (pF)
Figure 40. Driver Type C Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V VDDEXT)
Rev. B
| Page 39 of 44 |
July 2013
250
ADSP-BF592
ENVIRONMENTAL CONDITIONS
To determine the junction temperature on the application
printed circuit board use:
T J = T CASE +   JT  P D 
where:
TJ = junction temperature (°C)
TCASE = case temperature (°C) measured by customer at top center of package.
JT = from Table 32
PD = power dissipation (see Total Power Dissipation on Page 19
for the method to calculate PD)
Table 32. Thermal Characteristics
Parameter
θJA
θJMA
θJMA
θJB
θJC
ΨJT
ΨJT
ΨJT
Condition
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
Typical
23.5
20.9
20.2
11.2
9.5
0.21
0.36
0.43
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Values of JA are provided for package comparison and printed
circuit board design considerations. JA can be used for a first
order approximation of TJ by the equation:
T J = T A +   JA  P D 
where:
TA = ambient temperature (°C)
Values of JC are provided for package comparison and printed
circuit board design considerations when an external heat sink
is required.
Values of JB are provided for package comparison and printed
circuit board design considerations.
In Table 32, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board
measurement complies with JESD51-8. The junction-to-case
measurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 2S2P JEDEC test board.
Rev. B
| Page 40 of 44 |
July 2013
ADSP-BF592
64-LEAD LFCSP LEAD ASSIGNMENT
Table 33 lists the LFCSP leads by signal mnemonic. Table 34
lists the LFCSP by lead number.
Table 33. 64-Lead LFCSP Lead Assignment (Alphabetical by Signal)
Signal
BMODE0
BMODE1
BMODE2
EXTCLK/SCLK
CLKIN
EMU
EXT_WAKE
GND
NMI
PF0
PF1
PF2
PF3
PF4
PF5
PF6
Lead No.
29
28
27
57
61
19
51
30
54
63
64
1
2
4
5
6
Signal
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PG
PG0
PG1
PG2
PG3
PG4
PG5
Lead No.
7
10
11
12
13
15
16
17
18
52
31
32
33
34
36
37
Signal
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
PG14
PG15
PPI_CLK
RESET
SCL
SDA
TCK
TDI
Lead No.
38
39
42
43
44
45
47
48
49
50
56
53
60
59
24
22
Signal
Lead No.
TDO
23
TMS
21
TRST
20
VDDEXT
3
VDDEXT
14
VDDEXT
25
VDDEXT
35
46
VDDEXT
VDDEXT
58
VDDINT
8
VDDINT
9
VDDINT
26
VDDINT
40
41
VDDINT
VDDINT
55
XTAL
62
GND*
65
* Lead no. 65 is the GND supply (see Figure 43 and Figure 44) for the processor (6.2 mm × 6.2 mm); this pad must connect to GND.
Table 34. 64-Lead LFCSP Lead Assignment (Numerical by Lead Number)
Lead No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Signal
PF2
PF3
VDDEXT
PF4
PF5
PF6
PF7
VDDINT
VDDINT
PF8
PF9
PF10
PF11
VDDEXT
PF12
PF13
Lead No.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Signal
PF14
PF15
EMU
TRST
TMS
TDI
TDO
TCK
VDDEXT
VDDINT
BMODE2
BMODE1
BMODE0
GND
PG0
PG1
Lead No.
Signal
49
PG14
50
PG15
51
EXT_WAKE
52
PG
53
RESET
54
NMI
55
VDDINT
56
PPI_CLK
57
EXTCLK/SCLK
58
VDDEXT
59
SDA
60
SCL
61
CLKIN
62
XTAL
63
PF0
64
PF1
65
GND*
* Pin no. 65 is the GND supply (see Figure 43 and Figure 44) for the processor (6.2 mm × 6.2 mm); this pad must connect to GND.
Rev. B
Lead No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
| Page 41 of 44 |
July 2013
Signal
PG2
PG3
VDDEXT
PG4
PG5
PG6
PG7
VDDINT
VDDINT
PG8
PG9
PG10
PG11
VDDEXT
PG12
PG13
ADSP-BF592
Figure 43 shows the top view of the LFCSP lead configuration.
Figure 44 shows the bottom view of the LFCSP lead
configuration.
PIN 64
PIN 49
PIN 1
PIN 48
PIN 1 INDICATOR
ADSP-BF592
64-LEAD LFCSP
TOP VIEW
PIN 16
PIN 33
PIN 17
PIN 32
Figure 43. 64-Lead LFCSP Lead Configuration (Top View)
PIN 49
PIN 64
PIN 48
PIN 1
ADSP-BF592
64-LEAD
LFCSP
BOTTOM VIEW
GND PAD
(PIN 65)
PIN 1 INDICATOR
PIN 33
PIN 16
PIN 32
PIN 17
Figure 44. 64-Lead LFCSP Lead Configuration (Bottom View)
Rev. B
| Page 42 of 44 |
July 2013
ADSP-BF592
OUTLINE DIMENSIONS
Dimensions in Figure 45 are shown in millimeters.
0.60 MAX
9.00
BSC SQ
0.60
MAX
48
64
49
1
PIN 1
INDICATOR
PIN 1
INDICATOR
8.75
BSC SQ
TOP VIEW
0.50
BSC
0.50
0.40
0.30
1.00
0.85
0.80
0.80 MAX
0.65 TYP
12° MAX
SEATING
PLANE
0.30
0.23
0.18
33
32
17
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE LEAD ASSIGNMENT AND
SIGNAL DESCRIPTIONS
SECTIONS OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
0.20 REF
Figure 45. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ1]
Very Thin Quad (CP-64-4)
Dimensions shown in millimeters
For information relating to the CP-64-4 package’s exposed pad, see the table endnotes on Page 41.
Rev. B
| Page 43 of 44 |
16
0.25 MIN
7.50
REF
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
1
6.35
6.20 SQ
6.05
EXPOSED PAD
(BOTTOM VIEW)
July 2013
ADSP-BF592
AUTOMOTIVE PRODUCTS
The ADSP-BF592 is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models and designers should review the
product specifications section of this data sheet carefully. Only the automotive grade products shown in Table 35 are available for use in
automotive applications. Contact your local ADI account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.
Table 35. Automotive Products
Model1
ADBF592WYCPZxx
Temperature
Range2
–40ºC to +105ºC
Instruction
Rate (Max)
400 MHz
Package Description
64-Lead LFCSP
Package
Option
CP-64-4
1
Z = RoHS compliant part.
Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 16 for junction temperature (TJ)
specification, which is the only temperature specification.
2
ORDERING GUIDE
Model1, 2
ADSP-BF592KCPZ-2
ADSP-BF592KCPZ
ADSP-BF592BCPZ-2
ADSP-BF592BCPZ
Temperature
Range3
0ºC to +70ºC
0ºC to +70ºC
–40ºC to +85ºC
–40ºC to +85ºC
Instruction
Rate (Max)
200 MHz
400 MHz
200 MHz
400 MHz
Package Description
64-Lead LFCSP
64-Lead LFCSP
64-Lead LFCSP
64-Lead LFCSP
1
Package
Option
CP-64-4
CP-64-4
CP-64-4
CP-64-4
Z = RoHS compliant part.
Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at
www.analog.com /Blackfin.
3
Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 16 for junction temperature (TJ)
specification, which is the only temperature specification.
2
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09574-0-7/13(B)
Rev. B
| Page 44 of 44 |
July 2013