a High Accuracy Ultralow IQ, 500 mA anyCAP® Low Dropout Regulator ADP3335 FEATURES High Accuracy Over Line and Load: ⴞ0.9% @ 25ⴗC, ⴞ1.8% Over Temperature Ultralow Dropout Voltage: 200 mV (Typ) @ 500 mA Requires Only CO = 1.0 F for Stability anyCAP = Stable with Any Type of Capacitor (Including MLCC) Current and Thermal Limiting Low Noise Low Shutdown Current: < 1.0 A 2.6 V to 12 V Supply Range –40ⴗC to +85ⴗC Ambient Temperature Range Ultrasmall Thermally-Enhanced 8-Lead MSOP Package FUNCTIONAL BLOCK DIAGRAM Q1 IN THERMAL PROTECTION NR gm DRIVER R2 SD BANDGAP REF GND NR ADP3335 OUT IN The ADP3335 is a member of the ADP330x family of precision low dropout anyCAP voltage regulators. The ADP3335 operates with an input voltage range of 2.6 V to 12 V and delivers a continuous load current up to 500 mA. The ADP3335 stands out from conventional LDOs with the lowest thermal resistance of any MSOP-8 package and an enhanced process that enables it to offer performance advantages beyond its competition. Its patented design requires only a 1.0 µF output capacitor for stability. This device is insensitive to output capacitor Equivalent Series Resistance (ESR), and is stable with any good quality capacitor, including ceramic (MLCC) types for space-restricted applications. The ADP3335 achieves exceptional accuracy of ± 0.9% at room temperature and ± 1.8% over temperature, line, and load. The dropout voltage of the ADP3335 is only 200 mV (typical) at 500 mA. This device also includes a safety current limit, thermal overload protection and a shutdown feature. In shutdown mode, the ground current is reduced to less than 1 µA. The ADP3335 has ultralow quiescent current 80 µA (typical) in light load situations. R1 CC APPLICATIONS PCMCIA Card Cellular Phones Camcorders, Cameras Networking Systems, DSL/Cable Modems Cable Set-Top Box MP3/CD Players DSP Supply GENERAL DESCRIPTION OUT ADP3335 VIN C IN 1F + IN SD OUT OUT + GND C OUT 1F VOUT ON OFF Figure 1. Typical Application Circuit anyCAP is a registered trademark of Analog Devices Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 ADP3335–SPECIFICATIONS1, 2, 3 (V = 6.0 V, C = C IN IN OUT = 1.0 F, TA = –40ⴗC to +85ⴗC, unless otherwise noted) Parameter Symbol Conditions Min OUTPUT Voltage Accuracy4 VOUT VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA to 500 mA TA = 25°C VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA to 500 mA TA = 85°C VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA to 500 mA TJ = 150°C VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA TA = 25°C IL = 0.1 mA to 500 mA TA = 25°C VOUT = 98% of VOUT(NOM) IL = 500 mA IL = 300 mA IL = 50 mA IL = 0.1 mA VIN = VOUT(NOM) + 1 V f = 10 Hz–100 kHz, CL = 10 µF IL = 500 mA, CNR = 10 nF f = 10 Hz–100 kHz, CL = 10 µF IL = 500 mA, CNR = 0 nF Line Regulation4 Load Regulation Dropout Voltage Peak Load Current Output Noise GROUND CURRENT In Regulation VDROP ILDPK VNOISE IGND In Dropout IGND In Shutdown IGNDSD SHUTDOWN Threshold Voltage SD Input Current Output Current In Shutdown VTHSD ISD IOSD Max Unit –0.9 +0.9 % –1.8 +1.8 % –2.3 +2.3 % 0.04 mV/V 0.04 mV/mA 200 140 30 10 800 47 370 230 110 40 mV mV mV mV mA µV rms µV rms 95 IL = 500 mA IL = 300 mA IL = 50 mA IL = 0.1 mA VIN = VOUT(NOM) – 100 mV IL = 0.1 mA SD = 0 V, VIN = 12 V ON OFF 0 ≤ SD ≤ 5 V TA = 25°C, VIN = 12 V TA = 85°C, VIN = 12 V Typ 4.5 2.6 0.5 80 120 10 6 2.5 110 400 mA mA mA µA µA 0.01 1 µA 1.2 1.2 1.2 0.4 3 5 5 V V µA µA µA 2.0 NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. 2 Ambient temperature of 85°C corresponds to a junction temperature of 125°C under pulsed full load test conditions. 3 Application stable with no load. 4 VIN = 2.6 V to 12 V for models with V OUT(NOM) ≤ 2.2 V. Specifications subject to change without notice. –2– REV. 0 ADP3335 ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V Power Dissipation . . . . . . . . . . . . . . . . . . . Internally Limited Operating Ambient Temperature Range . . . . –40°C to +85°C Operating Junction Temperature Range . . . –40°C to +150°C θJA 2-layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153°C/W θJA 4-layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110°C/W Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C Pin No. Mnemonic Function 1, 2, 3 OUT 4 5 GND NR 6 SD 7, 8 IN *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. Output of the Regulator. Bypass to ground with a 1.0 µF or larger capacitor. All pins must be connected together for proper operation. Ground Pin. Noise Reduction Pin. Used for further reduction of output noise (see text for detail). Capacitor required if COUT > 3.3 µF. Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shutdown is not used, this pin should be connected to the input pin. Regulator Input. All pins must be connected together for proper operation. PIN CONFIGURATION OUT 1 ADP3335 8 IN IN TOP VIEW OUT 3 (Not to Scale) 6 SD OUT 2 7 GND 4 5 NR ORDERING GUIDE Model Output Voltage* Package Option Branding Information ADP3335ARM-1.8 ADP3335ARM-2.5 ADP3335ARM-2.85 ADP3335ARM-3.3 ADP3335ARM-5 1.8 V 2.5 V 2.85 V 3.3 V 5V RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) LFA LFC LFD LFE LFF *Contact the factory for other output voltage options. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3335 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE ADP3335–Typical Performance Characteristics (T = 25ⴗC unless otherwise noted.) A 2.201 2.202 VOUT = 2.2V IL = 0 VOUT = 2.2V VIN = 6V 2.200 2.199 150mA 2.198 2.197 300mA 2.196 2.195 140 IL = 100A 2.199 100 2.198 2.197 2.196 2.195 80 40 20 2.193 2 4 6 8 10 INPUT VOLTAGE – Volts 0 12 Figure 2. Line Regulation Output Voltage vs. Supply Voltage 100 200 300 400 OUTPUT LOAD – mA 0 500 Figure 3. Output Voltage vs. Load Current 0.5 0.4 0.3 0.2 0 –0.3 –0.4 100 200 300 400 OUTPUT LOAD – mA 500mA 0.1 –0.2 0 GROUND CURRENT – mA OUTPUT CHANGE – % GROUND CURRENT – mA 0.6 –0.1 1.0 0 300mA 0.7 2.0 500 500mA 12 IL = 500mA 6 5 300mA 4 3 2 100mA 1 50mA 0 0 0 –40 –15 5 25 45 65 85 105 –40 –15 5 25 45 65 85 105 125 JUNCTION TEMPERATURE – ⴗC 125 JUNCTION TEMPERATURE – ⴗC Figure 5. Ground Current vs. Load Current 4 6 8 10 INPUT VOLTAGE – Volts 8 7 0.8 3.0 2 0 0.9 4.0 0 Figure 4. Ground Current vs. Supply Voltage 1 5.0 IL = 0 60 2.194 500mA 2.194 VOUT = 2.2V 120 GROUND CURRENT – A 2.200 OUTPUT VOLTAGE – Volts OUTPUT VOLTAGE – Volts 2.201 Figure 6. Output Voltage Variation % vs. Junction Temperature Figure 7. Ground Current vs. Junction Temperature 150 100 50 0 VOUT = 2.2V SD = VIN RL = 4.4⍀ 3.0 2.5 2.0 100 200 300 400 OUTPUT LOAD – mA Figure 8. Dropout Voltage vs. Output Current 500 3 2 COUT = 10F 0 1.0 4 0.5 0 2 3 TIME – Sec 4 Figure 9. Power-Up/Power-Down –4– COUT = 1F 1 1.5 1 0 VOUT – Volts 200 VIN – Volts INPUT/OUTPUT VOLTAGE – Volts DROPOUT VOLTAGE – mV 250 VOUT = 2.2V SD = VIN RL = 4.4⍀ 2 0 200 400 600 TIME – s 800 Figure 10. Power–Up Response REV. 0 VOUT = 2.2V RL = 4.4⍀ CL = 1F 2.189 3.500 3.000 40 80 140 TIME – s 2.190 2.179 3.500 Volts Volts 2.1 VOUT = 2.2V RL = 4.4⍀ CL = 10F 400 200 180 200 3 0 2 FULL SHORT 800m⍀ SHORT 800 Figure 13. Load Transient Response 2.2 3 400 600 TIME – s VIN = 6V VOUT = 2.2V RL = 4.4⍀ 1F 1 10F 10F 0 1F 2 1 0 0 200 400 600 TIME – s 800 200 Figure 14. Load Transient Response RIPPLE REJECTION – dB CL = 1F IL = 500mA –40 200 120 IL = 500mA WITHOUT NOISE REDUCTION 100 IL = 500mA WITH NOISE REDUCTION 80 IL = 0mA WITHOUT NOISE REDUCTION 60 40 CL = 10F IL = 50A 1k 10k 100k FREQUENCY – Hz 1M 10M Figure 17. Power Supply Ripple Rejection REV. 0 VOUT = 2.2V IL = 1mA 10 CL = 10F CL = 10F CNR = 10nF CNR = 0 1 CL = 1F CNR = 0 0.1 CL = 1F CNR = 10nF 0.01 20 –90 100 800 Figure 16. Turn On–Turn Off Response 100 –70 10 400 600 TIME – s 140 –60 –80 0 CNR = 10nF CL = 10F IL = 500mA CL = 1F IL = 50A –50 2 800 160 VOUT = 2.2V –30 400 600 TIME – s Figure 15. Short Circuit Current RMS NOISE – V –20 VIN = 4V VSD 200 VOLTAGE NOISE SPECTRAL DENSITY – V/ Hz mA A 400 80 140 TIME – s Figure 12. Line Transient Response 2.3 VIN = 4V VOUT = 2.2⍀ CL = 1F 0 40 2.2 2.1 3.000 180 Figure 11. Line Transient Response 2.2 VOUT = 2.2V RL = 4.4⍀ CL = 10F 2.189 VIN – Volts VIN – Volts 2.179 2.200 VOUT 2.190 2.3 2.210 Volts 2.200 mA 2.210 VOUT – Volts VOUT – Volts ADP3335 0 0 IL = 0mA WITH NOISE REDUCTION 10 20 30 CL – F 40 Figure 18. RMS Noise vs. CL (10 Hz–100 kHz) –5– 50 0.001 10 100 1k 10k 100k FREQUENCY – Hz 1M Figure 19. Output Noise Density ADP3335 With the ADP3335 anyCAP LDO, this is no longer true. It can be used with virtually any good quality capacitor, with no constraint on the minimum ESR. This innovative design allows the circuit to be stable with just a small 1 µF capacitor on the output. Additional advantages of the pole-splitting scheme include superior line noise rejection and very high regulator gain, which leads to excellent line and load regulation. An impressive ± 1.8% accuracy is guaranteed over line, load, and temperature. THEORY OF OPERATION The new anyCAP LDO ADP3335 uses a single control loop for regulation and reference functions. The output voltage is sensed by a resistive voltage divider consisting of R1 and R2 which is varied to provide the available output voltage option. Feedback is taken from this network by way of a series diode (D1) and a second resistor divider (R3 and R4) to the input of an amplifier. INPUT Additional features of the circuit include current limit and thermal shutdown and noise reduction. OUTPUT COMPENSATION CAPACITOR Q1 NONINVERTING WIDEBAND DRIVER gm ATTENUATION (VBANDGAP/VOUT) R3 PTAT VOS R1 D1 (a) R4 PTAT CURRENT ADP3335 APPLICATION INFORMATION Capacitor Selection CLOAD Output Capacitors: as with any micropower device, output transient response is a function of the output capacitance. The ADP3335 is stable with a wide range of capacitor values, types and ESR (anyCAP). A capacitor as low as 1 µF is all that is needed for stability; larger capacitors can be used if high output current surges are anticipated. The ADP3335 is stable with extremely low ESR capacitors (ESR ≈ 0), such as multilayer ceramic capacitors (MLCC) or OSCON. Note that the effective capacitance of some capacitor types may fall below the minimum at cold temperature. Ensure that the capacitor provides more than 1 µF at minimum temperature. RLOAD R2 GND Figure 20. Functional Block Diagram A very high gain error amplifier is used to control this loop. The amplifier is constructed in such a way that equilibrium produces a large, temperature-proportional input ,“offset voltage” that is repeatable and very well controlled. The temperatureproportional offset voltage is combined with the complementary diode voltage to form a “virtual bandgap” voltage, implicit in the network, although it never appears explicitly in the circuit. Ultimately, this patented design makes it possible to control the loop with only one amplifier. This technique also improves the noise characteristics of the amplifier by providing more flexibility on the trade-off of noise sources that leads to a low noise design. Input Bypass Capacitor An input bypass capacitor is not strictly required but is advisable in any application involving long input wires or high source impedance. Connecting a 1 µF capacitor from IN to ground reduces the circuit's sensitivity to PC board layout. If a larger value output capacitor is used, then a larger value input capacitor is also recommended. Noise Reduction The R1, R2 divider is chosen in the same ratio as the bandgap voltage to the output voltage. Although the R1, R2 resistor divider is loaded by the diode D1 and a second divider consisting of R3 and R4, the values can be chosen to produce a temperature stable output. This unique arrangement specifically corrects for the loading of the divider thus avoiding the error resulting from base current loading in conventional circuits. A noise reduction capacitor (CNR) can be used to further reduce the noise by 6 dB–10 dB (Figure 18) low leakage capacitors in 10 pF–500 pF range provide the best performance. Since the noise reduction pin (NR) is internally connected to a high impedance node, any connection to this node should be carefully done to avoid noise pickup from external sources. The pad connected to this pin should be as small as possible and long PC board traces are not recommended. The patented amplifier controls a new and unique noninverting driver that drives the pass transistor, Q1. The use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole-splitting arrangement to achieve reduced sensitivity to the value, type, and ESR of the load capacitance. When adding a noise reduction capacitor, maintain a minimum load current of 1 mA when not in shutdown. Most LDOs place very strict requirements on the range of ESR values for the output capacitor because they are difficult to stabilize due to the uncertainty of load capacitance and resistance. Moreover, the ESR value, required to keep conventional LDOs stable, changes depending on load and temperature. These ESR limitations make designing with LDOs more difficult because of their unclear specifications and extreme variations over temperature. –6– REV. 0 ADP3335 It is important to note that as CNR increases, the turn-on time will be delayed. With NR values greater than 1 nF, this delay may be on the order of several milliseconds. CNR NR OUT OUT IN OUT Device power dissipation is calculated as follows: ( ) ( ) PD = VIN − VOUT I LOAD + VIN IGND Where ILOAD and IGND are load current and ground current, VIN and VOUT are input and output voltages respectively. Assuming ILOAD = 400 mA, IGND = 4 mA, VIN = 5.0 V and VOUT = 3.3 V, device power dissipation is: ADP3335 IN Calculating Junction Temperature PD = (5 – 3.3) 400 mA + 5.0(4 mA) = 700 mW VIN CIN 1F + SD GND + VOUT COUT 1F ON OFF The proprietary package used in the ADP3335 has a thermal resistance of 110°C/W, significantly lower than a standard MSOP-8 package. Assuming a 4-layer board, the junction temperature rise above ambient temperature will be approximately equal to: Figure 21. Typical Application Circuit ∆TJA = 0.700 W × 110°C / W = 77.0°C Paddle-Under-Lead Package The ADP3335 uses a patented paddle-under-lead package design to ensure the best thermal performance in an MSOP-8 footprint. This new package uses an electrically isolated die attach that allows all pins to contribute to heat conduction. This technique reduces the thermal resistance to 110°C/W on a 4-layer board as compared to >160°C/W for a standard MSOP-8 leadframe. Figure 22 shows the standard physical construction of the MSOP-8 and the paddle-under-lead leadframe. DIE Figure 22. Thermally Enhanced Paddle-Under-Lead Package Thermal Overload Protection The ADP3335 is protected against damage from excessive power dissipation by its thermal overload protection circuit which limits the die temperature to a maximum of 165°C. Under extreme conditions (i.e., high ambient temperature and power dissipation) where die temperature starts to rise above 165°C, the output current is reduced until the die temperature has dropped to a safe level. The output current is restored when the die temperature is reduced. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed 150°C. REV. 0 To limit the maximum junction temperature to 150°C, maximum allowable ambient temperature will be: TAMAX = 150°C – 77.0°C = 73.0°C Printed Circuit Board Layout Consideration All surface mount packages rely on the traces of the PC board to conduct heat away from the package. In standard packages the dominant component of the heat resistance path is the plastic between the die attach pad and the individual leads. In typical thermally enhanced packages one or more of the leads are fused to the die attach pad, significantly decreasing this component. To make the improvement meaningful, however, a significant copper area on the PCB must be attached to these fused pins. The patented paddle-under-lead frame design of the ADP3335 uniformly minimizes the value of the dominant portion of the thermal resistance. It ensures that heat is conducted away by all pins of the package. This yields a very low 110°C/W thermal resistance for an MSOP-8 package, without any special board layout requirements, relying only on the normal traces connected to the leads. This yields a 33% improvement in heat dissipation capability as compared to a standard MSOP-8 package. The thermal resistance can be decreased by, approximately, an additional 10% by attaching a few square cm of copper area to the IN pin of the ADP3335 package. It is not recommended to use solder mask or silkscreen on the PCB traces adjacent to the ADP3335’s pins since it will increase the junction-to-ambient thermal resistance of the package. Shutdown Mode Applying a TTL high signal to the shutdown (SD) pin or tying it to the input pin, will turn the output ON. Pulling SD down to 0.4 V or below, or tying it to ground will turn the output OFF. In shutdown mode, quiescent current is reduced to much less than 1 µA. –7– ADP3335 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C3774–5–4/00 (rev. 0) 8-Lead mini_SO (RM-8) 0.122 (3.10) 0.114 (2.90) 8 5 0.199 (5.05) 0.187 (4.75) 0.122 (3.10) 0.114 (2.90) 1 4 PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 0.011 (0.28) 0.003 (0.08) 33ⴗ 27ⴗ 0.028 (0.71) 0.016 (0.41) PRINTED IN U.S.A. 0.006 (0.15) 0.002 (0.05) 0.120 (3.05) 0.112 (2.84) 0.043 (1.09) 0.037 (0.94) –8– REV. 0