ON CM2006-02QR Praetorian l-c lcd and camera emi filter array with esd protection Datasheet

Praetorian® L-C LCD and Camera
EMI Filter Array with ESD Protection
CM2006
Features
Product Description
•
The CM2006 connects between the VGA or DVI-I port
connector and the internal analog or digital flat panel
controller logic. The CM2006 incorporates ESD
protection for all signals, level shifting for the DDC
signals and buffering for the SYNC signals. ESD
protection for the video, DDC and SYNC lines is
implemented with low-capacitance current steering
diodes.
All connector interface pins are designed to safely
handle the high current spikes specified by IEC-610004-2 Level 4 (±8kV contact discharge). The ESD
•
•
•
•
•
•
•
•
•
Includes ESD protection, level-shifting, buffering
and sync impedance matching
VESA VSIS Version 1 Revision 2 compatible
interface
Supports optional NAVI signalling requirements
7 channels of ESD protection for all VGA port
connector pins. All pins meet IEC-61000-4-2 Level
4 ESD requirements (±8kV contact discharge)
Very low loading capacitance from ESD protection
diodes on VIDEO lines (3pF maximum)
Schmitt-triggered input buffers for HSYNC and
VSYNC lines
Bidirectional level shifting N-channel FETs provided
for DDC_CLK and DDC_DATA channels
Backdrive protection on all lines
Compact 16-lead QSOP package
RoHS-compliant, lead-free finishing
Applications
VGA and DVI-I ports in:
• Monitors
• TVs
protection for the DDC, SYNC and VIDEO signal pins is
designed to prevent "backdrive current" when the device
is powered down while connected to a video source that
is powered up.
Separate positive supply rails are provided for the
VIDEO / SYNC signals and DDC signals to facilitate
interfacing with low voltage video controller ICs and
microcontrollers to provide design flexibility in multisupply-voltage environments.
Two Schmitt-triggered non-inverting buffers redrive and
condition the HSYNC and VSYNC signals from the
video connector (SYNC1, SYNC2). These buffers
accept VESA VSIS compliant TTL input signals and
convert them to CMOS output levels that swing between
ground and VCC.
Two N-channel MOSFETs provide the level shifting
function required when the DDC controller or EDID
EEPROM is operated at a lower supply voltage than the
monitor. The gate terminals for these MOSFETS
(VCC_DDC) should be connected to the supply rail (typically
3.3V, 2.5V etc.) that supplies power to the transceivers
of the DDC controller.
The CM1693 is housed in space saving, low profile,
0.40mm pitch uDFN packages in a RoHS compliant,
lead-free format.
©2010 SCILLC. All rights reserved.
May 2010 – Rev. 2
Publication Order Number:
CM2006/D
CM2006
Electrical Schematic
VCC_DDC
VCC
BYP
1
8
11
7
VIDEO_1
VIDEO_2
VIDEO_3
GND
DDC_IN1
DDC_IN2
ENABLE
SYNC_IN1
SYNC_IN2
10
DDC_OUT1
DDC_OUT2
3
4
RT
RT
5
6
16
9
14
GND
12
2
13
15
Rev. 2 | Page 2 of 9 | www.onsemi.com
SYNC_OUT2
SYNC_OUT1
CM2006
PIN DESCRIPTIONS
LEAD(s)
NAME
DESCRIPTION
1
VCC
2
ENABLE
Active high enable. Disables the Sync buffer outputs when low.
3
VIDEO_1
Video signal ESD protection channel. This pin is typically tied one of the video lines between
the controller device and the video connector.
4
VIDEO_2
Video signal ESD protection channel. This pin is typically tied one of the video lines between
the controller device and the video connector.
5
VIDEO_3
Video signal ESD protection channel. This pin is typically tied one of the video lines between
the controller device and the video connector.
6
GND
Ground reference supply pin.
7
VCC_DDC
This is an isolated supply input for the DDC_1 and DDC_2 level-shifting N-FET gates.
8
BYP
9
DDC_IN1
10
DDC_OUT1
DDC signal output. Connects to the monitor DDC logic.
11
DDC_OUT
DDC signal output. Connects to the monitor DDC logic.
12
DDC_IN2
DDC signal input. Connects to the video connector side of one of the DDC lines
13
SYNC_IN1
14
SYNC_OUT1
15
SYNC_IN2
16
SYNC_OUT2
This is a supply input for the SYNC_1 and SYNC_2 level shifters, video protection and the
DDC circuits.
An external 0.22uF bypass capacitor is required on this pin.
DDC signal input. Connects to the video connector side of one of the DDC lines.signal
output.
Sync signal buffer input. Connects to the video connector side of one of the sync lines.
Sync signal buffer output. Connects to the monitor SYNC logic.
Sync signal buffer input. Connects to the video connector side of one of the sync lines.
Sync signal buffer output. Connects to the monitor SYNC logic.
Ordering Information
PART NUMBERING INFORMATION
1
Pins
Package
Ordering Part Number
Part Marking
16
QSOP
CM2006-02QR
CM2006-02QR
Note 1: Parts are shipped in Tape and Reel form unless otherwise specified.
Rev.2 | Page 3 of 9 | www.onsemi.com
CM2006
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNITS
VCC_DDC and VCC Supply Voltage Inputs
[GND - 0.5] to +6.0
V
DC Voltage at Inputs
VIDEO_1, VIDEO_2, VIDEO_3
DDC_IN1, DDC_IN2
DDC_OUT1, DDC_OUT2
SYNC_IN1, SYNC_IN2, ENABLE
[GND - 0.5] to [VCC + 0.5]
[GND - 0.5] to 6.0
[GND - 0.5] to 6.0
[GND - 0.5] to [VCC + 0.5]
V
V
V
V
Operating Temperature Range
-40 to +85
°C
Storage Temperature Range
-40 to +150
°C
500
mW
RATING
UNITS
-40 to +85
°C
5
V
Package Power Rating (TA=25°C)
STANDARD OPERATING CONDITIONS
PARAMETER
Operating Temperature Range
VCC
Rev. 2 | Page 4 of 9 | www.onsemi.com
CM2006
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
SYMBOL PARAMETER
ICC_DDC
ICC
CONDITIONS
10
µA
VCC Supply Current
VCC = 5V; SYNC inputs at GND or VCC;
SYNC outputs unloaded
1
mA
VCC = 5V; SYNC inputs at 3.0V;
SYNC outputs unloaded
2.0
mA
1.0
V
IF = 10mA
VIH
Logic High Input Voltage
VCC = 5.0V; Note 2
VIL
Logic Low Input Voltage
VCC = 5.0V; Note 2
VHYS
Hysteresis Voltage
VCC = 5.0V; Note 2
VOH
Logic High Output Voltage
IOH = 0mA, VCC = 5.0V; Note 2
VOL
Logic Low Output Voltage
IOL = 0mA, VCC = 5.0V; Note 2
ROUT
SYNC Driver Output Resistance
VCC = 5.0V; SYNC Inputs at GND or 3.0V
Input Current
VIDEO Inputs
SYNC_IN1, SYNC_IN2 Inputs
IBACKDRIVE
VON
CIN_VID
MAX UNITS
VCC_DDC = 5.0V
ESD Diode Forward Voltage
IOFF
TYP
VCC_DDC Supply Current
VF
IIN
MIN
Level Shifting N-MOSFET "OFF" State
Leakage Current
2.0
V
0.5
400
V
mV
4.0
V
0.15
V
24
Ω
VCC = 5.0V; VIN = VCC or GND
±10
µA
VCC = 5.0V; VIN = VCC or GND
±10
µA
(VCC_DDC - VDDC_IN) 0.4V; VDDC_OUT = VCC_DDC
10
µA
(VCC_DDC - VDDC_OUT) 0.4V; VDDC_IN = VCC_DDC
10
µA
7
Current conducted from input pins when Vcc VCC < VINPUT_PIN ; Note 5
is powered down.
Voltage Drop Across Level-shifting
N-MOSFET when "ON"
VCC_DDC = 2.5V; VS = GND; IDS = 3mA;
VIDEO Input Capacitance
15
10
µA
0.18
V
VCC = 5.0V; VIN = 2.5V; f = 1MHz
3
pF
VCC = 2.5V; VIN = 1.25V; f = 1MHz
3.5
pF
tPLH
SYNC Driver L => H Propagation Delay
CL = 50pF; VCC = 5.0V; Input tR and tF 5ns
12
ns
tPHL
SYNC Driver H => L Propagation Delay
CL = 50pF; VCC = 5.0V; Input tR and tF 5ns
12
ns
tR, tF
SYNC Driver Output Rise & Fall Times
CL = 50pF; VCC = 5.0V; Input tR and tF 5ns
VESD1
ESD Withstand Voltage, Sync_out pins only VCC = 5V; Notes 3 and 4
±2
kV
VESD
ESD Withstand Voltage
±8
kV
VCC = 5V; Notes 3 and 5
3
ns
Note 1: All parameters specified over standard operating conditions unless otherwise noted.
Note 2: These parameters apply only to the SYNC drivers. Note that ROUT = RT + RBUFFER.
Note 3: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. BYP and VCC must be bypassed to
GND via a low impedance ground plane with a 0.22µF, low inductance, chip ceramic capacitor at each supply pin. ESD
pulse is applied between the applicable pins and GND. ESD pulses can be positive or negative with respect to GND.
Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_IN1, SYNC_IN2, DDC_IN1 and DDC_IN2. All pins are ESD
protected to the industry standard ±2kV Human Body Model (MIL-STD-883, Method 3015).
Note 4: This specification applies to the SYNC_OUT pins only.
Note 5: Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_IN1, SYNC_IN2, DDC_IN1 and DDC_IN2.
Rev.2 | Page 5 of 9 | www.onsemi.com
CM2006
Application Information
Figure 1. Typical Application Connection Diagram
NOTES
1
2
The CM2006 should be placed as close to the VGA or DVI-I connector as possible.
The ESD protection channels VIDEO_1, VIDEO_2, VIDEO_3 may be used interchangeably between the R, G, B
signals.
3 If differential video signal routing is used, the RED, BLUE, and GREEN signal lines should be terminated with external
37.5 ohm resistors.
4 "VF" are external video filters for the RGB signals.
5 Supply bypass capacitors C1 and C2 must be placed immediately adjacent to the corresponding Vcc pins. Connections
to the Vcc pins and ground plane must be made with minimal length copper traces (preferably less than 5mm) for best
ESD protection.
6 The bypass capacitor for the BYP pin has been omitted in this diagram. This results in a reduction in the maximum ESD
withstand voltage at the DDC_OUT pins from ±8kV to ±2kV. If 8kV ESD protection is required, a 0.22µF ceramic
bypass capacitor should be connected between BYP and ground.
7 The SYNC buffers may be used interchangeably between HSYNC and VSYNC.
8 The EMI filters at the SYNC_OUT and DDC_OUT pins (C5 to C12, and Ferrite Beads FB1 to FB4) are for reference
only. The component values and filter configuration may be changed to suit the application.
9 The DDC level shifters DDC_IN, DDC_OUT, may be used interchangeably between DDCA_CLK and DDCA_DATA.
10 R1, R2 are optional. They may be used, if required, to pull the DDC_CLK and DDC_DATA lines to VCC_5V when no
VGA card is connected to the VGA monitor. If used, it should be noted that "back current" may flow between the DDC
pins and VCC_5V via these resistors when VCC_5V is powered down.
Rev. 2 | Page 6 of 9 | www.onsemi.com
CM2006
Mechanical Details
QSOP Mechanical Specifications
CM2006 devices are packaged in 16-pin QSOP packages. Dimensions are presented below.
PACKAGE DIMENSIONS
Package
QSOP (JEDEC name is SSOP)
Pins
16
Dimensions
Millimeters
Inches
Min
Max
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
B
0.20
0.30
0.008
0.012
C
0.18
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
3.81
3.98
0.150
0.157
e
0.64 BSC
0.025 BSC
H
5.79
6.19
0.228
0.244
L
0.40
1.27
0.016
0.050
# per tube
100 pcs*
# per tape
and reel
2500 pcs
Controlling dimension: inches
Package Dimensions for QSOP-16
* This is an approximate number which may vary.
Rev.2 | Page 7 of 9 | www.onsemi.com
CM2006
Tape and Reel Specifications
PART NUMBER
PACKAGE SIZE
(mm)
POCKET SIZE (mm)
B0 X A0 X K0
TAPE WIDTH
W
REEL
DIAMETER
QTY PER
REEL
P0
P1
CM2006
4.90 X 3.89 X 1.55
5.30 X 6.50 X 2.10
12mm
330mm (13")
2500
4mm
8mm
Rev. 2 | Page 8 of 9 | www.onsemi.com
CM2006
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products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising
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parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the
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