TI BQ3060PWR Sbs 1.1-compliant gas gauge and protection with cedv Datasheet

bq3060
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SLUS928A – MARCH 2009 – REVISED NOVEMBER 2009
SBS 1.1-COMPLIANT GAS GAUGE and PROTECTION with CEDV
Check for Samples: bq3060
FEATURES
1
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Advanced CEDV (Compensated
End-of-Discharge Voltage) Gauging
Fully Integrated 2, 3, and 4 Series Li-Ion or
Li-Polymer Cell Battery Pack Manager
8-Bit RISC CPU With Ultra-Low Power Modes
Full Array of Programmable Protection
Features
– Voltage, Current, and Temperature
SHA-1 Authentication
Flexible Memory Architecture With Integrated
Flash Memory
Supports Two-Wire SMBus v1.1 Interface With
High-speed 400kHz Programming Option
P-CH High Side Protection FET Drive
Low Power Consumption Sleep Mode: < 69 μA
High-Accuracy Analog Front End With Two
Independent ADCs
– High-Resolution, 15~22-bit Integrator for
Coulomb Counting
– 16-Bit Delta-Sigma ADC With a 16-Channel
Multiplexer for Voltage, Current, and
Temperature
Ultra Compact Package: 24-Pin TSSOP PW
APPLICATIONS
•
•
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Netbook/Notebook PCs
Medical and Test Equipment
Portable Instruments
DESCRIPTION
The Texas Instruments bq3060 Battery Manager is a
fully integrated, single-chip, pack-based solution that
provides a rich array of features for gas gauging,
protection, and authentication for 2, 3, or 4 series cell
Li-Ion battery packs. With a footprint of merely
7.8mmx6.4mm in a compact 24-pin TSSOP package,
the bq3060 maximizes functionality and safety while
dramatically cutting the solution cost and size for
smart batteries.
Using its integrated high-performance analog
peripherals, the bq3060 measures and maintains an
accurate record of available capacity, voltage,
current, temperature, and other critical parameters in
Li-Ion or Li-Polymer batteries, and reports the
information to the system host controller over an
SMBus 1.1 compatible interface.
The bq3060 provides software-1st level and 2nd level
safety protection on overvoltage, undervoltage,
overtemperature, and overcharge, as well as
hardware-overcurrent in discharge, short circuit in
charge and discharge protection.
Table 1. ORDERING INFORMATION
(1)
AVAILABLE OPTIONS
PACKAGE TSSOP
(PW)
Standard
bq3060PW (1)
The bq3060 can be ordered in tape and reel by adding the suffix R to the orderable part number, i.e.,
bq3060PWR.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
bq3060
SLUS928A – MARCH 2009 – REVISED NOVEMBER 2009
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SYSTEM PARTITIONING DIAGRAM
Pack +
FUSE
SMBD
Fuse Blow &
Detection
Logic
SMBD
SMBC SMBC
ZVCHG
CHG
DSG
PACK BAT
RBI
Pre Charge
FET Drive
Oscillator
P-Channel
FET Drive
Power Mode
Control
VSS
SMB 1.1
System
Control
PRES PRES
AFE HW
Control
Data Flash
Memory
Charging
Algorithm
SHA-1
Authentication
Voltage
Measurement
Over
Temperature
Protection
Temperature
Measurement
TS1
Over- &
UnderVoltage
Protection
CEDV
Gas Gauging
Over
Current
Protection
Coloumb
Counter
TS2
Watchdog
Cell Voltage Mux
& Translation
External Cell
Balancing Driver
VC1
VC1
VDD
VC2
VC2
OUT
VC3
VC3
CD
VC4
VC4
GND
bq294xz
SRN
HW Over
Current &
Short Circuit
Protection
SRP
REG27
Regulator
bq3060
Pack RSNS
5mW –20mW typ.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted) (1)
VMAX
Supply voltage range
VALUE
UNIT
–0.3 to 34
V
VVC2–0.3 to VVC2+8.5 or 34,
whichever is lower
V
VC2
VVC3–0.3 to VVC3+8.5
V
VC3
VVC4–0.3 to VVC4+8.5
V
VC4
VSRP–0.3 to VSRP+8.5
V
–0.3 to VREG27
V
–0.3 to 6.0
V
–0.3 to VREG27 + 0.3
V
CHG, DSG, ZVCHG, FUSE
–0.3 to BAT
V
RBI, REG27
–0.3 to 2.75
V
50
mA
PACK w.r.t. Vss
VC1, BAT
VIN
Input voltage range
SRP, SRN
SMBD, SMBC
TS1, TS2, /PRES
VO
Output voltage range
ISS
Maximum combined sink current for input pins
TFUNC
Functional temperature
–40 to 110
°C
TSTG
Storage temperature range
–65 to 150
°C
(1)
2
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
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SLUS928A – MARCH 2009 – REVISED NOVEMBER 2009
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage
BAT
VSTARTUP
Start up voltage at PACK
Vshutdown
VPACK or VBAT, whichever is higher
VIN
Input voltage range
25
3.8
3
Operating temperature
5.5
V
3.3
V
V
VVC3
VVC3+5
VC3
VVC4
VVC4+5
VC4
VSRP
VSRP+5
5
25
–0.3
1
85
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V
μF
1
–40
Copyright © 2009, Texas Instruments Incorporated
V
3.2
VC2
0
UNIT
5.2
VVC2+5
SRP to SRN
External 2.7V REG capacitor
VVC2+5
VVC2
PACK
TOPR
MAX
VC1, BAT
VCn – VC(n+1), (n=1, 2, 3, 4 )
CREG27
TYP
PACK
°C
3
bq3060
SLUS928A – MARCH 2009 – REVISED NOVEMBER 2009
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PIN DETAILS
TSSOP (PW)
(TOP VIEW)
BAT
DSG
VC1
VC2
VC3
VC4
SRP
SRN
TS1
TS2
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PACK
CHG
ZVCHG
FUSE
REG27
VSS
RBI
PRES
SMBC
NC
SMBD
NC
Table 2. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BAT
1
P
Power input from battery
DSG
2
O
P-CH FET Drive controlling discharge
VC1
3
IA
Sense voltage input terminal and external cell balancing drive output for most positive cell, and
battery stack measurement input.
VC2
4
IA
Sense voltage input terminal and external cell balancing drive output for second most positive
cell.
VC3
5
IA
Sense voltage input terminal and external cell balancing drive output for third most positive cell.
VC4
6
IA
Sense voltage input terminal and external cell balancing drive output for least positive cell.
SRP
7
IA
Analog input pin connected to the internal coulomb-counter peripheral for integrating a small
voltage between SRP and SRN where SRP is the top of the sense resistor.
SRN
8
IA
Analog input pin connected to the internal coulomb-counter peripheral for integrating a small
voltage between SRP and SRN where SRN is the bottom of the sense resistor.
TS1
9
I/O,IA
Thermistor input TS1
TS2
10
I/O,IA
Thermistor input TS2
NC
11
-
Keep this pin floating
NC
12
-
Keep this pin floating
NC
13
-
Keep this pin floating
SMBD
14
I/OD
NC
15
-
SMBC
16
I/OD
SMBus clock pin
PRES
17
I/OD
Active low input to sense system insertion and typically requires additional ESD protection
RBI
18
P
RAM backup pin to provide backup potential to the internal DATA RAM if power is momentarily
lost by using a capacitor attached between RBI and VSS
VSS
19
P
Device ground
REG27
20
P
Internal power supply 2.7V bias output
FUSE
21
I/OD
ZVCHG
22
O
P-CH precharge FET Drive controlling pre-charge and zero-volt charge
CHG
23
O
P-CH FET Drive controlling charge
PACK
24
P
PACK positive terminal and alternative power source
4
SMBus data pin
Keep this pin floating
Push-pull fuse drive and secondary protector activation input sensing
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SLUS928A – MARCH 2009 – REVISED NOVEMBER 2009
ELECTRICAL SPECIFICATIONS
GENERAL PURPOSE I/O
Typical values stated where TA = 25°C and VBAT=VPACK= 14.4V, Min/Max values stated where TA = –40°C to 85°C and
VBAT=VPACK= 3.8V to 25V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
2
VIH
High-level input voltage
/PRES, SMBD, SMBC, TS1, TS2
VIL
Low-level input voltage
/PRES, SMBD, SMBC, TS1, TS2
VOH
Output voltage high
/PRES, SMBD, SMBC, TS1, TS2, IL = –0.5
mA
VOH(FUSE)
High level fuse output
tR(FUSE)
FUSE output rise time
ZO(FUSE)
FUSE output impedance
VFUSE_DET
FUSE detect input voltage
VOL
Low-level output voltage
CIN
Input capacitance
Ilkg
Input leakage current
/PRES, SMBD, SMBC, TS1, TS2
SMBD and SMBC pull-down disabled
RPD(SMBx)
SMBD and SMBC pull-down
TA = –40°C to 100°C
RPAD
Pad resistance
TS1, TS2
TYP
MAX
UNIT
V
0.8
V
VREG27–0.5
VBAT = 3.8 V to 9 V, CL = 1 nF
VBAT = 9 V to 25 V, CL = 1nF
V
3
VBAT–0.3
8.6
7.5
8
9
CL = 1 nF,
VOH(FUSE) = 0 V to 5 V
0.8
V
10
μs
2
6
kΩ
2
3.2
/PRES, SMBD, SMBC, TS1, TS2, IL = 7 mA
V
0.4
V
5
600
pF
1
μA
950
1300
kΩ
87
110
Ω
SUPPLY CURRENT
PARAMETER
TEST CONDITION
MAX
UNIT
μA
69
μA
Discharge FET ON, Charge FET OFF ([NR]=1, [NRCHG]=0)
66
μA
Discharge FET OFF, Charge FET OFF ([NR]=0, System not
present)
61
μA
TA = –40°C to 110°C
0.5
1
Firmware running, no flash writes
ISLEEP
Sleep mode
Shutdown mode
TYP
Discharge FET ON, Charge FET ON ([NR]=1, [NRCHG]=1)
Normal mode
ISHUTDOWN
MIN
441
ICC
μA
REG27 POWER ON RESET
MIN
TYP
MAX
UNIT
VREG27IT–
Negative-going voltage input
PARAMETER
At REG27
TEST CONDITIONS
2.22
2.35
2.34
V
VREG27IT+
Positive-going voltage input
At REG27
2.25
2.5
2.6
V
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INTERNAL LDO
PARAMETER
TEST CONDITIONS
VREG
Regulator output voltage
IREG27 = 10 mA
TA = –40°C to 85°C
ΔV(REGTEMP)
Regulator output change
with temperature
IREG = 10 mA
TA = –40°C to 85°C
ΔV(REGLINE)
Line regulation
IREG = 10 mA
ΔV(REGLOAD)
Load regulation
IREG = 0.2 to 10 mA
I(REGMAX)
Current limit
MIN
TYP
MAX
UNIT
2.5
2.7
2.75
V
±0.5%
±2
±4
mV
±20
±40
mV
50
mA
25
SRx WAKE FROM SLEEP
PARAMETER
VWAKE_ACR
TEST CONDITION
Accuracy of VWAKE
MIN
TYP
MAX
VWAKE = 1.2 mV
0.2
1.2
2
VWAKE = 2.4 mV
0.4
2.4
3.6
2
5
6.8
5.3
10
13
VWAKE = 5 mV
VWAKE = 10 mV
VWAKE_TCO
Temperature drift of VWAKE accuracy
0.5
tWAKE
Time from application of current and wake of bq3060
0.2
UNIT
mV
%/°C
1
ms
COULOMB COUNTER
PARAMETER
TEST CONDITION
Input voltage range
MIN
TYP
-0.20
0.25
Conversion time
Single conversion
Effective resolution
Single conversion
Integral nonlinearity
TA = –25°C to 85°C
±0.007
TA = –25°C to 85°C
10
Offset error
(1)
250
–0.8%
(1)
(2)
V
Bits
±0.034
%FSR
0.3
0.5
μV/°C
0.2%
0.8%
Full-scale error drift
μV
150
Effective input resistance
UNIT
ms
15
Offset error drift
Full-scale error (2)
MAX
2.5
PPM/°C
MΩ
Post Calibration Performance
Uncalibrated performance. This gain error can be eliminated with external calibration.
ADC
PARAMETER
TEST CONDITION
Input voltage range
MIN
TYP
–0.2
Conversion time
0.8×VREG27
31.5
Resolution (no missing codes)
16
Effective resolution
14
70
Offset error drift
Full-scale error
VIN = 1 V
–0.8%
6
160
±0.2%
8
%FSR
μV
μV/°C
0.4%
150
Effective input resistance
(1)
Bits
1
Full –scale error drift
V
Bits
±0.020
(1)
UNIT
ms
15
Integral nonlinearity
Offset error
MAX
PPM/°C
MΩ
Channel to channel offset
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SLUS928A – MARCH 2009 – REVISED NOVEMBER 2009
EXTERNAL CELL BALANCE DRIVE
PARAMETER
TEST CONDITIONS
MIN
Cell balance ON for VC1, VCi-VCi+1 = 4V, where i = 1~4
RBAL_drive
TYP
MAX
UNIT
5.7
Internal pull-down
Cell balance ON for VC2, VCi-VCi+1 = 4V, where = i = 1~4
resistance for external
Cell balance ON for VC3, VCi-VCi+1 = 4V, where = i = 1~4
cell balance
Cell balance ON for VC4, VCi-VCi+1 = 4V, where = i = 1~4
3.7
kΩ
1.75
0.85
CELL VOLTAGE MONITOR
PARAMETER
CELL Voltage Measurement Accuracy
(1)
TEST CONDITIONS
(1)
MIN
TYP
MAX
UNIT
TA = –10°C to 60°C
±10
±20
mV
TA = –40°C to 85°C
±10
±35
TYP
MAX
This is the performance expected for non-calibrated device.
INTERNAL TEMPERATURE SENSOR
PARAMETER
T(TEMP)
TEST CONDITIONS
MIN
Temperature sensor accuracy
UNIT
±3%
°C
THERMISTOR MEASUREMENT SUPPORT
PARAMETER
RERR
Internal resistor drift
R
Internal resistor
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–230
TS1, TS2
ppm/°C
17
20
kΩ
INTERNAL THERMAL SHUTDOWN
PARAMETER (1)
TMAX
Maximum REG27 temperature
TRECOVER
Recovery hysteresis temperature
(1)
TEST CONDITIONS
MIN
TYP
125
MAX
UNIT
175
°C
10
°C
Parameters assured by design. Not production tested.
HIGH FREQUENCY OSCILLATOR
PARAMETER
f(OSC)
f(EIO)
Frequency error (1)
t(SXO)
Start-up time (2)
(1)
(2)
TEST CONDITIONS
MIN
Operating frequency of CPU clock
TYP
MAX
UNIT
2.097
MHz
TA = –20°C to 70°C
–2%
±0.25%
2%
TA = –40°C to 85°C
–3%
±0.25%
3%
3
6
TA = –25°C to 85°C
ms
The frequency drift is included and measured from the trimmed frequency at VBAT = VPACK = 14.4 V, TA = 25°C
The startup time is defined as the time it takes for the oscillator output frequency to be ±3% when the device is already powered.
LOW FREQUENCY OSCILLATOR
PARAMETER
f(LOSC)
Operating frequency
f(LEIO)
Frequency error (1)
t(LSXO)
Start-up time (2)
(1)
(2)
TEST CONDITIONS
MIN
TYP
MAX
32.768
MHz
TA = –20°C to 70°C
–1.5%
±0.25%
1.5%
TA = –40°C to 85°C
–2.5%
±0.25%
2.5%
TA = –25°C to 85°C
UNIT
100
ms
The frequency drift is included and measured from the trimmed frequency at VBAT = VPACK = 14.4 V, TA = 25°C.
The startup time is defined as the time it takes for the oscillator output frequency to be ±3%.
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FLASH
PARAMETER (1)
TEST CONDITIONS
MIN
Data retention
Flash programming write-cycles
t(ROWPROG)
Row programming time
t(MASSERASE)
t(PAGEERASE)
ICC(PROG)
Flash-write supply current
ICC(ERASE)
Flash-erase supply current
(1)
TYP
MAX
10
UNIT
Years
20k
Cycles
2
ms
Mass-erase time
250
ms
Page-erase time
25
ms
4
6
mA
TA = –40°C to 0°C
8
22
TA = 0°C to 85°C
3
15
mA
Specified by design. Not production tested
RAM BACKUP
I(RBI)
PARAMETER
TEST CONDITIONS
RBI data-retention input current
VRBI > V(RBI)MIN, VREG27 < VREG27IT-, TA =
70°C to 110°C
MIN
TYP
MAX
UNIT
20
1500
nA
VRBI > V(RBI)MIN, VREG27 < VREG27IT-, TA =
–40°C to 70°C
RBI data-retention voltage (1)
V(RBI)
(1)
500
1
V
Specified by design. Not production tested.
CURRENT PROTECTION THRESHOLDS
PARAMETER
TEST CONDITIONS
V(OCD)
OCD detection threshold voltage range, typical
ΔV(OCDT)
OCD detection threshold voltage program step
V(SCCT)
SCC detection threshold voltage range, typical
ΔV(SCCT)
SCC detection threshold voltage program step
V(SCDT)
SCD detection threshold voltage range, typical
ΔV(SCDT)
SCD detection threshold voltage program step
V(OFFSET)
SCD, SCC and OCD offset
V(Scale_Err)
SCD, SCC and OCD scale error
8
MIN
TYP
MAX
RSNS = 0
50
200
RSNS = 1
25
100
RSNS = 0
10
RSNS = 1
5
RSNS = 0
RSNS = 1
RSNS = 0
RSNS is set in
STATE_CTL
register
–300
–50
–225
-50
RSNS = 0
100
450
RSNS = 1
50
225
50
RSNS = 1
25
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mV
mV
-25
RSNS = 0
mV
mV
–100
RSNS = 1
UNIT
mV
mV
–10
10
–10%
10%
mV
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SLUS928A – MARCH 2009 – REVISED NOVEMBER 2009
CURRENT PROTECTION TIMING
PARAMETER
TEST CONDITIONS
t(OCDD)
Overcurrent in discharge delay
t(OCDD_STEP)
OCDD step options
MIN
TYP
1
MAX
31
2
t(SCDD)
Short circuit in discharge delay
t(SCDD_STEP)
SCDD step options
t(SCCD)
Short circuit in charge delay
t(SCCD_STEP)
SCCD step options
0
915
AFE.STATE_CNTL[SCDDx2] = 1
0
1830
61
AFE.STATE_CNTL[SCDDx2] = 1
122
0
t(DETECT)
Current fault detect time
915
tACC
Overcurrent and short circuit
delay time accuracy
35
μs
μs
μs
μs
61
VSRP-SRN = VTHRESH + 12.5 mV,
TA = –40°C to 85°C
ms
ms
AFE.STATE_CNTL[SCDDx2] = 0
AFE.STATE_CNTL[SCDDx2] = 0
UNIT
160
Accuracy of typical delay time with WDI active
–20%
20%
Accuracy of typical delay time with no WDI
input
–50%
50%
TEST CONDITIONS
μs
P-CH FET DRIVE
PARAMETER
VO(FETON)
VO(FETOFF)
Output voltage, charge
and discharge FETs on
Output voltage, charge
and discharge FETs off
MIN
TYP
MAX
VO(FETONDSG) = V(BAT)–V(DSG), RGS = 1MΩ,
TA = –40°C to 110°C, BAT = 20 V (1)
12
15
18
VO(FETONCHG) = V(PACK)–V(CHG), RGS =1MΩ,
TA = –40°C to 110°C, PACK = 20 V (1)
12
15
18
VO(FETOFFDSG) = V(BAT)–V(DSG),
TA = –40°C to 110°C, BAT = 16 V
0.2
VO(FETOFFCHG) = V(PACK)–V(CHG),
TA = –40°C to 110°C, PACK = 16 V
0.2
tr
Rise time
CL = 4700 pF
tf
Fall time
CL = 4700 pF
(1)
VDSG: 10% to 90%
70
200
VCHG: 10% to 90%
70
200
VDSG : 90% to 10%
70
200
VCHG: 90% to 10%
70
200
UNIT
V
V
μs
μs
For a VBAT or VPACK input range of 3.8 V to 25 V, MIN VO(FETON) voltage is 12V or V(BAT)–1V, whichever is less.
PRE-CHARGE/ZVCHG FET DRIVE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
12
15
18
V
VBAT–0.5
V
200
μs
V(PreCHGON)
VO(PreCHGON) = V(PACK)–V(ZVCHG),
pre-charge FET on (1)
RGS =1 MΩ, TA = –40°C to 110°C
V(PreCHGOFF)
Output voltage, pre-charge FET
off (1)
RGS =1 MΩ, TA = –40°C to 110°C
tr
Rise time
CL = 4700 pF,
RG = 5.1 kΩ
VZVCHG: 10% to 90%
80
tf
Fall time
CL = 4700 pF,
RG = 5.1 kΩ
VZVCHG : 90% to 10%
1.7
(1)
UNIT
ms
For a VBAT or VPACK input range of 3.8 V to 25 V, MIN V(PreCHGON) voltage is 12 V or V(BAT)–1V, whichever is less.
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SMBus
PARAMETER
TEST CONDITIONS
MIN
TYP
UNIT
100
kHz
SMBus operating frequency
Slave mode, SMBC 50% duty cycle
fMAS
SMBus master clock frequency
Master mode, no clock low slave extend
tBUF
Bus free time between start and stop
4.7
μs
tHD:STA
Hold time after (repeated) start
4.0
μs
tSU:STA
Repeated start setup time
4.7
μs
tSU:STO
Stop setup time
4.0
μs
tHD:DAT
Data hold time
tSU:DAT
Data setup time
0
Transmit mode
300
Error signal/detect
Clock low period
tHIGH
Clock high period
See
(2)
tLOW:SEXT
Cumulative clock low slave extend time
See
tLOW:MEXT
Cumulative clock low master extend
time
tF
Clock/data fall time
(3)
(4)
(5)
(6)
kHz
ns
250
See
(1)
tLOW
(1)
(2)
51.2
Receive mode
tTIMEOUT
tR
10
MAX
fSMB
ns
25
35
Clock/data rise time
ms
μs
4.7
50
μs
(3)
25
ms
See
(4)
10
ms
See
(5)
300
ns
See
(6)
1000
ns
4.0
The bq3060 times out when any clock low exceeds tTIMEOUT
tHIGH, Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 μs causes reset of any transaction involving bq3060 that is in
progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0). If NC_SMB is set then
the timeout is disabled.
tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
Rise time tR = VILMAX – 0.15) to (VIHMIN + 0.15)
Fall time tF = 0.9VDD to (VILMAX – 0.15)
Timing Measurement Intervals
t LOW
tR
tF
t HD:STA
SCLK
t SU:STA
t HIGH
t HD:STA
t HD:DAT
t SU:STO
t SU:DAT
SDATA
t BUF
P
S
S
P
t TIMEOUT Measurement Intervals
Start
Stop
t LOW:SEXT
SCLK ACK1
t LOW:MEXT
SCLK ACK1
t LOW:MEXT
t LOW:MEXT
SCLK
SDATA
(1)
10
SCLKACK is the acknowledge-related clock pulse generated by the master.
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bq3060
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SLUS928A – MARCH 2009 – REVISED NOVEMBER 2009
SMBus XL
PARAMETER
fSMBXL
SMBus XL operating frequency
tBUF
Bus free time between start and stop
tHD:STA
Hold time after (repeated) start
tSU:STA
Repeated start setup time
tSU:STO
Stop setup time
tTIMEOUT
Error signal/detect
tLOW
Clock low period
tHIGH
Clock high period
(1)
(2)
TEST CONDITIONS
Slave mode
MIN
40
TYP
MAX
UNIT
400
kHz
4.7
μs
4
μs
4.7
μs
μs
4
See
(1)
See
(2)
25
35
ms
1
1
μs
1
2
μs
The bq3060 times out when any clock low exceeds tTIMEOUT
tHIGH, Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 μs causes reset of any transaction involving bq3060 that is in
progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0). If NC_SMB is set then
the timeout is disabled.
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11
bq3060
SLUS928A – MARCH 2009 – REVISED NOVEMBER 2009
www.ti.com
FEATURE SET
Primary (1st Level) Safety Features
The bq3060 supports a wide range of battery and system protection features that can easily be configured. The
primary safety features include:
•
•
•
•
•
Cell over/undervoltage protection
Charge and discharge overcurrent
Short circuit
Charge and discharge overtemperature
AFE Watchdog
Secondary (2nd Level) Safety Features
The secondary safety features of the bq3060 can be used to indicate more serious faults via the FUSE (pin 21).
This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging and
discharging. This pin is also used as an input to sense the state of the fuse. The secondary safety protection
features include:
•
•
•
•
•
•
•
•
•
Safety overvoltage
Safety overcurrent in charge and discharge
Safety overtemperature in charge and discharge
Charge FET and Zero-Volt Charge FET fault
Discharge FET fault
Cell imbalance detection
Fuse blow by a secondary voltage protection IC
AFE register integrity fault (AFE_P)
AFE communication fault (AFE_C)
Charge Control Features
The bq3060 charge control features include:
•
•
•
•
•
•
•
Supports JEITA temperature ranges. Reports charging voltage and charging current according to the active
temperature range.
Handles more complex charging profiles. Allows for splitting the standard temperature range into 2
sub-ranges and allows for varying the charging current according to the cell voltage.
Reports the appropriate charging current needed for constant current charging and the appropriate charging
voltage needed for constant voltage charging to a smart charger using SMBus broadcasts.
Reduce the charge difference of the battery cells in fully charged state of the battery pack gradually using a
voltage-based cell balancing algorithm during charging. A voltage threshold can be set up for cell balancing to
be active. This prevents fully charged cells from overcharging and causing excessive degradation and also
increases the usable pack energy by preventing premature charge termination
Supports pre-charging/zero-volt charging
Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range
Reports charging fault and also indicate charge status via charge and discharge alarms.
Gas Gauging
The bq3060 uses advanced CEDV (Compensated End-of-Discharge Voltage) technology to measure and
calculate the available capacity in battery cells. The bq3060 accumulates a measure of charge and discharge
currents and compensates the charge current measurement for temperature and state-of-charge of the battery.
The bq3060 estimates self-discharge of the battery and also adjusts the self-discharge estimation based on
temperature.
See bq3060 Technical Reference(SLUU319) for further details.
12
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bq3060
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SLUS928A – MARCH 2009 – REVISED NOVEMBER 2009
Lifetime Data Logging Features
The bq3060 offers limited lifetime data logging for the following critical battery parameters for analysis purposes:
• Lifetime maximum temperature
• Lifetime minimum temperature
• Lifetime maximum battery cell voltage
• Lifetime minimum battery cell voltage
Authentication
The bq3060 supports authentication by the host using SHA-1.
Power Modes
The bq3060 supports 3 different power modes to reduce power consumption:
•
•
•
In Normal Mode, the bq3060 performs measurements, calculations, protection decisions and data updates in
1 second intervals. Between these intervals, the bq3060 is in a reduced power stage.
In Sleep Mode, the bq3060 performs measurements, calculations, protection decisions and data update in
adjustable time intervals. Between these intervals, the bq3060 is in a reduced power stage. The bq3060 has
a wake function that enables exit from Sleep mode, when current flow or failure is detected.
In Shutdown Mode the bq3060 is completely disabled.
Configuration
Oscillator Function
The bq3060 fully integrates the system oscillators. Therefore the bq3060 requires no external components for
this feature.
System Present Operation
The bq3060 checks the PRES pin periodically (1 second). If PRES input is pulled to ground by external system,
the bq3060 detects the presence of the system.
2-, 3-, or 4-Cell Configuration
In a 2-cell configuration, VC1 is shorted to VC2 and VC3. In a 3-cell configuration, VC1 is shorted to VC2.
Cell Balance Control
If cell balancing is required, the bq3060 cell balance control allows a weak, internal pull-down for each VCx pin.
The purpose of this weak pull-down is to enable an external FET for current bypass. Series resistors placed
between the input VCx pins and the positive battery cell terminals control the VGS of the external FET. See
bq3060 Cell balancing using external MOSFET (SLUA509) for more details.
Battery Parameter Measurements
The bq3060 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a
second delta-sigma ADC for individual cell and battery voltage, and temperature measurement.
Charge and Discharge Counting
The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage
drop across a small-value sense resistor between the SR1 and SR2 pins. The integrating ADC measures bipolar
signals from -0.20 V to 0.25 V. The bq3060 detects charge activity when VSR = V(SRP)- V(SRN)is positive, and
discharge activity when VSR = V(SRP) - V(SRN) is negative. The bq3060 continuously integrates the signal over
time, using an internal counter. The fundamental rate of the counter is 0.65 nVh.
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13
bq3060
SLUS928A – MARCH 2009 – REVISED NOVEMBER 2009
www.ti.com
Voltage
The bq3060 updates the individual series cell voltages at one second intervals. The internal ADC of the bq3060
measures the voltage, scales, and offsets, and calibrates it appropriately. To ensure an accurate differential
voltage sensing, the IC ground should be connected directly to the most negative terminal of the battery stack,
not to the positive side of the sense resistor. This minimizes the voltage drop across the PCB trace.
Voltage Calibration and Accuracy
The bq3060 is calibrated for voltage prior to shipping from TI. The bq3060 voltage measurement signal chain
(ADC, high voltage translation, circuit interconnect) will be calibrated for each cell. The external filter resistors,
connected from each cell to the VCx input of the bq3060, are required to be 1kΩ. The accuracy of the
factory-calibrated devices is +/- 10mV per cell at room temperature at 4V cell voltage. Without any customer
voltage calibration, this is the level of accuracy expected as long as the filter resistor value is 1kΩ. If better
voltage accuracy is desired, customer voltage calibration is required. An application note on calibrating and
programming the bq3060 is available in the product web folder. See Data Flash Programming and Calibrating the
bq3060 Gas Gauge(SLUA502) for more details.
Current
The bq3060 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge current
using a 5 mΩ to 20 mΩ typ. sense resistor.
Auto Calibration
The bq3060 can automatically calibrate its offset between the A to D converter and the output of the high voltage
translation circuit. Also, the bq3060 provides an auto-calibration for the coulomb counter to cancel the voltage
offset error across SRN and SRP for maximum charge measurement accuracy. The bq3060 performs
auto-calibration when the SMBus lines stay low continuously for a minimum of 5 s.
Temperature
The bq3060 has an internal temperature sensor and inputs for 2 external temperature sensor inputs TS1 and
TS2 used in conjunction with two identical NTC thermistors (default is Semitec 103AT) to sense the battery cell
temperature. The bq3060 can be configured to use internal or up to 2 external temperature sensors.
Communications
The bq3060 uses SMBus v1.1 with Master Mode and package error checking (PEC) options per the SBS
specification.
SMBus On and Off State
The bq3060 detects an SMBus off state when SMBC and SMBD are logic-low for ≥ 2 seconds. Clearing this
state requires either SMBC or SMBD to transition high. Within 1 ms, the communication bus is available.
SBS Commands
See bq3060 Technical Reference(SLUU319) for further details.
Spacer
REVISION HISTORY
Changes from Original (March 2009) to Revision A
•
14
Page
Changed Device From: Product Preview To: Production ..................................................................................................... 1
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Oct-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
BQ3060PW
PREVIEW
TSSOP
PW
24
60
TBD
Call TI
Call TI
BQ3060PWR
PREVIEW
TSSOP
PW
24
2000
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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