Altera EN5329QI 2a powersoc low profile synchronous buck dc-dc converter with integrated inductor Datasheet

Enpirion® Power Datasheet
EN5329QI 2A PowerSoC
Low Profile Synchronous Buck DC-DC
Converter with Integrated Inductor
Description
Features
The EN5329QI is a highly integrated, low profile,
highly efficient, 2A synchronous buck power system
on a chip (PowerSoCTM). The device features an
advance integrated inductor, integrated MOSFETs, a
PWM voltage-mode controller, and internal
compensation providing the smallest possible solution
size.
The EN5329QI is a member of the EN53x9QI family
of pin compatible and interchangeable devices. The
pin compatibility enables an easy to use scalable
family of products covering the load range from 1.5A
up to 3A in a low profile 4mm x 6mm x 1.1mm QFN
package.
The EN5329QI operates at high switching frequency
and allows for the use of tiny MLCC capacitors. It also
enables a very wide control loop bandwidth providing
excellent transient performance and reduced output
impedance. The internal compensation is designed
for unconditional stability across all operating
conditions.
Altera’s Enpirion integrated inductor solution
significantly helps to reduce noise. The complete
power converter solution enhances productivity by
offering greatly simplified board design, layout and
manufacturing requirements. Altera’s Enpirion
products are RoHS compliant and lead-free
manufacturing environment compatible.
• Integrated Inductor
• Solution Footprint as Small as 50 mm2
• Low Profile, 1.1mm
• High Reliability Solution: 42,000 Years MTBF
• High Efficiency, up to 95 %
• Low Output Ripple Voltage; <5mVP-P Typical
• 2.4 V to 5.5 V Input Voltage Range
• 2A Continuous Output Current Capability
• Pin Compatible w/ EN5319 1.5A and EN5339 3A
• Output Enable and Power OK Signal
• Under Voltage Lockout, Over Current, Short Circuit,
and Thermal Protection
• RoHS Compliant; Halogen Free; 260°C Reflow
Applications
• Applications with Low Profile Requirement such as
SSD and Embedded Computing
• SAN/NAS Accelerator Appliances
• FPGA, ASSP, PLD, ASIC, and Processors Noise
Sensitive Applications
Efficiency vs. Output Current
100
100k
90
POK
VOUT
COUT
PVIN
TST0
TST1
CIN
22µF
EN5329QI Ca
TST2
PGND
AVIN
1µF
EFFICIENCY (%)
ENABLE POK
VIN
VOUT
AGND
Ra
VFB
PGND
2x 22µF
or
1x 47µF
Rb
80
70
60
50
Actual Solution Size
50mm2
CONDITIONS
VIN = 3.3V
40
30
VOUT = 2.5V
20
VOUT = 1.2V
10
0
0
Figure 1. Simplified Applications Circuit
2
Figure 2. Highest Efficiency in Smallest Solution Size
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1.5
OUTPUT CURRENT (A)
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Rev B
EN5329QI
Ordering Information
Part Number
EN5329QI
EVB-EN5329QI
Package Markings
EN5329
EN5329
Temp Rating (°C)
-40 to +85
Package Description
24-pin (4mm x 6mm x 1.1mm) QFN T&R
QFN Evaluation Board
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Pin Assignments (Top View)
NC(SW)
NC(SW)
NC(SW)
NC(SW)
PVIN
PVIN
ENABLE
POK
24
23
22
21
20
19
18
17
Keep-Out
NC(SW) 1
PGND 2
25
PGND
16 AVIN
15 AGND
26
PGND
PGND 3
14 VFB
Keep-Out
VOUT 4
10
11
12
TST1
TST0
PGND
9
TST2
8
PGND
7
VOUT
VOUT
6
VOUT
5
13 NC
Figure 3: Pin Out Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Grey area highlights exposed metal on the bottom of the package that is not to be mechanically or electrically
connected to the PCB. There should be no traces on PCB top layer under these keep out areas.
NOTE C: White ‘dot’ on top left is pin 1 indicator on top of the device package.
Pin Description
PIN
NAME
1, 21-24
NC(SW)
2-3, 8-9
PGND
4-7
VOUT
10
11
TST2
TST1
FUNCTION
NO CONNECT: These pins are internally connected to the common switching node of the
internal MOSFETs. They must be soldered to PCB but not be electrically connected to any
external signal, ground, or voltage. Failure to follow this guideline may result in device
damage.
Input and output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. See VOUT, PVIN descriptions and Layout Recommendation for more
details.
Regulated converter output. Connect to the load and place output filter capacitor(s) between
these pins and PGND pins 8 and 9. See layout recommendation for details
Test Pin. For Altera internal use only. Connect to AVIN at all times.
Test Pin. For Altera internal use only. Connect to AVIN at all times.
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PIN
12
NAME
TST0
13
NC
14
VFB
15
AGND
16
AVIN
17
POK
18
ENABLE
19-20
PVIN
25,26
PGND
FUNCTION
Test Pin. For Altera internal use only. Connect to AVIN at all times.
NO CONNECT: This pin must be soldered to PCB but not electrically connected to any other
pin or to any external signal, voltage, or ground. This pin may be connected internally. Failure
to follow this guideline may result in device damage.
This is the external feedback input pin. A resistor divider connects from the output to AGND.
The mid-point of the resistor divider is connected to VFB. A feed-forward capacitor is required
parallel to the upper feedback resistor (RA). The output voltage regulation is based on the
VFB node voltage equal to 0.600V.
The quiet ground for the control circuits. Connect to the ground plane with a via right next to
the pin.
Analog input voltage for the control circuits. Connect this pin to the input power supply (PVIN)
at a quiet point. Decouple with a 1uF capacitor to AGND.
POK is an open drain output. Refer to Power OK section for details. Leave POK open if
unused.
Output Enable. A logic high level on this pin enables the output and initiates a soft-start. A
logic low signal disables the output and discharges the output to GND. This pin must not be
left floating.
Input power supply. Connect to input power supply and place input filter capacitor(s) between
these pins and PGND pins 2 to 3.
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heatsinking purposes. See Layout Recommendation section.
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Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating
conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
PARAMETER
SYMBOL
MIN
MAX
UNITS
Voltages on : PVIN, AVIN, VOUT
-0.3
6.5
V
Voltages on: ENABLE, POK, TST0, TST1, TST2
-0.3
VIN+0.3
V
Voltages on: VFB
-0.3
2.7
V
-65
150
°C
150
°C
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
260
°C
ESD Rating (Human Body Model)
2000
V
ESD Rating (Charge Device Model)
500
V
Storage Temperature Range
TSTG
Maximum Operating Junction Temperature
TJ-ABS Max
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
VIN
2.4
5.5
V
Output Voltage Range (Note 1)
VOUT
0.6
VIN – VDO
V
Output Current
IOUT
0
2
A
Operating Ambient Temperature
TA
-40
+85
°C
Operating Junction Temperature
TJ
-40
+125
°C
Input Voltage Range
Thermal Characteristics
PARAMETER
SYMBOL
TYP
UNITS
Thermal Resistance: Junction to Ambient (0 LFM) (Note 2)
θJA
36
°C/W
Thermal Resistance: Junction to Case (0 LFM)
θJC
6
°C/W
Thermal Shutdown
TSD
150
°C
Thermal Shutdown Hysteresis
TSDH
15
°C
Note 1: VDO (dropout voltage) is defined as (ILOAD x Dropout Resistance). Please see Electrical Characteristics Table.
Note 2: Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for
high thermal conductivity boards.
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Electrical Characteristics
NOTE: VIN = 5V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted.
Typical values are at TA = 25°C.
PARAMETER
Operating Input Voltage
Feedback Node Initial
Accuracy
Output Variation (Note 3)
(Line, Load, Temperature)
VFB, ENABLE, TST0/1/2
Pin Input Current (Note 4)
Shutdown Current
Under Voltage Lock-out –
VIN Rising
Under Voltage Lock-out –
tVIN Falling
Soft-start Time
SYMBOL
VIN
VVFB
VOUT
VUVLOR
VUVLOF
TEST CONDITIONS
TA = 25°C; VIN = 5V
ILOAD = 100 mA
2.4V ≤ VIN ≤ 5.5V
0 ≤ ILOAD ≤ 2A
ENABLE Low
Voltage Above Which UVLO is
Not Asserted
Voltage Below Which UVLO is
Asserted
Time from Enable High (Note 4)
MIN
2.4
0.588
Output Ripple Voltage
Logic Low
Logic High
VOUT Rising
VOUT Falling
ISINK = 1 mA
0.91
2.4V ≤ VIN ≤ 5.5V
3.5
FOSC
COUT = 2 x 22 µF 0603 X5R
MLCC, VOUT = 3.3 V, ILOAD = 2A
COUT = 2 x 22 µF 0603 X5R
MLCC, VOUT = 1.8 V, ILOAD = 2A
MAX
5.5
UNITS
V
0.612
V
+3
%
+/-40
nA
20
µA
2.2
V
2.1
V
1.40
1.89
ms
150
300
mΩ
0.4
VIN
V
0.0
1.4
POK High
VRIPPLE
0.600
-3
Dropout Resistance
ENABLE Voltage
Threshold
POK Threshold
POK Threshold
POK Low Voltage
POK Pin VOH Leakage
Current
Current Limit Threshold
Operating Frequency
TYP
92
90
0.15
0.4
%
%
V
0.5
2
µA
5
3.2
A
MHz
5
mVP-P
5
mVP-P
Note 3: Output voltage variation is based on using 0.1% accuracy resistor values.
Note 4: Parameter not production tested but is guaranteed by design.
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Typical Performance Curves
Efficiency vs. Output Current
100
90
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs. Output Current
100
70
60
50
VOUT = 2.5V
40
VOUT = 1.8V
30
VOUT = 1.2V
20
CONDITIONS
VIN = 3.3V
VOUT = 1.0V
10
0
70
60
50
VOUT = 3.3V
40
VOUT = 2.5V
30
VOUT = 1.8V
20
VOUT = 1.2V
10
VOUT = 1.0V
0
0
0.5
1.5
1
2
0
OUTPUT CURRENT (A)
1.5
2
3.36
IOUT = 1A
3.5
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1
Output Voltage vs. Output Current
Dropout Voltage
IOUT = 2A
3.4
3.3
3.2
3.1
3
CONDITIONS
VOUT = 3.3V
2.9
2.8
VOUT = 3.3V
3.34
3.32
3.3
3.28
CONDITIONS
VIN = 5V
3.26
3.24
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4
0
0.5
1
1.5
INPUT VOLTAGE(V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
Output Voltage vs. Output Current
2.56
2
1.86
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
0.5
OUTPUT CURRENT (A)
3.6
VOUT = 2.5V
2.54
2.52
2.5
2.48
CONDITIONS
VIN = 5V
2.46
2.44
VOUT = 1.8V
1.84
1.82
1.8
1.78
CONDITIONS
VIN = 5V
1.76
1.74
0
0.5
1
1.5
2
0
OUTPUT CURRENT (A)
0.5
1
1.5
2
OUTPUT CURRENT (A)
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CONDITIONS
VIN = 5V
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Rev B
EN5329QI
Typical Performance Curves (Continued)
Output Voltage vs. Output Current
Output Voltage vs. Output Current
2.56
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.26
VOUT = 1.2V
1.24
1.22
1.2
1.18
CONDITIONS
VIN = 5V
1.16
VOUT = 2.5V
2.54
2.52
2.5
2.48
CONDITIONS
VIN = 3.3V
2.46
2.44
1.14
0
0.5
1
1.5
0
2
0.5
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2
1.26
VOUT = 1.8V
1.84
1.82
1.8
1.78
CONDITIONS
VIN = 3.3V
1.76
VOUT = 1.2V
1.24
1.22
1.2
1.18
CONDITIONS
VIN = 3.3V
1.16
1.74
1.14
0
0.5
1
1.5
2
0
0.5
OUTPUT CURRENT (A)
1.815
1.815
OUTPUT VOLTAGE (V)
1.820
1.810
1.805
1.800
1.795
CONDITIONS
Load = 5mA
1.785
1.5
2
Output Voltage vs. Input Voltage
1.820
1.790
1
OUTPUT CURRENT (A)
Output Voltage vs. Input Voltage
OUTPUT VOLTAGE (V)
1.5
Output Voltage vs. Output Current
Output Voltage vs. Output Current
1.86
1.810
1.805
1.800
1.795
1.790
CONDITIONS
Load = 500mA
1.785
1.780
1.780
2.5
3.1
3.7
4.3
INPUT VOLTAGE (V)
4.9
2.5
5.5
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OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
December 3, 2013
3.1
3.7
4.3
INPUT VOLTAGE (V)
4.9
5.5
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Rev B
EN5329QI
Typical Performance Curves (Continued)
Output Voltage vs. Input Voltage
1.820
1.815
1.815
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
1.820
1.810
1.805
1.800
1.795
1.790
CONDITIONS
Load = 1A
1.785
1.810
1.805
1.800
1.795
1.790
CONDITIONS
Load = 2A
1.785
1.780
1.780
2.5
3.1
4.3
3.7
INPUT VOLTAGE (V)
4.9
5.5
2.5
1.840
1.030
1.830
1.020
1.010
1.000
0.990
0.980
LOAD = 2A
0.970
LOAD = 100mA
CONDITIONS
VIN = 5V
VOUT_NOM = 1.0V
5.5
1.810
1.800
1.790
1.780
1.770
LOAD = 100mA
CONDITIONS
VIN = 5V
VOUT_NOM = 1.8V
1.760
-40
-15
10
35
60
AMBIENT TEMPERATURE (°C)
85
-40
GUARANTEED OUTPUT CURRENT (A)
3.5
3
2.5
2
1.5
1
CONDITIONS
Conditions
VIN
VIN
==
5.0V
5.0V
= 1.0V
= 3.3V
VOUT
VOUT
0.5
0
-40
-15
10
35
60
AMBIENT TEMPERATURE(°C)
-15
10
35
60
AMBIENT TEMPERATURE (°C)
85
No Thermal Derating
No Thermal Derating
GUARANTEED OUTPUT CURRENT (A)
4.9
1.820
LOAD = 2A
0.960
85
3.5
3
2.5
2
1.5
1
CONDITIONS
Conditions
VIN
VIN
==
5.0V
5.0V
= 3.3V
= 3.3V
VOUT
VOUT
0.5
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4.3
INPUT VOLTAGE (V)
Output Voltage vs. Temperature
1.040
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Output Voltage vs. Temperature
3.1
December 3, 2013
0
-40
-15
10
35
60
AMBIENT TEMPERATURE(°C)
85
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Rev B
EN5329QI
Typical Performance Characteristics (Continued)
Output Ripple at 20MHz
Output Ripple at 20MHz
VOUT
(AC Coupled)
VOUT
(AC Coupled)
CONDITIONS
VIN = 3.3V
VOUT = 1.8V
IOUT = 2A
CIN = 1x 22µF (0805)
COUT = 2 x 22µF (0603)
CONDITIONS
VIN = 5V
VOUT = 3.3V
IOUT = 2A
CIN = 1x 22µF (0805)
COUT = 2 x 22µF (0603)
Output Ripple at 500MHz
Output Ripple at 500MHz
VOUT
(AC Coupled)
VOUT
(AC Coupled)
CONDITIONS
VIN = 3.3V
VOUT = 1.8V
IOUT = 2A
CIN = 1x 22µF (0805)
COUT = 2 x 22µF (0603)
CONDITIONS
VIN = 5V
VOUT = 3.3V
IOUT = 2A
CIN = 1x 22µF (0805)
COUT = 2 x 22µF (0603)
Startup Waveforms at 2A
Startup Waveforms at 0A
ENABLE
ENABLE
VOUT
VOUT
POK
POK
LOAD
LOAD
VIN = 5V, VOUT = 1.8V
CIN = 1 X 22µF (0805), COUT = 2 x 22µF (0603), IOUT = 0A
VIN = 5V, VOUT = 1.8V
CIN = 1 X 22µF (0805), COUT = 2 x 22µF (0603), IOUT = 2A
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Typical Performance Characteristics (Continued)
Load Transient from 0 to 2A
Load Transient from 0 to 1A
VOUT
(AC Coupled)
VOUT
(AC Coupled)
CONDITIONS
VIN = 3.3V
VOUT = 1.8V
CIN = 1 X 22µF (0805)
COUT = 2 x 22µF (0603)
CONDITIONS
VIN = 3.3V
VOUT = 1.8V
CIN = 1 X 22µF (0805)
COUT = 2 x 22µF (0603)
LOAD
LOAD
Load Transient from 0 to 1A
Load Transient from 0 to 2A
VOUT
(AC Coupled)
VOUT
(AC Coupled)
CONDITIONS
VIN = 5V
VOUT = 2.5V
CIN = 1 X 22µF (0805)
COUT = 2 x 22µF (0603)
LOAD
LOAD
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CONDITIONS
VIN = 5V
VOUT = 2.5V
CIN = 1 X 22µF (0805)
COUT = 2 x 22µF (0603)
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Rev B
EN5329QI
Functional Block Diagram
PVIN
POK
UVLO
POK
Thermal Limit
Current Limit
ENABLE
NC
(SW)
Soft Start
P-Drive
Logic
(-)
VOUT
PWM
Comp
(+)
N-Drive
PGND
Sawtooth
Generator
Compensation
Network
VFB
(-)
Error
Amp
(+)
DAC
VREF
BIAS
Package Boundary
TST
AVIN
AGND
Figure 4: Functional Block Diagram
Functional Description
impedance and excellent load transient response.
The EN5329QI features include Power OK, under
voltage lockout (UVLO), over current protection,
short circuit protection, and thermal overload
protection.
Overview
The EN5329QI is a highly integrated synchronous
buck converter with an internal inductor utilizing
advanced CMOS technology to provide high
switching frequency, while also maintaining high
efficiency. The EN5329QI is a high power density
device packaged in a tiny 4x6x1.1mm 24-pin QFN
package. Its high switching frequency allows for the
use of very small MLCC input and output filter
capacitors and results in a total solution size as
small as 50mm2.
The EN5329QI is a member of a family of pin
compatible devices. This offers scalability for
applications where load currents may not be known
apriori, and/or speeds time to market with a
convenient common solution footprint.
The EN5329QI buck converter uses Type III
voltage mode control to provide pin-point output
voltage accuracy, high noise immunity, low output
Stability and Compensation
The EN5329QI utilizes an internal compensation
network that is designed to provide stable operation
over a wide range of operating conditions. The
output compensation circuit may be customized to
improve transient performance or reduce output
voltage ripple with dynamic loads.
Soft-Start
The EN5329QI has an internal soft-start circuit that
controls the ramp of the output voltage. The control
circuitry limits the VOUT ramp rate to levels that are
safe for the Power MOSFETs and the integrated
inductor.
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on the ENABLE pin will initiate the converter to start
the soft-start cycle and regulate the output voltage
to the desired value. A logic low will allow the
device to discharge the output and go into
shutdown mode for minimal power consumption.
When the output is discharged, an auxiliary NFET
turns on and limits the discharge current to 300 mA
or below. The ENABLE pin should not be left
floating.
The EN5329QI has a constant startup up time
which is independent of the VOUT setting. The
output rising slew rate is proportional to the output
voltage. The startup time is approximately 1.4ms
from when the ENABLE is first pulled high until
VOUT reaches the regulated voltage level.
Excess bulk capacitance on the output of the
device can cause an over-current condition at
startup. Since the slew rate varies with the output
voltage setting, the maximum capacitance is a
function of the VOUT setting.
The maximum capacitance on the output power
rail, including the output filter capacitors and all
decoupling and bulk capacitors on the supply rail is
given by:
Thermal Shutdown
When excessive power is dissipated in the device,
its junction temperature rises. Once the junction
temperature exceeds the thermal shutdown
temperature of 150°C, the thermal shutdown circuit
turns off the converter, allowing the device to cool.
When the junction temperature drops 15°C, the
device will be re-enabled and go through a normal
startup process.
COUT_TOTAL_MAX [µF] = 3.41x103 / VOUT
NOTE: The above number and formula assume a
no load condition at startup.
Power OK
Over Current/Short Circuit Protection
When an over current condition occurs, VOUT is
pulled low and the device disables switching
internally. This condition is maintained for a period
of 1.2 ms and then a normal soft-start cycle is
initiated. If the over current condition still persists,
this cycle will repeat.
The Power OK (POK) feature is an open drain
output signal used to indicate if the output voltage
is within 92% of the set value. Within this range, the
POK output is allowed to be pulled high. Outside
this range, the POK output is maintained low.
During transitions such as power up and power
down, the POK output will not change state until the
transition is complete for enhanced noise immunity.
Under Voltage Lockout
The POK has 1mA sink capability. When POK is
pulled high, the worst case pin leakage current is
as low as 500nA over temperature. This allows a
large pull up resistor such as 100kΩ to be used for
minimal current consumption in shutdown mode.
The POK output can also be conveniently used as
an enable input of the next stage for power
sequencing of multiple converters.
An under voltage lockout circuit will hold off
switching during initial power up until the input
voltage reaches sufficient level to ensure proper
operation. If the voltage drops below the UVLO
threshold the lockout circuitry will again disable
switching. Hysteresis is included to prevent
chattering between UVLO high and low states.
Enable
The ENABLE pin provides means to shut down the
converter or initiate normal operation. A logic high
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Application Information
temperature. Therefore, they are not suitable for
switch-mode DC-DC converter filtering, and must
be avoided.
Setting the Output Voltage
The EN5329 uses a simple and flexible resistor
divider network to program the output voltage. A
feed-forward capacitor (Ca) is used to ensure the
stability of the converter. Table 3 shows the
required critical component values as a function of
VOUT. It is recommended to use 1% or better
feedback resistors to ensure output voltage
accuracy. The Ra resistor value is fixed at 348k as
shown in Table 3. Based on that value, the bottom
resistor Rb can be calculated below as:
Rb =
Table 1: Recommended Input Capacitors
The VOUT is the nominal output voltage. The Rb
and Ra resistors have the same units based on the
above equation.
100k
POK
VIN
CIN
22µF
EN5329QI Ca
AVIN
1µF
AGND
22µF, 10V,
X5R, 0805
Murata
GRM21BR61A226ME51
In some rare applications modifications to the
compensation may be required. The EN5329QI
provides the capability to modify the control loop
response to allow for customization for specific
applications. For more information, contact Power
Applications support.
COUT
TST2
PGND
P/N
LMK212BBJ226MG-T
VOUT
VOUT
PVIN
TST0
TST1
MFG
Taiyo Yuden
Output Filter Capacitor Selection
The EN5329QI output capacitor selection may be
determined based on two configurations. Table 3
provides
the
allowed
output
capacitor
configurations based on operating conditions. For
lower output ripple, choose 2 x 22µF for the output
capacitors. For smaller solution size, use one 47µF
output capacitor. Table 2 shows the recommended
type and brand of output capacitors to use. For
details regarding other configurations, contact
Power
Applications
support
(www.altera.com/mysupport).
Ra× 0.6 V
VOUT − 0.6 V
ENABLE POK
Description
Ra
VFB
PGND
2x 22µF
or
1x 47µF
Rb
Table 2: Recommended Output Capacitors
Figure 5. Typical Application Circuit.
(NOTE: Enable can be separated from PVIN if the
application requires it)
AVIN Filter Capacitor
A 1.0 µF, 10V, 0402 MLCC capacitor should be
placed between AVIN and AGND as close to the
pins as possible. This will provide high frequency
bypass to ensure clean chip supply for optimal
performance.
MFG
P/N
47µF, 6.3V,
X5R, 0805
Taiyo Yuden
JMK212BBJ476MG-T
Murata
GRM21BR60J476ME15
22µF, 6.3V,
X5R, 805
Taiyo Yuden
JMK212ABJ226MG
Murata
GRM21BR60J226ME39
Murata
GRM188R60J226MEA0
22µF, 6.3V,
X5R, 0603
Table 3. Required Critical Components
(Note: Follow Layout Recommendations)
Input Filter Capacitor Selection
A single 22µF, 0805 MLCC capacitor is needed on
PVIN for all applications. Connect the input
capacitor between PVIN and PGND as close to the
pins as possible. Placement of the input capacitor
is critical to ensure low noise and EMI.
Low ESR MLCC capacitors with X5R or X7R or
equivalent dielectric should be used for the input
capacitors. Y5V or equivalent dielectrics lose too
much capacitance with frequency, DC bias, and
VOUT (V)
Ca (pF)
Vout ≤ 2.5V
8.2
2.5V < Vout ≤ 3.3V
6.8
Vout ≤ 2.5V
8.2
2.5V < Vout ≤ 3.3V
6.8
Vout ≤ 2.5V
8.2
2.5V < Vout ≤ 3.3V
6.8
Vout > 3.3V
6.8
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Ra (kΩ)
Cout (µF)
348
1x47uF/0805
348
2x22uF/0603
348
2x22uF/0805
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Rev B
EN5329QI
Power Up/Down Sequencing
During power-up, ENABLE should not be asserted
before PVIN, and PVIN should not be asserted
before AVIN. The PVIN should never be powered
when AVIN is off. During power down, the AVIN
should not be powered down before PVIN. Tying
PVIN and AVIN or all three pins (AVIN, PVIN,
ENABLE) together during power up or power down
meets these requirements.
Pre-Bias Start-up
The EN5329QI does not support startup into a prebiased condition. Be sure the output capacitors are
not charged or the output of the EN5329QI is not
pre-biased when the EN5329QI is first enabled.
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Thermal Considerations
For VIN = 5V, VOUT = 3.3V at 2A, η ≈ 92%
η = POUT / PIN = 92% = 0.92
Thermal considerations are important power supply
design facts that cannot be avoided in the real
world. Whenever there are power losses in a
system, the heat that is generated needs to be
accounted for. Altera’s Enpirion PowerSoCTM helps
alleviate some of those concerns.
Altera’s Enpirion EN5329QI DC-DC converter is
packaged in a 4x6x1.1mm 24-pin QFN package.
The QFN package is constructed with exposed
thermal pads on the bottom of the package. The
exposed thermal pad should be soldered directly on
to a copper ground pad on the printed circuit board
(PCB) to act as a heat sink. The recommended
maximum junction temperature for continuous
operation is 125°C. Continuous operation above
125°C may reduce long-term reliability. The device
has a thermal overload protection circuit designed
to turn off the device at an approximate junction
temperature value of 150°C.
The EN5329QI is guaranteed to support the full 2A
output current up to 85°C ambient temperature.
The following example and calculations illustrate
the thermal performance of the EN5329QI.
Example:
PIN = POUT / η
PIN ≈ 6.6W / 0.92 ≈ 7.2W
The power dissipation (PD ) is the power loss in the
system and can be calculated by subtracting the
output power from the input power.
PD = PIN – POUT
≈ 7.2W – 6.6W ≈ 0.6W
With the power dissipation known, the temperature
rise in the device may be estimated based on the
theta JA value (θJA). The θJA parameter estimates
how much the temperature will rise in the device for
every watt of power dissipation. The EN5329QI has
a θJA value of 36 ºC/W without airflow.
Determine the change in die temperature (ΔT)
based on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 0.6W x 36°C/W = 21.6°C ≈ 22°C
VOUT = 3.3V
The junction temperature (T J ) of the device is
approximately the ambient temperature (T A) plus
the change in temperature. We assume the initial
ambient temperature to be 25°C.
IOUT = 2A
T J = T A + ΔT
First calculate the output power.
T J ≈ 25°C + 22°C ≈ 47°C
POUT = 3.3V x 2A = 6.6W
The maximum operating junction temperature
(T JMAX) of the device is 125°C, so the device can
operate at a higher ambient temperature. The
maximum ambient temperature (T AMAX) allowed can
be calculated.
VIN = 5V
Next, determine the input power based on the
efficiency (η) shown in Figure 6.
100
90
T AMAX = T JMAX – PD x θJA
EFFICIENCY (%)
80
≈ 125°C – 22°C ≈ 103°C
~92%
70
60
The ambient temperature can actually rise by
another 78°C, bringing it to 103°C before the
device will reach T JMAX. This indicates that the
EN5329QI can support the full 2A output current
range up to approximately 103°C ambient
temperature given the input and output voltage
conditions. Note that the efficiency will be slightly
lower at higher temperatures and these calculations
are estimates.
50
40
30
20
CONDITIONS
VIN = 5V
VOUT = 3.3V
10
0
0
0.5
1
1.5
2
OUTPUT CURRENT (A)
Figure 6: Efficiency vs. Output Current
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Engineering Schematic
Figure 7. Engineering Schematic with Critical Components
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Layout Recommendations
ground plane through as many vias as possible.
The drill diameter of the vias should be 0.33mm,
and the vias must have at least 1 oz. copper plating
on the inside wall, making the finished hole size
around 0.20-0.26mm. Do not use thermal reliefs or
spokes to connect the vias to the ground plane.
This connection provides the path for heat
dissipation from the converter.
Recommendation 4: Multiple small vias (the same
size as the thermal vias discussed in
recommendation 3) should be used to connect
ground terminal of the input capacitor and output
capacitors to the system ground plane. It is
preferred to put these vias along the edge of the
GND copper closest to the +V copper. These vias
connect the input/output filter capacitors to the
GND plane, and help reduce parasitic inductances
in the input and output current loops.
Recommendation 5: AVIN is the power supply for
the small-signal control circuits. It should be
connected to the input voltage at a quiet point. In
Figure 8 this connection is made at the input
capacitor. Place a 1µF capacitor from the AVIN pin
to AGND right next to device pins.
Recommendation 6: The layer 1 metal under the
device must not be more than shown in Figure 8.
See the section regarding exposed metal on bottom
of package. As with any switch-mode DC/DC
converter, try not to run sensitive signal or control
lines underneath the converter package on other
layers.
Recommendation 7: The VOUT sense point should
be just after the last output filter capacitor. Keep the
sense trace short in order to avoid noise coupling
into the node.
Recommendation 8: Keep RA, CA, RB close to the
VFB pin (See Figures 6). The VFB pin is a highimpedance, sensitive node. Keep the trace to this
pin as short as possible. Whenever possible,
connect RB directly to the AGND pin instead of
going through the GND plane.
Recommendation 9: Altera provides schematic
and layout reviews for all customer designs. Please
contact local sales representatives for references to
Power
Applications
support
(www.altera.com/mysupport).
Figure 8. Optimized Layout Recommendations
This layout only shows the critical components
and top layer traces for minimum footprint with
ENABLE as a separate signal. Alternate
ENABLE configurations & the POK pin need to
be connected and routed according to
customer application. Please see the Gerber
files at www.altera.com/enpirion for details on
all layer.
Recommendation 1: Input and output filter
capacitors should be placed on the same side of
the PCB, and as close to the EN5329QI package
as possible. They should be connected to the
device with very short and wide traces. Do not use
thermal reliefs or spokes when connecting the
capacitor pads to the respective nodes. The +V and
GND traces between the capacitors and the
EN5329QI should be as close to each other as
possible so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 2: The system ground plane
should be the first layer immediately below the
surface layer. This ground plane should be
continuous and un-interrupted below the converter
and the input/output capacitors.
Recommendation 3: The thermal pad underneath
the component must be connected to the system
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Design Considerations for Lead-Frame Based Modules
Exposed Metal Pads on Package Bottom
QFN lead-frame based package technology utilizes exposed metal pads on the bottom of the package that
provide improved thermal dissipation, lower package thermal resistance, smaller package footprint and
thickness, larger lead size and pitch, and excellent lead co-planarity. As the EN5329 package is a fully
integrated module consisting of multiple internal devices, the lead-frame provides circuit interconnection and
mechanical support of these devices resulting in multiple exposed metal pads on the package bottom.
Only the two large thermal pads and the perimeter leads are to be mechanically/electrically connected to the
PCB through a SMT soldering process. All other exposed metal is to remain free of any interconnection to the
PCB. Figure 9 shows the recommended PCB metal layout for the EN5329 package. A GND pad with a solder
mask "bridge" to separate into two pads and 24 signal pads are to be used to match the metal on the package.
The PCB should be clear of any other metal, including traces, vias, etc., under the package to avoid electrical
shorting.
The Solder Stencil Aperture should be smaller than the PCB ground pad. This will prevent excess solder from
causing bridging between adjacent pins or other exposed metal under the package. Please consult EN5329QI
Soldering Guidelines for more details and recommendations.
Figure 9. Recommended Footprint for PCB (Top View)
Note: Grey area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.
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Recommended PCB Footprint
Figure 10. EN5329 PCB Footprint (Top View)
The solder stencil aperture for the thermal pads (shown in blue) is based on Altera’s manufacturing recommendations
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Package Mechanical
Figure 11. EN5329QI Package Dimensions (Bottom View)
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS,
QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other
countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's
standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera.
Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders
for products or services.
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