ams AS3658D-BCTP Power and audio management unit for portable device Datasheet

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ams AG
The technical content of this austriamicrosystems datasheet is still valid.
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Tel: +43 (0) 3136 500 0
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AS3658
D a ta S h e e t C o n f i d e n t i a l
P o w e r a n d A u d i o M a n a g e m e n t U n i t f o r P o r ta b l e D e v i c e s
System Control
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2 Key Features
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The AS3658 is highly integrated power and audio
management unit. The AS3658 is designed to include
sophisticated audio features like high performance
audio DAC and ADC. It has several analog and digital
audio interface which are explained in detail in the
following sections. The AS3658 is an integrated solution
for power supply generation and monitoring, battery
management including charging.
- High Current (1.0A) Linear Charger with external
pass transistor (no step down charger)
- 0.1 Ω Battery switch for start-up and trickle charge
- Integrated USB charger up to 880mA (can be used
as wall adapter charger); current accuracy 440500mA for USB specification, in-circuit trimmable
(±1.2% trimsteps)
- Autonomous Battery Temperature Supervision
(0ºC-45ºC or 0ºC- 50ºC) for 10k and 100k NTC
- Charging Timeout (1h-8h in 30min steps)
- Charging in Stanby mode
- Completely Autonomous (no SW)
Power Management Features
lv
1 General Description
- Serial Control Interface
- On/Off Control Module with Boot-ROM / GPIO
- Reset Generation for system controller
- Programmable Interrupt Controller and Watchdog
- Low power off mode (9µA; 2.5V LDO on)
- 88 bit unique ID or Boot fuse array
- Reset with long ON-Keypress (SW-Interuptable)
- Touchscreen Interface (10 bit, interrupt)
Supply Voltage Generation
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- 2 RF Programmable Low Noise LDOs (250mA) (1
LDO can be a current controlled switch for hotplug
(200mA ± 40%))
- 1 RF Programmable Low Noise LDO (400mA)
- 4 Programmable Dig. Low Power LDOs(200mA)
- 2 General Purpose PWM DC/DC step up converter
with three programmable current sinks (e.g. forwhite led); for current mode feedback is automatically slected (DCDC_CURR1,2,3)
- 3 General Purpose high efficiency DC/DC step
down converter (DCDC 1 support DVM)
- 1 Low noise charge pump with 5V output voltage
- 1 Ultra Low Power 2.5V LDO (always on)
Current sinks
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- 4 programmable(8-bit) from 0.15mA to 38.25mA
(±5% ) optional useable as GPIOs
- 3 programmable high voltage (15V) (8-bit) from
0.15mA to 38.25mA (±5% )
- internal PWM generator (extended time range)
(can control DCDC_CURR1,2,3)
10-bit 40µs Successive Approximation ADC
- Two external Inputs (ADC_IN1, ADC_IN2)
Battery Management
- Wide Battery Supply Range 3.0…5.5V
- On-Chip Bandgap Tuning for High Accuracy (±1%)
- Thermal and Current Protection (int. sensor)
- Standby Mode exit by interrupt e.g. Onkey/RTC
Audio
-
94dB Audio DAC, 16-48kHz sampling rate
Two Digital Audio Inputs (2 x I2S interface)
2.9V low Noise LDO for Audio DAC
Two Headphone Amplifier Output with GND
separation
- Two I2S Inputs and one I2S Output
- I2S master mode with programmable sample rate
(controlled by internal PLL)
- GND Buffer for Headphone Amplifier
- Line/ Headphone outputs with GND separation
- Audio ADC, 82dB SNR with 16ksps
- Microphone Bias Supply and Amplifier (mono)
- 5 Band Adjustable Audio Equalizer (± 12dB in 3dB
gain steps)
- SPDIF Output
- Audio Mixer and Gain Stages
- PCM Interface
Real Time Clock (RTC)
- Alarm and Time function
- Repeated Wakeup (every second or minute)
- 32kHz output
- Backup Battery Charger and Switchover
Programmable System clock
- 1.6 MHz to 2.3 MHz with 100 kHz steps
Package
- BGA124 8x8mm, 0.5mm pitch (can be assembled
without micro via boards)
- Full featured chemistry independent step down
charger with Gas Gauge and Current limitation
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Revision 1v13
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AS3658
Data Sheet Confidential
- Applications
3 Applications
The AS3658 is ideal for PDA, PMP, GPS-Navigation Systems and 1 Cell Li+ or 3 Cell NiMH powered devices.
Figure 1. Blockdiagram AS3658
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Revision 1v13
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Data Sheet Confidential
- Applications
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Figure 2. Application Diagram
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AS3658
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AS3658
Data Sheet Confidential
- Applications
Table of Contents
1 General Description
..............................................................................................................................1
2 Key Features
.........................................................................................................................................1
3 Applications
...........................................................................................................................................2
4 Pin Assignments
................................................................................................................................... 6
5 Absolute Maximum ratings
6 Electrical Characteristics
..................................................................................................................12
.....................................................................................................................13
7 Typical Operating Characteristics
.......................................................................................................14
8 Detailed Description-Power Management Functions
8.1 Step Up DC/DC Converters
8.2 Current Sinks
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...............................................................................................................................................7
..........................................................................15
.........................................................................................................................15
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4.1 Pin Description
...............................................................................................................................................25
8.3 General Purpose Input / Output (CURR1_GPIO1 … CURR4_GPIO4)
8.4 Backup Battery Charger
.......................................................30
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..............................................................................................................................38
8.5 Smooth switchover Power Management Overview
8.6 Battery switch SINT (Vsupply, Battery)
8.7 External Step Down/Linear Charger
8.8 USB Charger
.....................................................................................41
........................................................................................................42
............................................................................................................44
...............................................................................................................................................48
8.9 Battery Charge Controller
............................................................................................................................51
8.10 Charger supervision functions
...................................................................................................................63
8.11 Step Down DC/DC Converters
...................................................................................................................67
8.12 Low Dropout Regulators (LDO)
.................................................................................................................78
8.13 5V Charge Pump
.......................................................................................................................................85
9 Detailed Description- Audio Functions
9.1 Audio Paths
................................................................................................87
.................................................................................................................................................87
9.2 Common mode voltage generation of HP_CM, LINE_CM
9.3 Audio Setup Registers
...........................................................................89
.................................................................................................................................90
9.4 ADC, DAC and Digital Audio Input
...............................................................................................................91
9.5 I2S master mode and PCM Mode
...............................................................................................................95
.....................................................................................................................................................98
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9.6 Line Input
9.7 Five Band Equalizer
9.8 Microphone Input
....................................................................................................................................99
......................................................................................................................................105
....................................................................................................................................108
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9.9 Audio Output Mixer
9.10 Line Output
.............................................................................................................................................109
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9.11 Headphone Output
9.12 SPDIF output
................................................................................................................................... 112
........................................................................................................................................... 115
10 Detailed Description - System Functions
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10.1 2C Serial Interface
................................................................................................................................... 116
10.2 Reset generator and XON-Key
10.3 Interrupt Controller
........................................................................................ 116
................................................................................................................118
...................................................................................................................................124
10.4 Startup ......................................................................................................................................................129
10.5 Protection Functions
10.6 Watchdog
................................................................................................................................134
................................................................................................................................................135
10.7 General Purpose 10 Bit ADC
...................................................................................................................136
10.8 Internal References (V, I, fclk)
..................................................................................................................139
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- Applications
10.9 Real-Time Clock (RTC) Module
10.10 Touchpen Interface
................................................................................................................................... 148
12 Package Drawings and Marking
.....................................................................................................154
12.1 Pinout Drawing (Top view) CTBGA 8x8mm
13 Ordering Information
.............................................................................................155
.......................................................................................................................156
Document Revision History
Table 1. Revision History
Rev
Description of Changes
1v00
-
9.1; 12
1v10
- updated package drawings
- updated audio path drawings
12,13
1v11
- updated packagemarkings and ordering information
12,13
1v12
23.3.2009
Author
pkm
pkm
23.9.2009
pkm
- updated packagemarkings and ordering information
23.10.2009
pkm
- typo corrections
23.9.2010
pkm
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15.4.2009
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1v13
Date
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Chapter
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11 Register map
...............................................................................................................140
................................................................................................................................143
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Revision 1v13
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Data Sheet Confidential
- Pin Assignments
4 Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
NC/
VSS
_CP
LRC
LK1
SCL
K3
VI2S
SDO
1
VCP
_N
VCP
_P
VCP
_OU
T
VDI
G34
_IN
VDI
G1_I
N
LOU
T_R
LINE
_CM
HPL
1
NC/
BV
SS
B
SDI2
SCLK1
SDI1
SDA
VSS_C
P
VCP_I
N
VDIG_
2
VDIG2
_IN
VDIG_
1
LOUT_
L
HP_C
M
C
Q32k
SCLK2
D
DCDC
_SENS
E_P1
MCLK
2
E
VSUP
PLY_4
F
VSUP
PLY_3
G
LX3
H
PGND
3
PGND
2
J
LX2
VSS_C
H
K
VSUP
PLY_1
VSUP
PLY_2
L
LX1
VOFF_
B
M
PGND
1
VGAT
E
N
PGAT
E1
P
NC/
VSSA
MCLK
1
LRCLK
2
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VDIG_
3
HPR1
HPL2
ALVD
D
HP_
CM_
PWR
AVDD
LINR
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VDIG_
4
LRCLK
3
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BVSS
XRES
ET
SPDIF
XINT
MICS
VDAC
LINL
DCDC
_SENS
E_N2
DCDC
_SENS
E_P2
VSSA
MICN
VSUP
PLY_6
DCDC
_FB1
FB3
VSSA
MICP
VBAT_
SW12
VREF
BAT_S
W
AGND
ISENS
N
ISEN
SP
GND_
SENS
E
RBIA
S
V_BAT
VBA
CK
DCDC
_FB2
FB2
VSSA
FB1
CURR
4_GPI
O4
VSUP
PLY_5
XON
CH_S
ENSE_
N
VCUR
R_GPI
O
CURR
1_GPI
O1
VSS_C
URR
DCDC
_CUR
R1
CURR
3_GPI
O3
CURR
2_GPI
O2
DCDC
_CUR
R3
GND_
SW
RPRO
GRAM
CREF
DCDC
_CUR
R2
ADC_I
N1
ADC_I
N2
VRF_2
VCHA
RGER
V2_5
VSUP_
USB
V_USB
VRF1_
IN
VRF_1
VRF23
_IN
VRF_3
XIN32
VSU
P_S
W12
VSU
P_S
W12
VBAT
_SW
12
XOU
T32
NC/
VSS
A
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ENSE_
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SCL
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DCDC
_SENS
E_N1
DCDC
_GATE
1
DCDC
_GATE
2
SDO3
HPR
2
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4.1
- Pin Assignments
Pin Description
Table 2. Pin list CTBGA124, 8x8MM (AS3658)
Pin
Number
Pin
Type
V_USB
P8
P
USB voltage supply input
VSUP_USB
P7
P
Supply output of USB charger (connect to Vsupply)
VCHARGER
N11
P
High voltage input coming from the charger; if the charger is
used connect a ceramic capacitor of 1µF
VGATE
M2
A
Switch ON control pin for the external PMOS Fet transistor of
the charger step down converter
VOFF_B
L2
A
Switch OFF control pin for the external PMOS Fet transistor of
the charger step down Buck converter
VSS_CH
J2
P
Ground pad of Step down Charger
Pin Name
Supply
Description
VSUP_SW12
VSUP_SW12
BAT_SW
CH_SENSE_N
CH_SENSE_P
ISENSP
ISENSN
Serial Interface
SCL
SDA
Control Interfaces
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P
VBAT
Battery switch input1 (battery side)
J14
P
VBAT
Battery switch input2 (battery side)
G14
P
VSUPPLY Battery switch input1 (supply side)
H14
P
VSUPPLY Battery switch input2 (supply side)
J13
A
P3
A
VSUPPLY
Charger step down converter, external shunt resistor negative
connection
P2
A
VSUPPLY
Charger step down converter, external shunt resistor positive
connection
K14
A
V2_5
Positive sensing input voltage for the external charging current
shunt resistor
K13
A
V2_5
Negative sensing input voltage for the external charging
current shunt resistor
D6
DI
B5
DIO
VSUPPLY SDA input / output in I2C mode
F7
OD
VSUPPLY
Bidirectional Reset Pin – add an external pull-up resistor to the
digital supply
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XRESET
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VBAT_SW12
H13
Battery switch output for external PMOS
VSUPPLY SCL input in I2C mode
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Charger
F8
OD
VSUPPLY
Interrupt Pin - add an external pull-up resistor to the digital
supply
XON
N4
IPU
V2_5
Input pin to startup the system (power on), internal pull-up,
apply zenerzap-programming voltage here
Q32K
C1
OD
XIN32
P13
A
V2_5
32kHz crystal oscillator input
XOUT32
N14
A
V2_5
32kHz crystal oscillator output
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XINT
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RTC
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VSUPPLY 32kHz oscillator digital output
Revision 1v13
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Data Sheet Confidential
- Pin Assignments
Table 2. Pin list CTBGA124, 8x8MM (AS3658)
Pin
Number
Pin
Type
VSUPPLY_5
N3
P
V_BAT
M13
P
VBAT
Battery supply for Reference blocks.
RPROGRAM
L9
A
V2_5
Select register setup at startup.
V2_5
N12
P
CREF
L10
A
V2_5
Reference voltage bypass capacitor connection
RBIAS
L14
A
V2_5
Internal Bias Reference Resistor (connect 220kΩ resistor)
GND_SENSE
L13
P
VSSA
GND reference for analog blocks (connect to GND plane
separate)
ADC_IN1
N8
A
V2_5
Analog input1 for ADC10
Pin Name
Supply
Description
Internal Refs
CURR1_GPIO1
CURR2_GPIO2
CURR3_GPIO3
CURR4_GPIO4
DCDC_CURR1
DCDC_CURR2
DCDC_CURR3
VCURR_GPIO
VSS_CURR_GPIO
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VBACK
Current Sinks
Internal regulator analogue output
Analog input2 for ADC10
N9
A
M14
A
N5
A
VCURR_ Current sink 1, or GPIO1
A
VCURR_ Current sink 2, or GPIO2
A
VCURR_ Current sink 3, or GPIO3
A
VCURR_ Current sink 4, or GPIO4
A
VCURR_ Step up DC/DC converter2 current source 1
A
VCURR_ Step up DC/DC converter2 current source 2
L7
A
VCURR_ Step up DC/DC converter2 current source 3
P4
A
P6
N6
L5
L6
N7
V2_5
Backup battery connection
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Supply voltage of GPIOs and current sinks
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ADC_IN2
Supply for voltage Measurement, always connect to
VSUPPLY
P5
A
VCURR_ Ground pad of Current sink / GPIO pads
GPIO
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General Purpose DC/DC Step up Converter 1 and 2
Supply for DCDC step up and control interface, always
connect to VSUPPLY
E1
P
DCDC_FB1
H4
A
VSUPPLY Step up DC/DC converter1 feedback input
DCDC_GATE1
F2
A
VSUPPLY Step up DC/DC converter1 control for external mosfet
DCDC_SENSE_P1
D1
A
VSUPPLY
Step up DC/DC converter1 external shunt resistor positive
connection
DCDC_SENSE_P2
G6
A
VSUPPLY
Step up DC/DC converter2 external shunt resistor positive
connection
DCDC_SENSE_N1
E2
A
VSUPPLY
Step up DC/DC converter1 external shunt resistor negative
connection
DCDC_SENSE_N2
G4
A
VSUPPLY
Step up DC/DC converter2 external shunt resistor negative
connection
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VSUPPLY_4
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- Pin Assignments
Table 2. Pin list CTBGA124, 8x8MM (AS3658)
Pin Name
Pin
Number
Pin
Type
DCDC_GATE2
G2
A
VSUPPLY Step up DC/DC converter2 control for external mosfet
DCDC_FB2
J4
A
VSUPPLY Step up DC/DC converter2 feedback input
Supply
Description
Linear Regulators (LDOs)
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Supply Pad for RF1 LDO (VRF_1), always connect to
Supply>3.0V
VRF1_IN
P9
P
VSUPPLY
VRF_1
P10
A
Output voltage of one of the RF LDO’s; can be used as HighVRF1_IN Side Switch, if used as LDO connect a ceramic capacitor of
1µF (±20%) or 2.2µF (+100%/-50%)
VRF23_IN
P11
P
VSUPPLY
VRF_2
N10
A
Output voltage of one of the RF LDO’s; can be used as HighVRF23_IN Side Switch, if used as LDO connect a ceramic capacitor of
1µF (±20%) or 2.2µF (+100%/-50%)
VDIG_1
VDIG2_IN
VDIG_2
VDIG34_IN
VDIG_3
VDIG_4
Charge Pump
VCP_IN
VCP_N
lv
A
Output voltage of one of the RF LDO’s; can be used as HighVRF23_IN Side Switch, if used as LDO connect a ceramic capacitor of
1µF (±20%) or 2.2µF (+100%/-50%)
A10
P
VSUPPLY Supply Pad for DIG1 LDO (VDIG_1)
B10
A
VDIG1_IN
B9
P
VSUPPLY Supply Pad for DIG2 LDO (VDIG_2)
B8
A
VDIG2_IN
A9
P
VSUPPLY Supply Pad for DIG3 and DIG4 LDO (VDIG_3, VDIG_4)
D8
A
VDIG3_IN
Output voltage of one of the DIG LDO’s. Connect a ceramic
capacitor of 1µF (±20%) or 2.2µF (+100%/-50%)
D7
A
VDIG4_IN
Output voltage of one of the DIG LDO’s. Connect a ceramic
capacitor of 1µF (±20%) or 2.2µF (+100%/-50%)
B7
P
VSUPPLY
Supply Pad for Charge Pump, always connect to
Supply>3.0V
A6
A
VSUPPLY HVS charge pump flying capacitor positive side
A7
A
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VCP_P
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VDIG1_IN
P12
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VRF_3
Supply Pad for RF2 and RF3 LDO (VRF_2, VRF_3), always
connect to Supply>3.0V
Output voltage of one of the DIG LDO’s. Connect a ceramic
capacitor of 1µF (±20%) or 2.2µF (+100%/-50%)
Output voltage of one of the DIG LDO’s. Connect a ceramic
capacitor of 1µF (±20%) or 2.2µF (+100%/-50%)
HVS charge pump flying capacitor negative side
Charge pump output, connect a ceramic capacitor of 2.2µF
(+100%/-50%)
A8
A
VSS_CP
B6
A
VSUPPLY Ground pad of charge pump
N1
A
VSUPPLY Gate output for external PMOS.(DCDC step down controller 1)
VSUPPLY_1
K1
P
Supply Pad for DCDC_Step down converter1, always connect
to VSUPPLY
LX1
L1
A
VSUPPLY DC/DC step down converter1 output
FB1
K4
A
VSUPPLY DC/DC step down converter1 feedback
PGND1
M1
A
VSUPPLY Power Ground of DCDC step down converter1
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VCP_OUT
DCDC Step Down Converters
Te
PGATE1
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AS3658
Data Sheet Confidential
- Pin Assignments
Table 2. Pin list CTBGA124, 8x8MM (AS3658)
Pin Name
Pin
Number
Pin
Type
VSUPPLY_2
K2
P
LX2
J1
A
VSUPPLY DC/DC step down converter2 output
FB2
J7
A
VSUPPLY DC/DC step down converter2 feedback
PGND2
H2
A
VSUPPLY Power Ground of DCDC step down converter2
VSUPPLY_3
F1
P
LX3
G1
A
VSUPPLY DC/DC step down converter3 output
FB3
H6
A
VSUPPLY DC/DC step down converter3 feedback
PGND3
H1
A
VSUPPLY Power Ground of DCDC step down converter3
VI2S
SDI1
SDO1
SCLK1
LRCLK1
MCLK1
SDI2
SCLK2
LRCLK2
MCLK2
SDO3(X-)
SCLK3(X+)
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Supply Pad for DCDC_Step down converter3, always connect
to VSUPPLY
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VSUPPLY_6
Description
Supply Pad for DCDC_Step down converter2, always connect
to VSUPPLY
G13
P
Supply for VI2S Regulator
A4
P
Supply Pad for I2S Interface, Connect to VDAC Supply
B4
I
VI2S
I2S_1 Data input to DAC
A5
O
VI2S
I2S_1 Data output from ADC
B3
I/O
VI2S
I2S_1 Shift clock input or output
A2
I/O
VI2S
I2S_1 Left/Right clock input or output
D9
I/O
VI2S
Master clock input or output for I2S1: DAC (128*Fsdac or 256
*Fsdac)
B1
I
VI2S
I2S_2 Data input to DAC
C2
I
VI2S
I2S_2 Shift clock
D10
I
VI2S
I2S_2 Left/Right clock
D2
I
VI2S
Master clock input for I2S2: DAC (128*Fsdac or 256 *Fsdac)
D5
I/O
VI2S
I2S_3 Data output (if touchpen interface disabled)
Touchpen Interface X- Input/Output (if touchpen interface
enabled)
ca
Audio
Supply
A3
I/O
VI2S
I2S_3 Shift clock output (if touchpen interface disabled)
Touchpen Interface X+ Input/Output (if touchpen interface
enabled)
I/O
VI2S
I2S_3 Left/Right clock output (if touchpen interface disabled)
Touchpen Interface Y- Input/Output (if touchpen interface
enabled)
SPDIF(Y+)
F4
I/O
VI2S
SPDIF digital output (if touchpen interface disabled)
Touchpen Interface Y+ Input/Output (if touchpen interface
enabled)
AGND
K11
A
VDAC
CM voltage bypass capacitor connection (1.45V)
VREF
J11
A
VDAC
VDAC voltage bypass capacitor connection (2.9V)
LINL
F14
A
VDAC
Line input left channel.
LINR
E14
A
VDAC
Line input right channel
GND_SW
L8
O
ni
E4
Te
ch
LRCLK3(Y-)
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VSUPPLY Digital output for controlling the external NMOS
Revision 1v13
10 - 157
AS3658
Data Sheet Confidential
- Pin Assignments
Table 2. Pin list CTBGA124, 8x8MM (AS3658)
Pin Name
Pin
Number
Pin
Type
Supply
VDAC
F13
A
VDAC
2.9V Output voltage of one of DAC LDO; Connect a ceramic
capacitor of 1µF (±20%) or 2.2µF (+100%/-50%)
HP_CM
B12
A
AVDD
Bypass capacitor connection of common mode voltage of
Audio headphone amplifier (AVDD/2)
HP_CM_PWR
D14
A
AVDD
Buffered voltage of HP_CM
LINE_CM
A12
A
ALVDD
Bypass capacitor connection of common mode voltage of
Audio line out amplifier (ALVDD/2)
LOUT_L
B11
A
ALVDD Line out output Left channel
LOUT_R
A11
A
ALVDD Line out output Right channel
ALVDD
D13
P
Supply pad of Line out amplifier
AVDD
E13
P
Supply pad of headphone amplifier
HPL1
A13
A
AVDD
Headphone output1 left channel
C13
A
AVDD
Headphone output1 right channel
C14
A
AVDD
Headphone output2 left channel
B14
A
AVDD
Headphone output2 right channel
G11
A
VDAC
Microphone Input N
H11
A
VDAC
Microphone Input P
F11
A
E11
P
G9
VSS
Analog Ground Pad
H9
VSS
Analog Ground Pad
J8
VSS
Analog Ground Pad
A1
VSS
Analog Ground Pad
P1
VSS
Analog Ground Pad
P14
VSS
Analog Ground Pad
A14
VSS
Power ground of headphone amplifier
HPR2
MICN
MICP
MICS
VSS
BVSS
VSSA
VSSA
VSSA
NC/VSS_CP
NC/VSSA
NC/VSSA
NC/BVSS
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HPL2
VSUPPLY Microphone Supply (2.95V) / Remote Input
AVDD
ca
HPR1
Description
Power ground of headphone amplifier
ni
Note: The following are the Pin Types
I: Digital Input Pin
ch
IPD: Digital Input Pin with internal pull-down resistor
IPU: Digital Input Pin with internal pull-up resistor
IODPU: Digital Input / Open Drain Output Pin with internal pull-up resistor
O: Digital Output Pin
Te
OD: Digital Open Drain Output Pin; requires external pull-up resistor
IO: Digital Input / Output Pin
A: Analog Pin
P: Power Pin
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Data Sheet Confidential
- Absolute Maximum ratings
5 Absolute Maximum ratings
Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in Section 6 Electrical
Characteristics on page 13 is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
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Table 3. Absolute Maximum Ratings
Parameter
Min
Max
Unit
Note
High voltage pins (VIN_HV)
-0.3
17.0
V
Applicable for high voltage pins
5V pins (VIN_MV)
-0.3
7.0
V
Applicable for pins 5V-pins
3.3V pins (VIN_LV)
-0.3
5.0
V
Applicable for 3.3V-Pins
Input pin current (IIN)
-25
+25
mA
At 25 ºC, Norm: Jedec 78
Storage Temperature Range
(Tstrg)
-55
125
ºC
Humidity
5
85
%
Noncondens
-1000
1000
V
Norm: MIL 883 E Method 3015; Setup
Applicable for pins: all
1
W
TA = 70ºC
0.72
W
TA = 84ºC
260
°C
IPC/JEDEC J-STD-020C, reflects moisture
sensitivity level only
The lead finish for Pb-free leaded packages is
matte tin (100% Sn).
235
245
°C
TPEAK
30
45
s
DWell, above 217 °C
1
Represents a max. floor live time of 168h
2
lv
3
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Electrostatic discharge 1kV (VESD)
Total Power Dissipation
Package Body Temperature
5
Solder Profile
1
Moisture Sensitive Level
3
4
ch
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1. HV pins
VCHARGER, VGATE, VOFF_B, DCDC_CURR1, DCDC_CURR2, DCDC_CURR3
2. 5V pins are
V_USB, CH_SENSE_N, CH_SENSE_P, VSUP_SW1, VSUP_SW2, VBAT_SW1, VBAT_SW2, V_BAT, SCL,
SDA, XRESET, XINT, VSUPPLY_3, CURR1_GPIO1…CURR4_GPIO4, DCDC_GATE1, DCDC_GATE2,
DCDC_SENSE_P1, DCDCSENSE_P2, DCDC_SENSE_N1, DCDC_SENSE_N2, DCDC_FB1, DCDC_FB2,
VCL, VCP_OUT, VCP_N, VCP_P, VCP_IN, VCP_IN, VRF1, VREF1_IN, VRF2, VRF23_IN, VRF3, VDIG1,
VDIG1_IN, VDIG2, VDIG2_IN, VDIG34_IN, VDIG_3, VDIG_4, PGATE1 VSUPPLY_1, VSUPPLY_2, LX1, LX2,
GND_SW, VSUPPLY_4, LINE_CM, HP_CM_PWR, HP_CM, HPLx, HPRx, ALVDD, AVDD, LSP_R, BVSS,
LSP_L, AVDD, VSUPPLY_5, VSUPPLY_6
3. 3.3V pins are
ISENSEP, ISENSEN, ADC_INx, RPROGRAM, V2_5, CREF, ON, VI2S, SDIx, SCLKx, MCLKx, LRCLKx,
SDOx, SPDIF, AGND, VREF, LINL,LINR, VDAC, Q32K, XIN32, XOUT32, VBACK, MICS, MICN, MICP
4. The following pins are connected to ESD setup:
Te
VSUPPLY_1...VSUPPLY_6, VCP_IN, VRF1_IN, VRF2_IN, VCURR connected together
VDIG1_IN, VDIG2_IN, VDIG34_IN connected together
AVDD, ALVDD connected together
VBAT_SW1 and VBAT_SW2 connected together
VSUP_SW1 and VSUP_SW2 connected together
All VSS connected together
5. austriamicrosystems strongly recommends to use underfill.
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Revision 1v13
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AS3658
Data Sheet Confidential
- Electrical Characteristics
6 Electrical Characteristics
Table 4. Electrical Characteristics
Symbol
Parameter
Condition
Min
High Voltage
VCHARGER, VGATE,
DCDC_CURR1,DCDC_CURR2,
DCDC_CURR3
0.0
Battery, Supply Voltage
For pins V_BAT, VSUPPLY1-6
(always connect all VSUPPLY1-6
pins together), VSUP_SW1-2,
VBAT_SW1-2, VRF1_IN, VRF2_IN,
VCP_IN, AVDD, ALVDD
3.0
Voltage on Pin V2_5
Internally generated
2.4
Typ
Max
Units
15.0
V
VBAT,
VSUPPLY,
VCURR_GPIO
V2_5
VCP_OUT
Output Voltage charge pump Voltage generated by charge pump
Ambient Temperature
ILOWPOWER
Low power mode current
consumption
-40
Current consumption in low power
1
mode with step down charger on
2
With step down charger off
IPOWEROFF
5.5
Power Off mode current
consumption
Current consumption in power off
3
mode
V
2.5
2.6
V
5.2
5.6
V
25
85
ºC
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TAMB
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3.6
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VHV
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Operating Conditions
7
mA
280
µA
10
µA
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1. With register bit low_power_on = 1, only Rf1=3.3V,Vout2=1.2V, Battery 3.6V,Vcharger=6.0V, no additional
external loads
2. With register bit low_power_on = 0, All regulators switched off, no additional external loads
3. After setting register bit xon_enable=1 and power_off=1; only V2_5 is active in Power Off mode
4. During startup from the AC/DC adapter, the battery voltage can be below 3.0V
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Data Sheet Confidential
- Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
7 Typical Operating Characteristics
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see individual block description
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Revision 1v13
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AS3658
Data Sheet Confidential
- Detailed Description-Power Management Functions
8 Detailed Description-Power Management Functions
8.1
Step Up DC/DC Converters
Figure 3. DC/DC step-up Converter 1
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The power management function consist of the DCDC Step up converters, Current Sink, GPIOs, general purpose 10
bit ADC, backup battery charger, main battery charger and power path management (consisting of the battery switch,
external step down/linear charger, USB charger and battery charge controller), step down dc/dc converters, low
dropout regulators (LDOs) and 5V charge pump.
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Revision 1v13
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AS3658
Data Sheet Confidential
- Detailed Description-Power Management Functions
Figure 4. DC/DC step-up Converter 2
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Table 5. DC/DC Converter parameters
Parameter
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Symbol
Quiescent Current
VFB1
Feedback voltage for external
resistor divider:
Typ
Max
140
1.20
Feedback voltage for current
sink regulation
1.25
1.30
0.5
Unit
Note
µA
Pulse skipping mode
V
for constant voltage control
V
DCDC_CURR1, DCDC_CURR2
or DCDC_CURR3
Additional tuning current at
DCDC_FB
0
31
µA
adjustable by software in 1µA
steps
Accuracy of feedback current
-5
5
%
@ full scale
mV
E.g.: 0.65A for 0.15Ω sense
resistor
1
Ω
ON-resistance of external
switching transistor
50
mA
at 15V output voltage
MHz
internal CLK frequency/2
Programmable: 0.8 to 1.15 MHz
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VFB2
ni
IVDD
Min
IDCDC_FB
Te
Vrsense_max Current limit voltage at Rsense
RSW
switch resistance
Iload
Load current
fIN
Switching frequency
www.austriamicrosystems.com
100
0
fclk_int/
2
Revision 1v13
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AS3658
Data Sheet Confidential
- Detailed Description-Power Management Functions
Table 5. DC/DC Converter parameters
Parameter
Cout
Output capacitor
L
Min
Typ
Max
Unit
Note
2.2
µF
ceramic, ±20%
Inductor
10
µH
Use inductors with small Cparasitic
(<100pF) to get high efficiency
tMIN_ON
Minimum on time
130
ns
MDC
Maximum duty cycle
91
%
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Symbol
lv
The DC/DC Step Up converter is a high efficiency current mode PWM regulator, which provides an output voltage
dependent on the maximum VDS voltage of the external transistor, and maximum load current selectable by the
external shunt resistor.
For Example:
5V,500mA @ 1.1Mhz
40V,20mA @ 550kHz
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25V,50mA @ 1.1MHz
A constant switching frequency results in a low noise on supply and output voltage.
8.1.1 Feedback selection
For step up DCDC 1, the feedback is always DCDC_FB1.
For step up DCDC 2 following feedback selections are possible:
Stpup2_fb selects the type of feedback for the DCDC_step_up2 converter:
DCDC_CURR1, DCDC_CURR2, DCDC_CURR3 or DCDC_FB2 feedback (see Figure 5)
Setting stpup2_fb to 00b enables the feedback on DCDC_FB2, stpup2_fb to 01b enables feedback at pin
DCDC_CURR1, setting step_up_fb to 10b enables feedback at pin DCDC_CURR2 and setting step_up_fb to 11b
enables feedback at pin DCDC_CURR3. The Step-up converter is regulated such that the required current at the
feedback path can be supported.
Always choose the path with the higher voltage drop as feedback to guarantee adequate supply for the other,
unregulated path.
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To protect the DCDC output voltage against overvoltage, if a LED string is broken, set stpup2_prot=1. In this mode the
output voltage will be limited by limiting the DCDC_FB voltage to 1.25V (select the external resistor network to adjust
this limitation voltage).
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Revision 1v13
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Data Sheet Confidential
- Detailed Description-Power Management Functions
Figure 5. DC/DC step up 2 converter with regulation of LED string on pin DCDC_CURR1,2 or 3
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Revision 1v13
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AS3658
Data Sheet Confidential
- Detailed Description-Power Management Functions
Figure 6. DC/DC step up 1 converter with regulated output voltage of 5V. Feedback is at pin DCDC_FB1
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Voltage Feedback: (see Figure 6)
For Step UP DCDC 1 voltage feedback is always selected on pin DCDC_FB1. For Step-up UP DCDC 2 set step2_fb to
00 to enable voltage feedback at pin DCDC_FB2.
Bit stepX_res (X = 1 or 2) should be set to 1 in voltage feedback mode using two resistors.
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The output voltage is regulated to a constant value, given by:
ni
Vstepup _ out =
R1 + R2
1.25 + I I DCDC _ FB • R1
R2
ch
If R2 is not used, the output voltage is:
Vstepup _ out = 1.25 + I I DCDC _ FB • R1
Vstepup_out: Step up regulator output voltage
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R1 Feedback resistor R1
R2 Feedback resistor R2
IVturning: Tuning current on DCDC_FB pin: stpupX_v (0µA to 15µA (1µA steps)) (X= 1 or 2)
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Revision 1v13
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- Detailed Description-Power Management Functions
Example:
Table 6. Step Up Output Voltage (Voltage mode or protection voltage)
Vstepup_out
Vstepup_out
µA
R1=1M Ω,R2 not used
R1=500k Ω,R2=64k Ω
0
-
11
1
-
11.5
2
-
12
3
-
12.5
4
-
13
5
6.25
13.5
6
7.25
7
8.25
10
11
12
13
14
15
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9.25
14
14.5
15
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Ivtuning
10.25
15.5
11.25
16
12.25
16.5
13.25
17
14.25
17.5
15.25
18
16.25
18.5
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Note: The voltage on pin DCDC_CURR1, DCDC_CURR2 and DCDC_CURR3 must never exceed 15V
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Revision 1v13
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AS3658
Data Sheet Confidential
- Detailed Description-Power Management Functions
Figure 7. DC/DC step up converter 1 with regulated output voltage (15V), and switch off function of output
voltage, to reduce shutdown current
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As the output voltage is always on, an additional output transistor can be added to reduce shutdown current through
R1, R2 and the connected output circuit.
Note: A similar circuit can be used for step up converter 2.
8.1.2 StepUp1 Load Detection and Overcurrent Protection Circuit
This circuit protects the DCDC step up1 converter during short circuit and startup, by regulation of the output current.
An additional feature is the detection of a minimum output load of the Step-up converter. It is also possible to use this
circuit without the DCDC step up converter, by using the sense resistor only:
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Detection circuit: If the voltage on Rsense exceeds VDETECT for more than 1msecond, or the DCDC Step up
converter is not in Pulseskip for more than 1 millisecond, the stepup1_det bit will be set.
ni
Overcurrent protection: If the Overcurrent voltage VOVCURRENT has been exceeded by more than 5 msec the Bit
stpup1_oc will be set and can only reset, by switching off and on the Protection circuit by writing Stpup1_shortprot
0 – 1. If stepup1_oc is set the load will be disconnected, if Stpup1_oc_timeout=1
Table 7. StepUp1 protection/detection circuit parameters
Parameter
Min
Typ
Max
Unit
Note
VDETECT
Detection Threshold
2
12.5
25
mV
For Rsense=0.150Ω =>
83mA typ.
VOVCURRENT
Overcurrent Threshold
rising
150
180
215
mV
For Rsense=0.150Ω =>
1.2A typ.
VOVhysteresis
Overcurrent Hysteresis
50
mV
tOV_timeout
Overcurrent timeout
5
ms
Interrupt and/or external PMOS
switching off after timeout
fclk_int = 2.2MHz
tdetect
Detection denounce
time
1
ms
fclk_int = 2.2MHz
Te
ch
Symbol
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AS3658
Data Sheet Confidential
- Detailed Description-Power Management Functions
Figure 8. StepUp 1 Load Detection and Overcurrent Protection Application Circuit
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Revision 1v13
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- Detailed Description-Power Management Functions
8.1.3 Step Up DCDC Converter Registers
Table 8. Step Up DC/DC Bit definitions
Step Up DC/DC control
Addr: 30
This register controls the different modes of the step up DCDC converter
Bit Name
Default
Access
Description
5
stpup1_on
ROM
R/W
On/Off control of the step up dc/dc converter1
6
stpup2_on
ROM
R/W
On/Off control of the step up dc/dc converter2
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Bit
Table 9. Step Up DC/DC Bit definitions
Step Up DC/DC control
Addr: 32
Bit Name
Default
lv
Bit
This register controls the different modes of the step up DCDC converter
Access
Description
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Invert input clock of step up2 converter
0
stpup2_clkinv
00h
R/W
0
Use positive edge of internal clk
1
Use negative edge of internal clk
1
stpup1_freq
00h
R/W
Defines the clock frequency of the step up1 dc/dc
converter;
0fclk_int/2 (0.8 to 1.15 MHz)
1fclk_int/4 (0.4 to 0.575 MHz)
2
-
00h
n/a
Always set to 0
Gain selection for DCDC step_up1:
3
stpup1_res
stpup2_fb_auto
00h
R/W
ni
stpup2_freq
ch
5
Te
6
7
-
stpup2_res
www.austriamicrosystems.com
00h
00h
Select 0 if DCDC is used with current feedback
(DCDC_CURR1,DCDC_CURR2,DCDC_CURR3)
or if DCDC_FB is used with current feedback only
(Only R1,C1 connected; (see Figure 6))
1
Select 1 if DCDC_FB1 or DCDC_FB2 is used with
external resistor divider (2 resistors)
0
step_up_fb select the feedback of the DCDC
converter
1
The feedback is automatically chosen within the
current sinks DCDC_CURR1,DCDC_ CURR2 and
DCDC_CURR3 (never DCDC_FB). Only those are
used for this selection, which are enabled and
connected to the step up converter
(currX_ctrl must be 10)
RW
ca
4
00h
0
Defines the clock frequency of the step up2 dc/dc
converter
R/W
0
fclk_int/2 (0.8 to 1.15 MHz)
1
fclk_int/4 (0.4 to 0.575 MHz)
n/a
Always set to 0
Gain selection for DCDC step_up2:
00h
R/W
0
Select 0 if DCDC is used with current feedback
(DCDC_CURR1,DCDC_CURR2,DCDC_CURR3)
or if DCDC_FB is used with current feedback only
(Only R1,C1 connected; (see Figure 6))
1
Select 1 if DCDC_FB1 or DCDC_FB2 is used with
external resistor divider (2 resistors)
Revision 1v13
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- Detailed Description-Power Management Functions
Table 10. Step Up DC/DC Bit definitions
Step Up1 DC/DC control
Addr: 33
Bit
This register controls the different modes of the step up1 DCDC
converter
Bit Name
Default Access
Description
4:0
stpup1_v
00h
R/W
00000
0 µA
00001
1 µA
.....
11111
31 µA
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Defines the tuning current at DCDC_fb1 pin;
stpup1_clkinv
00h
R/W
0
Use positive edge of internal clk
1
Use negative edge of internal clk
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5
lv
Invert input clock of step up1 converter;
Enables Protection and Detection circuit for DCDC step
up1
6
stpup1_shortprot
00h
RW
0
No protection and load detection
1
Short protection and load detection enabled
Controls GPIO1 switch off, after overcurrent timeout (5ms)
for DCDC step up1
7
stpup1_oc_timeout
00h
RW
0
disabled
1
enabled
Table 11. Step Up DC/DC Bit definitions
Step Up2 DC/DC control
Addr: 34
Bit
Bit Name
This register controls the different modes of the step up2 DCDC
converter
Default Access
Description
Defines the tuning current at DCDC_fb2 pin;
stpup2_v
00h
R/W
ch
stpup2_fb
Te
6:5
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0 µA
00001
1 µA
.....
11111
ni
ca
4:0
00000
31 µA
Controls the feedback source
00h
00
DCDC_FB enabled (external resistor divider)
01
DCDC_CURR1 feedback enabled (feedback
through white LEDs)
10
DCDC_CURR2 feedback enabled (feedback
through white LEDs)
11
DCDC_CURR3 feedback enabled (feedback
through white LEDs)
R/W
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Table 11. Step Up DC/DC Bit definitions
Step Up2 DC/DC control
Addr: 34
7
stpup2_prot
Default Access
00h
RW
Description
DCDC converter 2 overvoltage protection to prevent
damage of external NFET, if DCDC_CURR1 or
DCDC_CURR2 or DCDC_CURR3 feedback selected, and
no LED string connected:
al
id
Bit Name
0
Overvoltage protection disabled
1
Switch off DCDC step up 2 if the voltage on
DCDC_FB2 exceeds 1.25V
lv
Bit
This register controls the different modes of the step up2 DCDC
converter
Table 12. stpup1_det and stpup1_oc Bit definitions
Low voltage status bit definitions
Bit
This register shows the status of the overcurrent protection of the
stepup1dcdc
am
lc s
on A
te G
nt
st
il
Addr: 53
Bit Name
Default Access
Description
Step up overcurrent status bit
6
stpup1_oc
NA
R
0
VRsense < VOVCURRENT
1
VRsense > VOVCURRENT for more than 5 msec (latched
state)
Step up detection status register
7
8.2
stpup1_det
NA
0
VRsense < VDETECT for more than 1msecond, and
DCDC Step up converter is in Pulseskip for more than
1 millisecond
1
VRsense > VDETECT for more than 1msecond, or the
DCDC Step up converter is not in Pulseskip for more
than 1 millisecond
R
Current Sinks
ca
These are general-purpose current sinks intended to control the backlight(s), buzzer and vibrator. The low voltage
current sink has an integrated protection against over voltage and can therefore also drive inductive loads (VPROTECT).
DCDC_CURR1 and DCDC_CURR2, DCDC_CURR3 are high voltage (15V) current sinks, e.g. for series of white
LEDs
ni
CURR1_GPIO, CURR2_GPIO, CURR3_GPIO, CURR4_GPIO are four 5V, 38.25mA current sinks, e.g. for buzzer,
vibrator, LEDs
Te
ch
CURR1_GPIO, CURR2_GPIO, CURR3_GPIO, CURR4_GPIO can be used as general propose Input/Output (GPIO)
functions optional (described in section General Purpose Input / Output (CURR1_GPIO1 … CURR4_GPIO4)).
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8.2.1 High voltage Current Sinks (DCDC_CURR1, DCDC_CURR2 and DCDC_CURR3)
Current sinks DCDC_CURR3, DCDC_CURR1 and DCDC_CURR2 can be controlled individually. The step-up DCDC
converter may supply them with voltages up to 15V. If any of these current sinks is used, connected VCURR_GPIO to
a supply with at least 3.0V.
Table 13. Current Sinks Characteristics
Min
IDCDC_Curr1,2,3
DCDC_CURR1,2 and
DCDC_CURR3
current, 00h-3Fh
0
IDCDC_protect
Current sink protection
Current
Δ
absolute Accuracy
-5
VDCDC_CURR1,
VDCDC_CURR2,
VDCDC_CURR3
Voltage compliance
0.45
Typ
Max
Unit
Note
38.25
mA
For V(DCDC_CURRx) > 0.45V
resolution = 0.15mA
µA
Protection Current if stpup2_on=1
and dcdc_currx_current=00h
+5
%
All Current sinks
15
V
during normal operation
am
lc s
on A
te G
nt
st
il
2
al
id
Parameter
lv
Symbol
Table 14. DCDC_CURR1 Current sink current bit definition
Addr: 39
Bit
Bit Name
DCDC_CURR1 Value
This register controls the current value of the dcdc_curr1 current sink
Default Access
Description
Defines the current into DCDC_CURR1 if enabled by
dcdc_curr1_ctrl
7:0
dcdc_curr1_current
00h
00h
power down (default state)
01h
0.15mA (LSB)
R/W
....
FFh
38.25mA
Table 15. DCDC_CURR2 Current sink current bit definition
Addr: 40
ni
dcdc_curr2_current
Default Access
00h
Description
Defines the current into DCDC_CURR2 if enabled by
dcdc_curr2_ctrl
00h
power down (default state)
01h
0.15mA (LSB)
R/W
....
FFh
38.25mA
Te
ch
7:0
Bit Name
This register controls the current value of the dcdc_curr2 current sink
ca
Bit
DCDC_CURR2 Value
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Table 16. DCDC_CURR3 Current sink current bit definition
DCDC_CURR3 Value
Addr: 45
Bit
This register controls the current value of the dcdc_curr3 current sink
Bit Name
Default Access
Description
Defines the current into DCDC_CURR3 if enabled by
dcdc_curr3_ctrl
dcdc_curr3_current
00h
power down (default state)
01h
0.15mA (LSB)
R/W
....
38.25mA
Table 17. Current sink control bit definition
Bit
CURR control
am
lc s
on A
te G
nt
st
il
Addr: 58
lv
FFh
al
id
7:0
00h
Bit Name
This register controls the mode of the DCDC current sinks
Default Access
Description
On/Off control of the pad DCDC_CURR1
1:0
dcdc_curr1_ctrl
00b
R/W
00
Current sink is turned off
01
Current sink is active
10
Current sink is active and LED string connected to
stpup2. Required for automatic feedback selection
11
Controlled by PWM generator (do not set pwm_div)
On/Off control of the pad DCDC_CURR2
3:2
dcdc_curr2_ctrl
00b
R/W
00
Current sink is turned off
01
Current sink is active
10
Current sink is active and LED string connected to
stpup2. Required for automatic feedback selection
11
Controlled by PWM generator (do not set pwm_div)
ca
On/Off control of the pad DCDC_CURR3
dcdc_curr3_ctrl
00b
R/W
Current sink is turned off
01
Current sink is active
10
Current sink is active and LED string connected to
stpup2. Required for automatic feedback selection
11
Controlled by PWM generator (do not set pwm_div)
Te
ch
ni
5:4
00
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8.2.2 Low voltage Current Sink (CURR1_GPIO1 … CURR4_GPIO4)
CURR1_GPIO1 … CURR4_GPIO4 can be controlled individually. Each one can sink up to 38.25mA. The voltage on
the current sinks must not exceed the supply VCURR_GPIO (can be connected e.g. to VSUPPLY).
The low voltage current sinks and the gpio pins share the same pins (see General Purpose Input / Output
(CURR1_GPIO1 … CURR4_GPIO4) on page 30) for enabling/disabling of the current sinks / gpio functions.
Table 18. Current Sinks Characteristics
Min
ICURR1,2,3,4
CURR1_GPIO1....
CURR4_GPIO4
current, 00h-1Fh
Δ
VCurr1,2,3,4
Typ
Max
Unit
Note
0
38.25
mA
For V(CURRx_GPIOx) > 0.2V
resolution = 0.15mA,
each current sink
absolute Accuracy
-5
+5
%
All Current sinks
Voltage compliance
0.2
V(VCU
RR)
V
during normal operation
Bit
am
lc s
on A
te G
nt
st
il
Table 19. CURR1 Current sink current Bit definition
Addr: 41
al
id
Parameter
lv
Symbol
Bit Name
CURR1 control
This register controls the mode of the curr1 current sinks
Default Access
Description
Defines the current into CURR1_GPIO1 if GPIO1_Mode =
011b and output enabled (e.g. GPIO1=1)
7:0
curr1_current
(00)h
R/W
00h
power down (default state)
01h
0.15mA (LSB)
....
FFh
38.25mA
Table 20. CURR2 Current sink current Bit definition
Addr: 42
Bit Name
This register controls the mode of the curr2 current sinks
Default Access
ca
Bit
CURR2 control
curr2_current
(00)h
Defines the current into CURR2_GPIO2 if GPIO2_Mode =
011b and output enabled (e.g. GPIO2=1)
R/W
00h
power down (default state)
01h
0.15mA (LSB)
....
FFh
38.25mA
Te
ch
ni
7:0
Description
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Table 21. CURR3 Current sink current Bit definition
CURR3 control
Addr: 43
Bit
This register controls the mode of the curr3 current sinks
Bit Name
Default Access
Description
Defines the current into CURR3_GPIO3 if GPIO3_Mode =
011b and output enabled (e.g. GPIO3=1)
curr3_current
(00)h
R/W
00h
power down (default state)
01h
0.15mA (LSB)
....
38.25mA
Table 22. CURR4 Current sink current Bit definition
CURR4 control
Addr: 44
lv
FFh
al
id
7:0
am
lc s
on A
te G
nt
st
il
This register controls the mode of the curr4 current sinks
Bit
Bit Name
Default Access
Description
Defines the current into CURR4_GPIO3 if GPIO4_Mode =
011b and output enabled (e.g. GPIO4=1)
7:0
curr4_current
(00)h
R/W
00h
power down (default state)
01h
0.15mA (LSB)
....
38.25mA
Te
ch
ni
ca
FFh
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8.3
- Detailed Description-Power Management Functions
General Purpose Input / Output (CURR1_GPIO1 … CURR4_GPIO4)
Figure 9. CURR1_GPIO1 … CURR4_GPIO4 block diagram
1
) "
!
01$2
) '(
/6
, '"
-, '"-
., '".
/, '"/
"
#$
-
-
.
.
/
/
!% ! $& ! ! '#$ ''
'"
ca
!
03% &%%
&))
4 5) .&
am
lc s
on A
te G
nt
st
il
!
'(
!
'! ) **+
lv
#
al
id
!# $ !# !# Te
ch
ni
The device contains 4 high current GPIO pins, which share the same pins as the low voltage current sinks and are
capable of sinking 100mA from VCURR_GPIO voltage. Each of the pins can be configured as open drain NMOS or
push-pull output with VCURR_GPIO high levels, as high impedance output or as digital input. When configured as
output the output source can be a register bit, or the PWM generator, furthermore the output signal can be inverted.
Integrated active clamp circuits can be enabled for the open drain NMOS output mode by setting GPIOxPulls=11b,
thus allowing to use the high current GPIO pins for driving inductive loads. A pull-up resistor to VCURR_GPIO can be
enabled for the open drain NMOS output mode by setting GPIOxPulls=10b. When configured as digital input the logic
level (GPIOxInvert=’0’) or the inverted logic level (GPIOxInvert=’1’) of the pin is reflected by bit GPIOxBit in the GPIO
Bit register.
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Moreover, a special function can be selected for each digital input pin and a pull-up resistor to VCURR_GPIO or a pulldown resistor can be enabled.
Table 23. High Current GPIO Pin Characteristics (VCURR1_GPIO1 … VCURR4_GPIO4)
VVSUPPLY=3.0 to 5.5V; Tamb= –20 to +70°C; unless otherwise specified
VOLH
Low level output
voltage switch
mode
VOL
Typ
Max
Unit
Note
VCURR_GPIO+
0.3
V
Pin VCURR_GPIO is used as supply for
the GPIO pins
–0.3
+0.35
V
IOL=+100mA; digital output
(GPIOxMode=100b and
currX_current=3Fh)
Low level output
voltage
–0.3
+0.4
V
IOL=+1mA; digital output
(GPIOxMode=000b ... 010b)
VOH
High level output
voltage
0.8·VCURR_G
VCURR_GPIO
V
IOH=–1mA; digital push-pull output
VIL
Low level input
voltage
–0.3
0.4
V
digital input
VIH
High level input
voltage
1.3
VCURR_GPIO
V
digital input
ILEAKAGE
Leakage current
10
µA
high impedance
Rpull-up
Pull-up resistance
78
kΩ
GPIOxMode=x0b; GPIOxPulls=10b;
VCURR_GPIO=3.6V
Rpull-down
Pull-down
resistance
161
kΩ
digital input; GPIOxPulls=01b;
VCURR_GPIO=3.6V
PIO.
al
id
VGPIOMAX
Maximum voltage
on
CURR1...4_GPIO
1…4 pins
Min
lv
Parameter
am
lc s
on A
te G
nt
st
il
Symbol
Table 24. CURR1_GPIO1 Bit definition
Addr: 18
Bit Name
This register controls the mode of the CURR1_GPIO1 Pin
Default Access
GPIO1Mode
Te
ch
2…0
ni
ca
Bit
GPIO1
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ROM
R/W
Description
000b
digital open drain NMOS output
(only NMOS enabled)
001b
digital push-pull output
(NMOS & PMOS enabled, no PWM out possible)
010b
digital input
(NMOS & PMOS disabled, digital input logic
enabled)
011b
digital open drain current sink operation Current
defined by curr1_current
100b
digital open drain switch operation On resistance
defined by curr1_current
high impedance (or SD1 in DCDC step
101b
down external controller mode
to
= 1100b)).NMOS & PMOS disabled,
111b (sd1_1A_mode
digital input logic disabled)
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Table 24. CURR1_GPIO1 Bit definition
GPIO1
Addr: 18
GPIO1IOSF
5
ROM
GPIO1Invert
7…6
Description
00b
input / output signal is written to or set by GPIO1Bit
in the GPIO Bit register
01b
PWM (O) / WDOG (I)
if used for PWM, pwm_h_time and pwm_l_time
define the high and low time of this output and only
allowed for GPIO1Mode=011b,100b
10b
Protection of DCDC stepUp1 GPIO 1 (O)
11b
Battery charging EOC indication output GPIO 1 (O)
If EOC=1 then GPIO1=1. DCDC_CURR3 is used as
output, if CURR_GPIO1 is used for external DCDC
controller
0
normal polarity of input / output signal
R/W
am
lc s
on A
te G
nt
st
il
4…3
Default Access
al
id
Bit Name
lv
Bit
This register controls the mode of the CURR1_GPIO1 Pin
ROM
GPIO1Pulls
ROM
R/W
R/W
1
inverted polarity of input / output signal
(not possible for PWM out)
00b
no pull-up or pull-down resistor is enabled in all
modes
01b
pull-down resistor is enabled in digital input mode
(clamp disabled)
10b
pull-up resistor is enabled for
GPIO1Mode=000b,010b,011b,100b (clamp
disabled)
11b
enable active clamp circuit for
GPIO1Mode=000b,010b,011b,100b (pull-up/down
disabled)
Table 25. CURR2_GPIO2 Bit definition
Addr: 19
Bit Name
This register controls the mode of the CURR1_GPIO2 Pin
Default Access
GPIO2Mode
ROM
R/W
Description
000b
digital open drain NMOS output
001b
digital push-pull output (no PWM out possible)
010b
digital input
011b
digital open drain current sink operation Current
defined by curr2_current
100b
digital open drain switch operation On resistance
defined by curr2_current
101b
to
111b
high impedance
Te
ch
2…0
ni
ca
Bit
GPIO2
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Table 25. CURR2_GPIO2 Bit definition
GPIO2
Addr: 19
Bit
This register controls the mode of the CURR1_GPIO2 Pin
Bit Name
Default Access
Description
is written to or set by GPIO2Bit in
00b input / output signal
the GPIO Bit register
GPIO2Invert
7…6
ROM
R/W
R/W
10b
Battery charging active indication output GPIO2 (O)
If Battery charging = 1 then GPIO2=1
11b
NA
0
normal polarity of input / output signal
1
inverted polarity of input / output signal
(not possible for PWM out)
00b
no pull-up or pull-down resistor is enabled in all
modes
01b
pull-down resistor is enabled in digital input mode
(clamp disabled)
am
lc s
on A
te G
nt
st
il
5
ROM
al
id
GPIO2IOSF
PWM (O) / WDOG (I)
if used for PWM, pwm_h_time and pwm_l_time
define the high and low time of this output and only
allowed for GPIO2Mode=011b,100b
lv
4…3
01b
GPIO2Pulls
ROM
R/W
pull-up resistor is enabled for
10b GPIO2Mode=000b,010b,011b,100b
(clamp disabled)
11b
enable active clamp circuit for
GPIO2Mode=000b,010b,011b,100b (pull-up/down
disabled)
Table 26. CURR3_GPIO3 Bit definition
Addr: 20
Bit Name
This register controls the mode of the CURR3_GPIO3 Pin
Default Access
ca
Bit
GPIO3
GPIO3Mode
ROM
R/W
Te
ch
ni
2…0
4…3
GPIO3IOSF
www.austriamicrosystems.com
ROM
R/W
Description
000b
digital open drain NMOS output
001b
digital push-pull output (no PWM out possible)
010b
digital input
011b
digital open drain current sink operation Current
defined by curr3_current
100b
digital open drain switch operation On resistance
defined by curr3_current
101b
to
111b
high impedance
00b
input / output signal is written to or set by GPIO3Bit
in the GPIO Bit register
01b
PWM (O) / WDOG (I)
if used for PWM, pwm_h_time and pwm_l_time
define the high and low time of this output and only
allowed for GPIO2Mode=011b,100b
10b
GPIO3 control of regulators if regX_gpio = 1 and
regX_on = 1
11b
Touchpen ADC wait input
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Table 26. CURR3_GPIO3 Bit definition
GPIO3
Addr: 20
This register controls the mode of the CURR3_GPIO3 Pin
5
GPIO3Invert
ROM
GPIO3Pulls
ROM
R/W
R/W
Description
0
normal polarity of input / output signal
1
inverted polarity of input / output signal
(not possible for PWM out)
00b
no pull-up or pull-down resistor is enabled in all
modes
01b
pull-down resistor is enabled in digital input mode
(clamp disabled)
10b
pull-up resistor is enabled for
GPIO3Mode=000b,010b,011b,100b (clamp
disabled)
11b
enable active clamp circuit for
GPIO3Mode=000b,010b,011b,100b (pull-up/down
disabled)
am
lc s
on A
te G
nt
st
il
7…6
Default Access
al
id
Bit Name
lv
Bit
Table 27. CURR4_GPIO4 Bit definition
Addr: 21
Bit
Bit Name
GPIO4Mode
This register controls the mode of the CURR4_GPIO4 Pin
Default Access
ROM
R/W
GPIO4IOSF
ch
4…3
ni
ca
2…0
GPIO4
Te
5
GPIO4Invert
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ROM
ROM
R/W
R/W
Description
000b
digital open drain NMOS output
001b
digital push-pull output (no PWM out possible)
010b
digital input
011b
digital open drain current sink operation Current
defined by curr4_current
100b
digital open drain switch operation On resistance
defined by curr4_current
101b
to
111b
high impedance
00b
input / output signal is written to or set by GPIO4Bit
in the GPIO Bit register
01b
PWM (O) / WDOG (I)
if used for PWM, pwm_h_time and pwm_l_time
define the high and low time of this output and only
allowed for GPIO4Mode=011b,100b
10b
GPIO4 control of regulators if regX_gpio = 1 and
regX_on = 0
11b
Touchpen dedicated interrupt output
0
normal polarity of input / output signal
1
inverted polarity of input / output signal
(not possible for PWM out)
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Table 27. CURR4_GPIO4 Bit definition
GPIO4
Addr: 21
7…6
GPIO4Pulls
Default Access
ROM
R/W
Description
00b
no pull-up or pull-down resistor is enabled in all
modes
01b
pull-down resistor is enabled in digital input mode
(clamp disabled)
10b
pull-up resistor is enabled for
GPIO4Mode=000b,010b,011b,100b (clamp
disabled)
11b
enable active clamp circuit for
GPIO4Mode=000b,010b,011b,100b (pull-up/down
disabled)
al
id
Bit Name
lv
Bit
This register controls the mode of the CURR4_GPIO4 Pin
Addr: 55
am
lc s
on A
te G
nt
st
il
Table 28. GPIO Signal Bit definition
GPIO Signal
This register controls the GPIO state / status
Bit Name
Default Access
0
GPIO1
0
R/W
This bit determines the output signal of the GPIO1 pin when
selected as output source
1
GPIO2
0
R/W
This bit determines the output signal of the GPIO2 pin when
selected as output source
2
GPIO3
0
R/W
This bit determines the output signal of the GPIO3 pin when
selected as output source
3
GPIO4
0
R/W
This bit determines the output signal of the GPIO4 pin when
selected as output source
4
GPIO1_in
NA
R
This bit reflects the logic level of the GPIO1 pin when
configured as digital input pin
5
GPIO2_in
NA
R
This bit reflects the logic level of the GPIO2 pin when
configured as digital input pin
6
GPIO3_in
NA
R
This bit reflects the logic level of the GPIO3 pin when
configured as digital input pin
7
GPIO4_in
R
This bit reflects the logic level of the GPIO4 pin when
configured as digital input pin
ca
Bit
Te
ch
ni
NA
Description
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The gpio block includes an internal programmable PWM generator (can be connected to any of the GPIO1_CURR1 …
GPIO4_CURR4 outputs). Its timing is defined by the following tables:
Table 29. PWM Frequency Control High Time Registers
PWM Frequency Control High Time Registers
Addr: 56
Bit Name
Default Access
Description
al
id
Bit
This register controls the PWM high time
This bit defines the high time of the pwm generator in
2/fclk_int units
pwm_h_time
00h
R/W
pwm_div * 2/ fclk_int
1
pwm_div * 4/ fclk_int
2
pwm_div * 6/ fclk_int
lv
7:0
0
....
pwm_div * 512/ fclk_int
am
lc s
on A
te G
nt
st
il
FFh
Table 30. PWM Frequency Control Low Time Registers
Addr: 57
Bit
Bit Name
PWM Frequency Control Low Time Registers
This register controls the PWM Low time
Default Access
Description
This bit defines the high time of the pwm generator in
2/fclk_int units
7:0
pwm_l_time
00h
R/W
0
pwm_div * 2/ fclk_int
1
pwm_div * 4/ fclk_int
2
pwm_div * 6/ fclk_int
....
FFh
pwm_div * 512/ fclk_int
Table 31. PWM Divider Registers bits
Bit Name
ni
Bit
pwm_div
ch
7:6
CURR control
This register controls the PWM divider
ca
Addr: 58
Default Access
00h
Description
This bit defines the divider ratio of the prescaler for the
PWM generator
R/W
00
Divide by 1
01
Divide by 2
10
Divide by 4
11
Divide by 16
Te
All Step Down DCDC converters and several LDOs can be directly on/off controlled by CURR3_GPIO3 or
CURR4_GPIO4. The CURR3_GPIO3 and/or CURR4_GPIO4 pin should be set to digital input mode (GPIO3Mode =
010b, GPIO4Mode = 010b) and the following register should be set accordingly:
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- Detailed Description-Power Management Functions
Note: The original digital interface on/off signal is used to switch between CURR3_GPIO3 and CURR4_GPIO4; e.g.
if ldo_rf1_gpio is set, ldo_rf1_on is (re-)used to selected either CURR3_GPIO3 (ldo_rf1_on=1) or
CURR4_GPIO4 (ldo_rf1_on=0) as input.
Table 32. Regulator GPIO Control Registers
Reg GPIO Ctrl
Addr: 31
Bit Name
Default Access
Description
ldo_rf1 on/off control
0
ldo_rf1_gpio
0
R/W
1
Controlled by software (ldo_rf1_on)
Controlled by CURR3_GPIO3, if ldo_rf1_on=1 and
GPIO3IOSF=10b
Controlled by CURR4_GPIO4, if ldo_rf1_on=0 and
GPIO4IOSF=10b
lv
0
al
id
Bit
This register enables/disables GPIO control of the regulators
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ldo_rf2 on/off control
1
ldo_rf2_gpio
0
0
Controlled by software (ldo_rf2_on)
1
Controlled by CURR3_GPIO3, if ldo_rf2_on=1 and
GPIO3IOSF=10b
Controlled by CURR4_GPIO4, if ldo_rf2_on=0 and
GPIO4IOSF=10b
R/W
ldo_dig1 on/off control
2
ldo_dig1_gpio
0
0
Controlled by software (ldo_dig1_on)
1
Controlled by CURR3_GPIO3, if ldo_dig1_on=1 and
GPIO3IOSF=10b
Controlled by CURR4_GPIO4, if ldo_dig1_on=0 and
GPIO4IOSF=10b;
do not set ldo_dig1_gpio if DCDC SD1 is in external
controller mode (sd1_1A_mode = 1100b)
R/W
ldo_dig2 on/off control
ldo_dig2_gpio
0
ni
sd1_gpio
0
Te
5
sd2_gpio
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1
Controlled by CURR3_GPIO3, if ldo_dig2_on=1 and
GPIO3IOSF=10b
Controlled by CURR4_GPIO4, if ldo_dig2_on=0 and
GPIO4IOSF=10b
do not set ldo_dig2_gpio if DCDC SD1 is in external
controller mode (sd1_1A_mode = 1100b)
sd1 on/off control
0
Controlled by software (sd1_on)
1
Controlled by CURR3_GPIO3, if sd1_on=1 and
GPIO3IOSF=10b
Controlled by CURR4_GPIO4, if sd1_on=0 and
GPIO4IOSF=10b
R/W
ch
4
Controlled by software (ldo_dig2_on)
R/W
ca
3
0
sd2 on/off control (or sd2 on/off control in 1A mode)
0
0
Controlled by software (sd2_on)
1
Controlled by CURR3_GPIO3, if sd2_on=1 and
GPIO3IOSF=10b
Controlled by CURR4_GPIO4, if sd2_on=0 and
GPIO4IOSF=10b
R/W
Revision 1v13
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AS3658
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- Detailed Description-Power Management Functions
Table 32. Regulator GPIO Control Registers
Reg GPIO Ctrl
Addr: 31
Bit
This register enables/disables GPIO control of the regulators
Bit Name
Default Access
Description
Sd3 on/off control
sd3_gpio
0
0
Controlled by software (sd3_on)
1
Controlled by CURR3_GPIO3, if sd3_on=1 and
GPIO3IOSF=10b
Controlled by CURR4_GPIO4, if sd3_on=0 and
GPIO4IOSF=10b
R/W
ldo_dig3 on/off control
8.4
0
Controlled by software (ldo_dig3_on)
1
Controlled by CURR3_GPIO3, if ldo_dig3_on=1 and
GPIO3IOSF=10b
Controlled by CURR4_GPIO4, if ldo_dig3_on=0 and
GPIO4IOSF=10b
R/W
lv
ldo_dig3_gpio
0
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6
Backup Battery Charger
The backup battery charger operates as a programmable voltage limited current source with a selectable output
resistor. It is enabled by setting BBCMode in the Backup Battery Charger register to a value other than ‘00’b and offers
the following features:
Backup battery presence detection
Selectable output resistor (RBBCOUT) to reduce the current at higher voltages
Programmable charge current IBBC
programmable maximum charging voltage VBBC
Reverse current protection turns off backup battery charger automatically if VSUPPLY<VVBACK; as soon as VSUPPLY
exceeds VVBACK charging is started again automatically
Charging is stopped automatically as soon as the backup battery is fully charged; if the voltage on pin VBACK
drops charging is started again automatically
Te
ch
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In case the main supply voltage VSUPPLY is larger than VVBACK charging of the backup battery is possible in state
“Off” as well; the device will check VVBACK every minute to determine if charging is required.
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- Detailed Description-Power Management Functions
Figure 10. Backup Battery Charger Block Diagram
Voltage limited
Current source
VBACK
Rb
al
id
VSUPPLY
lv
Digital
Control
Table 33. Backup Battery Charger Characteristics
symbol
Parameter
Min
Typ
Max
VSUPPLY
Supply voltage range
VBBC
Maximum charging
voltage
2.4
2.5
2.6
2.9
3.0
3.1
IBBC
Charge current
-30%
VDELTA
Delta voltage for
resistive mode
160
5.5
3.3
5.5
Note
BBCVolt=’0’
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3.0
Unit
BBCCur +30%
220
300
V
BBCVolt=’1’
BBCVolt=’0’
V
BBCVolt=’1’
A
Value is set by BBCCur in the
Backup Battery Charger register
mV
BBCResOff=’0’
20
IVSUPPLY
30
Supply current
0.5
BBCResOff=’0’
BBCResOff=’1’
µA
BBCPwrSave=’1’; backup battery
full.
Table 34. Backup Battery Charger Register
Addr: 38
ni
BBCMode
ch
1:0
Bit Name
Te
2
4:3
This register controls the Backup battery charger mode
Default Access
ca
Bit
Backup Battery Charger
BBCResOff
00b
0
Description
00b
Backup battery charger is disabled
01b
Backup battery charger is enabled in states “Power
Off mode”, “standby mode” and “Active mode”.
(32kHz OSC has to be enabled in that mode
rtcmode=01b or 10b)
1Xb
Backup battery charger is enabled in state “Active
mode” and “standby mode”. (32kHz OSC has to be
enabled in that mode rtcmode=01b or 10b)
0
Enable output resistor
1
Bypass output resistor
R/W
R/W
This value determines the charge current IBBC.
BBCCur
www.austriamicrosystems.com
00b
R/W
00b
IBBC=50µA
10b
IBBC=200µA
01b
IBBC=100µA
11b
IBBC=400µA
Revision 1v13
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- Detailed Description-Power Management Functions
Table 34. Backup Battery Charger Register
Backup Battery Charger
Addr: 38
Bit
This register controls the Backup battery charger mode
Bit Name
Default Access
Description
This value determines the maximum charging voltage
VBBC.
BBCPwrSave
7
1
R/W
R/W
0
VBBC=2.5V
1
VBBC=3.0V
0
Normal operation of the backup battery charger
1
The backup battery charger checks if it is actually
charging the battery (bit BUChAct=’1’) and it is
disabled if it is not. Every 10s (every 64s in state
“Off”) the voltage of the backup battery is checked
again to determine if charging is required. This
practically reduces the current consumption to 0 if
the backup battery is full.
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6
0
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BBCVolt
lv
5
-
reserved
-
Figure 11. Backup Battery Charger Characteristics
IBACK
400µA
Rb=0N
ca
200µA
Rb=0FF
100µA
VBACK
ni
50µA
Vback_lim
Te
ch
Vback_lim-VDelta
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8.5
- Detailed Description-Power Management Functions
Smooth switchover Power Management Overview
Figure 12. Power Source Management Architecture
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The power source management architecture handles the smooth transitions between the two chargers (USB Charger
on VBUS, DCDC Step Down charger or Linear Charger on VCHARGER) and the battery. It takes care about the
system power supply VSUPPLY and its power requirements.
There are following operating conditions possible
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1. No Charger connected
The internal switch SINT and the (optional) external switch MBATSW are closed and VSUPPLY is directly supplied by
VBAT. Because of the very low impedance of the switches the energy losses are minimized.
2. The active charger can deliver more current than the system requires
The system is directly supplied by the charger and the remaining energy can be used to charge the battery (CC/CV
charger). In case of deeply discharged batteries, the system is always immediately started and the internal current
source between VSUPPLY and VBAT delivers the trickle current to the battery.
3. The current limited (e.g. for USB with 500mA) charger cannot deliver the current, the system requires
In this case, the ideal diode starts conducting and delivers the remaining current to the system
The transitions between the different power states are done autonomously by the AS3658 allowing an uninterrupted
operation of the system.
Te
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The blocks are described in more detail in the following sections.
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8.6
- Detailed Description-Power Management Functions
Battery switch SINT (Vsupply, Battery)
Figure 13. Battery Switch Diagram
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The internal Battery switch enables normal operation of the System during trickle charging of a deeply discharged
battery.
The Switch provides the following functions:
Trickle charging, if VBAT is smaller than ResVolt. The current is defined in TrickleCurrent[1:0]
PMOS is switched on if VBAT is greater then ResVolt.
Constant current charging, if the external charger is in linear operation, or the USB charger is used. the current is
defined by constant_current[2:0].
Current limitation during tricklecharge, to avoid inrush current: Itrickle_Ilimit
Current limitation during Constant current charging to avoid inrush current: ICC_Ilimit
ca
Undervoltage protection of Vsupply during trickle charge or constant current charge with linear charger. The
charging current is regulated down, if Vsupply drops below Vsupply_min
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Ideal diode operation in Isolate Battery mode and disable charging mode, during charger is unplugged. This
operation is for the internal battery switch only. External battery switch is open in that mode. Regulation will start, if
the VSUPPLY voltage drops by more then VDiode below the VBAT voltage. After three milliseconds debounce time,
if no charger is recognized, the internal and external battery switch (if enabled) is closed to have a low Ω ic
connection between VBAT and VSUPPLY.
Table 35. Battery switch parameters
Parameter
Min
VSupply
Input voltage
3.0
Itrickle_limit
Trickle current limit
ICC_limit
Constant current
current limit
Te
Symbol
www.austriamicrosystems.com
Typ
Max
Unit
Note
5.5
V
PIN VSUP_SW1,VSUP_SW2
400
800
mA
mA
Revision 1v13
Current Limit in constant current
mode (Linear charger mode or USB
charger only)
Note: applies only for the battery
switch alone
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- Detailed Description-Power Management Functions
Table 35. Battery switch parameters
Min
VDiode
Ideal Diode start
voltage
Vsupply_min
Vsupply level for
charging current
regulation (reduction),
to avoid voltage drop
on vsupply
Typ
50
Unit
Note
mV
3.9
3.6
-6%
3%
4.2
V
Trickle current (or constant current in
linear mode) will be regulated down,
if vsupply drops below this level
Ω
VSUP_SW=3.6V
4.5
SINT P-Switch ON
resistance
RSW
Max
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Parameter
0.10
Table 36. USB-Charger Bit definitions
USB Charger Control
Bit
5
This register controls the mode of the USB charger, and the charger state
machine
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Addr: 10
Bit Name
dis_batsw_tmp_prot
7
lv
Symbol
ext_batsw_en
Default Access
ROM
ROM
Description
0
Over temperature protection of battery switch
enabled. (If battery switch is in current source mode,
charging is stopped if chip temperature exceeds
110º)
1
Over temperature protection of battery switch
disabled
0
External battery switch disabled (Pin BAT_SW =
max(VSUPPLY,VBAT))
1
External battery switch enabled (Pin BAT_SW=0V, if
status bits batsw_on=1 and batsw_mode=1. These
bits are controlled by the charger state machine)
R/W
R/W
Table 37. Battery switch status Bit definitions
Addr: 100
Bit Name
batsw_mode
ni
2
batsw_on
Default Access
NA
NA
Description
0
Trickle charging (or constant current charging in
linear mode), if batsw_on=1. External PMOS switch
disabled
1
Switch on Battery switch, if batsw_on=1. External
PMOS switch enabled
0
Battery switch off
1
Battery switch on (Mode defined by batsw_mode)
R
R
Te
ch
3
These bits show the status of the battery switch
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Bit
Charger status_usb
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8.7
- Detailed Description-Power Management Functions
External Step Down/Linear Charger
The inductive dcdc step down charger (or the external linear charger) converts the input voltage from VCHARGER to
VSUPPLY. The system (DCDC converters, LDOs…) are connected directly to VSUPPLY; the ideal diode and the internal
battery switch SINT (together with the external battery switch MBATSW) connect VSUPPLY to VBAT to allow charging of
the battery.
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Figure 14. Step Down Charger Application Diagram with optional reverse polarity and short protection
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If the input voltage can be up to 50V additional three transistors and a simple voltage regulator with a zener diode are
required. These circuit ‘isolates’ the AS3658 from the high input voltage and keep the pins VCHARGER, VOFF_B and
VGATE within its operating limits (<15V). The actual circuit is shown in the following figure:
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Figure 15. Charger Block Diagram for voltages >15V (Protection up to 50V; minimum Vcharger voltage 8V)
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Instead of using an inductive DCDC step down charger, the AS3658 supports external linear charging mode with an
PMOS transistor. The operating mode is selected by connecting the pin VOFF_B to GND (for 5.5V limited chargers,
the USB charger can be used alternatively):
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- Detailed Description-Power Management Functions
Figure 16. External Linear Charger Application Diagram (VOFF_B connected to GND)
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Table 38. Charger External Components
Component
Value
MCHARGER,
MBATSW,
MREVPOL
P-channel MOSFET
Si1403, FDC642P or FDC5614P similar
MCHRGPU
P-channel MOSFET
BSS84 or FDG312P or similar
RCHRGPU1
Pull-up resistor1
2kΩ ± 5%
Pull-up resistor2
ni
RCHRGPU2
ca
Symbol
Note
100Ω ± 5%
for MCHRGPU =BSS84
50Ω ± 5%
for MCHRGPU=FDG312P
10µH
5V or 6V Vcharger input
22µH
12V Vcharger input
Inductor for charging
DCHARGER
Diode
MBRS130 or PMEG2010
DCHRGPROT
Zener Diode
5.6V Zener Diode
RCHSHUNT
Current sense resistor
charger
70mΩ ± 5%, 125mW
e.g. Vishay Dale WSL0805
series
RSENSE
Current sense resistor
50mΩ ± 1%, 125mW for IVBAT,DC<1.5A
e.g. Vishay Dale WSL0805
series
RFILTER1,2
Filter resistor
4.7kΩ ± 1%
CFILTER
Filter capacitor
1µF ± 20%, X5R or X7R dielectric
Can be omitted if fuel gauge
and charger functionality is
not used
CCHARGER
Bypass capacitor on
charger pin
1µF ± 20%, X5R or X7R dielectric +
22µF ± 20%, Tantal dielectric
Te
ch
LCHARGER
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Table 38. Charger External Components
Symbol
Component
Value
Note
Minimum total
capacitance parallel to
Vsupply
22µF± 20%, X5R or X7R dielectric
10 µH inductor
CVSUPPLY
47µF± 20%, X5R or X7R dielectric
22 µH inductor
al
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Figure 17. Step down charger Efficiency (Measured) VSupply=4.4V
Step down charger
100
lv
90
70
Vcharger=5V, f=550kHz
60
Vcharger=6V, f=550kHz
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Efficiency (%)
80
Vcharger=12V, f=550kHz
50
Vcharger=5V, f=275kHz
40
Vcharger=6V, f=275kHz
30
Vcharger=12V, f=275kHz
20
10
0
0,0000
0,2000
0,4000
0,6000
0,8000
1,0000
1,2000
Output current (A)
8.7.1 External Step Down/Linear Charger Characteristics
The battery charge controller controls the external Step Down/ Linear charger.
During Trickle charge of the deeply discharged battery the step down/Linear converter regulates the Vsupply to Vchlimit.
ca
In step down charger mode, If the VBAT voltage exceeds ResVoltRise, the internal battery switch is switched on, the
Vsupply voltage drops down to VBAT immediately, and the step down converter operates as controlled current source
to Vsupply. The battery current is regulated to the value defined in ConstantCurrent register.
ni
In linear charger mode, the Vsupply is still regulated to Vchlimit, if the VBAT voltage exceeds ResVoltRise. The current is
regulated by the battery switch to the value defined in the constant current register.
ch
In EOC operation (see Battery Charge Controller on page 51), the operation of the charger depends on the bit
isolate_battery:
If isolate_battery = 1 and EOC the output is regulated to Vchlimit.
If isolate_battery = 0 and EOC the output is not allowed to drop below VEOC (3.6V).
Te
Table 39. Step down Charger parameters
Symbol
Parameter
Min
Typ
Max
Unit
Note
Vrsense_max
Current limit voltage at
Rsense
70
100
130
mV
e.g.: 1.4A for 0.07O sense
resistor typ.
Cout_10
Output capacitor with 10µH
inductor
20
60
µF
X7R ceramic
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Table 39. Step down Charger parameters
Parameter
Min
Cout_22
Output capacitor with 22µH
inductor
Cout_Linear
Output capacitor in linear
mode
L
Inductor
Itrickle_limit
Trickle current limit
Typ
Max
Unit
Note
40
60
µF
X7R ceramic
20
60
µF
X7R ceramic
10/22
µH
(see Table 38)
400
mA
al
id
Symbol
Table 40. Step down Charger Bit definitions
Step Down charger control
Addr: 37
Bit Name
0
sdc_frequ
0
R/W
1
sdc_pon
1
R/W
2
8.8
Default Access
Description
0
fclk_int/4 (use as default, if Vcharger>6V)
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Bit
lv
These bits configures the step down charger
sdc_pass_mode
0
R/W
1
fclk_int/8 (use as default, if Vcharger<6V)
0
Disable 100% PMOS on mode for step down charger
1
Enable 100% PMOS on mode to reduce voltage drop
in low dropout regulation
0
Normal mode of step down charger mode
1
step down charger in pass through mode. Use this
mode with max. 5.5V charger only.
Vsupply=Vcharger in that mode, if no_charging=1.
USB Charger
Figure 18. USB Charger Block Diagram
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Revision 1v13
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AS3658
Data Sheet Confidential
- Detailed Description-Power Management Functions
The AS3658 serves an integrated USB charger for Li+ batteries. The USB Charger is a current and voltage limited
charger, which can be used to charge Li+ batteries directly from the USB supply. The VBAT voltage limit is set by the
register ChVoltEOC (3.9V – 4.25V in 50mV steps; identical for USB charger and step down charger) and the current
limit is set by the register usb_current (94mA to 881mA). The Vsupply voltage limit is set to Vchlimit during trickle and
constant current charging.
al
id
For USB charging, it is recommended to start with a current limit of 94mA and after negotiates via the USB bus (this
has to be done by e.g. the uProcessor directly) a different current setting can be set to speed up charging (e.g.
470mA).
If Bit usb_chgEn=1 in the Boot ROM is set, VSUPPLY can start up with USB supply allowing startup from the USB
supply.
lv
If ChEn=1 and chdet=1 (external charger enabled and connected) the usb_charger will be deactivated automatically.
(The Battery charger overrides the USB charger). It's not possible to use the internal and the external charger in
parallel.
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End of charge of the USB charger is reached, if the current through the battery falls below the value set in the
Tricklecurrent [1:0] register.
Table 41. USB-Charger Bit definitions
USB Charger control
Addr: 10
Bit
This register controls the mode of the USB charger, and the charger state
machine
Bit Name
Default Access
Description
Sets the USB input current limit.
usb_Current
ROM
R/W
Te
ch
ni
ca
3:0
4
usb_chgEn
www.austriamicrosystems.com
(0000)b
94mA (USB low current)
(0001)b
141mA
(0010)b
189mA
(0011)b
237mA
(0100)b
285mA
(0101)b
332mA
(0110)b
380mA
(0111)b
428mA
(1000)b
470mA (USB high current)
(1001)b
517mA
(1010)b
598mA
(1011)b
668mA
(1100)b
759mA
(1101)b
881mA
(1110)b
881mA (do not use)
(1111)b
881mA (do not use)
ON/OFF control of USB charger
ROM
R/W
0
USB charger disabled.
1
USB charger enabled.
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Table 41. USB-Charger Bit definitions
USB Charger control
Addr: 10
5
Default Access
dis_batsw_tmp_prot
no_charging
7
0
Overtemperature protection of battery switch
enabled. (If battery switch is in current
source mode, charging is stopped if chip
temperature exceeds 110ºC)
1
Overtemperature protection of battery switch
disabled
0
Normal battery charger operation (usb
charger and/or step down charger)
1
USB and Step down charger is supplying
VSUPPLY, but battery switch is open.
USB charger or external charger regulate to
Vchlimit
R/W
ROM
R/W
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ROM
Description
al
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Bit Name
lv
Bit
This register controls the mode of the USB charger, and the charger state
machine
ext_batsw_en
ROM
0
External battery switch disabled (Pin
BAT_SW= VSUPPLY,VBAT)
1
External battery switch enabled (Pin
BAT_SW=0V, if status bits batsw_on=1 and
batsw_mode=1. These bits are controlled by
the charger state machine)
R/W
Table 42. Charger status Bit definitions
Addr:100
Charger status_usb
These bits show the status of the USB charger
Bit
Bit Name
Default
Access
Description
0
USB_ChDet
NA
R
set to 1 if charger is detected
1
USB_Chact
NA
R
Set to 1 if charger is active
4
Ch_overvoltage
NA
R
Set to 1 if overvoltage on pin VCHARGER is applied
Charger Detection:
ca
The Charger will be detected by comparison of the V_USB voltage with the Vsupply voltage.
If V_USB is 50mV higher than VSupply voltage or V_USB > 4.3V or the USB_ChDet is set to 1.
Table 43. USB Charger Characteristics,VUSB=4.3…5.5V; Tamb=–20…+85°C; unless otherwise specified.
Parameter
Min
Typ
Min
Unit
Note
USBcurrent for 500mA
selection
440
470
500
mA
Resistor on pin RBias to ground of
220kΩ
84
95
104
mA
Resistor on pin RBias to ground of
220kΩ
ni
Symbol
ch
Iusbcurrent500mA
USBcurrent for 100mA
selection
Te
Iusbcurrent100A
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- Detailed Description-Power Management Functions
Table 44. USB-Charger additional trimming
USB Current control
Addr:130
Bit
This register adds or subtracts current limit
Bit Name
Default Access
Description
00h
R/W
101
usbcurrent-3.8%
110
usbcurrent-2.5%
111
usbcurrent-1.2%
000
usbcurrent+0%
001
usbcurrent+1.2%
010
usbcurrent+2.5%
011
8.9
lv
usb_add_trim_current
usbcurrent-5.1%
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100
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Increase or decrease The USB current limit for additional in
system trimming:
usbcurrent+3.8%
Battery Charge Controller
The AS3658 device serves as a standalone battery charge controller supporting rechargeable lithium ion (Li+) and
nickel metal hybrid (NiMH) batteries. Requiring only a few external components, a full-featured battery charger with a
high degree of flexibility can easily be realized. The main features of the controller are:
Charge adapter detection
Charging of deeply discharged batteries
Low current (trickle) charging
Real constant current charging by regulation of the battery current instead of the charge current
2 different top-off charging modes: Pulse charging and constant voltage charging
Fuel gauge enables highly accurate remaining capacity estimation of the battery
Overvoltage protection for charge adapter input and main battery
Battery presence indication
Operation without battery
Reverse polarity and short protection
ca
Charging timout timer
Battery NTC supervision
ni
8.9.1 Charge Controller Operating Modes and Building Blocks
Linear Step down Charger detection
ch
The charging circuit automatically detects, if a step down charger or a linear charger is connected externally, by
measuring the voltage on the pin VOFF_B. If this pin is tied to GND, the circuit detects a linear charger. Otherwise the
step down charger is detected
Te
Charge adapter detection
The charge controller uses an integrated detection circuit to determine if an external charge adapter has been applied
to the VCHARGER or V_USB pin. If the adapter voltage exceeds the supply voltage at pin V_SUPPLY5 by VCHDET the
ChDet or USB_CHDet bit in the Charger Status register will be set. The detection circuit will reset the charge controller
(ChDet or USB_CHDet is cleared) as soon as the voltage at the VCHARGER or USB_CHDet pin drops to only VCHMIN
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above the battery voltage. In case the AS3658 device is reset the charge controller will also be reset, even if a charge
adapter is applied to the VCHARGER or V_USB pin.
Charging deeply discharged batteries
al
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To be able to charge even completely discharged batteries the AS3658 device contains an internal voltage regulator
that uses the voltage of the external charge adapter at pin VCHARGER or V_USB to generate a bootstrap voltage
V2_5V to supply the internal circuitry necessary for charging. As soon as the battery voltage exceeds 2.5V, the
bootstrap regulator is disabled and the battery voltage will be used to generate the internal supply voltage to supply the
charger circuitry.
Low current (trickle) charging
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Trickle charge mode is started when an external charge adapter has been detected and ChEn or usb_chgEn is set,
and the battery voltage at pin V_BAT is below the ResVoltRise threshold VRESRISE. The Battery switch is open in that
case (batsw_on=1 batsw_mode=0). Bits ChAct and/or USBChAct and Trickle will be set in the Charger Status
registers. In this mode the charge current into the battery will be limited to TrickleCurrent (set in the Charger Current
register) by the battery switch to prevent undue stress on either the battery or any of the charger components in case
of deeply discharged batteries. if Vsupply drops below Vsupply_min threshold the trickle current is regulated down, to
keep the Vsupply voltage up, even with an current limited charger (e.g.:USB charger). Once VRESRISE has been
exceeded, the battery switch will be closed and the charge controller will proceed to constant current charge mode.
The Vsupply voltage of the step down charger will be set to Vcurr_preset to prevent undervoltage on vsupply during
the transition between Trickle and constant current charging.
Constant current charging
Constant current charging is initiated by setting bit ChEn and/or USBChEn in the Charger Control register, and
resetting the No_charging bit. Note that ChEn and/or USBChEn should be set by default to enable operation of the
device without a battery connected to the system. The ChAct and/or USBChAct bit is set when the charger has started,
and the charge current into the battery will be limited to ConstantCurrent (set in the Charger Current register) by the
battery charge controller. When the battery approaches full charge, its instantaneous voltage will exceed the charge
termination threshold VCHOFF. VCHOFF depends on the ChVoltEOC.The top-off charge mode will be started (bit CVM
will be set).
Constant voltage charging
Constant voltage charge mode is initiated and the CVM bit will be set when the VCHOFF threshold has been exceeded
for the first time and bit Pulse is not set. In the following the charge controller will act to regulate the battery voltage to
a value set by ChVoltEOC in the Charger Config register.
ni
ca
The charge current is monitored during constant voltage charging. It will be decreasing from its initial value during
constant current charging and eventually drop below the value set by TrickleCurrent in the Charger Current register. If
the measured charge current is less than or equal to TrickleCurrent and the battery voltage is larger than VCHRES, the
charging cycle is terminated and EOC is set. Then the charge controller starts the EOC operation.
EOC operation
ch
There are two possibilities:
Te
1. If isolate_bat=1 the battery switch will be switch off and the battery charger regulates to its highest voltage Vchlimit..
The advantage of this mode is a longer lifetime of the Li+ battery, because there is no discharging after the EOC
condition. If autoresume=1 and the battery voltage drops below VCHRES the battery charger continues charging, by
checking in trickle charge mode, if there is a battery connected, and then starting with constant voltage.
2. If isolate_bat=0 the battery switch remains closed for step down charger or will be closed for linear and usb charger,
and the power to the system is supplied by the battery. The battery charger and the USB charger regulates to VEOC,
in case the battery is removed. If autoresume=1 and the battery voltage drops below VCHRES the battery charger
continues charging, by checking in trickle charge mode, if there is a battery connected, and then starting with
battery charging.
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Battery Detection and Restart of Charging:
al
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In EOC state, If the battery voltage drops below VCHRES and the bit AutoResume is set, the battery detection is
started. The battery switch will be switched into current source mode and VSUPPLY will be regulated to Vchlimit (all
charger). The AS3658 measured the battery current with the fuel gauge in this mode. If there is no current, the AS3658
is kept in this state and the bit NoBat is set. Otherwise the bit NoBat is cleared and the charger and the AS3658
continues in battery charging mode. In addition, if the ntc_on<1:0>=01b (NTC temperature supervision is active) the
NoBat bit is cleared and charging is restarted, if a NTC resistor with normal or high temperature is detected.
Overvoltage protection for external linear charger:
lv
During charging with the external linear charger the battery charge controller constantly monitors the voltage of the
charge adapter at pin VCHARGER. In case the charge adapter voltage exceeds VVCHIN,MAX rise for longer than
3mesec and bit ChOVDetEn in the Charger Control register is set to 1, charging is disabled immediately. If the voltage
on the pin VCHARGER drops below VVCHIN,MAX fall, the charger is re-enabled.
Figure 19. Typical charging cycle (step down charger)
VCHARGER = 6V
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VSUPPLY = 4.4V (isolate_bat=1)
VSUPPLY = 4.2V (isolate_bat=0)
VBAT = 4.2V
VSUPPLY = 4.4V
VBAT = 2V
VBAT = Vres_rise (e.g: 3.4V)
IBAT = ConstantCurrent (e.g 700mA)
Constantvoltage
IBAT = 0mA
IBAT = TrickleCurrent (e.g 200mA)
EOC
CH_DET = 0
ca
CH_DET = 1
I2C Write
NO_CHARGING = 0
Te
ch
ni
NO_CHARGING = 1
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Figure 20. Typical charging cycle (External linear charger or USB charger)
VCHARGER = 6V
VSUPPLY = 4.4V...5.0V (isolate_bat=1)
VSUPPLY = 4.4V..5.0V
VSUPPLY = 4.2V (isolate_bat=0)
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VBAT = 4.2V
IBAT = ConstantCurrent (e.g 700mA)
lv
VBAT = Vres_rise (e.g: 3.4V)
VBAT = 2V
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Constantvoltage
IBAT = TrickleCurrent (e.g 200mA)
IBAT = 0mA
EOC
CH_DET = 1
CH_DET = 0
I2C Write
NO_CHARGING = 1
NO_CHARGING = 0
Table 45. Charger Characteristics VVBAT=3.0…5.5V; Tamb=–20…+85°C; unless otherwise specified
Parameter
Min
Typ
Min
Unit
Note
Vchlimit
Voltage limit of charger
(if not in current
limitation mode)
-3%
ch_volt
age
3%
V
Max. Vsupply voltage
15.0
V
For input voltage higher than 15V see
above protection circuit; for chargers with
input voltages down to 4.5V see:
‘Application Note for DC/DC Step down
Charger for
Chargers Supplying 4.5V to 5.5V’
ca
Symbol
VCHDET
Charge adapter
detection threshold
ch
VCHMIN
ni
VCHARGER VCHARGER operating
range
Charge adapter
detection hold voltage
Te
VCHMIN_hold
Vchin,max
rise
Vchin,max fall
Charger adapter
overvoltage threshold
rising
Charger adapter
overvoltage threshold
falling
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5.0
50
75
105
mV
0
20
35
mV
Hysteresis is > 40mV; for USB and step
down charger
-5
-20
-40
mV
Vchdet falling threshold, if
VSUPPLY>4.35V for V_USB and
VCHARGER, and for V_USB, if
usb_hold_chdet=1. Warning:
Backcharging is possible if
usb_hold_chdet=1
6.0
6.5
7.0
V
ChOVDetEn=’1’ for external linear
charger only
V
ChOVDetEn=’1’ for external linear
charger only
6.0
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Table 45. Charger Characteristics VVBAT=3.0…5.5V; Tamb=–20…+85°C; unless otherwise specified
Symbol
Parameter
Typ
Min
Unit
ISTARTmax
Maximum load current
during startup on
Vsupply
VUVLO
Undervoltage lockout
threshold
–3%
2.7…
3.4
+3%
V
Value is set by ResVoltRise in the Battery
Voltage Monitor register
VCHOFF
Charge termination
threshold
–0.06
3.90…
4.25
+0.06
V
Li+ battery; value is set by ChVoltEOC in
the Charger Config register
VCHRES
Charger resume
voltage
V
Value is set by ChVoltResume in the
Charger Config register. Do not set
VCHRES higher than VCHOFF!
Vcurr_preset
Charger constant
current pre-set voltage
VEOC
Charger EOC voltage
mA
3.85…
4.20
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5
Note
lv
Min
VRESRI
SE
V
3.60
V
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+
100mV
If isolate_bat=0; to prevent a system reset
if the battery is removed in EOC operation
Table 46. Charger status Bit definitions
Addr:99
Charger status
These bits show the status of the charger
Bit Name
Default
Access
Description
0
ChDet
NA
R
Bit is set when external charge adapter has been
detected on pin VCHARGER
1
ChAct
NA
R
Bit is set when step down charger is operating
(independent of Reg. bit no_charging)
2
Resume
NA
R
Bit is set when battery voltage has dropped below resume
level
3
Trickle
NA
R
Bit is set when charger is in trickle charge mode
4
CVM
NA
R
Bit is set when charger is in top-off charge mode
(constant voltage mode)
5
EOC
R
Bit is set when charging has been terminated. Bit is
cleared automatically when ChEn is cleared, no_charging
is set or charging is resumed.
NA
R
Bit is set when battery detection circuit indicates that no
battery is connected to the system. Detection is started
after EOC and if bit autoresume=1 only. Bit is cleared
automatically when a battery is connected, when DisBDet
is set and/or when ChEn is cleared.
NA
R
Bit is set, if Linear charger is detected, and chDet=1. This
state is latched on the rising edge of chDet. Detected if
VOFF_B is connected to ground
ni
NoBat
ch
6
ca
Bit
ChLinear
Te
7
NA
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Table 47. Charger control Bit definitions
Charger Control1
Addr:11
0
Default Access
ChEn
Ch_pwroff_en
ROM
0
Disable step down charger (Independent of bit
no_charging)
1
Enable step down charger (default) (Independent
of bit no_charging)
0
Startup of AS3658 if charger is connected in
power_off mode
1
Don't exit power off mode, if charger is already
connected before entering power off mode; no
autonomous charging upon static charger detect.
Startup with rising edge of VCHARGER or V_USB,
RTC wakeup and XON pin only
0
Overvoltage detection with linear external charger
enabled
1
Overvoltage detection with linear external charger
enabled. Battery charging disabled, if voltage
exceeded
0
Charging does not restart automatically in EOC
when bit Resume is set.
1
Charging will restart automatically in EOC when bit
Resume is set
0
Normal charge_detect operation
1
Charger detect of USB charger will not be reset, if
VUSB=VBAT. (Allow Battery charging, with
V_USB<4.4V down to 3.3V); for this case, software
should detect the removal of the charger
0
Read: no timeout
reached
Write: reset charger timeout counter
1
tCHARGING,MAX timeout reached and charging
stopped
R/W
R/W
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ROM
Description
al
id
Bit Name
lv
Bit
These bits controls the charger
2
CHOVDetEn
3
AutoResume
4
usb_hold_chdet
charging_tmax
ROM
ROM
ROM
ca
5
ROM
Ch_det_500ms
ROM
R/W
R/W
R/W
R/W
Controls the charge detect debounce timer on pin
VCHARGER, if external charger is connected. (If the
charger is removed the debounce time is always 3msec)
0
VCHARGER debounce timer is 3msec
1
VCHARGER debounce timer is 500msec
Te
ch
ni
6
R/W
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Table 48. Battery, supply voltage Bit definitions
Battery voltage monitor
Addr:12
Bit
These bits controls the battery/Supply voltage monitor (Reset levels)
Bit Name
Default Access
Description
ROM
(101b)
R/W
001b
VRESRISE=2.8V
010b
VRESRISE=2.9V
011b
VRESRISE=3.0V
100b
VRESRISE=3.1V
101b
VRESRISE=3.2V
lv
ResVoltRise
VRESRISE=2.7V
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2:0
000b
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This value determines the reset level VRESRISE for rising
VBAT. It is recommended to set this value at least 200mV
higher than VRESFALL.
110b
VRESRISE=3.3V
111b
VRESRISE=3.4V
This value determines the reset level VRESFALL for falling
VVBAT. It is recommended to set this value at least 200mV
lower than VRESRISE.
ResVoltFall
SupResEn
ni
6
FastResEn
ROM
(0b)
ROM
R/W
VRESFALL=2.7V
001b
VRESFALL=2.8V
010b
VRESFALL=2.9V
011b
VRESFALL=3.0V
100b
VRESFALL=3.1V
101b
VRESFALL=3.2V
110b
VRESFALL=3.3V
111b
VRESFALL=3.4V
0
A reset is generated if Vsupply falls below 2.7V.
(If VVBAT falls below VRESFALL only an interrupt is
generated (if enabled) and the Processor can shut
down the system)
R/W
R/W
1
A reset is generated if Vsupply falls below
VRESFALL
0
Vresetfall debounce time = 3msec
1
Vresetfall debounce time = 4µsec
Te
ch
7
ROM
(011b)
ca
5:3
000b
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Table 49. Charger Config Register
Charger Config
Addr:13
Bit
These bits configure the charger
Bit Name
Default Access
Description
ROM
001b
3.95V
010b
4.00V
011b
4.05V
100b
4.10V
101b
4.15V
110b
4.20V
111b
4.25V
lv
ChVoltEOC
3.90V
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2:0
000b
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Sets the end-of-charge voltage level VCHOFF.
Regulate down battery charging current on that level of
Vsupply during trickle charging and/or linear charging, to
prevent voltage drop on vsupply:
4:3
Vsupply_min
ROM
00b
3.90V
01b
3.60V
10b
4.20V
11b
4.50V
Sets the resume voltage level VCHRES
ChVoltResume
3.85V
001b
3.90V
010b
3.95V
011b
4.00V
100b
4.05V
101b
4.10V
110b
4.15V
111b
4.20V
ni
8.9.2 Fuel Gauge
ROM
ca
7:5
000b
The fuel gauge circuit enables remaining capacity estimation of the battery by tracking the net current flow into and out
of the battery using a voltage-to-frequency converter.
ch
Voltage-to-Frequency Converter
Te
The voltage-to-frequency (VFC) converter constantly monitors the voltage drop across an external current sense
resistor Rsense connected in series between the negative battery terminal and ground. The use of an additional
external RC lowpass filter is highly recommended. Using two 4.7kΩ resistors (Rfilt1,2) and a 1µF ceramic capacitor
(Cfilt), the filter cut-off is approximately 16.9 Hz. This filter will capture the effect of most spikes, and will thus allow the
current accumulators to accurately reflect the total charge that has gone into or out of the battery.
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The key building block of the VFC is an integrator. It will integrate the voltage VSNS across input pins ISENSP and
ISENSN. If VSNS is positive (battery is charged), the output voltage of the integrator increases; a negative input voltage
(battery is discharged) will cause the integrator output voltage to decrease.
Table 50. Fuel Gauge parameters
Typ
Max
Unit
Note
fCLK
Internal reference
clock
fclk_int/
2
MHz
internal CLK frequency/2
Programmable: 0.8 to 1.15 MHz
fVFC
Sample frequency
fCLK/59
Hz
VISENSP
VISENSN
Input voltage
-0.1
ZISENSP
ZISENSN
Input impedance
4.67
AVFC
Discharge and Charge
gain
91.0
Hz / V
FRVFC
Fundamental rate
3.05
µVh
VOFF
Uncompensated offset
voltage
-500
VOFF,COMP
Compensated offset
voltage
-50
0.1
V
MΩ
fCLK = 1.1MHz
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Min
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Parameter
lv
Symbol
500
µV
±10
50
Charge Current Accumulator
The output signals of the charge count dividers are used as inputs for the charge current accumulator that is realized
as a 15-bit up-down counter with separate inputs for incrementing and decrementing the counter. An additional sign bit
indicates the polarity of the counter value that is maintained in two’s complement format. The current accumulator is
updated at a rate equivalent to one count per 3.05µVh, which is equivalent to one count per 61.03µAh when using a
50mΩ current sense resistor. It will roll over beyond (7FFF)h when incremented and (0000)h when decremented, and
the value given by the counter will be ambiguous in that case. It is the responsibility of the host to read the counter
before rollover occurs.
ca
The content of the charge current accumulator will be transferred into the DeltaCharge register when the UpdReq bit in
the FuelGauge register has been set. The update of the register has to be synchronized to the sample clock fVFC and
can take up to 1.5 clock cycles (max. 2.5µs). After the registers have been updated successfully, the UpdReq bit is
cleared automatically and the charge current accumulator together with the sign bit will be reset.
Elapsed Time Counter
ni
The sample clock fVFC of the fuel gauge circuit is fed to a 14-bit clock count divider. Its output signal is used as a
clocking signal for the 16-bit elapsed time counter, resulting in an equivalent rate of 1.1379 counts per second
(4096.60 counts = 1 hour). The elapsed time counter will rollover beyond (FFFF)h, and the value given by the counter
will be ambiguous in that case. It is the responsibility of the host to read the counter before rollover occurs.
Te
ch
The content of the elapsed time counter will be transferred into the ElapsedTime register when the UpdReq bit in the
FuelGauge register has been set. The update of the register has to be synchronized to the sample clock fVFC and can
take up to 1.5 clock cycles (max. 2.5µs). After the registers have been updated successfully, the UpdReq bit is cleared
automatically and the elapsed time counter will be reset.
Offset Calibration Mode
Although the VFC compensates for the offset of the integrator the fuel gauge features an additional offset calibration
mode to enhance the measurement accuracy even further. By setting the CalReq bit in the FuelGauge register the
integrator is reset and the offset calibration mode is activated. The charge count dividers are bypassed during offset
calibration to allow a faster calibration procedure with adequate resolution. The offset is accumulated during 16 clocks
of the elapsed time counter, the resulting offset calibration value FGOffCal has a resolution of 3.05µV and is
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transferred to the DeltaCharge register. The CalReq bit is cleared automatically after the calibration has completed
successfully and FGOffCal has been written to the register.
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Please note that offset calibration is not possible while the charger is active. If the CalReq bit is set while the charger is
active the calibration will start automatically after the charger has been disabled by clearing the ChEn bit or if the
external charge adapter has been removed. If during an offset calibration procedure the charger is enabled the offset
calibration mode is terminated, the CalReq bit is cleared, the current value of the elapsed time counter is transferred to
the ElapsedTime register and the DeltaCharge register is loaded with (FFFF)h.
Calculation of Battery Status
The host system can calculate all the parameters necessary for estimating the remaining battery capacity by
evaluating ElapsedTime, DeltaCharge and FGOffCal.
Calculating Elapsed Time
am
lc s
on A
te G
nt
st
il
Δt = ElapsedTime x 3600 / 4096.60 [s]
lv
The host system can evaluate the change in time Δt by setting the UpdReq bit in the FuelGauge register and reading
ElapsedTime after UpdReq has been automatically cleared. The change in time in seconds is given by:
(EQ 1)
Note that the absolute accuracy of Δt is directly related to the absolute accuracy of the internal reference oscillator. To
cancel the error associated with the accuracy of the oscillator, a correction factor CV can be introduced. CV can be
evaluated by comparing the change in time calculated by (1) with some reference value ΔtREF obtained from a RTC or
measured during system calibration. CV is given by:
CV = ΔtREF / Δt
(EQ 2)
By multiplying Δt and CV the correct value for the change in time can be calculated:
ΔtCORR = CV x Δt [s]
(EQ 3)
Calculating Average Current
The host system can calculate the average current during the last time period by setting the UpdReq bit in the
FuelGauge register and reading DeltaCharge and ElapsedTime after UpdReq has been automatically cleared.
Together with FGOffCal determined during offset calibration mode the average current is given by:
IAVG = DeltaCharge / (Δt x AVFC x Rsense) – FGOffCal x 3.05µV / Rsense [A]
(EQ 4)
ca
Δt is the change in time in seconds calculated by (1), AVFC is the gain of the VFC in Hz/V, Rsense is the value of the
sense resistor in Ω and FGOffCal is the offset calibration value. As DeltaCharge and Δt both are proportional to the
oscillator frequency, no correction factor needs to be introduced in the formula.
Calculating Accumulated Current
ni
Accumulated current is used to calculate the absolute remaining capacity of the battery. It is given by:
IACC = IAVG x ΔtCORR [A]
(EQ 5)
ch
Calculating the Remaining Capacity
Remaining capacity is the entire goal of fuel gauging. It is given by:
(EQ 6)
Revision 1v13
60 - 157
Te
RC = RC + IACC [As]
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Calculating the Time to Empty
The time to empty is calculated from the average current IAVG given by (4). The longer the time period for which IAVG is
calculated, the more accurate the value for IAVG and therefore the estimated time to empty will be. It is given by:
TTE = RC / IAVG [s]
(EQ 7)
Fuel Gauge
Addr:15
These bits configures the fuel gauge
Bit Name
0
FGEn
UpdReq
ROM
ROM
R/W
R/W
Description
0
Disable Fuel Gauge
1
Enable Fuel Gauge
This bit controls the update of the DeltaCharge and
ElapsedTime registers. When set, the bit is cleared
automatically after the registers have been updated
successfully. Bit should not be set to “0” by the host
am
lc s
on A
te G
nt
st
il
1
Default Access
lv
Bit
al
id
Table 51. Fuel Gauge Bit definitions
0
Update of registers complete
1
Request update of registers
This bit controls the offset calibration. When set, the bit is
cleared automatically after the calibration has completed
successfully.
2
CalReq
ROM
R/W
0
Calibration complete OR terminate offset
calibration
1
Request offset calibration
Sets the mode for offset calibration
4:3
CalMod
ROM
R/W
00
Connect inputs to ground internally
01
Use ISENSP and ISENSN (do not use)
10
do not use
11
do not use
Table 52. Delta Charger MSB bit definitions
ca
DeltaChargeMSB
Addr:101
Default
Access
Description
DeltaChargeMSB
(00)h
R
The register is maintained in two’s complement format
with a resolution of 3.05µVh and a full-scale value of
±99.98mVh. When using a 50mΩ current sense resistor
this is equivalent to a resolution of 61.03µAh and a fullscale value of 1.999Ah. Sign is set for negative values.
Register will be updated after setting bit UpdReq to “1”.
sign
0
R
Sign bit of the delta charge register
ch
6:0
Bit Name
ni
Bit
These bits represent the MSB value of the fuel gauge Delta charge
register
Te
7
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Table 53. DeltaChargerLSB bit definitions
DeltaChargeLSB
Addr:102
Bit Name
7:0
DeltaChargeLSB
Default
Access
Description
R
The register is maintained in two’s complement format
with a resolution of 3.05µVh and a full-scale value of
±99.98mVh. When using a 50mΩ current sense resistor
this is equivalent to a resolution of 61.03µAh and a fullscale value of 1.999Ah. Sign is set for negative values.
Register will be updated after setting bit UpdReq to “1”.
(00)h
al
id
Bit
These bits represent the LSB value of the fuel gauge Delta charge
register
ElapsedTimeMSB
Addr:103
lv
Table 54. ElapsedTimeMSB bit definitions
These bits represent the MSB value of the fuel gauge Elapsed Time
register
Bit Name
Default Access
Description
6:0
ElapsedTimeMSB
(00)h
R
The elapsed time count is stored in the register with a
resolution of 0.8788s and a full-scale value of 15.997 hours.
Register will be updated after setting bit UpdReq to “1”.
7
sign
0
R
Sign bit of the elapsed time register
am
lc s
on A
te G
nt
st
il
Bit
Table 55. ElapsedTimeLSB bit definitions
ElapsedTimeLSB
Addr:104
These bits represent the LSB value of the fuel gauge Elapsed Time
register
Bit
Bit Name
7:0
ElapsedTimeLSB
Default Access
(00)h
R
Description
The elapsed time count is stored in the register with a
resolution of 0.8788s and a full-scale value of 15.997 hours.
Register will be updated after setting bit UpdReq to “1”.
8.9.3 Charger Operation
ca
The charger controls the battery current through the internal transistor between VSUP_SW1,2 and VBAT_SW1,2, the
step down charger and the battery switch between VSUPPLY and VBAT.
Charge Current Regulator
ni
The regulator is programmed by setting TrickleCurrent and ConstantCurrent in the ChargerCurrent register and yields
a resolution of 0.625mV or 12.5mA when using a sense resistor of 50mΩ.
Table 56. Charge Current Regulator parameters
Parameter
ch
Symbol
tMEAS
Measurement period
Typ
Max
Unit
68.65
ms
0.625
mV
Note
fclk_int = 2.2MHz
Te
IMEAS,LSB
Min
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Table 57. Charger Current Bit definitions
Charger current
Addr:16
Bit
These bits define the battery charging current and voltage
Bit Name
Default Access
Description
-1
TrickleCurrent
ROM
R/W
1.25mV x Rsense
01b
2.50mV x Rsense
10b
5.00mV x Rsense
11b
10.0mV x Rsense
-1
-1
-1
lv
1:0
-1
00b
al
id
Sets the trickle current. Default is (01)b = 2.5mV x Rsense .
Sets the charging current in constant current mode
-1
from (0mV…35mV) x Rsense in steps of 5mV x
am
lc s
on A
te G
nt
st
il
-1
Rsense .
4:2
ConstantCurrent
ROM
R/W
-1
000
0mV x Rsense
001
5mV x Rsense
-1
....
111
35mV x Rsense
-1
Charger voltage after EOC and isolate_battery=1
7:5
ROM
ca
8.10
ch_voltage
R/W
000b
4.3V
001b
4.4V
010b
4.5V
011b
4.6V
100b
4.7V
101b
4.8V
110b
4.9V
111b
5.0V
Charger supervision functions
ch
ni
The charger supervision functions allow charging without processor control by continuously checking the NTC
temperature resistor within the battery pack using ADC_IN1 pin. The charging cycle is automatically paused, if the
NTC indicates a temperature range out of 0º to 45º (or 0º to 50º). If the temperature gets into this range again the
charging cycle is resumed.
In addition there is a charge timer that stops charging after a defined time, as additional security feature.
Te
The timer will be reset at charger insertion (charger detect) or at EOC state. The timer is counting during active
charging only (Trickle charging, Constant current charging, Constant voltage charging).
In case the battery voltage does not reach EOC voltage within tCHARGINGMAX after charging has been started,
charging_tmax interrupt will be generated and charging will be stopped. Charging can be started again by writing
charging_tmax=0 in the charger_control1 register.
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Figure 21. Charger Supervision functions – internal circuit
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8 %,
Table 58. NTC Chargersupervision Characteristics, VVBAT=3.0…5.5V; Tamb=–20…+85°C; unless otherwise
specified.
Symbol
Parameter
Min
Typ
Max
Unit
Note
Sample time for NTC
measurement high or
low temperature
33
ms
Alternating measurement of the NTC
sensor for high temperature and low
temperature with two different
currents
Vcomp
Comparator threshold
for high and low
temperature
measurement
1.8
V
On pin ADC_IN1, if ntc_on<1:0>=1
µA
ntc_type=0, ntc_high_temp=0,
@ 1.8V threshold
ca
tsample
-7%
High temperature
IHightemp50deg_1 current for 50 deg limit,
0k
10k NTC
-7%
ch
ni
High temperature
IHightemp45deg_1 current for 45 deg limit,
0k
10k NTC
Te
High temperature
IHightemp0deg_10k current for 0 deg limit,
10k NTC
High temperature
IHightemp45deg_1 current for 45 deg limit,
00k
100k NTC
Low temperature
ILowtemp50deg_10 current for 50 deg limit,
0k
100k NTC
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388
+7%
4.64
457
kΩ
+7%
µA
3.94
kΩ
60.5
µA
29.7
kΩ
39.2
µA
4.59
kΩ
46.8
µA
38.5
kΩ
Revision 1v13
ntc_type=0, ntc_high_temp=1,
@ 1.8V threshold
ntc_type=0
@ 1.8V threshold
ntc_type=1, ntc_high_temp=0,
@ 1.8V threshold
ntc_type=1, ntc_high_temp=1,
@ 1.8V threshold
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Table 58. NTC Chargersupervision Characteristics, VVBAT=3.0…5.5V; Tamb=–20…+85°C; unless otherwise
specified.
Parameter
Min
Typ
Low temperature
ILowtemp0deg_100 current for 0 deg limit,
k
100k NTC
Hystereses
NTC Current
hystereses
IHightempADC_10k
Current for ADC
measurement High
temp range, 10k NTC
IHightempADC_100
Current for ADC
measurement High
temp range, 100k NTC
ILowtempADC_10k
ILowtempADC_100
k
Unit
Note
6.32
µA
284
kΩ
ntc_type=1
@ 1.8V threshold
±4%
(approx. 1º .), ntc_hyst=0
±8%
(approx. 2º.), ntc_hyst=1
ntc_on<1:0>=2, ntc_type=0,
ntc_high_temp=0
23.6
µA
ntc_on<1:0>=2, ntc_type=1,
ntc_high_temp=0
Current for ADC
measurement Low
temp range, 10k NTC
36
µA
ntc_on<1:0>=3, ntc_type=0,
ntc_high_temp=0
Current for ADC
measurement Low
temp range, 100k NTC
3.7
234
+7%
lv
µA
-7%
am
lc s
on A
te G
nt
st
il
k
Max
al
id
Symbol
µA
ntc_on<1:0>=3, ntc_type=1,
ntc_high_temp=0
Table 59. Charger supervision bit definitions
Addr:14
Bit
Bit Name
Charger supervision
These bits define charging timer and battery temp. supervision settings
Default Access
Description
ca
Charging timeout timer
ch_timeout
ROM
R/W
Te
ch
ni
3:0
4
auto_shutdown
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ROM
0000b
Charging timeout disabled
0001b
1 hour
0010b
1.5 hour
0011b
2 hour
0100b
2.5 hour
0101b
3 hour
0110b
3.5 hour
0111b
4 hour
1000b
4.5 hour
1001b
5 hour
1010b
5.5 hour
1011b
6 hour
1100b
6.5 hour
1101b
7 hour
1110b
7.5 hour
1111b
8 hour
0
Revision 1v13
(see Reset generator and XON-Key on page 118)
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Table 59. Charger supervision bit definitions
Charger supervision
Addr:14
Bit
These bits define charging timer and battery temp. supervision settings
Bit Name
Default Access
Description
5
ntc_high_temp
ROM
R/W
0
45 º maximum temp
1
50º maximum temp
Low temp is always 0º
al
id
Selects the high temp level:
Selects the NTC temperature hysteresis
ntc_hyst
ROM
R/W
0
2º hysteresis
1
1º hysteresis
lv
6
Select the NTC resistor type
ntc_type
ROM
R/W
0
1
Table 60. FuelGauge
Addr:15
Bit
Bit Name
ntc_on
100kΩ NTC resistor
FuelGauge
This bit controls first startup out of power on reset
Default Access
ROM
R/W
Description
00
Disable NTC supervision
01
Enable NTC supervision
10
Enable NTC for ADC measurement high temp
11
Enable NTC for ADC measurement low temp
Te
ch
ni
ca
7:6
10kΩ NTC resistor
am
lc s
on A
te G
nt
st
il
7
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8.11
- Detailed Description-Power Management Functions
Step Down DC/DC Converters
8.11.1 Step Down DC/DC Converters Operating Modes
The step down dcdc converters have four operating modes to deliver different output currents for the applications. The
operating mode is selected by setting the register sdx_1A_mode (the default is set by the Boot ROM).
77B
!
!
""#
!"
#
lv
al
id
Figure 22. DC/DC step-down SD1, SD2, SD3 Normal Operating Mode; sdx_1A_mode = 0000b
!
"
"
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on A
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nt
st
il
"
"
"
!"
""#
"
!
!
"
#
!
""#
#
Figure 23. DC/DC step-down SD1, SD2, SD3 1A Operating Mode; sdx_1A_mode = 1010b
!
ca
Te
ch
ni
"
!
""#
#
!"
!
"
"
"
"
"
!"
$#
"
#
#
!
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!
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If one of the DCDC step down converters is not used for an application, connect it as follows:
Figure 24. DC/DC step-down SD3 (as example) not used
!
al
id
lv
Figure 25. DC/DC step-down SD1, SD2, SD3 External Controller Operating Mode; sdx_1A_mode = 1100b
am
lc s
on A
te G
nt
st
il
12 3
./ 45
.6 7
34627 34
146 2 48
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ch
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#
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Te
Note: VCURR_GPIO has to be connected to VSUPPLY if the external controler mode is used.
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Figure 26. DC/DC step-down SD1, SD2, SD3 External Controller Operating Mode and SD2 in 1A mode;
sd1_1A_mode = 1101b
-
. / 0
!
"%,
& !#
,
-
!"#
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.6 7
34627 34
146 2 48
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ch
ni
ca
Note: The LDO VDIG2 and the Low voltage current source / GPIO pin CURR1_GPIO1 cannot be used in the
‘External Controller’ operating mode configuration.
VCURR_GPIO has to be connected to VSUPPLY if the external controler mode is used.
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8.11.2 Step Down DC/DC Converter Characteristics
Figure 27. Step Down DC/DC Converter Block diagram
-
'
(
$ $ %&
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ni
ca
The step-down converter is a high efficiency fixed frequency current mode regulator. By using low resistance internal
PMOS and NMOS switches efficiency up to 95% can be achieved. The fast switching frequency allows using small
inductors, without increasing the current ripple. The unique feedback and regulation circuit guarantees optimum load
and line regulation over the whole output voltage range, up to an output current of 500mA, with an output capacitor of
only 10µF. The implemented current limitation protects the DCDC and the coil during overload condition.
ch
To allow optimized performance in different applications, there are bit settings possible, to get the best compromise
between high efficiency and low input, output ripple:
Low ripple, low noise operation:
Te
Bit settings:
sdX_dis_curmin=1
In this mode there is no minimum coil current necessary before switching off the PMOS. As result, the ON time of the
PMOS will be reduced down to tmin_on at no or light load conditions, even if the coil current is very small or the coil
current is inverted. This results in a very low ripple and noise, but decreased efficiency, at light loads, especially at low
input to output voltage differences. Because of the inverted coil current in that case the regulator will not operate in
pulse skip mode.
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Figure 28. sdX_dis_curmin=1 operation
am
lc s
on A
te G
nt
st
il
lv
al
id
1: LX voltage, 2:coil current (1mV=1mA) 3: Vout
High efficiency operation (default setting):
Bit settings:
sdX_dis_curmin=0
In this mode there is a minimum coil current necessary before switching off the PMOS. As result there are less pulses
at low output load necessary, and therefore the efficiency at low output load is increased. This results in higher ripple,
and noisy pulse skip operation up to a higher output current.
Figure 29. sdX_dis_curmin=0 operation
Te
ch
ni
ca
1: LX voltage, 2:coil current (1mV=1mA) 3: Vout
It’s also possible to switch between these two modes during operation:
For Example:
sdX_dis_curmin=0: System is in idle state. No audio, RF signal. Decreased supply current preferred. Increased ripple
doesn’t affect system performance.
sdX_dis_curmin=1: System is operating. Audio signal on and/or RF signal used. Decreased ripple and noise preferred.
Increased power supply current can be tolerated.
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100% PMOS ON mode for low dropout regulation: For low input to output voltage difference the sdX_dis_pon bit
can be set, to allow 100% duty cycle of the PMOS transistor.
Low power mode: The sdX_lpo mode bit can be set all the time. This mode allows internal power down, of not used
blocks during pulseskip mode, which results in a better efficiency at light output loads.
Inductor setting: The step down regulator is optimized for 2.2µH at 2.2MHz and 4.7µH at 1.1MHz
Symbol
VOUT
Min
Typ
Max
Unit
PIN VSUPPLY_1,VSUPPLY_2,
VSUPPLY_3
Input voltage
3.0
5.5
V
Regulated output
voltage
0.6
3.3
V
-50
+50
mV
output voltage <2.0V
-100
+100
mV
output voltage >2.0V
Output voltage
tolerance
ILIMIT
Current limit
800
mA
am
lc s
on A
te G
nt
st
il
VOUT_tol
RPSW
RNSW
Iload
P-Switch ON
resistance
0.5
Ω
V_SUPPLYx=3.0V
N-Switch ON
resistance
0.5
Ω
V_SUPPLYx=3.0V
500
mA
Load current
fSW
Switching frequency
ηeff
Efficiency
0
2.2
MHz
sdX_frequ=0, fclk_int =2.2MHz
1.1
MHz
sdX_frequ=1, fclk_int =2.2MHz
90
%
Iout=100mA, Vout=2.3V, Vsup.=3V
250
IVDD
Note
lv
VIN
Parameter
al
id
Table 61. Step Down DC/DC Converter parameters
Current consumption
Operating current without load
µA
100
Low power mode current
0.1
Shutdown current
Minimum on time
80
ns
tMIN_OFF
Minimum off time
40
ns
10
µF
Ceramic X5R or X7R
2.2
µF
Ceramic X5R or X7R
4.7
µF
Ceramic X5R or X7R; CVSUPPLY1
in external controller mode or 1A
operating mode
ca
tMIN_ON
External Components
Output capacitor
ni
CVSD1-3, CVSD1A
Input capacitor
ch
CVSUPPLY1-3
2.2
Inductor
Te
LSD1-SD3
8.0
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4.7
2.2
Revision 1v13
sdX_frequ=0, ± 10% tolerance
µH
sdX_frequ=1, ± 10% tolerance
SD1 external controller mode; use
sd1_freq=1 (1.1Mhz)
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Table 62. Step Down DC/DC Bit definitions
Step Down Control1
Addr:35
These bits configures the step down converters
Bit
Bit Name
Default Access
Description
0
sd1_psw_on
0
R/W
1
-
0
n/a
2
-
0
n/a
3
sd1_nsw_on
0
R/W
Only if sd1_on = 0, switch on NSW (0.5Ω NMOS)
4
sd2_psw_on
0
R/W
Only if sd2_on = 0, switch on PSW (0.5Ω PMOS)
5
-
0
n/a
6
-
0
n/a
7
sd2_nsw_on
0
R/W
lv
al
id
Only if sd1_on = 0, switch on PSW (0.5Ω PMOS)
Only if sd2_on = 0, switch on NSW (0.5Ω NMOS)
Addr:36
am
lc s
on A
te G
nt
st
il
Table 63. Step Down DC/DC Bit definitions
Step Down Control2
These bits configures the step down converters
Bit
Bit Name
Default Access
0
sd3_psw_on
0
R/W
1
-
0
n/a
2
-
0
n/a
3
sd3_nsw_on
0
R/W
Description
Only if sd3_on = 0, switch on PSW (0.5Ω PMOS)
Only if sd3_on = 0, switch on NSW (0.5Ω NMOS)
Step down low power mode:
4
sdX_lpo
0
R/W
0
Increased current consumption in pulseskip mode
1
Decreased current consumption in pulseskip
mode
Step down pon feature control
sd1_dis_pon
0
R/W
sd2_dis_pon
0
Te
7
sd3_dis_pon
www.austriamicrosystems.com
0
PON feature enabled: 100% duty cycle (pmos
always on) if output voltage drops more than 4%.
Increased output ripple in that operation.
1
PON feature disabled: Maximum dutycycle=1(tmin_off*fsw)
Step down pon feature control
R/W
ch
6
ni
ca
5
0
PON feature enabled: 100% duty cycle (pmos
always on) if output voltage drops more than 4%.
Increased output ripple in that operation.
1
PON feature disabled: Maximum dutycycle=1(tmin_off*fsw)
Step down pon feature control
0
R/W
0
PON feature enabled: 100% duty cycle (pmos
always on) if output voltage drops more than 4%.
Increased output ripple in that operation.
1
PON feature disabled: Maximum dutycycle=1(tmin_off*fsw)
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- Detailed Description-Power Management Functions
Table 64. Step Down DC/DC Bit definitions
Step Down charger control
Addr:37
These bits configures the step down converters
Bit
Bit Name
3
-
Default Access
0
Description
n/a
sd1_dis_curmin
0
0
curmin feature enabled: Inductor current regulated
to min 170mA. Higher efficiency in low dropout
and low output current operation. Higher output
ripple and noise.
1
curmin feature disabled: Decreased efficiency in
low dropout mode and at low output current. Small
output ripple and noise.
R/W
lv
4
al
id
Step down curmin feature control
Step down curmin feature control
curmin feature enabled: Inductor current regulated
to min 170mA. Higher efficiency in low dropout
and low output current operation. Higher output
ripple and noise.
1
curmin feature disabled: Decreased efficiency in
low dropout mode and at low output current. Small
output ripple and noise.
am
lc s
on A
te G
nt
st
il
5
0
sd2_dis_curmin
0
R/W
Step down curmin feature control
6
sd3_dis_curmin
0
0
curmin feature enabled: Inductor current regulated
to min 170mA. Higher efficiency in low dropout
and low output current operation. Higher output
ripple and noise.
1
curmin feature disabled: Decreased efficiency in
low dropout mode and at low output current. Small
output ripple and noise.
R/W
Table 65. Step Down DC/DC Reg Power1 ctrl Bit definitions
Addr:23
Bit Name
These bits control the on/off function of the step down regulator
Default Access
ca
Bit
Reg Power1 Ctrl
sd1_on
ROM
R/W
ch
ni
4
sd2_on
Te
5
www.austriamicrosystems.com
ROM
R/W
Description
Switch on/off the step down1 dc/dc converter; it is possible
to on/off control DCDC SD1 by CURR3_GPIO3 or
CURR4_GPIO4 (see General Purpose Input / Output
(CURR1_GPIO1 … CURR4_GPIO4) on page 30)
0
Step Down DC/DC 1 off
1
Step Down DC/DC 1 on
Switch on/off the step down2 dc/dc converter; it is possible
to on/off control DCDC SD2 by CURR3_GPIO3 or
CURR4_GPIO4 (see General Purpose Input / Output
(CURR1_GPIO1 … CURR4_GPIO4) on page 30)
0
Step Down DC/DC 2 off
1
Step Down DC/DC 2 on
Revision 1v13
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Table 65. Step Down DC/DC Reg Power1 ctrl Bit definitions
Reg Power1 Ctrl
Addr:23
Bit Name
6
sd3_on
Default Access
ROM
R/W
Description
Switch on/off the step down3 dc/dc converter; it is possible
to on/off control DCDC SD3 by CURR3_GPIO3 or
CURR4_GPIO4 (see General Purpose Input / Output
(CURR1_GPIO1 … CURR4_GPIO4) on page 30)
al
id
Bit
These bits control the on/off function of the step down regulator
0
Step Down DC/DC 3 off
1
Step Down DC/DC 3 on
Step Down Voltage1
Addr:00
These bits control the step down regulator voltage, frequency, clk phase
Bit Name
5:0
Default Access
Description
am
lc s
on A
te G
nt
st
il
Bit
lv
Table 66. Step Down Voltage1 Bit definitions
step_down1_v
ROM
R/W
Control the voltage selection for the step down1 DC/DC
converter
000000 0.6 V
…
(LSB=50mV)
111000 – 11111 3.4 V
Select the step down1 frequency
6
sd1_frequ
7
sd1_clkinvert
ROM
ROM
R/W
R/W
0
fclk_int
1
fclk_int/2 (0.8MHz to 1.15 MHz)
(1.6MHz to 2.3 MHz)
Inverts the input clock of the step down1 converter
Table 67. Step Down Voltage2 Bit definitions
Addr:01
Bit
Bit Name
ni
sd2_frequ
ch
6
step_down2_v
These bits control the step down regulator voltage, frequency, clk phase
Default Access
ROM
ca
5:0
Step Down Voltage2
sd2_clkinvert
ROM
Control the voltage selection for the step down2 DC/DC
converter
000000 0.6 V
…
(LSB=50mV)
111000 – 11111 3.4 V
Select the step down2 frequency
R/W
R/W
0
fclk_int
1
fclk_int/2 (0.8MHz to 1.15 MHz)
(1.6MHz to 2.3 MHz)
Inverts the input clock of the step down1 converter
Te
7
ROM
R/W
Description
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- Detailed Description-Power Management Functions
Table 68. Step Down Voltage3 Bit definitions
Step Down Voltage3
Addr:02
Bit Name
5:0
step_down3_v
Default Access
ROM
R/W
Description
Control the voltage selection for the step down3 DC/DC
converter
000000 0.6 V
…
(LSB=50mV)
111000 – 11111 3.4 V
al
id
Bit
These bits control the step down regulator voltage, frequency, clk phase
Select the step down3 frequency
sd3_frequ
7
sd3_clkinvert
ROM
ROM
R/W
R/W
0
fclk_int
1
fclk_int/2 (0.8MHz to 1.15 MHz)
(1.6MHz to 2.3 MHz)
lv
6
Inverts the input clock of the step down1 converter
Addr:17
Bit
am
lc s
on A
te G
nt
st
il
Table 69. Step down1 high current and DVM definitions
Bit Name
Charge Pump Control
These bits control the step down high current mode and DVM step size
Default Access
Description
Time step of DVM voltage change of step down1
If voltage of step down1 (step_down1_v) is changed during
operation, voltage is decreased or increased by 25 mV
steps with the following time separation between steps:
3:2
sd1_dvm_time
ROM
R/W
00
0 µsec, immediate change (no DVM)
01
4 µsec
10
8 µsec
11
16 µsec
ni
sdx_1A_mode
Te
ch
7:4
ca
Select 1A mode of step down2 (combined operation of SD2
and SD3 with a single coil and up to 1A output current) and/
or controller mode of SD1
www.austriamicrosystems.com
ROM
R/W
1010
1A mode selected Controlled by SD2 The
following pins have to be connected:
VSUPPLY2<->VSUPPLY3, LX2<->LX3, PGND2<>PGND3
Stepdown3 is not usable in that mode
1100
External controller mode. LDO DIG1 and current
sink / GPIO CURR1_GPIO1 cannot be used. Set
ldo_dig1_on=0, GPIO1Mode=111b (tristate),
GPIO1Pulls=00b (no pull-up or pull-down)
1101
External controller mode SD1, and 1A mode
controlled by SD2
The following pins have to be connected:
VSUPPLY2<->VSUPPLY3, LX2<->LX3, PGND2<>PGND3
Stepdown3 is not usable in that mode
all other codes (0000...1001,1011,1110...1111) normal
mode
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Table 70. Step Down DC/DC Bit definitions
Step Down Control3
Addr:133
Configurate the SD converters to reduce voltage drops on fast transient
high current load steps. Double the output capacitor size has to be used!
Default Access
0
sd1_uvlimit
0
R/W
1
sd2_uvlimit
0
R/W
2
sd3_uvlimit
0
R/W
Description
0
Normal operation
1
Enable SD1 undervoltage limit.
0
Normal operation
1
Enable SD3 undervoltage limit.
0
Normal operation
1
Enable SD3 undervoltage limit.
8.11.3 Typical Performance Characteristics
ca
am
lc s
on A
te G
nt
st
il
Figure 30. DC/DC step-down Efficiency (sdX_dis_curmin=0, sdX_lpo=0)
al
id
Bit Name
lv
Bit
Te
ch
ni
Figure 31. PCB Layout recommendation
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8.12
- Detailed Description-Power Management Functions
Low Dropout Regulators (LDO)
The low dropout regulators are linear high performance regulators with programmable output voltage.
They are controlled by the following registers:
Table 71. LDO_RF1 voltage bit definitions
LDO_RF1 voltage
Addr:03
Default Access
ldo_rf1_v
ROM
R/W
5
rf1_lcurr_en
ROM
R/W
6
rf1_swprot_en
ROM
R/W
Control the voltage selection for LDO VRF_1
00000 1.85V
… (LSB=50mV)
11111 3.40V
0
current limitation = Ilimit
1
current limitation Ilimit=Ilimit/2
If ‘1’ current limitation is enabled, if RF1-LDO is operating
as High side switch
am
lc s
on A
te G
nt
st
il
4:0
Description
al
id
Bit Name
lv
Bit
These bits control the LDO_RF1 voltage and mode
Table 72. LDO_RF2 voltage bit definitions
Addr:04
LDO_RF2 voltage
These bits control the LDO_RF2 voltage and mode
Bit
Bit Name
Default Access
4:0
ldo_rf2_v
ROM
R/W
5
rf2_lcurr_en
ROM
R/W
Description
Control the voltage selection for LDO VRF_2
00000 1.85V
… (LSB=50mV)
11111 3.40V
0
current limitation = Ilimit
1
current limitation Ilimit=Ilimit/2
Table 73. LDO_RF3 voltage bit definitions
Addr:05
Bit Name
ldo_rf3_v
ni
4:0
rf3_lcurr_en
ch
5
These bits control the LDO_RF3voltage and mode
Default Access
ca
Bit
LDO_RF3 voltage
rf3_hotplug_en
R/W
ROM
R/W
ROM
R/W
Control the voltage selection for LDO VRF_3
00000 1.85V
… (LSB=50mV)
11111 3.40V
0
current limitation = Ilimit
1
current limitation Ilimit=Ilimit/2
0
normal mode
1
200mA current limited switch, if bit rf3_sw=1
(rf3_lcurr_en=0)
Te
6
ROM
Description
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Table 74. LDO_DIG1 voltage bit definitions
LDO_DIG1 voltage
Addr:06
These bits control the LDO_DIG1 voltage
Bit Name
5:0
ldo_dig1_v
Default Access
ROM
Description
Control the voltage selection for LDO DIG_1
(see Table 82)
R/W
Table 75. LDO_DIG2 voltage bit definitions
LDO_DIG2 voltage
Addr:07
These bits control the LDO_DIG2 voltage
Bit Name
5:0
ldo_dig2_v
Default Access
ROM
Description
lv
Bit
R/W
Control the voltage selection for LDO DIG_2(see Table 82)
am
lc s
on A
te G
nt
st
il
Table 76. LDO_DIG3 voltage bit definitions
Addr:08
al
id
Bit
Bit
Bit Name
5:0
ldo_dig3_v
LDO_DIG3 voltage
These bits control the LDO_DIG3 voltage
Default Access
ROM
R/W
Description
Control the voltage selection for LDO DIG_3(see Table 82)
Table 77. LDO_DIG4 voltage bit definitions
Addr:09
Bit
Bit Name
5:0
ldo_dig4_v
LDO_DIG4 voltage
These bits control the LDO_DIG4 voltage
Default Access
ROM
R/W
Description
Control the voltage selection for LDO DIG_4(see Table 82)
Table 78. LDOs Reg Power1 ctrl Bit definitions
Addr:23
Bit Name
ldo_rf1_on
ni
0
ldo_rf2_on
ch
1
Te
2
3
These bits control the on/off function of the ldo regulator
Default Access
ca
Bit
Reg Power1 Ctrl
ldo_dig1_on
ldo_dig2_on
www.austriamicrosystems.com
ROM
ROM
ROM
ROM
Description
R/W
Switch on control of RF1 LDO; Important: Set rf1_sw=0
before setting ldo_rf1_on=1; it is possible to on/off control
LDO RF_1 by CURR3_GPIO3 or CURR4_GPIO4 (see
General Purpose Input / Output (CURR1_GPIO1 …
CURR4_GPIO4) on page 30)
R/W
Switch on control of RF2 LDO; Important: Set rf2_sw=0
before setting ldo_rf2_on=1; it is possible to on/off control
LDO RF_2 by CURR3_GPIO3 or CURR4_GPIO4 (see
General Purpose Input / Output (CURR1_GPIO1 …
CURR4_GPIO4) on page 30)
R/W
Switch on control of DIG1 LDO;
it is possible to on/off control LDO DIG_1 by
CURR3_GPIO3 or CURR4_GPIO4 (see General Purpose
Input / Output (CURR1_GPIO1 … CURR4_GPIO4) on
page 30)
R/W
Switch on control of DIG2 LDO. do not set if DCDC SD1 is
in external controller mode (if sd1_1A_mode = 1100b).
it is possible to on/off control LDO DIG_2 by
CURR3_GPIO3 or CURR4_GPIO4(see General Purpose
Input / Output (CURR1_GPIO1 … CURR4_GPIO4) on
page 30)
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Table 79. LDOs Reg Power2ctrl Bit definitions
Reg Power2 Ctrl
Addr:30
These bits control the on/off function of the ldo regulator
Bit Name
Default Access
Description
0
ldo_rf3_on
ROM
R/W
Switch on control of RF3 LDO; Important: Set rf3_sw=0
before setting ldo_rf3_on=1
1
ldo_dig3_on
ROM
R/W
Switch on control of DIG3 LDO; it is possible to on/off
control LDO DIG_3 by CURR3_GPIO3 or CURR4_GPIO4
(see General Purpose Input / Output (CURR1_GPIO1 …
CURR4_GPIO4) on page 30)’
2
ldo_dig4_on
ROM
R/W
Switch on control of DIG4 LDO
3
rf1_sw
ROM
R/W
If ‘1’ RF1-LDO is operating as High side switch (Ron=1Ω),
valid if ldo_rf1_on=0
4
rf2_sw
ROM
R/W
If ‘1’ RF2-LDO is operating as High side switch (Ron=1Ω),
valid if ldo_rf2_on=0
7
rf3_sw
lv
al
id
Bit
If ‘1’ RF3-LDO is operating as High side switch (Ron=1Ω),
valid if ldo_rf3_on=0
am
lc s
on A
te G
nt
st
il
ROM
R/W
8.12.1 RF LDO’s (VRF_1, VRF_2, VRF_3)
These LDO’s are designed to supply sensitive analogue circuits like LNA’s, Transceivers, VCO’s and other critical RF
components of cellular radios. Another application is the supply of audio devices or as a reference for AD and DA
converters. The design is optimized to deliver the best compromise between quiescent current and regulator
performance for battery powered devices.
Stability is guaranteed with ceramic output capacitors of 1µF ±20% (X5R) or 2.2µF +100/-50% (Z5U) for RF2, RF3 and
2.2µF ±20% (X5R) or 4.7µF +100/-50% (Z5U) for RF1. The low ESR of these caps ensures low output impedance at
high frequencies. Regulation performance is excellent even under low dropout conditions, when the power transistor
has to operate in linear mode. Power supply rejection is high enough to suppress the PA-ripple on the battery in TDMA
systems at the output. The low noise performance allows direct connection of noise sensitive circuits without additional
filtering networks. The low impedance of the power device enables the device to deliver up to IOUT current even at
nearly discharged batteries without any decrease of performance.
Te
ch
ni
ca
With vrf2_lcurr_en=0 and vrf3_lcurr_en=0 the regulator VRF_2, VRF_3 can deliver up to 250mA
With vrf1_lcurr_en=0 the regulator VRF_1 can deliver up to 400mA
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Figure 32. Analog LDO Block diagram
& '()) 2 3 4 !"# $ Ω %
*
)('+ ),-',, lv
μ . /.02
00 μ . /. 1)/
%
al
id
am
lc s
on A
te G
nt
st
il
Table 80. Analog LDO (VRF_1, VRF_2, VRF_3) Characteristics, Vx_IN=4V; ILOAD=150mA; Tamb=25ºC;
CLOAD =2.2µF (Ceramic); unless otherwise specified
Symbol
Vx_IN
IOUT
Parameter
Min
Supply voltage rage
Output current
RON
1
Unit
Power supply rejection
ratio
IOFF
Shut down current
Note
3
5.5
V
0
150
0
200
0
250
VRF_2, rf2_lcurr_en=0
VRF_3, rf3_lcurr_en=0
0
400
VRF_1, rf1_lcurr_en=0
VRF_2, rf2_lcurr_en=1
VRF_3, rf3_lcurr_en=1
mA
VRF_1, rf1_lcurr_en=1
0.5
Ω
VRF_1
1
Ω
VRF_2, VRF_3
70
dB
40
f=1kHz
f=100kHz
nA
Supply current
50
µA
without load
Output noise
50
µVrms
10Hz < f < 100kHz
200
µs
VRF_1,2,3 are set to low current
during startup time
1.85
2.85
V
VRFX_IN>3.0V, VRF_1 @
Iout=300mA, VRF_2 and VRF_3 @
Iout=150mA (X=1,2)
1.85
3.4
V
VRFX_IN>3.55V, VRF_1 @
Iout=300mA, VRF_2 and VRF_3@
Iout=150mA (X=1,2)
-50
50
mV
-1
1
ca
100
ni
PSRR
IVDD
Noise
Startup time
ch
tstart
Max
On resistance
Typ
Te
Vout
Output voltage
Vout_tol
Output voltage
tolerance
VLineReg
Line regulation
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-10
10
Revision 1v13
Static
mV
Transient; Slope: tr=10µs
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Table 80. Analog LDO (VRF_1, VRF_2, VRF_3) Characteristics, Vx_IN=4V; ILOAD=150mA; Tamb=25ºC;
CLOAD =2.2µF (Ceramic); unless otherwise specified
Symbol
Parameter
VLoadReg
Load regulation
ILIMIT_VRF1_HCUR
Current limitation
800
mA
VRF_1, rf1_lcurr_en=0
ILIMIT_VRF1_LCURR
Current limitation
400
mA
VRF_1, rf1_lcurr_en=1 and during
startup
ILIMIT_VRF2,3_L
Current limitation
VRF_2,3 low current
limit
300
mA
rf2_lcurr_en=1, rf3_lcurr_en=1
ILIMIT_VRF2,3_H
Current limitation
VRF_2,3 high current
limit
500
mA
rf2_lcurr_en=0, rf3_lcurr_en=0
CLOAD_RF1
Load capacitor
2
5
µF
ceramic only (VRF_1)
Load capacitor
1
5
µF
ceramic only (VRF_2,3) for
rf1_lcurr_en=1 and rf2_lcurr_en=1
Load capacitor
2
5
µF
ceramic only (VRF_2,3) for
rf1_lcurr_en=0 and rf2_lcurr_en=0
CLOAD_RF2,3_L
CLOAD_RF2,3_H
Typ
Unit
Note
1
10
Transient; Slope: tr=10µs
al
id
-10
Static
mV
lv
-1
Max
am
lc s
on A
te G
nt
st
il
R
Min
1. Guaranteed by design and verified by laboratory evaluation and characterization; not production tested.
8.12.2 Digital LDO’s (VDIG_1, VDIG_2, VDIG_3, VDIG_4)
The Digital LDO’s can be used in any medium power system or subsystem where quiescent power consumption of the
regulator itself has to be minimized without sacrificing its performance. For its stability a cheap 1µF ceramic capacitor
is required. The 5V charge pump will be switched on automatically, if one of the digital LDO’s are switched on.
Figure 33. Digital LDO Block diagram
μ ca
ni
ch
Table 81. Digital LDO (VDIG1, VDIG2, VDIG3, VDIG4) Characteristics,VSUPPLY=4V; ILOAD=200mA; Tamb=25ºC;
CLOAD =1µF (Ceramic); unless otherwise specified
Parameter
Min
VDIGX_IN
Supply voltage range
Te
Symbol
IOUT
RON
Output current
Max
Unit
1
5.5
V
0
200
mA
Vout<2.2V;
VDIGX_IN>Vout+RON*IOUT
0
100
mA
Vout<2.5V;
VDIGX_IN>Vout+RON*IOUT
4
Ω
Vout<2.2V
1
On resistance
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Typ
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Note
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Table 81. Digital LDO (VDIG1, VDIG2, VDIG3, VDIG4) Characteristics,VSUPPLY=4V; ILOAD=200mA; Tamb=25ºC;
CLOAD =1µF (Ceramic); unless otherwise specified
Symbol
Parameter
Min
PSRR
Power supply rejection
ratio
60
IOFF
Shut down current
100
nA
IVDD
Supply current
20
µA
tstart
Startup time
200
µs
2.20
V
Vsupply>3.0V, VCP=5.2V,
Iout<200mA
2.5
V
Vsupply>3.0V, VCP=5.2V,
Iout<100mA
50
mV
Vout<1.85V
Unit
dB
30
0.75
Note
f=1kHz
f=100kHz
al
id
Output voltage
Max
without load
lv
Vout
Typ
Output voltage
tolerance
-50
Vout_tol_hv
Output voltage
tolerance
-60
60
mV
Vout>1.85V
-10
10
mV
Static
-50
50
-20
20
-50
50
VLineReg
am
lc s
on A
te G
nt
st
il
Vout_tol_lv
Line regulation
VLoadReg
Load regulation
ILIMIT
Current limitation
400
Transient; Slope: tr=10µs
mV
Static
Transient; Slope: tr=10µs
mA
Te
ch
ni
ca
1. Guaranteed by design and verified by laboratory evaluation and characterization; not production tested
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- Detailed Description-Power Management Functions
Table 82. Digital LDO (VDIG_1.4) Programming voltage table
Code (b)
VOUT(V)
Code (d)
Code (b)
VOUT(V)
0
000000
0.75
22
010110
1.80
1
000001
0.80
23
010111
1.80
2
000010
0.85
24
011000
1.80
3
000011
0.90
25
011001
4
000100
0.95
26
011010
5
000101
1.00
27
011011
6
000110
1.05
28
011100
7
000111
1.10
29
011101
1.80
8
001000
1.15
30
011110
1.80
9
001001
1.20
31
011111
1.80
001010
1.25
32
100000
1.50 (do not use)
001011
1.30
33
100001
1.60 (do not use)
001100
1.35
34
100010
1.70 (do n0t use)
001101
1.40
35
100011
1.80 (do not use)
001110
1.45
36
100100
1.90
001111
1.50
37
100101
2.00
010000
1.55
38
100110
2.10
010001
1.60
39
100111
2.20
010010
1.65
40
101000
2.30
010011
1.70
41
101001
2.40
010100
1.75
42
101010
2.50
010101
1.80
al
id
Code (d)
1.80
1.80
1.80
am
lc s
on A
te G
nt
st
il
lv
1.80
10
11
12
13
14
15
16
17
18
19
20
21
ca
Note: Full performance for Vout ≤ 2.20V; max. 100mA output current for Vout ≤ 2.50V; do not use values Vout>2.50V
8.12.3 Low power LDO (V2_5)
ch
ni
The Low power LDO V2_5 is needed to supply the chip core (analog and digital) of the device. It is designed to get the
lowest possible power consumption, and still offering reasonable regulation characteristics. The regulator has three
supply inputs selecting automatically the higher one. This gives the possibility to supply the chip core either with the
battery or with the charger depending on the conditions. Bulk switch comparators are used to avoid any parasitic
current flow. To ensure high PSRR and stability, a low-ESR ceramic capacitor of min. 1µF must be connected to the
output.
Table 83. Low power LDO (V2_5) Characteristics,VBAT=4V; ILOAD_ext=0; Tamb=25ºC; CLOAD =2.2 µF (Ceramic);
unless otherwise specified
Te
Symbol
Parameter
VBAT
VCHARGER
Supply voltage rage
RON
On resistance
PSRR
Power supply rejection
ratio
www.austriamicrosystems.com
Min
Typ
Max
2.8
5.5
4
15
50
60
Unit
V
Ω
dB
40
Revision 1v13
Note
Guaranteed per design
f=1kHz
f=100kHz
84 - 157
AS3658
Data Sheet Confidential
- Detailed Description-Power Management Functions
Table 83. Low power LDO (V2_5) Characteristics,VBAT=4V; ILOAD_ext=0; Tamb=25ºC; CLOAD =2.2 µF (Ceramic);
unless otherwise specified
Max
Unit
Shut down current
100
nA
IVDD
Supply current
3
µA
tstart
Startup time
200
µs
Vout
Output voltage
2.4
2.6
V
Vout_tol
Output voltage
tolerance
-50
50
mV
VLineReg
-10
10
Line regulation
VLoadReg
Load regulation
8.13
Typ
2.5
-50
50
-10
10
-50
50
Note
Guaranteed per design, consider
chip internal load for measurements.
al
id
IOFF
Min
Static
mV
lv
Parameter
Transient; Slope: tr=10s
Static
mV
Transient; Slope: tr=10s
am
lc s
on A
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nt
st
il
Symbol
5V Charge Pump
Figure 34. 5V Charge Pump Block diagram
5
55
5
!
5
#$
%
"
ca
The charge pump uses the pad VCP_IN as input, regulates and doubles its voltage with the help of the flying capacitor
between CAPP and CAPN to its output VCP_OUT (the output is automatically limited not to exceed VCPOUT). If the bit
cp_pulseskip is set, the charge pump operates in pulse skip mode, and only starts cycles if its output voltage is below
this level. In this mode the supply current is reduced, but the output ripple is increased.
ni
The charge pump requires the following external components:
Min
CFLY
External flying
capacitor
370
470
850
nF
Ceramic X5R or X7R low-ESR
capacitor between CAPP and CAPN
CSTORE
External storage
capacitor
1.76
2.2
2.64
µF
Ceramic X5R or X7R low-ESR
capacitor between VCP_OUT and
VSS
Dout
Schottky Diode for
startup between
VCP_IN and
VCP_OUT
1
A
Peak current of schottky Diode
Table 84. Charge Pump External Components
Parameter
Te
ch
Symbol
www.austriamicrosystems.com
Typ
Min
Unit
Note
Revision 1v13
85 - 157
AS3658
Data Sheet Confidential
- Detailed Description-Power Management Functions
Make the connections of the external capacitors as short as possible.
Table 85. Charge Pump Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
5.5
V
Note
VCPIN
Charge Pump input
voltage
3.0
fIN
Switching frequency
ICPOUT
Output Current
0.0
VCPOUT
Output Voltage
4.9
VCPSKIP
Output Voltage during
pulseskip
4.92
V
Use with cp_frequ=1 only
ICP_noload
Supply current without
load
2
mA
1.1MHz switching frequency
ICP_pulseskip
Charge pump supply
current without load in
pulseskip mode
20
MHz
cp_freq=0, fclk_int=2.2MHz
0.55
MHz
cp_freq=1, fclk_int=2.2MHz
100
mA
VCP_IN = 3.2V, Clock = fclk_int/2;
cp_pulseskip=0; fin=1.1MHz
5.6
V
lv
am
lc s
on A
te G
nt
st
il
5.2
al
id
1.1
µA
cp_pulseskip=1 and cp_frequ=1
Table 86. CP Power1 ctrl Bit definitions
Addr:23
Reg Power1 Ctrl
These bits control the on/off function of the ldo regulator
Bit
Bit Name
Default
Access
Description
7
cp_on
ROM
R/W
Switch on of the charge pump block, charge pump is
automatically activated if any of the following blocks are
active: VDIG_1, VDIG_2, VDIG_3, VDIG_4
Table 87. Charge Pump Bit definitions
Addr:17
Bit
Bit Name
Charge Pump Control
These bits control the Charge Pump
Default Access
Description
ca
Switches on the pulseskip mode of the charge pump
cp_freq
ROM
ROM
R/W
0
Normal fixed frequency mode
1
Pulse skip, low power mode (Set cp_frequ=1 in
this mode)
Defines the clock frequency of the step up dc/dc converter
R/W
0
fclk_int/2 (0.8 to 1.15 MHz)
1
fclk_int/4 (0.4 to 0.575 MHz)
Te
ch
1
cp_pulseskip
ni
0
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Revision 1v13
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AS3658
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- Detailed Description- Audio Functions
9 Detailed Description- Audio Functions
The audio functions consist of all the audio features of AS3658 as shown in the following block diagram:
9.1
am
lc s
on A
te G
nt
st
il
lv
al
id
Figure 35. AS3658 Audio Functions
Audio Paths
Following Audio paths are possible (only one configuration is possible at the same time):
ch
ni
ca
Figure 36. AS3658 I2S I/O 1 or I2S I/O2 Playback
Te
Note: As the touch screen interface is merged with I2S Output 3 and SPDIF Output 4 either the touch screen
interface or I2S Output 3 and SPDIF Output 4 can be used at the same time.
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Revision 1v13
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AS3658
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- Detailed Description- Audio Functions
am
lc s
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nt
st
il
lv
al
id
Figure 37. AS3658 Line In Recording
Figure 38. AS3658 Microphone Recording
Te
ch
ni
ca
It is also possible to use the Audio ADC and the Audio DAC at the same time. In this case, the sampling frequency of
the Audio DAC is either two or four times the sampling rate of the Audio ADC (ADC: max. 16ks / seconds). The
equalizer should not be used in this case:
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Revision 1v13
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AS3658
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- Detailed Description- Audio Functions
am
lc s
on A
te G
nt
st
il
lv
al
id
Figure 39. AS3658 Microphone Recording and I2S I/O Playback (either I2S 1 or I2S 2/PCM)
Figure 40. AS3658 Recording of the Mixed output signal and parallel playback (either I2S 1 or I2S 2/PCM)
Common mode voltage generation of HP_CM, LINE_CM
ca
9.2
ni
The common mode voltage of the Headphone and Lineout is stored in the C_hpcm and C_linecm capacitor
(connected between HP_CM to VSS and LINE_CM to VSS). These capacitor are also responsible for the popless
startup, PSRR of the amplifiers and sense path of the GND cancellation circuit.
Startup and PSRR is defined by the value of the external capacitors. The RC limits the maximum achievable PSRR:
R=6MΩ typ, C=0.1...1µF:
ch
Table 88. common mode voltage, Audio start-up and PSRR
Startup time (typ)
µF
Te
Capacitor value for C_hpcm and
C_linecm
Maximum achievable PSRR
@ 1kHz (typ)
@ 100Hz (typ)
msec
dB
dB
0.1
150
76
56
1
1500
90
76
www.austriamicrosystems.com
Revision 1v13
89 - 157
AS3658
Data Sheet Confidential
9.3
- Detailed Description- Audio Functions
Audio Setup Registers
Audio LDO has to be switched on first (aud_ldo_on=1), and enables all other functions.
Table 89. AudioSet1 Register
Audio Set1
Addr:74
Bit
Bit Name
0
lin_on
Default Access
0
R/W
Description
0
Line input disabled
1
Line input enabled
al
id
These bits control the Audio functions
Switch on control of AUDIO DAC
dac_on
mix_on
0
R/W
R/W
0
DAC disabled
1
DAC enabled (Switch on, if I2S signal valid only)
0
Mixer switched off
1
Mixer switched on
0
GND switch off 0V at pin GND_SW
1
GND switch on Vsupply at pin GND_SW
am
lc s
on A
te G
nt
st
il
2
0
lv
1
3
gnd_sw_on
0
R/W
4
aud_ldo_on
0
R/W
Audio LDO ON control
0
Audio LDO off
1
Audio LDO on
0
Change of LRCLK at falling edge of MCLK
1
Change of LRCLK at rising edge of MCLK
0
MCLK = LRCLK* 128
1
MCLK = LRCLK* 256
0
Equalizer switched off (bypassed)
1
Equalizer switched on
MCLK invert selection
5
mclk_invert
0
R/W
6
mclk256
0
R/W
7
equ_on
0
R/W
Table 90. AudioSet2Register
ca
Audio Set2
Addr:75
Bit Name
Default Access
ch
ni
Bit
These bits control the Audio functions
Te
1,0
ibr_dac<1:0>
Bias current reduction settings for DAC:
00b
R/W
2
dith_on
0
R/W
3
I2S_3_on
0
R/W
www.austriamicrosystems.com
Description
00
default
01
Don't use
10
Don't use
11
Don't use
1
add dither to the audio stream
0
no dither added
0
Switch off I2S_3 output
1
Switch on I2S_3 output
Revision 1v13
90 - 157
AS3658
Data Sheet Confidential
- Detailed Description- Audio Functions
Table 90. AudioSet2Register
Audio Set2
Addr:75
These bits control the Audio functions
Bit
Bit Name
Default Access
Description
Bias current reduction settings for headphone output
R/W
6
I2S_select
0
R/W
7
I2S_mclk_en
0
R/W
01
17%
10
34%
11
50%
0
Select I2S_1 input
1
Select I2S_2 input
0
Generation of the master clock by the internal PLL
1
Use Pin MCLK_1, MCLK_2 as masterclock input
al
id
0
am
lc s
on A
te G
nt
st
il
9.4
ibr_hph<1:0>
0%
lv
5,4
00
ADC, DAC and Digital Audio Input
9.4.1 General
Digital audio data can be fed into the AS3658 via the I2S interface This input data is used by the 18-bit DAC to
generate the analog audio signal.
The stage is set to mute by default; If the DAC input is not enabled.
9.4.2 Signal Description
The digital audio interface uses the standard I2S format:
Left justified
MSB first
One additional leading bit
MCLK has to have a fixed ratio of 128 or 256 to LRCLK. With a LRCLK equal to 16, 32, 44.1 or 48kHz, the MCLK can
be generated by the on-chip PLL (do not use the internal PLL if there is jitter on the LRCLK1 or 2). For lower sample
rates the bit pll_mode has to be set (for sample rates between 8kHz and 12kHz).
ca
The high going edge of MCLK has to have timing separation from LRCLK edges. If the clock generation is so that
LRCLK edges are at the same time as MCLK high going edges, the MCLK can be inverted to guarantee a proper DAC
function.
Te
ch
ni
This audio input interfaces uses an I2S synchronizer to be able to handle audio sample length of 24bits or less.
www.austriamicrosystems.com
Revision 1v13
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AS3658
Data Sheet Confidential
- Detailed Description- Audio Functions
Figure 41. I2S Control Diagram
i2s_s elect
mc lk_invert
0
i2s_mc lk_en
1
i2s_master_on
i2s_lrck_sclk_out_en
SDO1
0
SDI
SCLK
Equalizer
LRCLK
MCLK
SDO
sc lk _invert
1
SDI1
0
i2s _select
pll_mode
I2S_mclk_en
ext_mclk
0
0
PLL
1
rising edge only
for PCM
com patibility
1
LRCLK1
i2s_s elect
LRCLK_out
SDO
SCLK
14 Bit ADC
LRCLK
MCLK
0
* 256
* 64
1
mc lk 256
0
MCLK1
*2
1
0
mclk_invert
1
A udio left
A udio right
A udio lef t
A udio right
Fadc2 pcm_mode samle_rate
0
0
LRCLK / 2
1
0
LRCLK / 4
0
1
LRCLK
lv
S ample rate
SDI2
sc lk_invert
i2s _master_on
SCLK2
mono to stereo
conversion f or
pc m_mode=1
1
i2s_master_on
SCLK1
18 Bit DAC
al
id
i2s_s elect
i2s_lrck_s clk _out_en
LRCLK2
am
lc s
on A
te G
nt
st
il
s do3_select
i2s _master_on
MCLK divider
MCLK2
i2s_lrck_sclk_out_en
i2s_master_on
0
i2s_mc lk_out_en
1
sdo_on_mclk1_en
SDO3
i2s _clk_divider<11:0>
SCLK3
mclk_invert
0
1
i2s_3_on
LRCLK3
SPDIF
SPDIF
spdif _ctrl<1:0>
Figure 42. I2S Timing Diagram
64 cycles
MCLK
LRCK
Left Channel
SDATA
15
16 bit
SDATA
17
Right Channel
ca
SCLK
2
1
0
2
1
15
0
17
2
1
0
2
1
0
ni
18 bit
64 cycles
ch
Table 91. PLL,MCLK Settings
I2S_select
mclk_invert
Description
0
0
0
I2S_1 selected (PLL used)
Internal MCLK synchronized to external LRCLK
0
0
1
I2S_1 selected (PLL used)
Internal LRCLK used, synchronized to external SDI
0
1
0
I2S_2 selected (PLL used)
Internal MCLK synchronized to external LRCLK
0
1
1
I2S_2 selected (PLL used)
Internal LRCLK used, synchronized to external SDI
Te
I2S_mclk_en
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Revision 1v13
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AS3658
Data Sheet Confidential
- Detailed Description- Audio Functions
Table 91. PLL,MCLK Settings
I2S_select
mclk_invert
Description
1
0
0
I2S_1 selected, external MCLK on MCLK_1
1
0
1
I2S_1 selected, external MCLK on MCLK_1 (inverted)
1
1
0
I2S_2 selected, external MCLK on MCLK_2
1
1
1
I2S_2 selected, external MCLK on MCLK_2 (inverted)
al
id
I2S_mclk_en
9.4.3 Parameter
Table 92. Audio DAC/ADC Parameter
Parameter
Min
Programmable gain DAC input
-43.43
Programmable gain ADC input
-34.5
Typ
1.07
dB
12
dB
am
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te G
nt
st
il
Gain step size
1.5
DAC THD+Noise at FS
-85
DAC SN/R (20Hz-20kHz, -60dBFS) A-weighted
Unit
lv
Analog Performance
Max
90
-75
94
DAC Inter channel Mismatch
0.25
ADC SN/R
82
dB
dB
dB
dB
dB
Table 93. I2S Parameter
I2S Inputs and Outputs VI2S=2.9V
VIL
VIH
Min
Typ
Max
SCLKx, LRCLKx, SDIx
-
-
0.42V
SCLKx, LRCLKx, SDIx
1.02V
-
3.3V
VOL
SDOX,SCLK3,LRCLK3,SPDIF,SCLK1,LRCLK1,MCLK1
0V
VOH
SDOX,SCLK3,LRCLK3,SPDIF,SCLK1,LRCLK1,MCLK1
VI2S
Table 94. DAC_L Register
Bit Name
ni
Bit
dal_vol
Te
ch
4:0
DAC_L
ca
Addr:77
These bits control the Audio DAC volume and functions
Default Access
00000b
volume settings for left DAC input, adjustable in 32 steps @
1.5dB
R/W
00000
-40.5 dB gain
00001
-39 dB gain
.....
5
-
-
-
6
dac_mute_off
0
R/W
www.austriamicrosystems.com
Description
11110
4.5 dB gain
11111
6 dB gain
0
DAC input is set to mute
1
normal operation
Revision 1v13
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AS3658
Data Sheet Confidential
- Detailed Description- Audio Functions
Table 95. DAC_R Register
DAC_R
Addr:78
Bit
These bits control the Audio DAC volume and functions
Bit Name
Default Access
Description
4:0
dar_vol
00000b
R/W
00000
-40.5 dB gain
00001
-39 dB gain
.....
4.5 dB gain
11111
6 dB gain
Table 96. ADC_L Register
Bit
ADC_L
am
lc s
on A
te G
nt
st
il
Addr:79
lv
11110
al
id
volume settings for right DAC input, adjustable in 32 steps
@ 1.5dB
Bit Name
These bits control the Audio ADC volume and functions
Default Access
Description
volume settings for left ADC input, adjustable in 32 steps @
1.5dB
4:0
adl_vol
00000b
R/W
00000
-34.5 dB gain
00001
-33 dB gain
.....
5
adc_on
0
R/W
6
adc_mute_off
0
R/W
11110
10.5 dB gain
11111
12 dB gain
0
ADC disabled
1
ADC enabled
0
ADC input is set to mute
1
normal operation
ca
Divider selection for ADC clock
ad_fs2
0
ADC sample clock is I2S LRCLK / 2; every ADC
sample is sent twice to the I2S output (upsampling by 2)
1
ADC sample clock is I2S LRCLK / 4; every ADC
sample is sent four times to the I2S output (upsampling by 4)
R/W
Te
ch
ni
7
0
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Revision 1v13
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AS3658
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- Detailed Description- Audio Functions
Table 97. ADC_R Register
ADC_R
Addr:80
Bit
These bits control the Audio ADC volume and functions
Bit Name
Default Access
Description
4:0
adr_vol
00000b
R/W
00000
-34.5 dB gain
00001
-33 dB gain
.....
7:6
9.5
0b
10.5 dB gain
11111
12 dB gain
0
normal mode
1
use ADC output as DAC input (for testing
purposes, equalizer is bypassed)
R/W
lv
adc2dac
11110
am
lc s
on A
te G
nt
st
il
5
al
id
volume settings for right ADC input, adjustable in 32 steps
@ 1.5dB
adcmux
00b
R/W
00
Microphone
01
Line In
10
reserved –do not use
11
Audio Sum (Output of Mixer)
I2S master mode and PCM Mode
The digital audio interface can also operate in master mode by using I2S1 interface.
The pin MCLK2 is used as clock input in that case. Any input clock between sampling rate and 24MHz may be used as
input clock.
In Master Mode operation SCLK1 as output has 32 clock cycles for each sample word.
SCLK = [MCLK / 4] = [LRCLK * 256 / 4] = LRCK * 64
Sample Rates
(EQ 8)
ca
In Master Mode the i2smaster control allows programming various sample rates. The master clock is generated from
the MCLK2 input. Sampling frequencies from 8kHz to 48kHz can be selected. For certain division ratios between
master clock and sample ratio a certain deviation is system inherent.
ni
LRCLK = f MCLK 2 *
1
1
*
2 RD + 2
Table 98. PLL,i2s_clk_divider settings
Actual sample
rate
Error
kHz
%
126
48,00
0,00
137,32
137
44,20
0,23
12288
190,00
190
32,00
0,00
29,400
12288
206,98
207
29,40
-0,01
24,000
12288
254,00
254
24,00
0,00
22,050
12288
276,64
277
22,02
-0,13
12,000
12288
510,00
510
12,00
0,00
MCLK2 input
kHz
kHz
48,000
12288
126,00
44,100
12288
32,000
Te
ch
Sample rate
www.austriamicrosystems.com
Divider
i2s_clk_divider
<10:0>
Revision 1v13
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AS3658
Data Sheet Confidential
- Detailed Description- Audio Functions
Table 98. PLL,i2s_clk_divider settings
Error
kHz
%
555
11,03
0,05
766,00
766
8,00
0,00
12000
123,00
123
48,00
0,00
44,100
12000
134,05
134
44,12
32,000
12000
185,50
186
31,91
29,400
12000
202,08
202
29,41
24,000
12000
248,00
248
24,00
22,050
12000
270,11
270
22,06
0,04
12,000
12000
498,00
498
12,00
0,00
kHz
kHz
11,025
12288
555,28
8,000
12288
48,000
8,000
0,04
-0,27
0,04
0,00
am
lc s
on A
te G
nt
st
il
11,025
i2s_clk_divider
<10:0>
Divider
lv
MCLK2 input
al
id
Actual sample
rate
Sample rate
12000
542,22
542
11,03
0,04
12000
748,00
748
8,00
0,00
Table 99. i2s master control1 Register
I2s master control1
Addr:131
This register controls the external clock divider for i2s master mode
Bit
Bit Name
Default
Access
7:0
i2s_clk_divider<7:0>
00h
R/W
Description
Bit 7:0 of divider for MCLK2 input pin
Table 100. i2s master control2 Register
I2s master control2
Addr:132
This register controls the external clock divider and modes for i2s master
mode
Bit Name
2:0
i2s_clk_divider<10:8>
000b
R/W
3
i2s_master_on
0b
R/W
ni
i2s_lrclk_sclk_out_en
ch
4
i2s_mclk_out_en
Te
5
6
sdo_on_ mclk1
www.austriamicrosystems.com
Description
Default Access
ca
Bit
0b
0b
0b
Bit 10:8 of divider for MCLK2 input pin
0
i2s master mode disabled
1
i2s master mode enabled
0
LRCLK1 and SCLK1 are used as input (slave
mode)
1
LRCLK1 and SCLK1 are used as output (master
mode).
Clock input for PLL is MCLK2
0
MCLK1 used as input (slave mode)
1
MCLK1 used as output for master clock of an
external I2S. Clock input for PLL is MCLK2
(MCLK1=256*LRCLK, if bit mclk256=1;
MCLK=128*LRCLK, if bit mclk256=0)
0
Normal operation of MCLK1 (input or output
according to bit is2_mclk_out_en bit)
1
MCLK1 used as SDO output (e.g. for audio ADC).
May be used as data output (SDO) for I2S_2 port
R/W
R/W
R/W
Revision 1v13
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AS3658
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- Detailed Description- Audio Functions
Table 100. i2s master control2 Register
I2s master control2
Addr:132
Bit Name
pcm_mode
0b
R/W
0
Normal I2S mode
1
PCM mode selected. The following additional
settings are necessary to enable PCM mono
mode:
sclk_invert=1
i2s_mclk_en=0 and mclk_invert=1 (internal PLL
used for generation of internal LRCLK)
lv
7
Description
Default Access
al
id
Bit
This register controls the external clock divider and modes for i2s master
mode
9.5.1 PCM mode settings
am
lc s
on A
te G
nt
st
il
Compatible with BlueCore3-ROM:
Figure 43. Short Frame Sync (shown with 16-bit Sample)
In short Frame Sync the falling edge of PCM_SYNC indicate the start of the PCM word. PCM_Sync is always one clock cycle long.
LRCLK PCM_SYNC
SCLK
PCM_CLK
SDI
PCM_OUT
SDO
1
PCM_IN Undefined
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10 11
10 11
12 13
12 13
14 15
14 15
16
16 Undefined
The following setup on PCM-Master side is needed:
AS3658 is slave only
ca
PCM_SYNC is in short frame mode
PCM_SYNC rate is 8ksamples/s
PCM_CLK= 512kHz only (64 x PCM_SYNC)
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16 Bit Linear coding of PCM_OUT and PCM_IN (MSB first, LSB last)
ch
Mono (single channel) operation only. Only the right channel of the AS3658 is used. The left channel is same as
right channel (in the input direction of AS3658) and has to be ignored by PCM master (in output direction of
AS3658)
Note: Internally the right channel is copied to the right and left channel.
The following setup of AS3658 is needed:
Te
Sclk_invert=1
i2s_mclk_en=0 and mclk_invert=1 (internal PLL used for generation of internal LRCLK)
pcm_mode=1 and ad_fs2=0 (Necessary to allow unsymmetrical LRCLK and sample rate of 8kHz of ADC)
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9.6
- Detailed Description- Audio Functions
Line Input
9.6.1 General
AS3658 includes one stereo single ended inputs.
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Figure 44. LineIn Block Diagram
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!" # Table 101. Line Inputs Parameter
Parameter
Analog Performance
Min
Rin
Typ
Max
50
Unit
kΩ
Table 102. LINE_IN_R Register
Addr:85
Bit
Bit Name
LINE_IN_R
These bits control the LINE_IN volume and functions
Default Access
Description
volume settings for right line input, adjustable in 32 steps
@ 1.5dB; gain from line input pin (LIN1R) to mixer input
4:0
lir_vol
00000b
R/W
00000
-34.5 dB gain
00001
-33 dB gain
5
mute_off_inr
0
-
11110
10.5 dB gain
11111
12 dB gain
Control of MUTE switch
R/W
0
right line input is set to mute
1
normal operation
-
do not change
Te
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7:6
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.....
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- Detailed Description- Audio Functions
Table 103. LINE_IN_L Register
Addr:86
LINE_IN_L
These bits control the LINE_IN volume and functions
Bit
Bit Name
Default
Access
Description
4:0
lil_vol
00000
R/W
00000
-34.5 dB gain
00001
-33 dB gain
.....
10.5 dB gain
11111
12 dB gain
lv
11110
al
id
volume settings for right line input, adjustable in 32 steps @
1.5dB; gain from line input pin (LIN1L) to mixer input
Control of MUTE switch
mute_off_inl
0
R/W
0
left line input is set to mute
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5
1
7:6
9.7
00
normal operation
n/a
do not change
Five Band Equalizer
The 5 Band equalizer is build of one low pass, one high pass and 3 band pass filter, and is optimized for 44.1kHz
sample frequency:
Low pass filter: 200Hz ( when programming negaitve gain values, this filter changes to a HP filter)
Band pass filter1: 340Hz / Q=1.0 (when programming negative gain values, this filter changes to a notch filter)
Band pass filter2: 1100Hz / Q=0.7 (when programming negative gain values, this filter changes to a notch filter)
Band pass filter3: 3375Hz / Q=1.0 (when programming negative gain values, this filter changes to a notch filter)
High pass filter: 5940Hz (when pragramming negative gain values, this filter changes to a LP filter)
The Q factors and the cut off frequency of the High and low pass filter are measured at 50% gain and are valid for
+6dB amplification of each band.
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The attenuation or amplification of each band can be dynamically adjusted by the serial interface. Additional a pre-gain
stage can adjust the input level. This gain stage is after the 16 to 24 bit extension and therefore additional gain, which
is compensated with the equalizer filter itself (eq_lp_gain, eq_band1,2,3_gain, eq_hp_gain) will not cause clipping:
Figure 45. Equalizer Block Diagram
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Figure 46. EQ Filter frequency response sum curve
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Figure 47. EQ Filter frequency response +12dB/+6dB/+3dB
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- Detailed Description- Audio Functions
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Figure 48. EQ Filter frequency response -3dB
Each band has a range from -12 to +12 dB with each increment equal to ±3dB.
For sample frequencies of the I2S stream different from 44.1kHz, the filter frequencies are shifted (ratiometric).
Table 104. EQ_LP Register
EQ_LP
ca
Addr: 90
Bit Name
Default
Access
ch
eq_lp_gain
Te
3:0
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0000b
Description
EQ_LP filter gain (-12dB... +12dB)
ni
Bit
These bits control the gain of the low pass filter in dB
R/W
0h
0dB
1h
3dB
2h
6dB
3h
9dB
4h
12dB
bh
-3dB
ch
-6dB
dh
-9dB
eh
-12dB
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- Detailed Description- Audio Functions
Table 105. EQ_Band1 Register
EQ_Band1
Addr: 91
Bit
Bit Name
These bits control the gain of the Band pass filter1 in dB
Default
Access
Description
0000b
R/W
1h
3dB
2h
6dB
3h
9dB
4h
12dB
bh
-3dB
ch
-6dB
dh
-9dB
lv
eq_band1_gain
0dB
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3:0
0h
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EQ_Band1 filter gain (-12dB... +12dB)
eh
-12dB
Table 106. EQ_Band2 Register
EQ_Band2
Addr: 92
Bit
Bit Name
These bits control the gain of the Band pass filter2 in dB
Default
Access
Description
EQ_Band2 filter gain (-12dB... +12dB)
eq_band2_gain
0000b
R/W
0dB
1h
3dB
2h
6dB
3h
9dB
4h
12dB
bh
-3dB
ch
-6dB
dh
-9dB
eh
-12dB
Te
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3:0
0h
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Table 107. EQ_Band3 Register
EQ_Band3
Addr:93
Bit
Bit Name
These bits control the gain of the Band pass filter3 in dB
Default
Access
Description
0000b
R/W
1h
3dB
2h
6dB
3h
9dB
4h
12dB
bh
-3dB
ch
-6dB
dh
-9dB
lv
eq_band3_gain
0dB
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3:0
0h
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EQ_Band3 filter gain (-12dB... +12dB)
eh
-12dB
Table 108. EQ_HP Register
EQ_HP
Addr:94
Bit
Bit Name
These bits control the gain of the High pass filter in dB
Default
Access
Description
EQ_HP filter gain (-12dB... +12dB)
eq_hp_gain
0000b
R/W
0dB
1h
3dB
2h
6dB
3h
9dB
4h
12dB
bh
-3dB
ch
-6dB
dh
-9dB
eh
-12dB
Te
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3:0
0h
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Table 109. EQ_preamp Register
EQ_preamp
Addr:95
Bit
Bit Name
These bits control the preamplifier of the EQ in dB
Default
Access
Description
00000b
R/W
01h
-1.5dB
02h
-3.0dB
03h
-4.5dB
04h
-6.0dB
05h
-7.5dB
06h
-9.0dB
07h
-10.5dB
lv
eq_pre_gain
0dB
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4:0
0h
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EQ_vol gain (-12dB ... +12dB with 1.5dB steps)
-12dB
09h
1.5dB
bh
3.0dB
ch
6.0dB
dh
7.5dB
eh
9.0dB
fh
10.5dB
10h
12dB
Te
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08h
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9.8
- Detailed Description- Audio Functions
Microphone Input
General
The audio front-end offers one microphone inputs and a low noise microphone voltage supply (microphone bias), voice
activation, microphone connect detection and push button remote control.
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Figure 49. Microphone Input Block diagram and External Circuit
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Gain Stage & Limiter
The integrated pre-amplifier allows 3 preset gain settings. There is also a limiter which attenuates high input signals
from e.g. electret microphones signal to 1Vp. The AGC has 15 steps with a dynamic range of about 29dB. The AGC is
ON by default but can be disabled by a microphone register bit.
Apart from the microphone pre-amplifier the microphone input signal can further be amplified with 32 @1.5dB
programmable logarithmic gain steps and MUTE. All gains and MUTE are independently programmable. The gain can
be set from –40.5dB to +6dB.
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The stage is set to mute by default. If the microphone input is not enabled, the volume settings are set to their default
values. Changing the volume and mute control can only be done after enabling the input.
Supply & Detection
ch
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The microphone input generates a supply voltage of 1.5V above AGND. The supply is designed for ≤ 2mA and has a
10mA current limit. In OFF mode the MICS terminal is pulled to AVDD with 30kΩ. A current of typically 50µA generates
an interrupt to inform the CPU, that a circuit is connected. When using the MICS terminal as ADC-10 input to monitor
external voltage the 30kΩ pull-up can be disabled.
Remote Control
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Fast changes of the supply current of typically 500µA are detected as a remote button press, and an interrupt is
generated.
Voice Activation
Further a built-in voice activation comparator can actuate an interrupt if microphone input voltage of about 5mVRMS is
detected.
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- Detailed Description- Audio Functions
Microphone Input Parameter
Table 110. Microphone Inputs Parameter, TA= 25oC unless otherwise mentioned
Min
VMICIN0
VMICIN1
Input Signal Level
VMICIN2
Typ
Max
Unit
Note
40
mVPEAK
AMICPRE = 28dB; AMIC = 0dB
20
mVPEAK
AMICPRE = 34dB; AMIC = 0dB
10
mVPEAK
AMICPRE = 40dB; AMIC = 0dB
MICP, MICN to AGND
RMICIN
Input Impedance
15
kΩ
MICIN
Input Impedance
Tolerance
±15
%
CMICIN
Input Capacitance
5
pF
AMICPRE
Microphone
Preamplifier Gain
28
dB
34
Programmable Gain
AMIC
-40.5
+6
dB
1.5
dB
Gain Step Precision
±0.25
dB
VMICLIMIT
Limiter Activation Level
1
VPEAK
AMICLIMIT
Limiter Gain Overdrive
15*2
dB
tATTACK
Limiter Attack Time
50
µs/6dB
tDECAY
Limiter Decay Time
120
ms/6dB
AMICMUTE
Mute Attenuation
100
dB
VMICSUP
Microphone Supply
Voltage
2.9
V
IMICMAX
Max. Microphone
Supply Current
10
mA
VNOISE
Microphone Supply
Voltage Noise
5
µV
IMICDET
Microphone Detection
Current
50
µA
Max. Remote
Detection Current
500
µA
discrete logarithmic gain steps
microphones nominally need a bias
current of 0.5mA-1mA
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Gain Steps
IREMDET
Preamplifier has 3 selectable (fixed)
gain settings
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Parameter
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Symbol
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- Detailed Description- Audio Functions
Register Description
Table 111. MIC_R Register
MIC_R
Addr:87
Bit Name
Default
Access
Description
al
id
Bit
Right Microphone Input Register
Configures the gain from microphone amplifier output
volume settings for right microphone input, adjustable
in 32 steps @ 1.5dB; gain from microphone amplifier
4:0
mr_vol
00000b
R/W
00000
-40.5 dB gain
00001
-39 dB gain
lv
.....
11110
4.5 dB gain
11111
6 dB gain
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Sets the gain of the microphone preamplifier
6:5
pre_gain
7
mic_agc_off
00
0
R/W
R/W
00
gain set to 28 dB
01
gain set to 34 dB
10
gain set to 40 dB
11
reserved, do not use
Control of limiter AGC (automatic gain control). Limits
high dynamic range of electret/MEMS microphone
(e.g. user shouts or blows into microphone)
0
automatic gain control enabled
1
automatic gain control disabled
Table 112. MIC_L Register
MIC_L
Addr:88
Default
ni
ml_vol
00000
Access
Te
5
rdet_off
Description
volume settings for left microphone input, adjustable in 32
steps @ 1.5dB; gain from microphone amplifier
R/W
00000
-40.5 dB gain
00001
-39 dB gain
.....
ch
4:0
Bit Name
ca
Bit
Left Microphone Input Register
Configures the gain from microphone amplifier output
0
R/W
11110
4.5 dB gain
11111
6 dB gain
Disables the microphone detect function (30kΩ pull-up
from MICS to VDAC) to use the terminal as ADC-10
input
0
microphone detection enabled
1
microphone detection disabled
Control of MUTE
6
mute_off
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0
R/W
0
microphone input set to mute
1
gain set to 34 dB
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- Detailed Description- Audio Functions
Table 112. MIC_L Register
MIC_L
Addr:88
Left Microphone Input Register
Configures the gain from microphone amplifier output
Bit Name
Default
Access
7
msup_off
0
R/W
9.9
Description
0
microphone supply on if mic_on=1
1
microphone supply off
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Bit
Audio Output Mixer
9.9.1 General
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The mixer stage sums up the audio signals of the following stages
Microphone Input
Line Input
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Digital Audio Input (DAC)
The mixing ratios have to be with the volume registers of the corresponding input stages. Please be sure that the input
signals of the mixer stage are not higher than 1Vp. If summing up several signals, each individual signal has of course
to be accordingly lower. This shall insure that the output signal is also not higher than 1Vp to get a proper signal for the
output amplifier.
This stage features an automatic gain control (AGC), which automatically avoids clipping.
9.9.2 Register Description
Table 113. AudioSet_3 Register
Audio_set3 register
Addr:76
Bit
Bit Name
Configures the mixer inputs and AGC
Default
Access
Description
Preset of PLL bias for the following sampling
frequencies
pll_mode
0
ca
0
hp_pulld_en
0
ch
Te
2
3
voxm_on
mic_on
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0
16-48kS
1
8-12kS
Controls the pulldown of the HP1 if HP2is enabled and
HP2, if HP1 is enabled
R/W
ni
1
R/W
0
Pulldown disabled if hp_on=1
1
Pulldown of the not used HP1/2 output
enabled, if hp_on=1
Switches on the voice recognition
0
R/W
0
OFF
1
ON
Switches on the microphone amplifier
0
R/W
0
OFF
1
ON
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- Detailed Description- Audio Functions
Table 113. AudioSet_3 Register
Audio_set3 register
Addr:76
Bit
Bit Name
Configures the mixer inputs and AGC
Default
Access
Description
Switches the signal limiter OFF
agc_off
0
R/W
0
automatic gain control for summing stage
enabled
1
automatic gain control for summing stage
disabled
al
id
4
Input from DAC to R and L
dacmix_off
0
R/W
0
1
ON
lv
5
OFF
Input from microphone to R and L
micmix_off
0
R/W
0
ON
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6
1
OFF
Input from line input to R and L
7
9.10
linmix_off
0
R/W
0
ON
1
OFF
Line Output
9.10.1 General
The line output is designed to provide the audio signal on 600 Ω min.
This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain
can be set from –40.5dB to +6dB.
9.10.2 No-Pop Function
To avoiding click and pop noise during power-up and shutdown, the output is automatically set to mute when the output
stage is disabled. Also the volume settings are set to their default values, and can’t be changed, as long the output
stage is not enabled.
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LINE_CM pin, which needs a 0.1µF... 1µF capacitor outside gets charged on power-up with 1µA to ALVDD/2. After
start-up the DC level of the following pins are the same: LOUT_L=LOUT_R=LINE_CM= ALVDD/2. The Start-up time
before releasing mute is about 150ms with 0.1µF. To avoid pop-noise 150ms discharging time of LINE_CM after a
shutdown, have to be waited before starting up again.
9.10.3 Ground Noise Cancellation
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The purpose of the ground cancellation circuit is to compensate noise (ground noise) between different grounds (e.g.
the ground where the AS3658 is soldered versus e.g. the ground of a car amplifier (see Figure 50)). This noise
between these different grounds can be caused e.g. by a high current devices like a motor-fan. The ground
cancellation circuit can be used for line and headphone amplifiers.
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The circuit works as follows:
The ground noise gets added inside the AS3658 to the audio signal (input LINE_CM for the Line Out amplifier or
HP_CM for headphone amplifier) in a way that it cancels inside the car amplifier. The sense point is connected with
RGND_SEP (20Ω) to the battery ground.
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The ground cancellation can be disabled by shorting the 20Ω resistor setting bit gnd_sw to ‘1’. This bit should be set if
e.g. a headphone instead of the car amplifier is connected to the output jack.
Note: A similar cicuit can be used for the headphone amplifier.
Figure 50. Ground Noise Cancellation Application Schematic
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9.10.4 Power Save Options
To save power, a reduction of the bias current can be selected.
Table 114. Line Power-Save Options
IDD_LINE (typ.)
0
2.2mA
1
1.5mA
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9.10.5 Parameter
IBR_LINE
Table 115. Line out Block Characteristics
Min
ni
Parameter
Typ
Max
Unit
Analog Performance
ch
R_Load at LOUT_L and LOUT_R single ended
Ω
600
±0.5
dB
SINAD no load, LineIn-> Line out, A-weighted
-97
dB
THD @ 1kHz, no load
-88
dB
THD @ 1kHz, 600Ω
-80
dB
90
dB
Te
Gain Step Precision (RLmin-max,20Hz-20kHz)
PSRR (200Hz-20kHz)
60
IOUT_powerdown
-20
Tpower_up (C_LINECM=100nF)
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150
µA
ms
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- Detailed Description- Audio Functions
Table 115. Line out Block Characteristics
Parameter
Min
Typ
100Hz
50
1kHz
50
10kHz
40
GND cancellation GND - AUDIO_GND to
LOUT_R, LOUT_L no load
Max
dB
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9.10.6 Register Description
Unit
To get an interrupt on an over-current event, the corresponding bit in the Interrupt enable register has to be set. All
other Line/headphone driver settings are controlled by the following two registers.
Table 116. LINE_OUT_R Register
LINE_OUT_R
Addr:83
lv
Right Line Register
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These bits control the Line in volume and mode
Bit
Bit Name
Default
Access
Description
volume settings for right Line output, adjustable in 32
steps @ 1.5dB
4:0
liner_vol
00000b
R/W
00000
-40.5 dB gain
00001
-39 dB gain
......
5
dac2line_on
0
11110
4.5 dB gain
11111
6 dB gain
0
Line_out amplifier input connected to mixer
output
1
Line_out amplifier input connected to Audio
DAC output gain stage (Mixer is bypassed in
this mode)
R/W
Bias current reduction settings for line output:
ibr_line<1:0>
00b
R/W
0%
01
17%
10
34%
11
50%
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7:6
00
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Left Line Register
Table 117. LINE_OUT_L Register
LINE_OUT_L
Addr:84
Bit
These bits control the Line in volume and mode
Bit Name
Default
Access
Description
4:0
liner_vol
00000b
R/W
00000
-40.5 dB gain
00001
-39 dB gain
......
6
line_on
7
9.11
11111
6 dB gain
0
lv
-
4.5 dB gain
reserved
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5
11110
al
id
volume settings for left Line output, adjustable in 32
steps @ 1.5dB
line_mute
0
0
R/W
R/W
0
Line stage not powered
1
power up Line stage
0
normal operation
1
Line output set to mute (mute is on during
power-up)
Headphone Output
The headphone output is designed to provide the audio signal with 2x40mW @ 16Ω or 2x20mW @32Ω, which are
typical values for headphones.
This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain
can be set from –40.5dB to +6dB.
9.11.1 Phantom Ground
HP_CM_PWR pin is the buffered HP_CM output. It can be used to drive the common mode level with a load of 2kΩ.
The phantom ground can be switched off to save power if not needed.
9.11.2 No-Pop Function
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To avoiding click and pop noise during power-up and shutdown, the output is automatically set to mute when the output
stage is disabled. Also the volume settings are set to their default values, and can’t be changed, as long the output
stage is not enabled.
ch
ni
HP_CM pin, which needs a 100nF to 1µF capacitor outside, gets charged on power-up with 1µA to AVDD/2. After startup the DC level of the following pins are the same: HPR=HPL=HP_CM=HP_CM_PWR=AVDD/2. The Start-up time
before releasing mute is about 150ms. To avoid pop-noise 150ms discharging time of HP_CM after a shutdown, have
to be waited before starting up again.
9.11.3 Over-current Protection
Te
This output stage has an over-current protection, which disables the output for 256ms or 512ms. This value can be set
in the headphone registers. The over-current protection limit of HPR and HPL pin is about 260mA while HP_CM_PWR
pin has a 370mA limit.
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- Detailed Description- Audio Functions
9.11.4 Power Save Options
To save power, especially when driving 32 Ω loads, a reduction of the bias current can be selected.
Bias current reduction settings for headphone output:
00: 0%
01: 17%
11: 50%
9.11.5 Parameters
Table 118. Power Amplifier Parameter
Min
R_Load at AOUTR and AOUTL single ended
16
Analog Performance
Max
Unit
Ω
1.13
am
lc s
on A
te G
nt
st
il
Vout
Typ
lv
Parameter
al
id
10: 34%
Vp
Gain Step Precision (RLmin-max,20Hz-20kHz)
±0.5
dB
SINAD no load, LineIn-> HPH, A-weighted
-97
dB
THD @ 1kHz, no load
-88
dB
THD @ 1kHz, 32Ω, 10mW
-80
dB
THD @ 1kHz, 32Ω, 20mW
-74
-66
dB
THD @ 1kHz, 16Ω, 40mW
-68
-60
dB
Channel Separation (32Ω, dc-coupled)
60
dB
90
dB
Shorted Protection Level
260
mA
Shorted Protection Level of common mode buffer
370
mA
PSRR (200Hz-20kHz)
60
IOUT_powerdown
-20
Tpower_up (HP_CM=0.1µF)
ca
GND cancellation GND - AUDIO_GND to
HP_R, HP_L no load
20
150
100Hz
50
1kHz
50
10kHz
40
µA
ms
dB
9.11.6 Register Description
Te
ch
ni
To get an interrupt on an over-current event, the corresponding bit in the Interrupt enable register has to be set.
Changing the bias current or the output driver strength is done via AudioSet2 register. All other headphone driver
settings are controlled by the following two registers.
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- Detailed Description- Audio Functions
Right Headphone Register
Table 119. HPH_OUT_R Register
Addr:81
Bit
Bit Name
HPH_OUT_R
These bits control the Right headphone ouput volume and mode
Default
Access
Description
4:0
hpr_vol
00000b
00000
-40.5 dB gain
00001
-39 dB gain
......
4.5 dB gain
lv
11110
al
id
volume settings for right headphone output, adjustable
in 32 steps @ 1.5dB
11111
6 dB gain
am
lc s
on A
te G
nt
st
il
headphone phantom ground disable
5
hpcm_off
0
1
normal operation
disable common mode buffer
headphone over current time out:
speaker over current time out:
7:6
hp_ovc_to
00h
00
256 ms
01
128 ms
10
512 ms
11
0 ms
Left Headphone Register
Table 120. HPH_OUT_L Register
Addr:82
Bit Name
These bits control the Left headphone ouput volume and mode
Default
Access
hpl_vol
00000b
ch
ni
4:0
0
R/W
6
hp_on
0
R/W
7
hp_mute
0
R/W
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00000
-40.5 dB gain
00001
-39 dB gain
......
hp_mux
Te
5
Description
volume settings for left headphone output, adjustable
in 32 steps @ 1.5dB
ca
Bit
HPH_OUT_L
11110
4.5 dB gain
11111
6 dB gain
0
use HPL1, HPR1 as headphone output
1
use HPL2, HPR2 as headphone output
0
headphone stage not powered
1
power up headphone stage
0
normal operation
1
headphone output set to mute (mute is on
during power-up)
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9.12
- Detailed Description- Audio Functions
SPDIF output
Enables and controls the SPDIF output pin. SPDIF functionality is enabled, if internal masterclock is used (internal
PLL), or the external masterclock = 256* LRCLK. (No SPDIF function if external masterclock= 128 *LRCLK)
Table 121. SPDIF Register
SPDIF
Addr:89
Bit Name
Default
Access
Description
al
id
Bit
These bits control the SPDIF output
ISPDIF output ON/OFF control and sample rate status
bits
spdif_cntr
00b
R/W
00
SPDIF output OFF
01
SPDIF output ON
10
reserved (do not use)
11
lv
1:0
reserved (do not use)
am
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on A
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nt
st
il
SPDIF sample status bit
2
spdif_invalid
0
R/W
0
1
sample valid
sample invalid
SPDIF master clock control bit
3
spdif_mclk_inv
0
R/W
0
1
master clock
master clock inverted
SPDIF copy control bit
4
spdif_copy_ok
0
R/W
0
1
copy not permitted
copy permitted
Select source of SDO3 output
5
sdo3_select
0
R/W
0
1
Select adc_output
Select Equalizer output
Invert serial data clock of I2S1 and I2S2
sclk_invert
0
ca
6
audio_off
0
0
1
Normal mode
Invert SCLK1 or SCLK2 input
switch off audio functionality for low power
touchpannel detection
R/W
0
Normal mode
1
audio bias switched off to reduce power
Te
ch
ni
7
R/W
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- Detailed Description - System Functions
10 Detailed Description - System Functions
The system functions consist of the I2C interface, the reset controller, the interrupt controller, startup sequences and
programming, the watchdog, internal references, the ON-key detect and the real time clock module.
2
I C Serial Interface
Table 122. I2C SDA,SCL Characteristics
Parameter
Min
VIL
SCL,SDA Low Level
input voltage
VIH
SCL,SDA High Level
input voltage
Typ
Max
Unit
-0.3
0.4
V
1.3
VSUPP
LY
V
Note
lv
Symbol
al
id
10.1
10.1.1 Feature List
am
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st
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Fast-mode capability (max. SCL-frequency is 400 kHzkHz)
7+1-bit addressing mode
60h x 8-bit data registers (word address 0x00 - 0x60)
Write formats: Single-Byte-Write, Page-Write
Read formats: Current-Address-Read, Random-Read, Sequential-Read
SDA input delay and SCL spike filtering by integrated RC-components
10.1.2 Transfer Formats
2
Figure 51. I C Byte-Write
S
DW
A
WA
A
reg_data
A P
START condition after STOP
repeated START
device address for write
device address for read
word address
acknowledge
no acknowledge
stop condition
slave as receiver
slave as transmitter
increment word address internally
ca
write register,
WA++
S
Sr
DW
DR
WA
A
N
P
white field
grey field
WA++
ni
AS3658 device address write (DW):80h = 10000000b
AS3658 device address read (DR): 81h = 10000001b
2
ch
Figure 52. I C Page-Write:
DW
A
WA
Te
S
A
reg_data 1
A
reg_data 2
write register
WA++
A
write register
WA++
…
reg_data n
A P
write register
WA++
Byte-Write and Page-Write are used to write data to the slave.
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The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state
(the bus is free). The device-write address is followed by the word address. After the word address any number of data
bytes can be send to the slave. The word address is incriminated internally, in order to write subsequent data bytes on
subsequent address locations.
For reading data from the slave device, the master has to change the transfer direction. This can be done either with a
repeated START condition followed by the device-read address, or simply with a new transmission START followed by
st
al
id
the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1 register
byte transmitted from the slave. In Read-Mode any number of subsequent register bytes can be read from the slave.
The word address is incriminated internally.
The diagrams below show various read formats available:
2
DW
A
WA
A Sr
DR
data
A
N P
am
lc s
on A
te G
nt
st
il
S
lv
Figure 53. I C Random-Read:
read register
WA++
WA++
Random-Read and Sequential-Read are combined formats. The repeated START condition is used to change the
direction after the data transfer from the master.
The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START
condition is followed by the device-write address and the word address.
st
In order to change the data direction a repeated START condition is issued on the 1 SCL pulse after the acknowledge
bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In
this state the slave transmits register data located by the previous received word address vector. The master responds
to the data byte with a not-acknowledge, and issues a STOP condition on the bus.
2
Figure 54. I C Sequential-Read:
DW
A
WA
A Sr
DR
ni
ca
S
A
data 1
A
data 2
…
A
data n
WA++
ch
read register
WA++
N P
Te
Sequential-Read is the extended form of Random-Read, as more than one register-data bytes are transferred
subsequently. In difference to the Random-Read, for a sequential read the transferred register-data bytes are
responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited
(consider the behavior of the word-address counter). To terminate the transmission the master has to send a notacknowledge following the last data byte and generate the STOP condition subsequently.
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2
Figure 55. I C Current-Address-Read:
S
DR
A
A
data 1
data 2
…
read register
WA++
data n
N P
WA++
read register
WA++
al
id
read register
WA++
A
To keep the access time as small as possible, this format allows a read access without the word address transfer in
advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read
st
Reset generator and XON-Key
am
lc s
on A
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nt
st
il
10.2
lv
address. Analogous to Random-Read, a single byte transfer is terminated with a not-acknowledge after the 1 register
byte. Analogous to Sequential-Read an unlimited number of data bytes can be transferred, where the data bytes has to
be responded with an acknowledge from the master. For termination of the transmission the master sends a notacknowledge following the last data byte and a subsequent STOP condition.
XRESET is a low active bi-directional pin. An external pull-up to the periphery supply has to be added.
During each reset cycle the following states are controlled by the AS3658:
Pin XRESET is forced to GND
Programmable Power-off function
Programmable Power-on sequence and regulator voltages
Programmable reset timer
All registers are set to their default values after power-on, except the reset control- and status-registers.
Note: Programming is controlled by the internal Mask-PROM and the external resistor RPROGRAM
Table 123. XRESET,XON Characteristics
Min
VXRESET_IL
XRESET Low Level
input voltage
VXRESET_IH
Max
Unit
-0.3
0.4
V
XRESET High Level
input voltage
1.3
VSUPP
LY
V
VXON_IL
XON Low Level input
voltage
-0.3
0.3*V2
_5
VXON_IH
XON High Level input
0.7*V2
_5
V2_5
IXON_PUP
Typ
ca
Parameter
ni
Symbol
XON Pull up current
12
Note
µA
ch
10.2.1 Reset Conditions
Reset can be activated from 7 different sources:
Power on (battery or charger insertion)
Te
Low Battery
Software forced reset
Power off mode
External triggered through the pin RESET
Overtemperature
Watchdog
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Voltage detection:
There are two types of voltage dependent resets: VPOR and VXRESET. VPOR monitors the voltage on V2_5 and
VXRESET monitors the voltage on VSUPPLY. The linear regulator for V2_5 is always on and uses the voltage
VCHARGER, VBAT or V_USB as its source.
The pin RESET is only released if V2_5 is above VPOR and VSUPPLY is above VXRESETRISE.
Table 124. Reset Levels
Parameter
Min
Typ
Max
Unit
Note
VPOR
Overall power on reset
1.5
2.0
2.3
V
Monitor voltage on V2_5; power on
reset for all internal functions
VXRESETRISE
Reset level for Vsupply
rising
ResVol
trise
V
Monitor voltage on Vsupply; rising
level
2.7
V
Monitor voltage on VSupply; falling
level
ResVol
tfall
V
if SupResEn=1 only
VRESETMASK
lv
am
lc s
on A
te G
nt
st
il
VXRESETFALLING Reset level for Vsupply
falling
al
id
Symbol
Mask time for
VXRESETFALLING
2.0
2.5
3.0
ms
Duration for VBAT<VXRESETFALLING
until a reset cycle is started
1
1. VRESET signal is debounced with the specified mask time for rising- and falling slope of VBAT.
VRESETFALLING is only accepted if the reset condition is longer than VRESETMASK. This guard time is used to avoid a
complete reset of the system in case of short drops of VBAT.
Power off:
To put the chip into ultra low power mode, write ‘1’ into xon_enable and ‘1’ into power_off. The chip stays in power off
mode until the external pin XON is pulled low, the charger is inserted or the level VPOR is touched to start a complete
reset cycle. The bit power_off is automatically cleared by this reset cycle. During power_off state all circuits are shut-off
except the Low Power LDO (V2_5). Thus the current consumption of AS3658 is reduced to less than 15 µA. The digital
part is supplied by V2_5, all other circuits are turned off in this mode, including references and oscillator. Except the
reset control registers all other registers are set to their default value after power-on.
Software forced reset
ca
Writing ‘1’ into the register bit force_reset immediately starts a reset cycle. The bit force_reset is automatically cleared
by this reset.
External triggered reset:
ni
If the pin XRESET is pulled from high to low by an external source (e.g. microprocessor or button) a reset cycle is
started as well.
Overtemperature reset:
ch
The reset cycle can be started by overtemperature conditions. (see Protection Functions on page 134)
Watchdog reset:
Te
If the watchdog is armed (register bit wtdg_on = 1 and wtdg_res_on = 1) and the timer expires it causes a reset. (see
Watchdog on page 135).
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- Detailed Description - System Functions
10.2.2 Reset Control Bits
Table 125. Reset Timer Register
Reset Timer
Addr:22
Bit Name
Default
Access
Description
Set RESTIME
ROM
R/W
RESTIME=10ms
001
RESTIME=20ms
010
RESTIME=35ms
011
RESTIME=50ms
100
RESTIME=65ms
101
RESTIME=80ms
110
RESTIME=95ms
111
RESTIME=110ms
lv
res_timer
000
am
lc s
on A
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nt
st
il
2:0
al
id
Bit
These bits control the reset timer and XON enable register
This flag enables the XON pad and sets the power on
state of the ASIC
3
xon_enable
ROM
R/W
0
XON pad disabled. Startup of chip; if
VBAT>VRESETRISING
1
XON pad enabled. Startup of chip; if
VBAT>VRESETRISING and XON=0
Table 126. Reset Control Register
Reset Control
Addr:105
Bit
Bit Name
Default
Access
Description
0
force_reset
0b
R/W
Setting to ‘1’ starts a complete reset cycle
1
power_off
0b
R/W
Setting to ‘1’ starts a reset cycle, but waits after the
Reg_off state for a falling edge on the pin XON or until
the charger is detected
2
ca
These bits control the power off mode and reset timer
xon_input
R/W
Read:This flag represents the state of the XON pad
directly
Write: Setting to '1' resets the 5 sec. Onkey reset timer
Te
ch
ni
NA
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- Detailed Description - System Functions
Table 126. Reset Control Register
Reset Control
Addr:105
Bit
Bit Name
These bits control the power off mode and reset timer
Default
Access
Description
Flags to indicate to the software the reason for the last
reset
NA
R
VRESETFALLING was reached (battery voltage
drop below 2.75V)
0010
software forced by force_reset
0011
software forced by power_off and XON was
pulled low
al
id
0001
lv
reset_reason
VPOR has been reached (battery or charger
insertion from scratch)
0100 software forced by power_off and charger was
detected
am
lc s
on A
te G
nt
st
il
6:3
0000
7
Onkey_reset_5s
1
R/W
0101
external triggered through the pin RESET
0110
reset caused by overtemperature T140
0111
reset caused by watchdog
1000
reset caused by 5 seconds on press
1001
reset caused by rtc_alarm register
1010
reset caused by rtc repeated wakeup
1011
reset caused by interrupt in standby mode
1100
reset caused by XON pulled low in standby
mode
0
Reset after 5 seconds ON pressed disabled
1
Reset after 5 seconds ON pressed enabled
Table 127. Internal references Bit definitions
Internal references Bit definitions
Bit Name
ni
Bit
standby_mode_on
Default
0
Access
Description
W
Setting to ‘1’ sets the AS3658 into standby mode. All
regulators defined in reg.17h “Reg Power1Ctrl” and
reg.1Eh “Reg Power2 Ctrl are disabled except those
regulators enabled by reg.81h “Reg standby mode”.
XRESET will be pulled to low. A normal startup of all
regulators will be done with any interrupt (has to be
enabled before entering standby mode). During this
startup, regulators defined by Reg standby mode
register are continuously on.
Te
ch
4
These bits control the internal reference mode and internal clk
frequency
ca
Addr:59
5
Clk_div2
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Divide internal clock oscillator by 2 to reduce
quiescent current for low power operation
0
0
Normal mode
1
Internal clock frequency divided by two. All
timings are increased by two. Switching
frequency of all DCDC converters are divided
by two. Reduced transient performance of
DCDC converters.
R/W
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- Detailed Description - System Functions
Table 127. Internal references Bit definitions
Internal references Bit definitions
Addr:59
Default
Reg_low_bias_mode
0
Access
R/W
Description
0
Normal mode
1
The quiescent current of the following
regulators is divided by approx. two: SD1,
SD2, SD3, RF1, RF2, RF3. The current
capability and performance is also reduce in
that mode. (E.g. Use this bit only to reduce
quiescent current, if system and processor is
in a low power mode)
al
id
6
Bit Name
Table 128. Reg standby mode Bit definitions
Reg standby mode
These bits control the on/off function of the regulators during standby
mode
am
lc s
on A
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nt
st
il
Addr:129
lv
Bit
These bits control the internal reference mode and internal clk
frequency
Bit Name
Default
Access
0
ldo_rf1_stby_on
0
R/W
1
ldo_rf2_stby_on
0
R/W
2
ldo_dig1_stby_on
0
R/W
3
ldo_dig2_stby_on
0
R/W
4
sd1_stby_on
0
R/W
5
sd2_stby_on
0
R/W
6
sd3_stby_on
0
R/W
7
cp_stby_on
0
R/W
Description
0
RF1 LDO is disabled in standby mode
1
RF1 LDO is enabled in standby mode
0
RF2 LDO is disabled in standby mode
1
RF2 LDO is enabled in standby mode
0
DIG1 LDO is disabled in standby mode
1
DIG1 LDO is enabled in standby mode
0
DIG2 LDO is disabled in standby mode
1
DIG2 LDO is enabled in standby mode
0
Step down 1 is disabled in standby mode
1
Step down 1 is enabled in standby mode
0
Step down 2 is disabled in standby mode
1
Step down 2 is enabled in standby mode
0
Step down 3 is disabled in standby mode
1
Step down 3 is enabled in standby mode
0
Charge pump is disabled in standby mode
1
Charge pump is enabled in standby mode
Te
ch
ni
ca
Bit
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- Detailed Description - System Functions
Table 129. Charger supervision
Fuel Gauge
Addr:14
Bit
Bit Name
This bit controls first startup out of power on reset
Default
Access
Description
Switch on Power off mode at first startup(e.g. First
battery insertion or first charger insertion)
Table 130. Fuel Gauge
Fuel Gauge
Addr:15
Bit
1
R/W
al
id
Boot
ROM
Startup of all regulators only if onkey is
pressed or rtc alarm (no startup on battery
insertion; no startup if charger detected, if
no_charging=0). xon_enable has to be set in
bootrom.
If a charger is detected and the bit
no_charging=0 (defined by BootROM) and
ch_pwroff_en=0 the AS3658 will start
charging without regulators startup (fully
autonomous charging).
If the bit no_charging=1 and a charger is
detected, the regulators are started and the
charging can be enabled with software
control.
lv
auto_shutdown
Startup of all regulators if battery is inserted,
charger insertion, onkey pressed or rtc alarm.
am
lc s
on A
te G
nt
st
il
4
0
Bit Name
This bit controls first startup out of power on reset
Default
Access
Description
Switch on Power off mode if low Vsupply is detected
during active or standby mode (Pin XON= high and bit
xon_enable=0)
5
power_off_at_v_suplow
R/W
0
If low battery is detected, continuously monitor
battery voltage and startup if battery voltage is
above ResVoltrise
1
If low battery is detected, enter power off
mode
ca
10.2.3 Reset Cycle
Boot
ROM
ni
During a reset cycle the pin XRESET is forced to low for at least RESTIME and all registers are set to their default
values (except the registers marked green in theTable 186 on page 148). During the reset time a normal startup
happens (see Startup on page 129), the reset is active until the reset timer (set by register bits res_timer<2:0>) expires.
Then the voltage on the pin XRESET is pulled high by the external resistor and the whole system is leaving the reset
state.
ch
10.2.4 Reset Control: res_con
Te
Reset is internally generated from a power supply supervisor and provided to internal logic as well as externally
through the open-drain pad XRESET. At this point, it could be also forced externally from an external power supply
supervisor. Additionally Reset can be forced by software.
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10.3
- Detailed Description - System Functions
Interrupt Controller
al
id
The interrupt controller generates an interrupt request for the host controller as soon as one or more of the bits in the
Interrupt 1…3 register is set by pulling low pin XINT. All the interrupt sources can be enabled in the Interrupt Mask 1…3
register. The Interrupt 1…3 registers are cleared automatically after the host controller has read them. To prevent the
AS3658 device from losing an interrupt event, the register that is read is captured before it is transmitted to the host
controller via the serial interface. As soon as the transmission of the captured value is complete a logical AND
operation with the bit wise inverted captured value is applied to the register to clear all interrupt bits that have already
been transmitted. Clearing the read interrupt bits takes 2 clock cycles, a read access to the same register before the
clearing process has completed will yield a value of ‘0’. Note that an interrupt that has been present at the previous
read access will be cleared as well in case it occurs again before the clearing process has completed.
am
lc s
on A
te G
nt
st
il
lv
During a read access to one of the interrupt registers the XINT pin will be released. As soon as the transferred bits of
the interrupt register have been cleared the XINT pin will be pulled low in case a new interrupt has occurred in the
meantime. By doing so the interrupt controller will work correctly with host controllers that are edge- and level-sensitive
on their interrupt request input. Multiple byte read access is recommended to avoid reading the Interrupt 1 register
over and over again in response to a new interrupt that has occurred in the same register (and thus pulling low pin
XINT) before the Interrupt 2,3 register has been read.
Table 131. Interrupt Status 1 Register
Interrupt Status1
Addr:50
These bits show the status of the interrupts
register is reset at power-on-reset and after each read access
Bit Name
Default
Access
Description
0
chstate_i
NA
R
Bit is set when the following status bits are set or reset:
Trickle, CVM, NoBat
1
cheoc_i
NA
R
Bit is set when the EOC status bits are set or reset:
2
charging_tmax_i
NA
R
Bit is set when charge timeout ( tricke, CV, CC) has
been expired
3
usb_chdet_i
NA
R
Bit is set when the USB_ChDet Bit is set or reset.
4
chdet_i
NA
R
Bit is set when the ChDet Bit is set or reset.
5
Onkey_i
NA
R
Bit is set when status XON bit is set or reset.
6
ovtmp_i
NA
R
Bit is set when the lower temperature threshold
Temp110 of the temperature sensor is exceeded for
longer than tRESMASK.
R
Bit is set when the main supply voltage VSUPPLY has
dropped below VRESFALL for longer than tRESMASK.
ca
Bit
7
Lowsup
NA
ni
Table 132. Interrupt Status 2 Register
ch
Addr:51
Interrupt Status2
These bits show the status of the interrupts
register is reset at power-on-reset and after each read access
Bit Name
Default
Access
Description
0
sd1_lv_i
NA
R
Bit is set when voltage of step down1 drops below low
voltage threshold (1msec debounce timer)
1
sd2_lv_i
NA
R
Bit is set when voltage of step down2 drops below low
voltage threshold
(1msec debounce timer)
2
sd3_lv_i
NA
R
Bit is set when voltage of step down3 drops below low
voltage threshold
(1msec debounce timer)
Te
Bit
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- Detailed Description - System Functions
Table 132. Interrupt Status 2 Register
Interrupt Status2
Addr:51
These bits show the status of the interrupts
register is reset at power-on-reset and after each read access
Bit Name
Default
Access
Description
3
dig1_lv_i
NA
R
Bit is set when voltage of LdoDig1 drops below low
voltage threshold
(1msec debounce timer)
4
dig2_lv_i
NA
R
Bit is set when voltage of LdoDig2 drops below low
voltage threshold
(1msec debounce timer)
5
hphcurr_i
NA
R
Bit is set when output stage of headphone amplifier
exceeds overcurrent limit.
6
bat_temp_i
NA
R
Bit is set when bit bat_hightemp or bat_lowtemp is set
or reset
7
stpup1_i
NA
R
Bit is set when stpup1_oc or stpup1_det is set.
am
lc s
on A
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nt
st
il
lv
al
id
Bit
Table 133. Interrupt Status 3 Register
Interrupt Status3
Addr:52
These bits show the status of the interrupts
register is reset at power-on-reset and after each read access
Bit Name
Default
Access
Description
0
dig3_lv_i
NA
R
Bit is set when voltage of LdoDig3 drops below low
voltage threshold
(1msec debounce timer)
1
dig4_lv_i
NA
R
Bit is set when voltage of LdoDig4 drops below low
voltage threshold
(1msec debounce timer)
2
rtc_alarm_i
NA
R
Bit is set by the RTC, if alarm registers=rtc registers
3
rtc_rep_i
NA
R
Bit is set by the RTC every second (Bit irq_min=0) or
minute (Bit irq_min=1)
4
mic_con_i
NA
R
Bit is set if a microphone is detected on MIC input
5
mic_rem_i
NA
R
Bit is set, if the microphone supply is increased
(remote key press detected) -> measure MICS supply
current
6
voxm_i
NA
R
Bit is set, if voice is detected on MIC input
tpen_i
NA
R
Bit is set, if the touchpen pendown is detected
ni
7
ca
Bit
ch
Table 134. Interrupt mask 1 Register
Interrupt Mask1
Addr:47
Bit Name
Default
Access
0
chstate_int_mask
1b
R/W
1
cheoc_int_mask
1b
R/W
Te
Bit
These bits mask the interrupt
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Description
0
Interrupt is enabled
1
Interrupt is disabled
0
Interrupt is enabled
1
Interrupt is disabled
Revision 1v13
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- Detailed Description - System Functions
Table 134. Interrupt mask 1 Register
Interrupt Mask1
Addr:47
These bits mask the interrupt
Access
2
charging_tmax_int_mask
1b
R/W
3
usb_chdet_int_mask
1b
R/W
4
chdet_int_mask
1b
R/W
5
onkey_int_mask
1b
R/W
6
ovtmp_int_mask
1b
R/W
7
LowSup_int_mask
1b
R/W
Description
0
Interrupt is enabled
1
Interrupt is disabled
0
Interrupt is enabled
1
Interrupt is disabled
0
Interrupt is enabled
1
Interrupt is disabled
0
Interrupt is enabled
1
Interrupt is disabled
0
Interrupt is enabled
al
id
Default
lv
Bit Name
am
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nt
st
il
Bit
1
Interrupt is disabled
0
Interrupt is enabled
1
Interrupt is disabled
Table 135. Interrupt mask 2 Register
Interrupt Mask2
Addr:48
Bit
Bit Name
Default
Access
0
sd1_lv_int_mask
1b
R/W
1
sd2_lv_int_mask
1b
R/W
2
sd3_lv_int_mask
1b
R/W
3
dig1_lv_int_mask
1b
4
ca
R/W
dig2_lv_int_mask
1b
R/W
5
ni
These bits mask the interrupt
1b
R/W
bat_temp_int_mask
1b
R/W
stpup1_int_mask
1b
R/W
ch
hphcurr_int_mask
Te
6
7
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Description
0
Interrupt is enabled
1
Interrupt is disabled
0
Interrupt is enabled
1
Interrupt is disabled
0
Interrupt is enabled
1
Interrupt is disabled
0
Interrupt is enabled
1
Interrupt is disabled
0
Interrupt is enabled
1
Interrupt is disabled
0
Interrupt is enabled
1
Interrupt is disabled
0
Interrupt is enabled
1
Interrupt is disabled
0
Interrupt is enabled
1
Interrupt is disabled
Revision 1v13
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- Detailed Description - System Functions
Table 136. Interrupt mask 3 Register
Interrupt Mask3
Addr:49
These bits mask the interrupt
Access
0
dig3_lv_int_m
1b
R/W
1
dig4_lv_int_m
1b
R/W
2
rtc_alarm_int_m
1b
R/W
3
rtc_rep_int_m
1b
R/W
4
mic_con_int_m
1b
R/W
5
mic_rem_int_m
1b
R/W
6
voxm_intm
1b
R/W
7
tpen_i_m
1b
R/W
Description
0
Interrupt is enabled
1
Interrupt is disabled
0
Interrupt is enabled
1
Interrupt is disabled
0
Interrupt is enabled
1
Interrupt is disabled
0
Interrupt is enabled
1
Interrupt is disabled
0
Interrupt is enabled
al
id
Default
lv
Bit Name
am
lc s
on A
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nt
st
il
Bit
1
Interrupt is disabled
0
Interrupt is enabled
1
Interrupt is disabled
0
Interrupt is enabled
1
Interrupt is disabled
0
Interrupt is enabled
1
Interrupt is disabled
Table 137. Low voltage status1 Register1
Low voltage status1
Addr:53
These bits show the low voltage status of the step down and digital
regulators
Bit Name
Default
Access
Description
0
sd1_lv
NA
R
Step down1 low voltage status bit (-10% voltage drop)
1
sd2_lv
NA
R
Step down2 low voltage status bit (-10% voltage drop)
ca
Bit
2
3
NA
R
Step down3 low voltage status bit (-10% voltage drop)
dig1_lv
NA
R
Ldo Dig1 low voltage status bit (-50mV voltage drop)
dig2_lv
NA
R
Ldo Dig2 low voltage status bit (-50mV voltage drop)
-
-
-
-
6
ni
4
sd3_lv
stpup1_oc
NA
R
Bit is set by analog part, if overcurrent of DCDC
StepUp1 occurs for more than 5msec (latched state)
7
stpup1_det
NA
R
Current Detection signal of step up 1
ch
5
Te
Table 138. Low voltage status2 Register1
Low voltage status2
Addr:54
These bits show the low voltage status of the step down and digital
regulators
Bit
Bit Name
Default
Access
Description
0
dig3_lv
0b
R
Ldo Dig3 low voltage status bit (-50mV voltage drop)
1
dig4_lv
0b
R
Ldo Dig4 low voltage status bit (-50mV voltage drop)
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- Detailed Description - System Functions
Table 138. Low voltage status2 Register1
Low voltage status2
Addr:54
These bits show the low voltage status of the step down and digital
regulators
Bit Name
Default
Access
Description
2
dcdc_curr1_lv
0b
R
Indicates low voltage on dcdc_curr1
3
dcdc_curr2_lv
0b
R
Indicates low voltage on dcdc_curr2
4
dcdc_curr3_lv
0b
R
Indicates low voltage on dcdc_curr3
5
bat_lowtemp
0b
R
Indicates NTC temperature of battery below 0º
6
bat_hightemp
0b
R
Indicates NTC temperature of batter above 45º (50º)
Te
ch
ni
ca
am
lc s
on A
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nt
st
il
lv
al
id
Bit
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10.4
- Detailed Description - System Functions
Startup
Figure 56. Startup flow chart
Power on reset
xon_enable=0
batsw_on=0
batsw_mode=0
Reset registers
except
xon_enable
YES
NO
al
id
xon_enable=1 and
(chdet=0 or
USBChdet=0)
XON pin pulled
to GND
NO
YES
NO
V BAT>V ResVolt?
Switch on
Battery switch
NO
NO
YES
batsw_on=1
batsw_mode=1
ChEn=1
am
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on A
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nt
st
il
Charger
detected ?
lv
YES
NO
USB Sup.
detected and
ChDet=0?
YES
YES
USB_ChEn=1
V SUPPLY>VResVolt?
YES
Startup Device
Active state
batsw_mode
trickle
Switch on
Switch off
batsw_on
0
1
1
1
X
0
batsw_on=0
batsw_mode=0
YES
power_off=1
YES
NO
batsw_on=0
batsw_mode=0
ca
NO
V SUPPLY<VResVolt?
YES
ni
NO
ch
force_reset=1
10.4.1 Normal Startup
Te
During a normal reset cycle (e.g. after the battery or a charger is inserted; (see Reset generator and XON-Key on page
118)), after V2_5 is above VPOR and Vsupply is above VRESETRISE a normal startup happens:
The external capacitor on CREF is charged to 1.8V
The 3bit A/D conversion is performed to measure the external resistor value RPROGRAM
Startup State machine reads out the internal Boot-ROM (address defined by boot_ctrl), Start sequence of StepDown Converter and LDO’s controlled by the Boot-ROM
Reset-Timer is set by the Boot-ROM
The reset is released when the Reset Timer expires (external pin XRESET)
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- Detailed Description - System Functions
10.4.2 Startup from Charger
If the voltage on pin VCHARGER is within VSTARTCHARGER, the AS3658 is started (even with VBAT = 0V). This
allows the battery to be charged (even from deeply discharged batteries) and finally a normal startup to happen.
Table 139. Charger Startup Conditions
Parameter
Min
Typ
Max
unit
Note
VSTARTCHARGER
Voltage on
VCHARGER for
system to start
4.0
5.0
15
V
on Pin VCHARGER
al
id
Symbol
10.4.3 Programmable Startup Sequences—Boot ROM
lv
The startup- and reset sequences of the device are highly configurable. The configuration of these sequences is
defined by the ratio of the internal trimmed bias resistors and RPROGRAM. At the beginning of each reset cycle a 3 bit
AD-conversion is performed. The result of this conversion is used to select 1 of 8 possible address-ranges of an
internal mask-programmable ROM. The information that is stored in this ROM defines the following parameters:
Voltage levels for all regulators and step down dcdc converters
am
lc s
on A
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nt
st
il
power-on sequence of RF_1, RF_2, DIG_1, DIG_2, SD1, SD2 and SD3
duration of the reset cycle
several other configuration bits (e.g. charger)
The following values of RPROGRAM are used to select the 8 possible address ranges (8 different startup voltage /
sequences settings can be used):
000: open
001: 320kΩ
010: 160kΩ
011: 80kΩ
100: 40kΩ
101: 20kΩ
110: 10kΩ
111: 0Ω
Table 140. Boot ROM Bits definitions
Boot_status
These bits show the boot status
Bit
Bit Name
Default
Access
Description
2:0
rom_adr
NA
R
Boot-ROM address
3
ni
ca
Addr:107
1
R
If ‘1’ Boot-ROM address is valid
rom_valid
Te
ch
Note: For detailed startup sequences see austriamicrosystems AG document AS3658_BootROM_*.
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- Detailed Description - System Functions
10.4.4 Additional Startup Settings
Table 141. Boot ROM Bits definitions
LDO_RF2_Voltage
Addr:4
double_reset
7
slow_startup
6
Default
ROM
Access
R/W
ROM
Description
0
Normal reset pulse
1
Apply double reset pulse after the normal rest
pulse that is define by res_timer. (pulse on
XRESET with 2msec high time and 2msec
low time
0
Normal startup of LDOs defined in boot rom
with a separation of 1 milliseconds
1
Startup of all LDOs defined by boot rom with a
time separation of 4 milliseconds
R/W
al
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Bit Name
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10.4.5 Programmable Startup Sequences with fuse registers—Boot OTP
lv
Bit
These bits defines the startup sequence
Its possible to program some startup registers, by using the fuse block:
Table 142. ROMF Bit definitions
FUSE4
Addr:196
These bits control the startup and are set by factory test
Bit
Bit Name
Default
Access
7
romf_en
0
R
Description
0
Fusible startup rom disabled
1
Feasible startup of rom enabled
(UniqueID0.UniqueID10) used for startup
Table 143. ROMF Bit definitions
addrf0
Addr:197
Bit
Bit Name
These bits control the startup and are set by factory test
Default
Access
Description
ca
Each bit represents a register address of the bootrom
table (0....31)
addrf<7:0>
0
R
ni
7:0
0
Use data of ROM table during startup for the
according address (0....31)
1
Use data of fuse register during startup for the
according address, starting with data of
register romf0 (up to register romf6 max.)
ch
Table 144. ROMF Bit definitions
addrf0
Addr:198
Te
Bit
7:0
Bit Name
These bits control the startup and are set by factory test
Default
Access
Description
Each bit represents a register address of the bootrom
table (0....31)
addrf<15:8>
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0
R
0
Use data of ROM table during startup for the
according address (0....31)
1
Use data of fuse register during startup for the
according address, starting with data of
register romf0 (up to register romf6 max.)
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Table 145. ROMF Bit definitions
addrf2
Addr:199
Bit
Bit Name
These bits control the startup and are set by factory test
Default
Access
Description
Each bit represents a register address of the bootrom
table (0....31)
0
R
0
Use data of ROM table during startup for the
according address (0....31)
1
Use data of fuse register during startup for the
according address, starting with data of
register romf0 (up to register romf6 max.)
al
id
addrf<23:16>
Table 146. ROMF Bit definitions
addrf3
Addr:200
lv
7:0
am
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on A
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nt
st
il
These bits control the startup and are set by factory test
Bit
Bit Name
Default
Access
Description
Each bit represents a register address of the bootrom
table (0....31)
7:0
addrf<31:24>
0
R
0
Use data of ROM table during startup for the
according address (0....31)
1
Use data of fuse register during startup for the
according address, starting with data of
register romf0 (up to register romf6 max.)
Table 147. ROMF Bit definitions
romf0
Addr:201
These bits control the startup and are set by factory test
Bit
Bit Name
Default
Access
Description
7:0
romf0
00h
R
Data for startup register (used for the first “1” in the
addrf<31:0> register
ca
Table 148. ROMF Bit definitions
Addr:202
7:0
Bit Name
ni
Bit
romf1
romf1
These bits control the startup and are set by factory test
Default
Access
Description
00h
R
Data for startup register (used for the second “1” in the
addrf<31:0> register
ch
Table 149. ROMF Bit definitions
romf2
Te
Addr:203
These bits control the startup and are set by factory test
Bit
Bit Name
Default
Access
Description
7:0
romf2
00h
R
Data for startup register (used for the third “1” in the
addrf<31:0> register
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- Detailed Description - System Functions
Table 150. ROMF Bit definitions
romf3
Addr:204
These bits control the startup and are set by factory test
Bit Name
Default
Access
Description
7:0
romf3
00h
R
Data for startup register (used for the fourth “1” in the
addrf<31:0> register
Table 151. ROMF Bit definitions
romf4
Addr:205
al
id
Bit
These bits control the startup and are set by factory test
Bit Name
Default
Access
Description
7:0
romf4
00h
R
Data for startup register (used for the fifth “1” in the
addrf<31:0> register
lv
Bit
am
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on A
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nt
st
il
Table 152. ROMF Bit definitions
romf5
Addr:206
These bits control the startup and are set by factory test
Bit
Bit Name
Default
Access
Description
7:0
romf5
00h
R
Data for startup register (used for the sixth “1” in the
addrf<31:0> register
Table 153. ROMF Bit definitions
romf6
Addr:207
Bit
Bit Name
romf6
Default
00h
Access
Description
R
Data for startup register (used for the seventh “1” in
the addrf<31:0> register
Te
ch
ni
ca
7:0
These bits control the startup and are set by factory test
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10.5
- Detailed Description - System Functions
Protection Functions
All LDO’s, the DCDC step ups and DCDC step downs have an integrated overcurrent protection. An overtemperature
protection of the chip is also integrated which can be switched on with the serial interface signal temp_pmc_on
(enabled by default; it is not recommended to disable the overtemperture protection). The chip has two signals for the
serial interface: ov_temp_110 and ov_temp_140. The flag ov_temp_110 is automatically reset if the overtemperature
condition is removed, whereas ov_temp_140 has to be reset by the serial interface with the signal rst_ov_temp_140.
al
id
If the flag ov_temp_140 is set, an automatic reset of the complete chip is initiated. The flag ov_temp_140 is not
affected by this reset cycle allowing the software to detect the reason for this unexpected shutdown.
Table 154. Overtemperature Detection
Min
Typ
Max
Unit
T110
ov_temp_110 rising
threshold
95
110
125
ºC
T140
ov_temp_140 rising
threshold
125
140
155
ºC
Thyst
ov_temp_110 and
ov_temp_140
hysteresis
Note
lv
Parameter
am
lc s
on A
te G
nt
st
il
Symbol
5
ºC
Table 155. Overtermperature detection Bit definition
Overtemperature Control
Addr:106
These bits control the startup and are set by factory test
Bit
Bit Name
Default
Access
Description
0
temp_pmc_on
1
R/W
Switch on / off of temperature supervision; default: on
– all other bits are only valid if set to ‘1’
Leave at 1, do not disable
1
ov_temp_110
NA
R
Flag that the overtemperature threshold 1 (T110) has
been reached
R
Flag that the overtemperature threshold 2 (T140) has
been reached – this flag is not reset by a
overtemperature caused reset and has to be reset by
rst_ov_temp_140
W
If the overtemperature threshold 2 has been reached,
the flag ov_temp_140 is set and a reset cycle is
started. ov_temp_140 should be reset by writing 1 and
afterward 0 to rst_ov_temp_140
2
ov_temp_140
rst_ov_temp_140
0
ca
3
NA
10.5.1 Temperature Supervision
ch
ni
A temperature sensor is implemented to provide over-temperature protection of the chip. It generates two flags linked
to the two temperature thresholds (110 degrees, 140 degrees). Both thresholds have an hysteresis to prevent
oscillation effects.
First threshold (110 degrees) sets the flag ov_temp_110, signalling the serial interface part and software the 110
degrees overtemperature condition. If enabled (ovtmp_int_mask=0), an interrupt can be send (interrupt ‘ovtmp’). Thus
software can react and can shutdown power consuming functions to decrease temperature.
Te
The second threshold (140 degrees) initiates a reset cycle and sets ov_temp_140: this sets all regulators into powerdown mode and stops charging, and performs the reset cycle of the AS3658.
rst_ov_temp_140 flag
In case of overtemperature and an activated reset (temp_pmc_on=1), the system loses any information about the error
which activated the reset state. Therefore, a flag is implemented, which indicates that the reset was caused by
overtemperature activation (ov_temp_140 is set). This flag is only resetable by writing ‘1’ to rst_ovtemp_140.
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10.6
- Detailed Description - System Functions
Watchdog
The purpose of the watchdog is to detect a deadlock of the software. If the watchdog is active, it must receive a
continuous trigger signal within a programmable time window. If there is no signal anymore for a certain time period
from a defined pad or special serial interface bit, it starts either a complete reset cycle or changes the state of an output
pin, which can be used e.g. as an interrupt to the processor.
The watchdog is highly configurable by the following register bits:
The watchdog time window is defined by the register wtdg_min_timer and wtdg_max_timer.
al
id
The complete block can be switched on by wtdg_on = 1 and off by wtdg_on = 0.
The trigger signal can be configured by register wtdg_trigger and wtdg_gpio_input. (Pin CURR1-CURR4 (GPIO1GPIO4) or register bit)
If the watchdog expires, the system can start automatically a reset cycle if wtdg_reset_on = 1
am
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nt
st
il
lv
Any of the general purpose input / outputs can be configured to output the watchdog signal. The Watchdog delivers
a signal “wtdg_alarm”, which is normal ‘0’ and goes to ‘1’ in the case of a timer-overflow. This signal can be used as
e.g. a reset or interrupt for a processor.
Table 156. Watchdog Register definitions
Watchdog control
Addr:60
Bit
Bit Name
These bits control the watchdog functions
Default
Access
Description
Switches on the complete watchdog
0
wtdg_on
1
0
wtdg_res_on
wtdg_trigger
0
ca
2
1
R/W
R/W
0
watchdog off
1
watchdog enabled
If the watchdog expires and wtdg_res_on = 1 a reset
cycle will be started
0
Use the register bit wtdg_sw_signal as trigger
signal for the watchdog
1
Use one of the GPIO pins CURR1_GPIO1 …
CURR4_GPIO4 as trigger input for the
watchdog; the actual pin is selected by setting
GPIOXIOSF to 01b(watchdog mode) and
GPIOXMode=010b (GPIO digital input)
(X=1...4)
R/W
Table 157. Watchdog minimum timer definitions
Bit
Watchdog_min timer
These bits set the watchdog minimum timer
Bit Name
Default
Access
Description
Wtdg_min_timer
00h
R/W
Defines the minimum watchdog trigger time
(LSB=7.5ms, range: 0 – 1.9s)
ch
7:0
ni
Addr:61
Te
Table 158. Watchdog max timer definitions
Bit
7:0
Watchdog_max timer
Addr:62
Bit Name
Wtdg_max_timer
www.austriamicrosystems.com
These bits set the watchdog maximum timer
Default
FFh
Access
Description
R/W
Defines the maximum watchdog trigger time
(LSB=7.5ms, range: 7.5ms – 1.9s), do not set to (00)h
Revision 1v13
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- Detailed Description - System Functions
Table 159. Watchdog software signal definitions
Watchdog software signal
Addr:63
This bit sets the watchdog software trigger
Bit
Bit Name
Default
Access
Description
0
wtdg_sw_signal
0
R/W
Trigger input by the serial interface if wtdg_trigger = 0
tmin
al
id
Figure 57. Watchdog timing diagram
tmax
wtdg_trigger
10.7
lv
tmax
am
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on A
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nt
st
il
tmin
General Purpose 10 Bit ADC
Table 160. ADC Characteristics
Resolution
Input Voltage
Range
Differential
Nonlinearity
Integral
Nonlinearity
Input Offset
Voltage
Input Impedance
Input Capacitance
Power Supply
Current
Power Down
Current
Parameter
Min
Typ
Max
10
Vin
Unit
1.8
V
DNL
± 0.25
LSB
INL
± 0.5
LSB
Vos
2
LSB
Rin
100
9
Idd
1LSB 1.76mV (depending on
selected channel)
MΩ
Cin
Idd
Note
Bit
0
ca
Symbol
pF
500
µA
100
nA
During conversion only
ni
Transient Parameters (25°C)
Tc
40
µs
Clock Frequency
fc
fclk_int/
8
kHz
Settling time of
S&H
ts
Te
ch
Conversion Time
ADC_IN1 pull up
current
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1
14.25
internal CLK frequency/8
Programmable:
0.2 to 0.2875 MHz
µs
15
15.75
Revision 1v13
µA
Pull up current for ADC_IN1, if
adc_idc=1111b
136 - 157
AS3658
Data Sheet Confidential
- Detailed Description - System Functions
Table 161. ADC control Registers bits
ADC_control
Addr:96
Bit
This register controls the 10 Bit ADC
Bit Name
Default
Access
Description
Selects an ADC channel
0000b
R/W
ADC2_IN (LSB = 1.76mV)
0010
VBAT Battery voltage (LSB=5.27mV)
0011
VCHARGER (LSB=17. 6mV) clamping at 10V
0100
V_USB Voltage (LSB=5.27mV)
0101
not used
0110
temperature sensor:
DIE temperature [°C] = adc_result * 0.866 –
274
al
id
0001
lv
adc_select
ADC1_IN (LSB = 1.76mV)
am
lc s
on A
te G
nt
st
il
3:0
0000
0111
ADC test channel – do not use
1000
check voltage on MICS for remote control or
external voltage measurement (LSB=3.52mV)
1001
VBACK voltage (LSB=3.52mV)
select ADC sampling frequency
4
adc_slow
5
-
0b
R/W
-
0
275kHz (conversion time: 60µs)
1
70kHz (conversion time: 240µs)
-
reserved (do not use)
6
adc_on
0b
R/W
Writing a 1 into this bit continuously activates the ADC
S/H and the input multiplexer. The ADC and the MUX
are also activated for a conversion period when
start_conversion is set to ‘1’ – useful for high
impedance input sources on ADC1_IN or ADC2_IN
7
start_conversion
0b
R/W
Writing a 1 into this bit starts one ADC conversion.
ca
Table 162. ADC MSB result register
Bit
Bit Name
0
ni
Addr:97
1
Default
Access
Description
D3
NA
R
ADC result register
D4
NA
R
ADC result register
D5
NA
R
ADC result register
ch
2
ADC_MSB result
This register shows the MSB result of the ADC conversion
D6
NA
R
ADC result register
D7
NA
R
ADC result register
5
D8
NA
R
ADC result register
6
D9
NA
R
ADC result register
7
result_not_ready
NA
R
Te
3
4
Indicates end of conversion
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0
result is ready
1
conversion is running
Revision 1v13
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AS3658
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- Detailed Description - System Functions
Table 163. ADC LSB result register
ADC_LSB result
Addr:98
Bit
Bit Name
Default
Access
Description
0
D0
NA
R
ADC result register
1
D1
NA
R
ADC result register
2
D2
NA
R
ADC result register
7:3
-
-
-
reserved (do not use)
ADC idac
Addr:46
Bit
Bit Name
lv
Table 164. ADC IDAC register
al
id
This register shows the LSB result of the ADC conversion
This register controls the current sink on pin ADC_IN1
Default
Access
Description
0
am
lc s
on A
te G
nt
st
il
Current source at ADC_IN1 input
Set to 0000 if battery temperature supervision
is enabled.
adc_idac
000b
R/W
0000
0µA (current sink disabled)
0001
1µA
...
1111
15 µA
Figure 58. ADC Timing-diagram
I2C Bus start_conversion=1
1
275kHz
Sample
ADC_ON
ni
result_not ready
12
13
old_Data
Data not valid
Data ready
Te
ch
D<9:0>
3
ca
start_adc
2
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10.8
- Detailed Description - System Functions
Internal References (V, I, fclk)
The internal reference circuits needs the following external components:
Table 165. Reference External Components
Parameter
Min
Typ
Max
Unit
Note
CEXT
External filter capacitor
-10%
100
+10%
nF
Ceramic low-ESR capacitor
between CREF and VSS
RBIAS
External bias current
set resistor
-1%
220
+1%
kΩ
Bias Current set resistor between
RBIAS and VSS
Table 166. References Parameters
al
id
Symbol
Parameter
Min
Typ
Max
Unit
Note
VCEXT
Reference Voltage
-1%
1.8
+1%
V
Low noise trimmed voltage
reference – connected to Pad
CREF; do not load
fCLK
Accuracy of Internal
reference clock
-10
fCLK
+10
%
Adjustable by serial interface
register clk_int
am
lc s
on A
te G
nt
st
il
lv
Symbol
To reduce the current consumption of the chip, the circuit can be set into a special low power mode with the serial
interface bit ‘low_power_on’. All specification parameters except the noise parameters are still valid for this mode.
Table 167. Internal references Bit definitions
Internal references Bit definitions
Addr:59
These bits control the internal reference mode and internal clk
frequency
Bit
Bit Name
Default
Access
0
low_power_on
0b
R/W
Description
0
Standard mode
1
Low power mode – all specification except
noise parameters are still valid
ca
Sets the internal CLK frequency fCLK used for fuel
gauge, DCDCs, PWM, charge pump.
All frequencies, timings and delays in this datasheet
are based on 2.2MHz clk_int
clk_int
ch
ni
3:1
110b
R/W
000b
1.6 MHz
001b
1.7 MHz
010b
1.8 MHz
011b
1.9 MHz
100b
2.0 MHz
101b
2.1 MHz
110b
2.2 MHz (default)
111b
2.3 MHz
Te
10.8.1 Low Power Mode
Use bit low_power_on (reg. References Control (see Table 167)) to activate the Low Power Mode. In this mode the
on-chip voltage reference and the temperature supervision comparators are operating in pulsed mode. This reduces
the quiescent current of the AS3658 by 45uA (typ.). Because of the pulsed function some specifications are not fulfilled
in this mode (e.g. increased noise), but still the full functionality is available.
Note: Low power mode can be controlled by the serial interface.
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10.9
- Detailed Description - System Functions
Real-Time Clock (RTC) Module
The RTC module provides time information to the system. It is implemented as a 6-bit counter that is incremented
every second - with the 32kHz oscillator delivering the necessary accurate time base – and is reset to 0 each time the
counter value is 60. An additional 24-bit minute counter is incriminated each time the 6-bit counter is reset to 0. Both
counters are set to 0 at a power-on-reset. The host controller can set the counter to any value by setting the RTC 1…4
registers.
am
lc s
on A
te G
nt
st
il
lv
al
id
To prevent ambiguous time information because of the 30-bit value being incremented before all of the 4 registers
have been read or written, a 30-bit parallel shadow register is implemented. Every time a write/read access via the
serial interface occurs the parallel shadow register is updated with the current value of the 30-bit counter. Any write
access to the RTC 1 register will disable the update of the parallel register and set the value of the appropriate byte of
the parallel register. Any subsequent write access to the RTC 4 register will transfer the current value of the 30-bit
parallel register to the RTC 1…4 registers and the update of the parallel register is enabled again. Similarly, any read
access to the RTC 1 register will freeze the current value of the parallel register and submit the appropriate byte to the
host controller via the serial interface. Any subsequent read access to the RTC 4 register will enable the update of the
parallel register again. This mechanism makes sure that the maximum error of the value that is written to or read from
the registers is 1 second.
The startup state after power on reset:RTCSecond=3F, RTCMinute1=FF, RTCMinute2=FF, RTCMinute3=FF
To start the RTC, rtc_mode bits have to be set to a non zero value, and the RTC registers have to be set.
The RTC stops automatically at its highest value (3F,FF,FF,FF) to prevent overrun.
Table 168. RTC Second Register
RTCSecond
Addr:64
These bits represents the actual RTC second register
register is reset at power-on-reset only
Bit
Bit Name
Default
Access
Description
5:0
RTCSecond
00h
R/W
Bits 5:0 of the 6-bit RTC second counter
7:6
-
-
reserved
Table 169. RTC Minute1 Register
RTCMinute1
Addr:65
Bit Name
7:0
RTCMinute1
Default
ca
Bit
These bits represents the actual RTC Minute1 register
register is reset at power-on-reset only
00h
Access
Description
R/W
Bits 7…0 of the 24-bit RTC minute counter
ni
Table 170. RTC Minute2 Register
RTCMinute2
ch
Addr:66
These bits represents the actual RTC Minute2 register
register is reset at power-on-reset only
Bit Name
Default
Access
Description
RTCMinute2
00h
R/W
Bits 15:8 of the 24-bit RTC minute counter
Te
Bit
7:0
Table 171. RTC Minute3 Register
RTCMinute3
Addr:67
These bits represents the actual RTC Minute3 register
register is reset at power-on-reset only
Bit
Bit Name
Default
Access
Description
7:0
RTCMinute3
00h
R/W
Bits 23:16 of the 24-bit RTC minute counter
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- Detailed Description - System Functions
The RTC module includes an alarm function. When the content of the RTC 1…4 registers equals the content of the
RTC Alarm 1…4 registers bit RTCAlarm will be set in the Interrupt 1 register. Furthermore the RTC module can
generate an interrupt every second (RTC1Sec will be set) and every minute (RTC1min will be set every time the 6-bit
second counter is reset to 0). For further details on interrupt generation please refer to Interrupt Controller on page
124.
Table 172. RTC Alarm second Register
RTC AlarmSecond
Addr:68
lv
These bits set the RTC Alarm Seconds
register is reset at power-on-reset only
al
id
To avoid ambiguous behavior during write access to the RTC Alarm 1…4 registers any write access to the RTC Alarm
1 register will disable the alarm function; any subsequent write access to the RTC Alarm 4 will enable the alarm
function again.
Bit Name
Default
Access
Description
5:0
RTCAlarmSecond
3Fh
R/W
Bits 5…0 of 6-bit RTC second alarm value
am
lc s
on A
te G
nt
st
il
Bit
Table 173. RTC Alarm minute1 Register
RTC AlarmMinute1
Addr:69
These bits set the RTC Alarm Minute1
register is reset at power-on-reset only
Bit
Bit Name
Default
7:0
RTCAlarmMinute1
FFh
Access
Description
Bits 7:0 of the 24-bit RTC minute alarm value
Table 174. RTC Alarm minute2 Register
RTC AlarmMinute2
Addr:70
These bits set the RTC Alarm Minute2
register is reset at power-on-reset only
Bit
Bit Name
Default
7:0
RTCAlarmMinute2
FFh
Access
Description
Bits 15:8 of the 24-bit RTC minute alarm value
Table 175. RTC Alarm minute3Register
ca
RTC AlarmMinute3
Bit
Bit Name
Default
7:0
ni
Addr:71
FFh
Access
Description
Bits 23:16 of the 24-bit RTC minute alarm value
Te
ch
RTCAlarmMinute3
These bits set the RTC Alarm Minute3
register is reset at power-on-reset only
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- Detailed Description - System Functions
Table 176. RTCT Register
RTCT
Addr:72
Bit
Bit Name
These bits set the RTC correction and RTC interrupt mode
register is reset at power-on-reset only
Default
Access
Description
0000000
R/W
100001
-472.8ppm
111111
-7.6ppm
000000
0ppm(default)
000001
7.6ppm
lv
RTC_TBC<6:0>
- 480.4ppm
am
lc s
on A
te G
nt
st
il
6:0
100000
al
id
These bits are used to correct the inaccuracy of the
used 32kHz crystal. Correction is done all 8 seconds
by removing or adding two clock cycles.
Trimming register for RTC, 128 steps @ 7.6ppm
7
rtc_irq_mode
0
R/W
011110
472.8ppm
011111
480.4ppm
0
generate an interrupt every second
1
generate an interrupt every minute
The interrupt has to be enabled by
rtc_rep_int_m=0
Table 177. Reset Timer Register
Reset Timer
Addr:22
These bits set RTC modes
Bit Name
Default
Access
4
rtc_alarm_wakeup_en
ROM
R/W
ca
Bit
rtc_mode
ROM
ROM
0
Disables RTC alarm wakeup in power off
mode
1
Enable RTC alarm wakeup in power off mode
0
Disables RTC repeated wakeup in power off
mode
1
Enable RTC repeated wakeup in power off
mode
00
32kHz oscillator off
01
32kHz oscillator enabled
10
32kHz oscillator enabled, Pin Q32k enabled
11
reserved (do not use)
R/W
R/W
Te
ch
7:6
rtc_rep_wakeup_en
ni
5
Description
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- Detailed Description - System Functions
10.10 Touchpen Interface
The touchpen interface controls a resistive touchpen. It has the following features:
Low Power Pen Detect
Measure pen X,Y position
Measure pen pressure (Z-position)
al
id
Interrupt, if X,Y,Z data is available; one dedicated output – CURR4_GPIO4 can be configured to be used as
touchpen interrupt output and/or standard interrupt output XINT
The conversion interval can be adjusted
Up to 16 ADC conversion can be averaged internally
The sample time of the ADC can be adjusted
lv
The pin CURR3_GPIO3 can be configured to enable/disable the ADC conversion (useful if the processor updates
the LCD to avoid parallel reading of the touchpen position)
am
lc s
on A
te G
nt
st
il
The touchpen interface shares the pins with the SPDIF output and the I2S Output 3. If the touchpen interface is used,
the SPDIF and the I2S Output 3 cannot be used (and has to be disabled).
Note: The touchpen interface and the ‘General Purpose 10 Bit ADC’ can be used at the same time.
Figure 59. Touchpen Block diagram
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143 - 157
AS3658
Data Sheet Confidential
- Detailed Description - System Functions
The touchpen controller is operating according to the following state diagram:
Figure 60. Touchpen State diagram
("
(&
*+,
am
lc s
on A
te G
nt
st
il
lv
al
id
(&
("
!"#"$%#&#&" '
.
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*+,
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) )
ni
10.10.1 Software guidelines
Te
ch
1. Setup the configuration registers (tpen – control 1..3) according the hardware
2. Enable receiving of touchpen interrupts (either through XINT or GPIO4_CURR4)
3. Upon receiving of a touchpen interrupt, readout tpen_xmsb, tpen_ymsb (and if required tpen_pressmsb and
tpen_xypresslsb) with a single I2C blockread. This ensured, that the x,y,z is correctly readout and all data belong
to one single touchpen x,y,z conversion
4. Perform all the required processing with the data (e.g. accept a pen-down only if the pen is forced onto the
touchscreen with a minimum pressure [z-position])
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- Detailed Description - System Functions
10.10.2 Touchpen Registers
Table 178. Touchpen Register Map
Register
Definition
Addr Default
Content
Name
b7
b6
b5
b4
b3
b2
b1
b0
XD2
108
NA
XD9
XD8
XD7
XD6
XD5
XD4
XD3
tpen_ymsb
109
NA
YD9
YD8
YD7
YD6
YD5
YD4
YD3
YD2
tpen_pressmsb
110
NA
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
tpen_xypresslsb
111
NA
PD1
PD0
0
YD1
YD0
0
XD1
XD0
tpen – control 1
112
00h
tpen_st_ tpen_eo
pen
c
tpen – control 2
113
00h
tpen_so tpen_wa tpen_curr
cpd
it
press
tpen – control 3
114
00h
tpen_soc
tpen_convint
tpen_on
lv
tpen_avg
al
id
tpen_xmsb
tpen_pu
tpen_sample
am
lc s
on A
te G
nt
st
il
tpen_timeo tpen_deb
ut _en
ounce
Note: The cells marked in color are Read only
Table 179. Touchpannel Result Register Bits
Touchpad_XMSB result
Addr:108
X-MSB result register
Bit
Bit Name
Default
Access
Description
7:0
tpen_xmsb
00000000
R
X – MSB Data
Table 180. Touchpannel Result Register Bits
Touchpad_YMSB result
Addr:109
Y-MSB result register
Bit
Bit Name
Default
Access
Description
7:0
tpen_ymsb
00000000
R
Y – MSB Data
ca
Table 181. Touchpannel Result Register Bits
Touchpad_Pressure result
Addr:110
7:0
Bit Name
Default
Access
Description
tpen_pressmsb
00000000
R
Pressure - Data
ni
Bit
Pressure result register
ch
Table 182. Touchpannel Result Register Bits
Touchpad_XY - LSB result
Te
Addr:111
X - MSB result register
Bit
Bit Name
Default
Access
Description
1:0
tpen_xlsb
00
R
X – LSB Data
4:3
tpen_ylsb
00
R
Y – LSB Data
7:6
tpen_presslsb
00
R
Pressure – LSB Data
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- Detailed Description - System Functions
Table 183. Touchpannel Control Register Bits
Touchpad – control 1
Addr:112
Bit
Bit Name
This register controls the different modes of the Touchpad
Default
Access
Description
Enables Touch Pen Function
tpen_on
0
0
OFF (No wakeup on pen down)
1
Pen Detect enabled
wakes up Pen
Digitizer
Check Pen_Status -> if pendetect or tpen_soc_pd=1 and tpen_soc=1
then perform X,Y,Z measurements
R/W
al
id
0
Conversion Interval Timer
00
R/W
01
every 512 clock periods (0,5 ms) ADC –
Averaging limited to max. 4
10
every 1024 clock periods (1ms) ADC –
Averaging limited to max. 8
11
every 10240 clock periods (10ms)
lv
tpen_convint
No delay between conversions
am
lc s
on A
te G
nt
st
il
2:1
00
Start Conversion (x,y, and z conversion)
3
tpen_soc
0
0
No Conversion if pen down detected
1
Start Conversion if pen down detected or
tpen_soc_pd=1 and tpen_on=1 (X, Y and
Z-Pressure Measurement)
R/W
Averaging of x and y measurement
5:4
tpen_avg
0
R/W
00
no averaging
01
4 measurements (per channel)
10
8 measurements (per channel)
11
16 measurements (per channel)
ADC - End of Conversion bit
tpen_eoc
0
ni
tpen_st_pen
TP in Power down or Conversion ongoing
1
Valid TP data available (x,y, and pressure)
generates an interrupt on GPIO4_CURR4
and/or XINT; the interrupt is released when
the readout from the tpen_xmsb is started
Pen status
0
R
0
penup
1
pendown
Te
ch
7
0
R/W
ca
6
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- Detailed Description - System Functions
Table 184. Touchpannel Control Register Bits
Touchpad – control 2
Addr:113
Bit
Bit Name
This register controls the different modes of the Touchpad
Default
Access
Description
Internal Resistor used for Pen detection
Do not use this Setting
00001
4kΩ
00010
8kΩ
...
tpen_pu
00000
R/W
00100
16kΩ
lv
4:0
al
id
00000
...
01000
32kΩ
am
lc s
on A
te G
nt
st
il
...
10000
64kΩ (most sensitive)
...
11111
~ 2kΩ
Current used for pressure measurement
5
tpen_currpress
6
0
tpen_wait
7
0
tpen_soc_pd
0
R/W
R/W
0
200µA
1
400µA
0
Do not wait until tpen_xmsb is readout
1
Start next ADC – conversion after data is
read from Register tpen_xmsb
0
Start conversion only if tpen_st_pen is 1
and tpen_soc=1 and tpen_on=1
1
Measure regardless of pen Status (only if
tpen_soc=1 and tpen_on=1)
R/W
Table 185. Touchpannel Control Register Bits
Bit Name
ni
Bit
tpen_sample
This register controls the different modes of the Touchpad
Default
Access
Te
2
3
tpen_debounce
Description
Sample Time of ADC
00
R/W
ch
0:1
Touchpad – control 3
ca
Addr:114
0
R/W
0
3µs
1
10µs
2
50µs
3
200µs
0
Pen-down Debounce Time 100µs
1
Pen-down Debounce Time = 3ms
Enables Timeout Signal (ADC conversion is
stopped during tiemeout = 1)
tpen_timeout _en
www.austriamicrosystems.com
0
R/W
Revision 1v13
0
off
1
GPIO3_CURR3 can be configured as input
for the timeout signal – see block diagram
147 - 157
AS3658
Data Sheet Confidential
- Register map
11 Register map
Table 186. Register Map
Default
hex
Content
Addr
Register
Definition
Step Down
Voltage1
0
0h
sd1_freq
ROM sd1_clki
nv
u
step_down1_v
Step Down
Voltage2
1
1h
sd2_freq
ROM sd2_clki
nv
u
step_down2_v
Step Down
Voltage3
2
2h
sd3_freq
ROM sd3_clki
nv
u
step_down3_v
LDO_RF1
Voltage
3
3h
ROM
rf1_swpr rf1_lcurr
ot_en
_en
ldo_rf1_v
LDO_RF2
Voltage
4
4h
ROM
double_r slow_sta rf2_lcurr
eset
rtup
_en
ldo_rf2_v
LDO_RF3
Voltage
5
LDO_DIG1
Voltage
6
LDO_DIG2
Voltage
7
LDO_DIG3
Voltage
8
LDO_DIG4
Voltage
9
USB Charger
Control
b5
b4
b3
b2
b1
rf3_hotpl rf3_lcurr
ug_en
_en
5h
ROM
6h
ROM
ldo_dig1_v
7h
ROM
ldo_dig2_v
8h
ROM
ldo_dig3_v
9h
ROM
ldo_dig4_v
10
Ah
No_char dis_bats
ROM ext_bats
w_temp usb_chg
w_en
ging
En
_prot
Charger
Control1
11
Bh
Auto
ch_det_ charging usb_hol
CHOVD Ch_pwr
ROM Isolate_b
at
500ms
_tmax d_chdet Resume
etEn
off_en
Battery voltage
monitor
12
Ch
SupRes
ROM FastRes
En
En
Charger Config 13
Dh
ROM
FuelGauge
15
Charger
Current
16
ldo_rf3_v
auto_sh
ROM ntc_type ntc_hyst ntc_high
_temp
utdown
Fh
ROM
ch
10h ROM
power_o
ff_at_vs
uplow
ch_voltage
ChEn
ResVoltRise
Vsupply_min
Eh
ntc_on
usb_Current
ResVoltFall
ChVoltResume
ca
14
ni
Charger
supervision
b0
al
id
b6
lv
b7
am
lc s
on A
te G
nt
st
il
Name
ChVoltEOC
ch_timeout
CalMod
CalReq
ConstantCurrent
UpdReq
FGEn
TrickleCurrent
17
11h ROM
GPIO 1
18
12h ROM
gpio1_pulls
gpio1_in
vert
gpio1_iosf
gpio1_mode
GPIO 2
19
13h ROM
gpio2_pulls
gpio2_in
vert
gpio2_iosf
gpio2_mode
GPIO 3
20
14h ROM
gpio3_pulls
gpio3_in
vert
gpio3_iosf
gpio3_mode
GPIO 4
21
15h ROM
gpio4_pulls
gpio4_in
vert
gpio4_iosf
gpio4_mode
Te
Charge Pump
Control
www.austriamicrosystems.com
sdx_1A_mode
Revision 1v13
sd1_dvm_time
cp_puls
eskip
cp_freq
148 - 157
AS3658
Data Sheet Confidential
- Register map
Table 186. Register Map
Default
hex
Content
Addr
Register
Definition
Reset Timer
22
16h ROM
Reg Power1
Ctrl @ 6 msec
23
17h ROM
cp_on
sd3_on
sd2_on
ldo_dig1 ldo_rf2_ ldo_rf1_
sd1_on ldo_dig2
_on
_on
on
on
Reg Power1
Ctrl @ 7 msec
24
18h ROM
cp_on
@7
msec
sd3_on
@7
msec
sd2_on
@7
msec
ldo_dig1 ldo_rf2_ ldo_rf1_
sd1_on ldo_dig2
_on
_on
on
on
@7
@7
@7
@7
@7
msec
msec
msec
msec
msec
Reg Power1
Ctrl @ 8 msec
25
19h ROM
cp_on
@8
msec
sd3_on
@8
msec
sd2_on
@8
msec
ldo_dig1 ldo_rf2_ ldo_rf1_
sd1_on ldo_dig2
_on
_on
on
on
@8
@8
@8
@8
@8
msec
msec
msec
msec
msec
b6
b5
b4
b3
b2
rtc_rep_ rtc_alar xon_ena
wakeup m_wake
ble
_en
up_en
b0
res_timer
al
id
rtc_mode
b1
lv
b7
am
lc s
on A
te G
nt
st
il
Name
sd3_on
@9
msec
sd2_on
@9
msec
ldo_dig1 ldo_rf2_ ldo_rf1_
sd1_on ldo_dig2
_on
_on
on
on
@9
@
9
@
9
@
9
@
9
msec
msec
msec
msec
msec
26
1Ah ROM
cp_on
@9
msec
Reg Power1
Ctrl @ 10 msec 27
1Bh ROM
cp_on
@10
msec
sd3_on
@ 10
msec
sd2_on
@ 10
msec
ldo_dig1 ldo_rf2_ ldo_rf1_
sd1_on ldo_dig2
_on
_on
on
on
@ 10
@
10
@10
@10
@
10
msec
msec
msec
msec
msec
Reg Power1
Ctrl @ 11 msec 28
1Ch ROM
cp_on
@ 11
msec
sd3_on
@11
msec
sd2_on
@ 11
msec
ldo_dig1 ldo_rf2_ ldo_rf1_
sd1_on ldo_dig2
_on
_on
on
on
@ 11
@ 11
@ 11
@ 11
@ 11
msec
msec
msec
msec
msec
1Dh ROM
cp_on
@ 12
msec
sd3_on
@ 12
msec
sd2_on
@ 12
msec
ldo_dig1 ldo_rf2_ ldo_rf1_
sd1_on ldo_dig2
_on
_on
on
on
@ 12
@ 12
@ 12
@ 12
@ 12
msec
msec
msec
msec
msec
rf3_sw
stpup2_ stpup1_
on
on
Reg Power1
Ctrl @ 9 msec
Reg Power1
Ctrl @ 12 msec 29
Reg Power2
Ctrl
30
1Eh ROM
Reg GPIO Ctrl
31
sd3_gpi sd2_gpi
1Fh ROM ldo_dig3
_gpio
o
o
Step Up DC/DC
Control
32
20h
00h
Step Up1 DC/
DC Control
33
21h
stpup1_o stpup1_ stpup1_
00h c_timeou shortprot
clkinv
t
stpup1_v
00h stpup2_p
rot
stpup2_v
ni
34
22h
ch
Step Up2 DC/
DC Control
rf1_sw
ldo_dig4 ldo_dig3
_on
_on
stpup2_fb
stpup1_f stpup2_
req
clkinv
35
23h
00h
Step Down
Control2
36
24h
sd2_dis
00h sd3_dis_
pon
_pon
Step down
charger control
37
25h
02h
sd3_dis sd2_dis sd1_dis
_curmin _curmin _curmin
sdc_pas
sdc_freq
s_mode sdc_pon
u
Backup Battery
charger
38
26h
40h
BBCPwr BBCVolt
Save
BBCRes
Off
DCDC_CURR1 39
value
27h
00h
Te
Step Down
Control1
www.austriamicrosystems.com
sd2_nsw
_on
ldo_rf3
sd1_gpi ldo_dig2 ldo_dig1 ldo_rf2_ ldo_rf1_
o
_gpio
_gpio
gpio
gpio
stpup2_f stpup2_f stpup1_r
req
b_auto
es
ca
stpup2_r
es
rf2_sw
sd2_psw sd1_nsw
_on
_on
sd1_psw
_on
sd1_dis sdX_lpo sd3_nsw
_pon
_on
sd3_psw
_on
BBCCur
BBCMode
dcdc_curr1_current
Revision 1v13
149 - 157
AS3658
Data Sheet Confidential
- Register map
Table 186. Register Map
Default
Content
b6
b5
b4
b3
28h
00h
dcdc_curr2_current
CURR1 value
41
29h
00h
curr1_current
CURR2 value
42
2Ah
00h
curr2_current
CURR3 value
43
2Bh
00h
curr3_current
CURR4 value
44
2Ch
00h
curr4_current
DCDC_CURR3 45
value
2Dh
00h
dcdc_curr3_current
2Eh
00h
ADC idac
46
b2
b1
b0
al
id
b7
lv
DCDC_CURR2 40
value
hex
Name
Addr
Register
Definition
adc_idac
2Fh
ovtmp_
FFh LowBat_i
nt_m
int_m
Interrupt Mask2 48
30h
FFh
Interrupt Mask3 49
31h
FFh
onkey_
int_m
chdet_
int_m
am
lc s
on A
te G
nt
st
il
Interrupt Mask1 47
usb_chd charging cheoc_i chstate_
et_
_tmax_i
nt_m
int_m
int_m
nt_m
stpup1_i bat_tem hphcurr_ dig2_lv_i dig1_lv_i sd3_lv_i sd2_lv_i sd1_lv_i
nt_m
p_m
int_m
nt_m
nt_m
nt_m
nt_m
nt_m
voxm_in mic_rem mic_con rtc_rep_i rtc_alar dig4_lv_i dig3_lv_i
t_m
_int_m
_int_m
nt_m m_int_m nt_m
nt_m
-
Interrupt
Status1
50
32h
NA
LowBat_i ovtmp_i
Interrupt
Status2
51
33h
NA
hphcurr_ dig2_lv_i dig1_lv_i sd3_lv_i sd2_lv_i sd1_lv_i
stpup1_i bat_tem
p_i
i
Interrupt
Status3
52
34h
NA
Low voltage
Status1
53
35h
NA
Low voltage
Status2
54
36h
NA
GPIO Signal
55
37h
NA
PWM
Frequency
Control High
Time
56
38h
00h
pwm_h_time
PWM
Frequency
Control Low
Time
57
39h
00h
pwm_l_time
CURR control
58
3Ah
00h
-
voxm_i
onkey_i
usb_chd charging cheoc_i chstate_
et_i
_tmax_i
i
mic_rem mic_con rtc_rep_i rtc_alar dig4_lv_i dig3_lv_i
_i
_i
m_i
stpup1_d stpup1_
et
oc
dig2_lv
dig1_lv
ca
gpio4_in gpio3_in gpio2_in gpio1_in
pwm_div
dcdc_curr3_ctrl
gpio4
Reg_low
standby
_bias_m clk_div2 _mode_
ode
on
59
3Bh
0ch
Watchdog
Control
60
3Ch
02h
Watchdog_min
Timer
61
3Dh
00h
wtdg_min_timer
Watchdog_max 62
Timer
3Eh
FFh
wtdg_max_timer
Watchdog
Software Signal 63
3Fh
00h
Te
gpio3
dcdc_curr2_ctrl
References
Control
www.austriamicrosystems.com
sd3_lv
bat_high bat_lowt dcdc_cu dcdc_cu dcdc_cu
temp
emp
rr3_lv
rr2_lv
rr1_lv
ni
ch
chdet_i
clk_int
sd2_lv
sd1_lv
dig4_lv
dig3_lv
gpio2
gpio1
dcdc_curr1_ctrl
low_pow
er_on
wtdg_tri wtdg_re wtdg_on
gger
s_on
wtdg_
sw_sig
Revision 1v13
150 - 157
AS3658
Data Sheet Confidential
- Register map
Table 186. Register Map
Default
hex
Content
Addr
RTCSecond
64
40h
00h
second<7:0>
RTCMinute1
65
41h
00h
minute<7:0>
RTCMinute2
66
42h
00h
minute<15:8>
RTCMinute3
67
43h
00h
minute<23:16>
RTCAlarmSeco 68
nd
44h
3Fh
alarmsecond<7:0>
RTCAlarmMinu 69
te1
45h
FFh
alarmminute<7:0>
RTCAlarmMinu 70
te2
46h
FFh
alarmminute<15:8>
RTCAlarmMinu 71
te3
47h
FFh
alarmminute<23:16>
b6
b5
b4
b3
b2
rtc_irq_
mode
RTCT
72
48h
00h
SRAM
73
49h
00h
Audio Set1
74
4Ah
00h
Audio Set2
75
4Bh
I2S_sele
00h I2S_mclk
_en
ct
Audio Set3
76
4Ch
00h
linmix_of micmix_ dacmix_
f
off
off
DAC_L
77
4Dh
00h
dac_mut
e_off
DAC_R
78
4Eh
00h
ADC_L
79
4Fh
00h
ADC_R
80
50h
00h
adcmux
adc2dac
adr_vol
HPH out R
81
51h
00h
hp_ovc_to
hpcm_of
f
hpr_vol
HPH out L
82
52h
00h
hp_mux
hpl_vol
Line out R
83
53h
00h
b0
rtc_tbc<6:0>
sram<7:0>
equ_on
aud_ldo
mclk256 mclk_inv
ert
_on
ibr_hph
agc_off
gnd_sw
_on
mix_on
I2S_3_o
n
dith_on
mic_on
voxm_o hp_pulld pll_mod
n
_en
e
ca
ad_fs2
hp_mute
adc_mut adc_on
_off
ibr_dac
hp_on
ni
ibr_line
adl_vol
liner_vol
54h
00h
line_mut
e
LINE_IN_R
85
55h
00h
mute_mi
c_sf
LINE_IN_L
86
56h
00h
MIC_R
87
57h
00h
MIC_L
88
58h
00h msup_off mute_off
rdet_off
_d
SPDIF
89
59h
sdo3_se spdif_co spdif_m spdif_inv
00h audio_off sclk_inv
ert
lect
py_ok
clk_inv
alid
EQ_LP
90
5Ah
00h
ch
lin_on
dar_vol
84
www.austriamicrosystems.com
dac_on
dal_vol
Line out L
Te
b1
al
id
b7
am
lc s
on A
te G
nt
st
il
Name
lv
Register
Definition
mic_agc
_off
line_on
dac2line
_on
linel_vol
mute_off
_inr
lir_vol
mute_off
_inl
lil_vol
pre_gain
mr_vol
ml_vol
spdif_cntr
eq_lp_gain
Revision 1v13
151 - 157
AS3658
Data Sheet Confidential
- Register map
Table 186. Register Map
Default
hex
Content
Addr
Register
Definition
EQ_Band1
91
5Bh
00h
eq_band1_gain
EQ_Band2
92
5Ch
00h
eq_band2_gain
EQ_Band3
93
5Dh
00h
eq_band3_gain
EQ_HP
94
5Eh
00h
eq_hp_gain
EQ_preamp
95
5Fh
00h
ADC_control
96
60h
00h start_con
version adc_on
ADC_MSB
result
97
61h
NA
ADC_LSB
result
98
62h
NA
ChargerStatus
99
63h
NA
ChargerStatus_ 100 64h
usb
NA
DeltaChargeMS 101 65h
NA
sign
DeltaChargeLS 102 66h
NA
2
ElapsedTimeM 103 67h
NA
2
ElapsedTimeLS 104 68h
NA
2
105 69h
NA
Onkey_r
eset_5s
Overtemperatu 106 6Ah
re Control
NA
B
B
SB
B
b5
b4
b3
b2
b1
eq_ pre_gain
D9
D8
D7
adc_select
D6
lv
result_no
t_ready
adc_slo
w
ChLinear
NoBat
EOC
CVM
Trickle
ch_over batsw_o
voltage
n
7
15
7
14
2
6
2
14
2
6
2
13
2
5
2
13
2
5
2
12
2
2
4
12
2
2
4
b0
al
id
b6
D5
D4
D3
D2
D1
D0
11
2
3
2
11
2
3
2
Resume
ChAct
ChDet
batsw_ USB_Ch USB_Ch
mode
Act
Det
10
2
2
2
2
2
10
2
2
2
2
2
9
1
9
1
8
2
0
2
8
2
0
2
xon_inp power_o force_re
ut
ff
set
reset_reason
rst_ov_t
ov_temp temp_p
emp_14 ov_temp
_140
_110
mc_on
0
rom_
valid
107 6Bh
NA
tpen_xmsb
108 6Ch
NA
XD9
XD8
XD7
XD6
XD5
XD4
XD3
XD2
tpen_ymsb
109 6Dh
NA
YD9
YD8
YD7
YD6
YD5
YD4
YD3
YD2
tpen_pressmsb 110 6Eh
NA
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
tpen_xypressls 111 6Fh
b
NA
PD1
PD0
0
YD1
YD0
0
XD1
XD0
tpen – control 1 112 70h
00h
tpen – control 2 113 71h
tpen_wa tpen_cur
00h tpen_soc
pd
it
rpress
Te
ni
ca
Boot_status
ch
Reset Control
b7
am
lc s
on A
te G
nt
st
il
Name
tpen – control 3 114 72h
tpen_st_ tpen_eo
pen
c
tpen_avg
tpen_convint
tpen_tim tpen_de
eout_en bounce
ASIC ID 1
127 7Fh
NA
1
1
0
0
ASIC ID 2
128 80h
NA
0
1
0
1
Reg_ standby
mod
129 81h
sd3_stb sd2_stb
00h cp_stby_
on
y_on
y_on
Revision 1v13
tpen_on
tpen_pu
00h
www.austriamicrosystems.com
tpen_so
c
rom_adr
1
1
tpen_sample
0
1
rev
ldo_dig1
sd1_stb ldo_dig2
ldo_rf1_
_stby_o _stby_o ldo_rf2_
y_on
stby_on stby_on
n
n
152 - 157
AS3658
Data Sheet Confidential
- Register map
Table 186. Register Map
Default
b7
b6
b5
b4
b3
b2
00
b1
b0
usb_add_trim_current<2:0>
i2s master
control1
131 83h
00
i2s master
control2
132 84h
00
step Down
Control3
133 85h
00
UniqueID0,
addrf0
197 C5h
NA
ID<7:0>, addrf<7:0>
UniqueID1,
addrf1
198 C6h
NA
ID<15:8>, addrf<15:8>
UniqueID2,
addrf2
199 C7h
NA
ID<23:16>, addrf<23:16>
UniqueID3,
addrf3
200 C8h
NA
ID<31:24>, addrf<31:24>
UniqueID4,
romf0
201 C9h
NA
ID<39:32>, romf0
UniqueID5,
romf1
202 CAh
NA
ID<47:40>, romf1
UniqueID6,
romf2
203 CBh
NA
ID<55:48>, romf2
UniqueID7,
romf3
204 CCh
NA
ID<63:56>, romf3
UniqueID8,
romf4
205 CDh
NA
ID<71:64>, romf4
UniqueID9,
romf5
206 CEh
NA
ID<79:72>, romf5
UniqueID10,
romf6
207 CFh
NA
ID<87:80>, romf6
i2s_clk_divider<7:0>
i2s_lrclk i2s_mas
pcm_mo sdo_on_
i2s_mclk _sclk_ou
mclk1_e
de
_out_en
ter_on
n
t_en
al
id
Usb_current_tri 130 82h
m
Content
i2s_clk_divider<10:8>
sd3_uvli sd2_uvli sd1_uvli
mit
mit
mit
Entries marked are read only
Entries are not reset in power off mode
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
lv
hex
Name
Addr
Register
Definition
www.austriamicrosystems.com
Revision 1v13
153 - 157
AS3658
Data Sheet Confidential
- Package Drawings and Marking
12 Package Drawings and Marking
PACKAGE
OUTLINE
DWG NO.
97SPP01046A
ISSUE
O
DATE
OCT.010, 2007
am
lc s
on A
te G
nt
st
il
±0.
lv
ASE
Advanced
Semiconductor
Engineering Korea, Inc.
al
id
Figure 61. CTBGA124 8x8 0.5mm pitch
TOP VIEW
BOTTOM VIEW
ca
(124 SOLDER BALLS )
ch
ni
SIDE VIEW
NOTE
1. GENERAL TOLERANCE : ± 0.10
Te
TITLE : POD for FBGA 8mm X 8mm X 1.09mm,
2L, 0.65CAP, 124BGA, 0.50PITCH, 0.30BALL
www.austriamicrosystems.com
Unit : mm
Dimension & Tolerance
ASME Y14.5M
Customer : AMS
COMPANY
ASE KOREA
SHEET
1 OF 2
Revision 1v13
154 - 157
AS3658
Data Sheet Confidential
- Package Drawings and Marking
al
id
Figure 62. CTBGA124 Marking
lv
Table 187. Package Code AYWWZZZ
A
Y
WW
ZZZ
B ... for Green
year
working week assembly / packaging
free choice
x
B, C, D, E, E1 or F
12.1
am
lc s
on A
te G
nt
st
il
Table 188. Boot ROM revison
Pinout Drawing (Top view) CTBGA 8x8mm
Figure 63. Pinout drawing
Bottom View (Ball Side)
14
13
A
12
11
10
9
8
7
6
5
4
3
2
1
A
B
B
C
C
D
D
E
E
F
ca
F
G
H
H
J
K
K
L
L
M
M
ch
ni
J
G
Te
N
P
14
13
12
www.austriamicrosystems.com
11
10
9
8
7
6
5
4
Revision 1v13
c
N
c
P
3
2
Inner Balls PCB Layout
Example shown
with dotted blue lines
1
155 - 157
AS3658
Data Sheet Confidential
- Ordering Information
13 Ordering Information
The device is available as the standard products listed in Table 189.
Table 189. Ordering Information
Marking
Descriptiom
Delivery Form
Audio Management Unit for Portable
AS3658B Power and
Devices, Boot-ROM Version B
Tape and Reel in
Dry Pack
AS3658C-BCTP
Audio Management Unit for Portable
AS3658C Power and
Devices, Boot-ROM Version C
Tape and Reel in
Dry Pack
AS3658D-BCTP
Audio Management Unit for Portable
AS3658D Power and
Devices, Boot-ROM Version D
Tape and Reel in
Dry Pack
AS3658E-BCTP
Audio Management Unit for Portable
AS3658E Power and
Devices, Boot-ROM Version E
Tape and Reel in
Dry Pack
AS3658E1-BCTP AS3658E1 Power and Audio Management Unit for Portable
Devices, Boot-ROM Version E1
Tape and Reel in
Dry Pack
Audio Management Unit for Portable
AS3658F Power and
Devices, Boot-ROM Version F
Tape and Reel in
Dry Pack
am
lc s
on A
te G
nt
st
il
AS3658F-BCTP
lv
AS3658B-BCTP
Package
BGA124
8x8mm, 0.5mm
pitch
BGA124
8x8mm, 0.5mm
pitch
BGA124
8x8mm, 0.5mm
pitch
BGA124
8x8mm, 0.5mm
pitch
BGA124
8x8mm, 0.5mm
pitch
BGA124
8x8mm, 0.5mm
pitch
al
id
Model
Description: AS3658x-BCTP
x: Boot-ROM version
B: Teperature Range: Z = -40ºC to 85ºC
CT: Pacakage: CTBGA
Te
ch
ni
ca
P:Delivery Form: Tape and Reel in Dry Pack
www.austriamicrosystems.com
Revision 1v13
156 - 157
AS3658
Data Sheet Confidential
- Ordering Information
Copyrights
Copyright © 1997-2010, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
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Disclaimer
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Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent infringement.
austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice.
Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring
extended temperature range, unusual environmental requirements, or high reliability applications, such as military,
medical life-support or life-sustaining equipment are specifically not recommended without additional processing by
austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show
deviations from the standard production flow, such as test flow or test location.
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The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or
consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the
technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
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Contact Information
Headquarters
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austriamicrosystems AG
A-8141 Schloss Premstaetten, Austria
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Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
www.austriamicrosystems.com
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Revision 1v13
157 - 157