TI1 DAC8830-EP 16-bit, ultra-low power, voltage-output digital-to-analog converter Datasheet

DAC8830-EP
DAC8831-EP
SGLS334C – AUGUST 2006 – REVISED APRIL 2007
16-Bit, Ultra-Low Power, Voltage-Output
Digital-to-Analog Converters
FEATURES
APPLICATIONS
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(1)
Controlled Baseline
– One Assembly
– One Test Site
– One Fabrication Site
Extended Temperature Performance of –55°C
to 125°C
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
16-Bit Resolution
2.7-V to 5.5-V Single-Supply Operation
Low Power: 15 μW for 3-V Power
High Accuracy, INL: 1 LSB
Low Glitch: 8 nV-s
Low Noise: 10 nV/√Hz
Fast Settling: 1 μs
Fast SPI Interface Up to 50 MHz
Reset to Zero-Code
Schmitt-Trigger Inputs for Direct Optocoupler
Interface
Industry-Standard Pin Configuration
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
Portable Equipment
Automatic Test Equipment
Industrial Process Control
Data Acquisition Systems
Optical Networking
DESCRIPTION
The DAC8830 and DAC8831 are single, 16-bit,
serial-input,
voltage-output
digital-to-analog
converters (DACs) operating from a single 3-V to 5-V
power supply. These converters provide excellent
linearity, low glitch, low noise, and fast settling over
the specified temperature range of –55°C to 125°C.
The output is unbuffered, which reduces the power
consumption and the error introduced by the buffer.
These parts feature a standard high-speed (clock up
to 50 MHz), 3-V or 5-V SPI serial interface to
communicate with the DSP or microprocessors.
The DAC8830 output is 0 V to VREF. However, the
DAC8831 provides bipolar mode output (±VREF)
when working with an external buffer. The DAC8830
and DAC8831 are both reset to zero-code after
power up.
For optimum performance, a set of Kelvin
connections to external reference and analog ground
input are provided on the DAC8831.
The DAC8830 is available in an SO-8 package and
the DAC8831 is available in an SO-14 package. Both
have industry standard pinouts (see Table 3, the
Cross Reference table in the Application Information
section for details).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
DAC8830-EP
DAC8831-EP
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SGLS334C – AUGUST 2006 – REVISED APRIL 2007
DAC8830
Functional Block Diagram
DAC8831
Functional Block Diagram
VDD
VDD
VREF−S
VREF−F
RINV
SCLK
Serial
Interface
CS
VOUT
AGND
Input
Register
DAC Latch
CS
SCLK
SDI
SDI
2
RFB
INV
DAC8830
DGND
RFB
LDAC
Serial Interface
and Control Logic
DAC
VREF
DAC
Input
Register
DAC Latch
DAC8831
DGND
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VOUT
+V
−
+
VO
−V
OPA277
AGNDF
OPA704
AGNDS OPA727
DAC8830-EP
DAC8831-EP
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SGLS334C – AUGUST 2006 – REVISED APRIL 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PRODUCT
MINIMUM
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
POWERON
RESET
VALUE
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
MARKING
PACKAGELEAD
PACKAGE (2)
DESIGNATOR
DAC8830MCD
±1
±1
Zero-Code
–55°C to 125°C
8830M
SO-8
D
DAC8831MCD
(1)
(2)
±1
±1
ORDERING
NUMBER
DAC8830MCDREP
Zero-Code
–55°C to 125°C
8831M
SO-14
TRANSPORT
MEDIA,
QUANTITY
Tape and Reel,
2500
DAC8830MCDEP
Tube, 75
DAC8831MCDREP
Tape and Reel,
2500
DAC8831MCDEP
Tube, 50
D
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the
Texas Instruments website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
UNIT
–0.3 to 7
V
Digital input voltage to DGND
–0.3 to VDD + 0.3
V
VOUT to AGND
–0.3 to VDD + 0.3
V
AGND, AGNDF, AGNDS to DGND
–0.3 to 0.3
V
Operating temperature range
–55 to 125
°C
Storage temperature range
–65 to 150
°C
150
°C
(TJ max – TA)/ θJA
W
SO-8
149.5
°C/W
SO-14
104.5
°C/W
Vapor phase (60 s)
215
°C
Infrared (15 s)
220
°C
VDD to AGND
Junction temperature range (TJ max)
Power dissipation
Thermal impedance, θJA
Lead temperature, soldering
(1)
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
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SGLS334C – AUGUST 2006 – REVISED APRIL 2007
Years Estimated Life
10000
1000
Wirebond Voiding Fail Mode
100
10
Electromigration Fail Mode
1
80
90
100
110
120
130
Continuous TJ − 5C
Figure 1. DAC8831MEP Operating Life Derating Chart
4
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140
150
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SGLS334C – AUGUST 2006 – REVISED APRIL 2007
ELECTRICAL CHARACTERISTICS
All specifications at TA = TMIN to TMAX, VDD = 3 V, or VDD = 5 V, VREF = 2.5 V (unless otherwise noted); specifications subject
to change without notice.
PARAMETER
CONDITIONS
MIN
TYP
MAX
TA = 25°C
±0.5
±1
TA = –40°C to 105°C (DAC8831
only)
±0.5
±1.5
UNIT
STATIC PERFORMANCE
Resolution
16
Linearity error
bits
TA = –55°C to 125°C (DAC8831
only)
Differential linearity error
Gain error
±4
TA = –55°C to 125°C (DAC8830
only)
±0.5
±1.5
All grades
±0.5
±1
TA = 25°C
±1
±5
±7
TA = –55°C to 125°C
±0.1
Gain drift
±0.25
TA = 25°C
Zero code error
LSB
LSB
ppm/°C
±1
TA = –40°C to 105°C (DAC8831
Only)
±2.5
TA = –55°C to 125°C (DAC8831
Only)
±3
TA = –55°C to 125°C (DAC8830
Only)
±2
±0.05
Zero code drift
LSB
LSB
ppm/°C
OUTPUT CHARACTERISTICS
Voltage output
Unipolar operation
(1)
(DAC8831 only)
Bipolar operation
Output Impedance
To 1/2 LSB of FS, CL = 10 pF
Slew rate (2)
CL = 10 pF
Digital-to-analog glitch
1 LSB change around major carry
Digital feedthrough (3)
(1)
(2)
(3)
VREF
V
VREF
V
6.25
Settling time
Output noise
0
–VREF
DAC8830
DAC8831
TA = 25°C
kΩ
1
μs
25
V/μs
8
nV-s
0.2
nV-s
10
nV/√Hz
18
Power supply rejection
VDD varies ±10%
Bipolar resistor
matching
DAC8831 only
RFB / RINV
1
±1
Ratio error
±0.0015%
±0.01%
Bipolar zero error
DAC8831 only
TA = 25°C
±0.25
±5
Bipolar zero drift
DAC8831 only
Ω/Ω
±7
TA = –55°C to 125°C
±0.2
LSB
LSB
ppm/°C
TheDAC8830 output is unipolar (0 V to VREF). TheDAC8831 output is bipolar (±VREF) when it connects to an external buffer (see the
Bipolar Output Operation section for details).
Slew Rate is measure from 10% to 90% of transition when the output changes from 0 to full scale.
Digital feedthrough is defined as the impulse injected into the analog output from the digital input. It is measured when the DAC output
does not change, CS is held high, while SCLK and DIN signals are toggled.
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SGLS334C – AUGUST 2006 – REVISED APRIL 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = TMIN to TMAX, VDD = 3 V, or VDD = 5 V, VREF = 2.5 V (unless otherwise noted); specifications subject
to change without notice.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VDD
V
REFERENCE INPUT
Reference input voltage range (4)
Reference input impedance (5)
1.25
Unipolar mode
Bipolar mode, DAC8831
Reference –3-dB bandwidth, BW
Code = FFFFh
Reference feedthrough
Code = 0000h,
VREF = 1 VPP at 100 kHz
9
Signal-to-noise ratio, SNR
Reference input capacitance
kΩ
7.5
1.3
MHz
1
mV
92
dB
Code = 0000h
75
Code = FFFFh
120
pF
DIGITAL INPUTS
VIL
Input low voltage
VIH
Input high voltage
VDD = 2.7 V
0.6
VDD = 5 V
0.8
VDD = 2.7 V
2.1
VDD = 5 V
2.4
V
V
Input current
±1
μA
Input capacitance
10
pF
Hysteresis voltage
0.4
V
POWER SUPPLY
VDD
2.7
IDD
Power
5.5
VDD = 3 V
5
20
VDD = 5 V
5
20
VDD = 3 V
15
60
VDD = 5 V
25
100
V
μA
μW
TEMPERATURE RANGE
Specified performance
(4)
(5)
6
–55
Specified by design. Vref production tested only at 2.5 V.
Reference input resistance is code dependent, minimum at 8555h.
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125
°C
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DAC8831-EP
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SGLS334C – AUGUST 2006 – REVISED APRIL 2007
PIN CONFIGURATION (NOT TO SCALE)
1
AGND
2
VREF
CS
3
4
DAC8831ID, DAC8831IBD,
DAC8831ICD (SO-14)
(TOP VIEW)
8
VDD
RFB
1
14
VDD
7
DGND
VOUT
2
13
INV
SDI
AGNDF
3
12
DGND
SCLK
AGNDS
4
11
LDAC
VREF−S
5
10
SDI
VREF−F
6
9
NC
CS
7
8
SCLK
6
5
DAC8831
VOUT
DAC8830
DAC8830ID, DAC8830IBD,
DAC8830ICD (SO-8)
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
NO.
DESCRIPTION
NAME
DAC8830
1
VOUT
Analog output of DAC
2
AGND
Analog ground
3
VREF
Voltage reference input
4
CS
Chip select input (active low). Data is not clocked into SDI unless CS is low.
5
SCLK
Serial clock input
6
SDI
Serial data input. Data is latched into input register on the rising edge of SCLK.
7
DGND
Digital ground
8
VDD
Analog power supply, 3 V to 5 V
1
RFB
Feedback resistor. Connect to the output of external operational amplifier in bipolar mode.
2
VOUT
Analog output of DAC
3
AGNDF
Analog ground (Force)
4
AGNDS
Analog ground (Sense)
5
VREF-S
Voltage reference input (Sense). Connect to external voltage reference.
6
VREF-F
Voltage reference input (Force). Connect to external voltage reference.
7
CS
Chip select input (active low). Data is not clocked into SDI unless CS is low.
8
SCLK
Serial clock input
DAC8831
9
NC
No internal connection
10
SDI
Serial data input. Data is latched into input register on the rising edge of SCLK.
11
LDAC
Load DAC control input. Active low. When LDAC is Low, the DAC latch is simultaneously updated with the
content of the input register.
12
DGND
Digital ground
13
INV
Junction point of internal scaling resistors. Connect to external operational amplifier’s inverting input in bipolar
mode.
14
VDD
Analog power supply, 3 V to 5 V
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SGLS334C – AUGUST 2006 – REVISED APRIL 2007
ttd
CS
DAC
Updated
tDelay
tsck
tLead
twsck
tLag
twsck
tDSCLK
SCLK
tsu
tho
SDI
BIT15 (MSB)
BIT14
BIT13, . . . ,1
BIT0
−−−Don’t Care
Figure 2. DAC8830 Timing Diagram
Case1: LDAC tied to LOW
t td
CS
DAC
Updated
t Delay
t sck
t Lead
t wsck
t Lag
t wsck
t DSCLK
SCLK
t su
t ho
SDI
BIT 15 (MSB)
LDAC
BIT 14
BIT 13, . . . ,1
BIT 0
LOW
−−−Don’t Care
Case2: LDAC Active
t td
CS
t Delay
t sck
t Lead
t wsck
t Lag
t wsck
t DSCLK
SCLK
t su
SDI
t ho
BIT 15 (MSB)
BIT 14
BIT 13, . . . ,1
BIT 0
t DLADC
HIGH
LDAC
DAC
Updated
−−−Don’t Care
Figure 3. DAC8831 Timing Diagram
8
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t WLDAC
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SGLS334C – AUGUST 2006 – REVISED APRIL 2007
TIMING CHARACTERISTICS: VDD = 5 V
(1) (2)
At –55°C to 125°C (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tsck
SCLK period
20
ns
twsck
SCLK high or low time
10
ns
tDelay
Delay from SCLK high to CS low
18
ns
tLead
CS enable lead time
12
ns
tLag
CS enable lag time
15
ns
tDSCLK
Delay from CS high to SCLK high
15
ns
ttd
CS high between active period
30
ns
tsu
Data setup time (input)
10
ns
tho
Data hold time (input)
0
ns
tWLDAC
LDAC width
30
ns
tDLDAC
Delay from CS high to LDAC low
30
ns
VDD high to CS low (power-up delay)
10
μs
(1)
(2)
Specified by design. Not production tested.
Sample tested during the initial release and after any redesign or process changes that may affect this parameter.
TIMING CHARACTERISTICS: VDD = 3 V (1)
(2)
At –55°C to 125°C (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tsck
SCLK period
20
ns
twsck
SCLK high or low time
10
ns
tDelay
Delay from SCLK high to CS low
18
ns
tLead
CS enable lead time
15
ns
tLag
CS enable lag time
15
ns
tDSCLK
Delay from CS high to SCLK high
15
ns
ttd
CS high between active period
30
ns
tsu
Data setup time (input)
10
ns
tho
Data hold time (input)
0
ns
tWLDAC
LDAC width
30
ns
tDLDAC
Delay from CS high to LDAC low
30
ns
VDD high to CS low (power-up delay)
10
μs
(1)
(2)
Specified by design. Not production tested.
Sample tested during the initial release and after any redesign or process changes that may affect this parameter.
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TYPICAL CHARACTERISTICS: VDD = 5 V
At TA = 25°C, VREF = 2.5 V (unless otherwise noted)
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +25_C
VREF = 2.5 V
0.50
0.50
0.25
0.25
0
−0.25
−0.25
−0.50
−0.75
−0.75
−1.00
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 5.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
TA = −40_ C
VREF = 2.5 V
0.75
0.50
0.25
0.25
DNL (LSB)
0.50
0
−0.25
TA = −40_ C
VREF = 2.5 V
0.75
0
−0.25
−0.50
−0.50
−0.75
−0.75
−1.00
−1.00
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 6.
Figure 7.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +85_C
VREF = 2.5 V
0.75
0.25
0.25
DNL (LSB)
0.50
0
−0.25
TA = +85_C
VREF = 2.5 V
0.75
0.50
0
−0.25
−0.50
−0.50
−0.75
−0.75
−1.00
−1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 8.
10
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 4.
1.00
INL (LSB)
0
−0.50
−1.00
INL (LSB)
TA = +25_ C
VREF = 2.5 V
0.75
DNL (LSB)
INL (LSB)
0.75
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 9.
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TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = 25°C, VREF = 2.5 V (unless otherwise noted)
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +25_ C
VREF = 5 V
TA = +25_C
VREF = 5 V
0.75
0.50
0.50
0.25
0.25
DNL (LSB)
INL (LSB)
0.75
0
−0.25
0
−0.25
−0.50
−0.50
−0.75
−0.75
−1.00
−1.00
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 10.
Figure 11.
LINEARITY ERROR
vs REFERENCE VOLTAGE
LINEARITY ERROR
vs SUPPLY VOLTAGE
0.75
0.75
0.50
0.50
0.25
Linearity Error (LSB)
Linearity Error (LSB)
VREF = 2.5 V
DNL
0
INL
−0.25
DNL
0.25
0
INL
−0.25
−0.50
−0.50
0
1
2
3
4
5
6
2.5
3.0
3.5
Reference Voltage (V)
4.0
4.5
5.0
Figure 12.
Figure 13.
GAIN ERROR
vs TEMPERATURE
ZERO-CODE ERROR
vs TEMPERATURE
1.25
VREF = 2.5 V
Zero−Code Error (LSB)
1.00
0.75
Gain Error (LSB)
6.0
0.50
Bipolar Mode
0.50
0.25
0
Unipolar Mode
−0.25
0.25
Bipolar Mode
0
−0.25
−0.50
−0.75
−60
5.5
Supply Voltage (V)
Unipolar Mode
VREF = 2.5 V
−40 −20
0
20
40
60
80
Temperature (_C)
100
120 140
−0.50
−60
Figure 14.
−40 −20
0
20
40
60
80
Temperature (_C)
100
120 140
Figure 15.
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TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = 25°C, VREF = 2.5 V (unless otherwise noted)
REFERENCE CURRENT
vs CODE (UNIPOLAR MODE)
REFERENCE CURRENT
vs CODE (BIPOLAR MODE)
300
300
VREF = 2.5 V
VREF = 2.5 V
250
Reference Current (µA)
Reference Current (µA)
250
200
150
100
200
150
100
50
50
0
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 16.
Figure 17.
SUPPLY CURRENT
vs DIGITAL INPUT VOLTAGE
SUPPLY CURRENT
vs TEMPERATURE
800
5
VREF = 2.5 V
700
4
600
Supply Current (µA)
Supply Current (µA)
VDD = 5 V
500
400
300
VDD = 3 V
200
VDD = 5 V
VLOGIC = 5 V
3
VDD = 3 V
VLOGIC = 3 V
2
1
100
0
0
1
2
3
Digital Input Voltage (V)
4
0
−60 −40
5
20 40
60
80
Temperature (_C)
100 120 140
Figure 19.
SUPPLY CURRENT
vs SUPPLY VOLTAGE
SUPPLY CURRENT
vs REFERENCE VOLTAGE
5.0
VREF = 2.5 V
4.5
4.5
4.0
Supply Current (µA)
4.0
Supply Current (µA)
0
Figure 18.
5.0
3.5
3.0
2.5
2.0
1.5
3.5
VDD = 5 V
3.0
2.5
2.0
VDD = 3 V
1.5
1.0
1.0
0.5
0.5
0
0
2.7
3.0 3.3
3.6 3.9 4.2 4.5 4.8
Supply Voltage (V)
5.1
5.4
5.7 6.0
0
0.5
Figure 20.
12
−20
1.0
1.5 2.0 2.5 3.0 3.5
Reference Voltage (V)
Figure 21.
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4.5
5.0
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TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = 25°C, VREF = 2.5 V (unless otherwise noted)
MAJOR-CARRY GLITCH
(FALLING)
MAJOR-CARRY GLITCH
(RISING)
VREF = 2.5 V
5V/div
VREF = 2.5 V
5V/div
LDAC
LDAC
VOUT
VOUT
0.1V/div
0.1V/div
Time (0.5µs/div)
Time (0.5µs/div)
Figure 22.
Figure 23.
DAC SETTLING TIME
(FALLING)
DAC SETTLING TIME
(RISING)
VREF = 2.5 V
5V/div
VREF = 2.5 V
5V/div
LDAC
LDAC
1V/div
VOUT
VOUT
1V/div
Time (0.2µs/div)
Time (0.2µs/div)
Figure 24.
Figure 25.
DIGITAL
FEEDTHROUGH
VREF = 2.5 V
5V/div
20mV/div
SDI
VOUT
Time (50ns/div)
Figure 26.
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TYPICAL CHARACTERISTICS: VDD = 3 V
At TA = 25°C, VREF = 2.5 V (unless otherwise noted)
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +25_C
VREF = 1.5 V
0.50
0.50
0.25
0.25
0
−0.25
−0.25
−0.50
−0.75
−0.75
−1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 28.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
TA = −40_C
VREF = 1.5 V
0.75
0.50
0.25
0.25
DNL (LSB)
0.50
0
−0.25
TA = −40_C
VREF = 1.5 V
0.75
0
−0.25
−0.50
−0.50
−0.75
−0.75
−1.00
−1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 29.
Figure 30.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +85_C
VREF = 1.5 V
0.75
0.25
0.25
DNL (LSB)
0.50
0
−0.25
TA = +85_C
VREF = 1.5 V
0.75
0.50
0
−0.25
−0.50
−0.50
−0.75
−0.75
−1.00
−1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 31.
14
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 27.
1.00
INL (LSB)
0
−0.50
−1.00
INL (LSB)
TA = +25_C
VREF = 1.5 V
0.75
DNL (LSB)
INL (LSB)
0.75
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 32.
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TYPICAL CHARACTERISTICS: VDD = 3 V (continued)
At TA = 25°C, VREF = 2.5 V (unless otherwise noted)
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +25_ C
VREF = 3 V
TA = +25_C
VREF = 3 V
0.75
0.50
0.50
0.25
0.25
DNL (LSB)
INL (LSB)
0.75
0
−0.25
0
−0.25
−0.50
−0.50
−0.75
−0.75
−1.00
−1.00
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 33.
Figure 34.
LINEARITY ERROR
vs REFERENCE VOLTAGE
GAIN ERROR
vs TEMPERATURE
1.00
0.75
0.75
Bipolar Mode
0.50
Gain Error (LSB)
Linearity Error (LSB)
0.50
DNL
0.25
0
−0.25
1.5
2.0
2.5
3.0
Unipolar Mode
−0.25
−0.50
VDD = 3 V
VREF = 2.5 V
−1.00
−60
−0.50
1.0
0
−0.75
INL
0.5
0.25
3.5
Reference Voltage (V)
20
40
60
80
Temperature (_C)
100
Figure 36.
ZERO-CODE ERROR
vs TEMPERATURE
REFERENCE CURRENT
vs CODE (UNIPOLAR MODE)
VREF = 1.5 V
250
Reference Current (µA)
0.25
0
Unipolar Mode
−0.25
Bipolar Mode
−0.50
120 140
300
VDD = 3 V
VREF = 2.5 V
Zero−Code Error (LSB)
0
Figure 35.
0.50
−0.75
−60
−40 −20
200
150
100
50
0
−40 −20
0
20
40
60
80
Temperature (_C)
100
120 140
0
Figure 37.
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 38.
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TYPICAL CHARACTERISTICS: VDD = 3 V (continued)
At TA = 25°C, VREF = 2.5 V (unless otherwise noted)
REFERENCE CURRENT
vs CODE (BIPOLAR MODE)
DIGITAL
FEEDTHROUGH
300
VREF = 2.5 V
VREF = 1.5 V
Reference Current (µA)
250
5V/div
SDI
200
150
20mV/div
VOUT
100
50
0
0
Time (50ns/div)
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 39.
Figure 40.
MAJOR-CARRY GLITCH
(FALLING)
MAJOR-CARRY GLITCH
(RISING)
VREF = 2.5 V
5V/div
VREF = 2.5 V
5V/div
LDAC
VOUT
LDAC
VOUT
0.1V/div
0.1V/div
Time (0.5µs/div)
Time (0.5µs/div)
Figure 41.
Figure 42.
DAC SETTLING TIME
(FALLING)
DAC SETTLING TIME
(RISING)
VREF = 2.5 V
VREF = 2.5 V
5V/div
LDAC
5V/div
1V/div
VOUT
VOUT
1V/div
Time (0.2µs/div)
Time (0.2µs/div)
Figure 43.
16
LDAC
Figure 44.
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THEORY OF OPERATION
General Description
The DAC8830 and DAC8831 are single, 16-bit, serial-input, voltage-output DACs. They operate from a single
supply ranging from 2.7 V to 5 V, and typically consume 5 μA. Data is written to these devices in a 16-bit word
format, via an SPI serial interface. To ensure a known power-up state, these parts were designed with a
power-on reset function. The DAC8830 and DAC8831 are reset to zero code. In unipolar mode, the DAC8830
and DAC8831 are reset to 0V, and in bipolar mode, the DAC8831 is reset to –VREF. Kelvin sense connections
for the reference and analog ground are included on the DAC8831.
Digital-to-Analog Sections
The DAC architecture for both devices consists of two matched DAC sections and is segmented. A simplified
circuit diagram is shown in Figure 45. The four MSBs of the 16-bit data word are decoded to drive 15 switches,
E1 to E15. Each of these switches connects one of 15 matched resistors to either AGND or VREF. The remaining
12 bits of the data word drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder network.
R
R
VOUT
2R
2R
S0
2R
S1
2R
S11
2R
E1
2R
E2
2R
E15
VREF
12−Bit R−2R Ladder
Four MSBs Decoded into
15 Equal Segments
Figure 45. DAC Architecture
Output Range
The output of the DAC is
VOUT = (VREF × Code/65536)
Where:
Code = Decimal data word loaded to the DAC latch
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THEORY OF OPERATION (continued)
Power-on Reset
Both devices have a power-on reset function to ensure the output is at a known state upon power up. In the
DAC8830 and DAC8831, on power up, the DAC latch and input registers contain all 0s until new data is loaded
from the input serial shift register. Therefore, after power up, the output from pin VOUT of the DAC8830 is 0 V.
The output from pin VOUT of the DAC8831 is 0 V in unipolar mode and –VREF in bipolar mode.
However, the serial register of the DAC8830 and DAC8831 is not cleared on power up, so its contents are
undefined. When loading data initially to the device, 16 bits or more should be loaded to prevent erroneous data
appearing on the output. If more than 16 bits are loaded, the last 16 are kept; if less than 16 are loaded, bits will
remain from the previous word. If the device must be interfaced with data shorter than 16 bits, the data should
be padded with 0s at the LSBs.
Serial Interface
The digital interface is standard 3-wire connection compatible with SPI, QSPI, Microwire, and Texas Instruments
DSP interfaces, which can operate at speeds up to 50 Mbps. The data transfer is framed by CS, the chip select
signal. The DAC works as a bus slave. The bus master generates the synchronize clock, SCLK, and initiates the
transmission. When CS is high, the DAC is not accessed, and the clock SCLK and serial input data SDI are
ignored. The bus master accesses the DAC by driving pin CS low. Immediately following the high-to-low
transition of CS, the serial input data on pin SDI is shifted out from the bus master synchronously on the falling
edge of SCLK, and latched on the rising edge of SCLK into the input shift register, MSB first. The low-to-high
transition of CS transfers the contents of the input shift register to the input register. All data registers are 16 bit.
It takes 16 clocks of SCLK to transfer one data word to the parts. To complete a whole data word, CS must go
high immediately after 16 SCLKs are clocked in. If more than 16 SCLKs are applied during the low state of CS,
the last 16 bits are transferred to the input register on the rising edge of CS. However, if CS is not kept low
during the entire 16 SCLK cycles, data is corrupted. In this case, reload the DAC latch with a new 16-bit word.
In the DAC8830, the contents of the input register are transferred into the DAC latch immediately when the input
register is loaded, and the DAC output is updated at the same time.
The DAC8831 has an LDAC pin allowing the DAC latch to be updated asynchronously by bringing LDAC low
after CS goes high. In this case, LDAC must be maintained high while CS is low. If LDAC is tied permanently
low, the DAC latch is updated immediately after the input register is loaded (caused by the low-to-high transition
of CS).
18
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APPLICATION INFORMATION
Unipolar Output Operation
These DACs are capable of driving unbuffered loads of 60 kΩ. Unbuffered operation results in low supply
current (typically 5 μA) and a low offset error. The DAC8830 provides a unipolar output swing ranging from 0 V
to VREF. The DAC8831 can be configured to output both unipolar and bipolar voltages. Figure 46 and Figure 47
show a typical unipolar output voltage circuit for each device, respectively. The code table for this mode of
operation is shown in Table 1.
Table 1. Unipolar Code
DAC Latch Contents
MSB
Analog Output
LSB
VREF × (65,535/65,536)
1111 1111 1111 1111
1000 0000 0000 0000
VREF × (32,768/65,536) =
0000 0000 0000 0001
VREF × (1/65,536)
0000 0000 0000 0000
0V
+5 V
+2.5 V
0.1 µF
0.1 µF
VDD
+
10 µF
OPA277
OPA704
OPA727
VREF
DAC
VOUT
VO = 0 to +VREF
AGND
Serial
Interface
CS
SCLK
VREF
Input
Register
DAC Latch
SDI
DAC8830
DGND
Figure 46. Unipolar Output Mode of DAC8830
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+5 V
+2.5 V
0.1 µF
VDD
0.1 µF
+
10 µF
OPA277
OPA704
OPA727
VREF−S VREF−F
RINV
RFB
RFB
+V
CS
SCLK
SDI
Serial Interface
and Control Logic
LDAC
DAC
INV
VOUT
VO = 0 to +VREF
−V
AGNDF
Input
Register
DAC Latch
AGNDS
DAC8831
DGND
Figure 47. Unipolar Output Mode of DAC8831
Assuming a perfect reference, the worst-case output voltage may be calculated from the following equation:
Unipolar Mode Worst-Case Output
V OUT_UNI + D
216
ǒVREF ) VGEǓ ) V ZSE ) INL
Where:
VOUT_UNI = Unipolar mode worst-case output
D = Code loaded to DAC
VREF = Reference voltage applied to part
VGE = Gain error in volts
VZSE = Zero scale error in volts
INL = Integral nonlinearity in volts
20
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Bipolar Output Operation
With the aid of an external operational amplifier, the DAC8831 may be configured to provide a bipolar voltage
output. A typical circuit of such an operation is shown in Figure 48. The matched bipolar offset resistors RFB and
RINV are connected to an external operational amplifier to achieve this bipolar output swing; typically, RFB = RINV
= 28 kΩ.
Table 2 shows the transfer function for this output operating mode. The DAC8831 also provides a set of Kelvin
connections to the analog ground and external reference inputs.
Table 2. Bipolar Code
DAC Latch Contents
MSB
Analog Output
LSB
1111 1111 1111 1111
VREF × (32,767/32,768)
1000 0000 0000 0000
VREF × (1/32,768)
0111 1111 1111 1111
0V
0000 0000 0000 0001
–VREF × (1/32,768)
0000 0000 0000 0000
–VREF × (32,767/32,768) = –VREF
+5 V
+2.5 V
0.1 µF
0.1 µF
RINV
R FB
Serial Interface
and Control Logic
SDI
RFB
INV
LDAC
SCLK
10 µF
VREF−S VREF−F
VDD
CS
+
DAC
VOUT
AGNDF
Input
Register
DAC Latch
+V
VO = −VREF to +VREF
OPA277
−V OPA704
OPA727
AGNDS
DAC8831
DGND
Figure 48. Bipolar Output Mode of DAC8831
Assuming a perfect reference, the worst-case output voltage may be calculated from the following equation:
Bipolar Mode Worst-Case Output
V OUT_BIP +
ƪǒVOUT_UNI ) VOSǓ (2 ) RD) * VREF(1 ) RD)ƫ
1 ) ǒ2)RDǓ
A
Where:
VOS = External operational amplifier input offset voltage
RD = RFB and RIN resistor matching error
A = Operational amplifier open-loop gain
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Output Amplifier Selection
For bipolar mode, a precision amplifier should be used, supplied from a dual power supply. This provides the
±VREF output.
In a single-supply application, selection of a suitable operational amplifier may be more difficult because the
output swing of the amplifier does not usually include the negative rail; in this case, AGND. This output swing
can result in some degradation of the specified performance unless the application does not use codes near 0.
The selected operational amplifier needs to have low-offset voltage (the DAC LSB is 38 μV with a 2.5-V
reference), eliminating the need for output offset trims. Input bias current should also be low because the bias
current multiplied by the DAC output impedance (approximately 6.25 kΩ) adds to the zero-code error.
Rail-to-rail input and output performance is required. For fast settling, the slew rate of the operational amplifier
should not impede the settling time of the DAC. Output impedance of the DAC is constant and
code-independent, but in order to minimize gain errors the input impedance of the output amplifier should be as
high as possible. The amplifier should also have a 3 dB bandwidth of 1 MHz or greater. The amplifier adds
another time constant to the system, thus increasing the settling time of the output. A higher 3-dB amplifier
bandwidth results in a shorter effective settling time of the combined DAC and amplifier.
Reference and Ground
Since the input impedance is code-dependent, the reference pin should be driven from a low impedance source.
The DAC8830 and DAC8831 operate with a voltage reference ranging from 1.25 V to VDD. References below
1.25 V result in reduced accuracy.
The DAC full-scale output voltage is determined by the reference. Table 1 and Table 2 outline the analog output
voltage for particular digital codes.
For optimum performance, Kelvin sense connections are provided on the DAC8831. If the application does not
require separate force and sense lines, they should be tied together close to the package to minimize voltage
drops between the package leads and the internal die.
Power Supply and Reference Bypassing
For accurate high-resolution performance, it is recommended that the reference and supply pins be bypassed
with a 10 μF tantalum capacitor in parallel with a 0.1 μF ceramic capacitor.
22
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CROSS REFERENCE
The DAC8830 and DAC8831 have an industry-standard pinout configuration (see Table 3).
Table 3. Cross Reference
MODEL
INL
(LSB)
DNL
(LSB)
POWER-ON
RESET TO
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
PACKAGE
OPTION
CROSS
REFERENCE
DAC8830ICD
±1
±1
Zero-Code
–40°C to 85°C
8-Lead Small Outline IC
SO-8
AD5541CR,
MAX541AESA
DAC8830IBD
±2
±1
Zero-Code
–40°C to 85°C
8-Lead Small Outline IC
SO-8
AD5541BR,
MAX541BESA
DAC8830ID
±4
±1
Zero-Code
–40°C to 85°C
8-Lead Small Outline IC
SO-8
AD5541AR,
MAX541CESA
DAC8830MCD
±1
±1
Zero-Code
–55°C to 125°C
8-Lead Small Outline IC
SO-8
N/A
N/A
±1
±1
Zero-Code
–40°C to 85°C
8-Lead Plastic DIP
PDIP-8
MAX541AEPA
N/A
±2
±1
Zero-Code
–40°C to 85°C
8-Lead Plastic DIP
PDIP-8
MAX541BEPA
N/A
±4
±1
Zero-Code
–40°C to 85°C
8-Lead Plastic DIP
PDIP-8
MAX541CEPA
N/A
±1
±1
Zero-Code
0°C to 70°C
8-Lead Small Outline IC
SO-8
AD5541LR
N/A
±2
±1.5
Zero-Code
0°C to 70°C
8-Lead Small Outline IC
SO-8
AD5541JR
N/A
±1
±1
Zero-Code
0°C to 70°C
8-Lead Plastic DIP
PDIP-8
MAX541AEPA
N/A
±2
±1
Zero-Code
0°C to 70°C
8-Lead Plastic DIP
PDIP-8
MAX541BEPA
N/A
±4
±1
Zero-Code
0°C to 70°C
8-Lead Plastic DIP
PDIP-8
MAX541CEPA
DAC8831ICD
±1
±1
Zero-Code
–40°C to 85°C
14-Lead Small Outline IC
SO-14
AD5542CR,
MAX542AESD
DAC8831IBD
±2
±1
Zero-Code
–40°C to 85°C
14-Lead Small Outline IC
SO-14
AD5542BR,
MAX542BESD
DAC8831ID
±4
±1
Zero-Code
–40°C to 85°C
14-Lead Small Outline IC
SO-14
AD5542AR,
MAX542CESD
DAC8831MCD
±1
±1
Zero-Code
–55°C to 125°C
14-Lead Small Outline IC
SO-14
N/A
N/A
±1
±1
Zero-Code
–40°C to 85°C
14-Lead Plastic DIP
PDIP-14
MAX542ACPD
N/A
±2
±1
Zero-Code
–40°C to 85°C
14-Lead Plastic DIP
PDIP-14
MAX542BCPD
N/A
±4
±1
Zero-Code
–40°C to 85°C
14-Lead Plastic DIP
PDIP-14
MAX542CCPD
N/A
±4
±1
Zero-Code
–55°C to 125°C
14-Lead Ceramic SB
SB-14
MAX542CMJD
N/A
±1
±1
Zero-Code
0°C to 70°C
14-Lead Small Outline IC
SO-14
AD5542LR
N/A
±2
±1.5
Zero-Code
0°C to 70°C
14-Lead Small Outline IC
SO-14
AD5542JR
N/A
±1
±1
Zero-Code
0°C to 70°C
14-Lead Small Outline IC
SO-14
MAX542AEPD
N/A
±2
±1
Zero-Code
0°C to 70°C
14-Lead Small Outline IC
SO-14
MAX542BEPD
N/A
±4
±1
Zero-Code
0°C to 70°C
14-Lead Small Outline IC
SO-14
MAX542CEPD
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PACKAGE OPTION ADDENDUM
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31-May-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC8830MCDEP
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
8830EP
DAC8830MCDREP
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
8830EP
DAC8831MCDEP
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
8831EP
DAC8831MCDREP
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
8831EP
V62/06671-01XE
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
8830EP
V62/06671-02XE
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
8830EP
V62/06671-03YE
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
8831EP
V62/06671-04YE
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
8831EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
31-May-2014
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DAC8830-EP, DAC8831-EP :
• Catalog: DAC8830, DAC8831
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DAC8830MCDREP
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
DAC8831MCDREP
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Feb-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC8830MCDREP
SOIC
DAC8831MCDREP
SOIC
D
8
2500
367.0
367.0
38.0
D
14
2500
367.0
367.0
38.0
Pack Materials-Page 2
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