AD AD7769JN Lc2mos analog i/o port Datasheet

a
FEATURES
Two-Channel, 8-Bit 2.5 ms ADC
Two 8-Bit, 2.5 ms DACs with Output Amplifiers
Span and Offset of ADC and DAC
Independently Adjustable
Low Power
LC2MOS
Analog I/O Port
AD7769
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Winchester Disk Servo Controllers
Floppy Disk Microstepping
Closed Loop Servo Systems
GENERAL DESCRIPTION
The AD7769 is a complete, two-channel, 8-bit, analog I/O port.
It has versatile input and output signal conditioning features
that make it ideal for use in head-positioning servos in Winchester disk systems. It is equally suitable for floppy disk microstepping head positioning, other closed loop digital servo systems
and general purpose 8-bit data acquisition.
The AD7769 contains a high speed successive approximation
ADC, preceded by a two-channel multiplexer and signal conditioning circuits. The input span of the ADC and the offset of
the zero point from ground can be independently set by applying ground referenced voltages. The AD7769 also contains two
independent, fast settling, 8-bit DACs with output amplifiers.
The output span and offset voltage of the DACs can be set independently of those of the ADC. This makes the AD7769 especially useful in disk drives, where only a positive supply rail is
available and the ranges of the ADC and DACs must be referenced to some positive voltage less than the supply.
The AD7769 is easily interfaced to a standard 8-bit mpu bus via
an 8-bit data port and standard microprocessor control lines.
The AD7769 is fabricated in Linear Compatible CMOS
(LC2MOS), an advanced, mixed technology process that combines precision bipolar circuits with low power CMOS logic.
The part is available in a 28-lead plastic DIP and 28-terminal
PLCC package.
PRODUCT HIGHLIGHTS
1. Two-Channel, 8-Bit Analog I/O port on a Single Chip.
The AD7769 contains a two-channel, high speed ADC with
input signal conditioning and two, fast settling 8-bit DACs
with output amplifiers, on a single chip.
2. Independent Control of Span and Offset.
The input voltage span of the ADC and the midpoint of the
transfer function, the output voltage swing of the two DACs
and the half-scale output voltage, can be set independently
by applying ground referenced control voltages.
3. Dynamic Specifications for DSP Users.
In addition to the traditional ADC and DAC specifications,
the AD7769 is specified with ac parameters including signalto-noise ratio, distortion and signal bandwidth.
4. Fast Microprocessor Interface.
The AD7769 has bus interface timing compatible with all
modern microprocessors, with bus access and relinquish
times less than 65 ns and a Write pulse width less than 90 ns.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.comFax:
617/326-8703
© Analog Devices, Inc., 1997
AD7769–SPECIFICATIONS
(V = +12 V 6 10%; V
ADC SPECIFICATIONS V
CC = +5 V 6 5%; AGND [ADC] = AGND [DAC] = DGND = 0 V; VBIAS [ADC] = +5 V;
1
[ADC]
=
+2.5
V;
f
SWING
CLK = 5 MHz external. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
J Version
A Version Units
8
±1
±1
*
*
*
Bits
LSB max
LSB max
± 2.5
± 3.0
*
*
LSB max
LSB max
± 2.5
± 3.5
*
*
LSB max
LSB max
± 2.0
± 2.5
*
*
LSB max
LSB max
± 3.5
±4
*
*
LSB max
LSB max
DC ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Bias Offset Error
+25°C
TMIN to TMAX
Bias Offset Match
+25°C
TMIN to TMAX
Plus or Minus Full-Scale Error
+25°C
TMIN to TMAX
Plus or Minus Full-Scale Match
+25°C
TMIN to TMAX
ADC TO DAC MATCHING
Bias Offset Match
+25°C
TMIN to TMAX
Plus or Minus Full-Scale Match
+25°C
TMIN to TMAX
DYNAMIC PERFORMANCE2
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Intermodulation Distortion (IMD)
Frequency Response
DD
LOGIC OUTPUTS
DB0–DB7, INT
VOL, Output Low Voltage
VOH, Output High Voltage
DB0–DB7
Floating State Leakage Current
Floating State Capacitance2
Output Coding
POWER REQUIREMENTS
VCC Range
See Terminology
No Missing Codes. See Terminology.
See Terminology
Channel A to Channel B
See Terminology
Channel A to Channel B
Channel A/B to VOUT A/B
VBIAS (DAC) = +5 V, VSWING (DAC) = +2.5 V.
± 2.5
± 3.5
*
*
LSB max
LSB max
± 3.5
± 4.0
*
*
LSB max
LSB max
44
48
60
0.1
*
*
*
*
dB min
dB max
dB typ
dB typ
VIN = 100 kHz Full-Scale Sine Wave with fSAMPLING = 400 kHz
VIN = 100 kHz Full-Scale Sine Wave with fSAMPLlNG = 400 kHz
fa = 99 kHz, fb = 96.7 kHz with fSAMPLING = 400 kHz
VIN = Full-Scale, dc to 200 kHz Sine Wave
V min
V max
mA max
Whichever Is the Higher
Whichever Is the Lower
With Respect to AGND (ADC). For Specified Performance.
With Respect to AGND (ADC). For Specified Performance.
ANALOG INPUTS
Input Voltage Ranges, VINA, VINB VBIAS – VSWING or 0
VBIAS + VSWING or 9.8
Input Currents, IINA, IINB
± 0.4
*
ADC REFERENCE INPUTS
Input Voltage Levels
VBIAS (ADC)
VSWING (ADC)
Input Currents
VBIAS (ADC) Input
VSWING (ADC) Input
Conditions/Comments
2/6.8
2.0/3.0
*
*
V min/max
V min/max
± 800
±1
*
*
µA max
µA max
0.4
4.0
*
*
V max
V min
± 10
10
*
*
Offset Binary
4.75/5.25
*
VDD Range
IDD @ +25°C
VUBAm VINB = TMIN to TMAX
10.8/13.2
20
22
*
*
*
ICC @ +25°C
TMIN to TMAX
5
6
*
*
ISINK = 1.6 mA
ISOURCE = 200 µA
µA max
pF max
V min/V max For Specified Performance. The Part Will Function with
VCC =5 V ± 10% with Degraded Performance.
V min/V max For Specified Performance
mA max
For ADC and DAC: VBIAS = 5.0 V; VSWING = 3.0 V; VINA,
mA max
VBIAS; DAC Code = FF (Hex); DACA and DACB Load = 5 kΩ
to AGND (DAC). Typically I DD = 14 mA.
mA max
Logic Inputs = 2.4 V, CLK Input = 0.8 V. Typically ICC = 1.5 mA.
mA max
NOTES
1
Temperature range as follows: J Version: 0°C to +70°C; A Version: –40°C to +85°C.
2
Sample tested at +25°C to ensure compliance.
*Specification same as J Version.
Specifications subject to change without notice.
–2–
REV. A
AD7769
DACA, DACB SPECIFICATIONS
Parameter
(VDD = +12 V 6 10%; VCC = +5 V 6 5%; AGND [DAC] = AGND [ADC] = DGND = 0 V;
VBIAS [DAC] = +5 V; VSWING [DAC] = +2.5 V; VOUTA, VOUTB load to AGND [DAC], RL = 5 kV,
CL = 100 pF. All specifications TMIN to TMAX1 unless otherwise noted.)
J Version A Version Units
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Bias Offset Error
+25°C
TMIN to TMAX
Bias Offset Match
+25°C
TMIN to TMAX
Plus or Minus Full-Scale Error
+25°C
TMIN to TMAX
Plus or Minus Full-Scale Match
+25°C
TMIN to TMAX
ADC to DAC MATCHING
8
±1
±1
*
*
*
Bits
LSB max
LSB max
± 2.0
± 2.5
*
*
LSB max
LSB max
± 2.5
± 3.5
*
*
LSB max
LSB max
± 1.5
± 2.0
*
*
LSB max
LSB max
± 3.5
± 4.0
*
*
LSB max
LSB max
Conditions/Comments
See Terminology
Guaranteed Monotonic. See Terminology.
See Terminology
VOUT A to VOUT B
See Terminology
VOUT A to VOUT B
As Per ADC Specifications
2
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Intermodulation Distortion (IMD)
ANALOG OUTPUTS
Output Voltage Ranges
VOUTA, VOUTB
DC Output Impedance
Short-Circuit Current
DAC REFERENCE INPUTS
Input Voltage Levels
VBIAS (DAC)
VSWING (DAC)
Input Currents
VBIAS (DAC) Input
VSWING (DAC) Input
AC CHARACTERISTICS2
Voltage Output Settling Time
Digital-to-Analog Glitch Impulse
Digital Feedthrough
LOGIC INPUTS
CS, RD, WR, ADC/DAC,
CHA/CHB, DB0–DB7
Input Low Voltage, VINL
Input High Voltage, VINH
Input Leakage Current
Input Capacitance
CLK
Input Low Voltage
Input High Voltage
Input Leakage Current
DB0–DB7
Input Coding
POWER REQUIREMENTS
44
48
55
*
*
*
dB min
dB max
dB typ
VOUT = 20 kHz Full-Scale Sine Wave With fSAMPLING = 400 kHz
VOUT = 20 kHz Full-Scale Sine Wave With fSAMPLING = 400 kHz
fa = 18.4 kHz, fb = 14.5 kHz with fSAMPLING = 400 kHz
VBIAS – VSWING or 0.5
VBIAS + VSWING or
VDD –2.0
0.5
*
20
*
V min
Whichever Is the Higher
V max
Ω typ
mA typ
Whichever Is the Lower
3/6.8
2.0/3.0
*
*
V min/max With Respect to AGND (DAC). For Specified Performance.
V min/max With Respect to AGND (DAC). For Specified Performance.
±2
±1
*
*
µA max
µA max
4
30
1
*
*
*
µs max
Settling Time to Within ± 1/2 LSB of Final Value. Typically 2.5 µs.
nV sec typ See Terminology
nV sec typ See Terminology
0.8
2.4
± 10
10
*
*
*
*
V max
V min
µA max
pF max
0.8
2.4
± 10
*
*
*
V max
V min
µA max
Offset Binary
As per ADC Specifications
NOTES
1
Temperature range as follows: J Version: 0°C to +70°C; A Version: –40°C to +85°C.
2
Sample tested at +25°C to ensure compliance.
*Specifications same as J Version.
Specifications subject to change without notice.
REV. A
–3–
External Clock. For Internal Clock Operation Connect
the CLK Pin to VDD.
AD7769
(V = +5 V 6 5%; V
TIMING CHARACTERISTICS1, 2 For ADC and DAC, V
= +12 V 6 10%; AGND [ADC] = AGND [DAC] = DGND = 0 V.
=
+5 V, VSWING = +2.5 V.)
BIAS
CC
Parameter
ADC /DAC CONTROL TIMING
CS to WR Setup Time
CS to WR Hold Time
ADC/DAC to WR Setup Time
ADC/DAC to WR Hold Time
CHA/CHB to WR Setup Time
CHA/CHB to WR Hold Time
WR Pulse Width
ADC CONVERSION TIMING
Using External Clock
WR to INT Low Delay
Using Internal Clock
WR to INT Low Delay
WR to INT High Delay
WR to Data Valid Delay3
ADC READ TIMING
CS to RD Setup Time
CS to RD Hold Mode
RD to Data Valid Delay3
Bus Relinquish Time after RD High4
RD to INT High Delay
RD Pulse Width
DAC WRITE TIMING
Data Valid to WR Setup Time
Data Valid to WR Hold Time
WR to DAC Output Settling Time
DD
Limit at Limit at
+258C TMIN, TMAX
Units
t1
t2
t3
t4
t5
t6
t7
0
0
0
0
0
0
80
0
0
0
0
0
0
80
ns min
ns min
ns
ns min
ns min
ns min
ns min
t8
2.6
2.6
µs max
t8
t9
t9
t10
t10
1.9/3.0
85
120
t8+70
t8+110
1.9/3.0
85
120
t8+70
t8+110
µs min/max
ns max
ns max
ns max
ns max
Load Circuit of Figure 3, CL = 20 pF
Typically 2.5 µs
Load Circuit of Figure 3, CL = 20 pF
Load Circuit of Figure 3, C L = 100 pF
Load Circuit of Figure 1, CL = 20 pF
Load Circuit of Figure 1, CL = 100 pF
t11
t12
t13
t13
t14
t15
t15
t16
0
0
15/65
30/100
15/65
80
110
t13
0
0
15/65
30/100
15/65
80
110
t13
ns min
ns min
ns min/max
ns min/max
ns min/max
ns max
ns max
ns min
Load Circuit of Figure 1, C L = 20 pF
Load Circuit of Figure 1, C L = 100 pF
Load Circuit of Figure 2
Load Circuit of Figure 3, CL = 20 pF
Load Circuit of Figure 3, C L = 100 pF
Determined by t13
t17
t18
t19
65
15
4
65
20
4
ns nıin
ns min
µs max
Load Circuit of Figure 4
Label
Test Conditions/Comments
Load Circuit of Figure 3, CL = 20 pF
NOTES
1
See Figures 11, 12 and 13.
2
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3
t10 and t13 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
t14 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Figure 1. Load Circuits for Data Access Time Test
Figure 2. Load Circuits for Bus Relinquish Time Test
Figure 3. Load Circuit for RD and WR to INT Delay Test
Figure 4. Load Circuit for DAC Settling Time Test
–4–
REV. A
AD7769
ABSOLUTE MAXIMUM RATINGS*
VDD to AGND or DGND . . . . . . . . . . . . . . . . . –0.3 V, +15 V
VCC to DGND . . . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V or 7 V
(Whichever is Lower)
AGND to DGND . . . . . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
Digital Inputs to DGND
(Pins 12, 13, 15–18) . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
Digital Outputs to DGND
(Pins 3–10, 11) . . . . . . . . . . . . . . . . . . . –0.3 V, VCC +0.3 V
Analog Inputs to AGND . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
Analog Outputs to AGND . . . . . . . . . . . . –0.3 V, VDD +0.3 V
Operating Temperature Range
Commercial (J Version) . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Power Dissipation (Any Package)
to +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Derates Above +75°C by . . . . . . . . . . . . . . . . . . . 6 mW/°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 10 secs) . . . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any one time.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7769 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Model
Temperature
Range
Package
Option*
AD7769JN
AD7769JP
AD7769AN
AD7769AP
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
N-28
P-28A
N-28
P-28A
WARNING!
ESD SENSITIVE DEVICE
NOTE
Do not allow VCC to exceed VDD by more than 0.3 V. In cases
where this can happen the diode protection scheme shown
below is recommended.
*N = Plastic DIP; P = Plastic Leaded Chip Carrier.
PIN CONFIGURATIONS
DIP
REV. A
PLCC
–5–
AD7769
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Description
1
2
3–10
VDD
VCC
DB7–DB0
11
INT
12
CLK
13
CHA/CHB
14
15
DGND
ADC/DAC
16
WR
17
18
19
RD
CS
VSWING (ADC)
20
21
22
AGND (ADC)
VINB
VBIAS (ADC)
23
VINA
24
25
AGND (DAC)
VSWING (DAC)
26
27
VOUTB
VBIAS (DAC)
28
VOUTA
+12 V Power Supply. This powers the analog circuitry.
+5 V Power Supply. This powers the logic circuitry.
Input/Output Data Bus. A bidirectional data port from which ADC output data may be read
and to which DAC input data may be written. DB7 is the Most Significant Bit.
Interrupt Output (active low). INT is set high on the falling edge of RD or WR to the ADC
and goes low at the end of a conversion.
Clock input. A clock is required for the ADC. An external TTL-compatible clock may be applied to
this input pin. Alternatively, tying this pin to VDD enables the internal clock oscillator. With an
external clock, the mark-space ratio can vary from 30/70 to 70/30.
Channel A/Channel B Select Input. Selects Channel A or Channel B of the DAC or ADC.
Used in conjunction with WR, RD, CS and ADC/DAC for read or write operations.
Digital Ground.
ADC or DAC Select Input. Selects either the ADC or the DAC for read or write operations in
conjunction with WR, RD, CS and CHA/CHB.
Write Input (edge triggered). This is used in conjunction with the ADC/DAC, CHA/CHB and CS
control inputs to start an ADC conversion or write data to the DAC. An ADC conversion starts on the
rising edge of WR.
Read Input (active low). This input must be low to access data from the ADC.
Chip Select Input (active low). The device is selected when this input is low.
ADC Reference Input. The voltage applied to this pin with respect to AGND (ADC) sets the
in put voltage Full-Scale Range (FSR) of the ADC. VIN (FSR) = 2 VSWING (ADC).
ADC Analog Ground.
Analog Input for Channel B. See VINA description.
ADC Reference Input. The voltage applied to this pin with respect to AGND (ADC) sets the
midpoint of the ADC transfer function.
Analog Input for Channel A. The input voltage range of both ADC channels is given by:
VIN A/B = VBIAS (ADC) ± VSWING (ADC).
DAC Analog Ground.
DAC Reference Input. The voltage applied to this pin with respect to AGND (DAC) sets the
output voltage Full-Scale Range (FSR) of the DACs. VOUT (FSR) = 2 VSWING (DAC).
Analog Output Voltage from DAC B. See VOUTA description.
DAC Reference Input. The voltage applied to this pin with respect to AGND (DAC) sets the
midpoint output voltage of the DACs.
Analog Output Voltage from DAC A. The output voltage range of both DACs is given by:
VOUT A/B = VBIAS (DAC) ± VSWING (DAC).
TERMINOLOGY
Relative Accuracy
Differential Nonlinearity
For an ADC, Relative Accuracy or endpoint nonlinearity is the
maximum deviation, in LSBs, of the ADC’s actual code transition points from a straight line drawn between the endpoints of
the ADC transfer function, i.e., the 00 to 01 and FE to FF Hex
(01111111 to 11111111 Binary) code transitions.
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB max ensures monotonicity (DAC) or no missed codes (ADC).
For a DAC, Relative Accuracy or endpoint nonlinearity is a
measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function, i.e., those voltages which correspond to codes 00 and FF
Hex.
For an ideal ADC, the output code for an input voltage equal to
VBIAS (ADC), should be 80 Hex (10000000 binary). The ADC
Bias Offset Error is the difference between the actual midpoint
voltage for code 80 Hex and VBIAS (ADC), expressed in LSBs.
Bias Offset Error
For an ideal DAC, the output voltage for code 80 Hex should
be equal to VBIAS (DAC). The DAC Bias Offset Error is the
difference between the actual output voltage and VBIAS (DAC),
expressed in LSBs.
For the specified input and output ranges, 1 LSB = 19.5 mV,
but will vary with VSWING. For both DACs and ADC,
1 LSB = 2 VSWING /256 = FSR/256.
–6–
REV. A
AD7769
Plus and Minus Full-Scale Error
Signal-to-Noise Ratio (SNR)
The ADC and DACs in the AD7769 can be considered as devices with bipolar (plus and minus) input ranges, but referred to
VBIAS instead of AGND. Plus Full-Scale Error for the ADC is the
difference between the actual input voltage at the FE to FF code
transition and the ideal input voltage (VBIAS + VSWING –1.5 LSB),
expressed in LSBs. Minus Full-Scale Error is similarly specified
for the 01 to 00 code transition, relative to the ideal input voltage
for this transition (VBIAS – VSWING +0.5 LSB). Plus Full-Scale
Error for the DACs is the difference, expressed in LSBs, between
the actual output voltage for input code FF and the ideal voltage
(VBIAS + VSWING – 1 LSB). Minus Full-Scale Error is similarly
specified for code 00, relative to the ideal output voltage (VBIAS –
VSWING). Note that Plus and Minus Full-Scale errors for the
ADC and the DAC outputs are measured after their respective
Bias Offset errors have been adjusted out.
SNR is the measured Signal-to-Noise Ratio at the output of the
converter. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency. SNR is dependent on the number
of quantization levels used in the digitization process; the more
levels, the smaller the quantization noise. The theoretical SNR
for a sine wave is given by
SNR = (6.02N + 1.76) dB
where N is the number of bits. Thus for an ideal 8-bit converter,
SNR = 49.92 dB.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7769, Total Harmonic Distortion is defined as
(V 22 + V 32 + V 42 + V 52 + V 62 )
V1
1/ 2
Digital-to-Analog Glitch Impulse
20 log
Digital-to-Analog Glitch Impulse is the impulse injected into the
analog outputs when the digital inputs change state with either
DAC selected. It is normally specified as the area of the glitch in
nV secs and is measured when the digital input code is changed
by 1 LSB at the major carry transition.
where V1 is the rms amplitude of the fundamental and V2,
V3, V4, V5 and V6 are the rms amplitudes of the individual
harmonics.
Intermodulation Distortion (IMD)
Digital Feedthrough
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products, of order (m+n), at sum and difference frequencies of
mfa+nfb, where m, n = 0, 1, 2, 3 . . . Intermodulation terms are
those for which neither m nor n is equal to zero. For example,
the second order terms include (fa+fb) and (fa–fb) and the third
order terms include (2fa+fb), (2fa–fb), (fa+2fb) and (fa–2fb).
Digital Feedthrough is also a measure of the impulse injected
into the analog outputs from the digital inputs but is measured
when the DACs are not selected. This is essentially feedthrough
across the die and package. It is important in the AD7769 since
it is a measure of the glitch impulse transferred to the analog
outputs when data is read from the ADC register. It is specified
in nV secs and measured with WR high and a digital code
change from all 0s to all 1s.
LOGIC TRUTH TABLE
ADC CHANNEL SELECT AND START CONVERSION
CS
ADC/DAC
CHA/CHB
0
0
0
0
0
0
X
0
1
WR
RD
DB0–DB7
INT
Comments
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
1
1
1
0
INT Is Set on Falling Edge of WR.
Select ADC Channel A and Start Conversion.
Select ADC Channel B and Start Conversion.
INT Goes Low at End of Conversion.
READ ADC DATA
CS
ADC/DAC
CHA/CHB
WR
RD
DB0–DB7
INT
Comments
0
0
0
X
X
X
X
X
X
X
X
X
0
ADC Data
ADC Data
High-Z
1
1
1
INT Is Set High on Falling Edge of RD.
ADC Data on Data Bus.
Data Outputs Impedance.
WR
RD
DB0–DB7
INT
Comments
X
1
1
0
0
X
µP Data
µP Data
ADC Data
ADC Data
High-Z
N/C
N/C
N/C
N/C
N/C
µP Writing Data to DACA.
µP Writing Data to DACB.
Data from Last ADC Conversion Will Be Written to DACA.
Data from Last ADC Conversion Will Be Written to DACB.
No Operation.
WRITE TO DACA OR DACB
CS
ADC/DAC
CHA/CHB
0
0
0
0
1
1
1
1
1
X
0
1
0
1
X
NOTES
1
If RD = 1, DB0–DB7 will remain high impedance. If RD = 0, DB0–DB7 will output previous ADC data. The RD input should not change during a conversion.
2
X = Don’t Care.
3
N/C = No Change.
REV. A
–7–
AD7769
midpoint code of the ADC, 80 Hex (10000000 Binary), occurs
at an input voltage equal to VBIAS. The input FSR of the ADC is
equal to 2 VSWING, so that the Plus Full-Scale code transition
(FE to FF Hex) occurs at a voltage equal to VBIAS + VSWING
–1.5 LSBs and the Minus Full-Scale code transition (01 to 00
Hex) occurs at a voltage VBIAS – VSWING +0.5 LSBs. The
transfer function of the DACs bears a similar relationship to
VBIAS and VSWING. The DAC output voltage for code 80 Hex
(10000000 binary) is equal to VBIAS, while FF Hex (11111111
binary) gives an output voltage of VBIAS + VSWING –1 LSB
(Plus Full-Scale) and 00 Hex gives an output voltage of VBIAS –
VSWING (Minus Full-Scale).
CIRCUIT DESCRIPTION
Analog Inputs and Outputs
The AD7769 provides the analog-to-digital and digital-to-analog
conversion functions required between the microcontroller and
the servo power amplifier in digital servo systems. It is intended
primarily for closed loop head positioning in Winchester disk
drives, but may also be used for microstepping in drives with
stepper motor head positioning or other servo applications. The
AD7769 contains a high speed, 8-bit, sampling ADC with two
input channels and two 8-bit DACs with output buffer amplifiers. A unique feature of the AD7769 is the input and output signal conditioning circuitry that allows the analog input and
output voltages to be referred to a point other than analog
ground. The input range and offset of the ADC, the output
swing and offset of the DACs may be adjusted independently by
the application of ground-referenced, positive control voltages,
VBIAS (ADC), VSWING (ADC), VBIAS (DAC) and VSWING (DAC).
Thus, for example, the peak-to-peak output swing of the DACs
could be set to 3 V above and 3 V below a bias voltage of 5 V.
The ability to refer input and output signals to some voltage
other than ground is of particular importance in disk drive applications. Typically, only +5 V digital and +12 V analog supply
voltages are available, and the analog signals are often referred
to a voltage around half the analog supply.
Driving the Analog Inputs and Reference Inputs
The analog inputs, VINA and VINB, must be driven from low
output impedance sources, such as from op amps. In addition,
VBIAS (ADC) must be driven from a similar type low impedance
source (e.g., voltage reference).
Figures 5 and 6 show the transfer functions of the ADC
and DACs and their relationship to VBIAS and VSWING. The
Op amps are not required to drive the VSWING (ADC), VBIAS
(DAC) and VSWING (DAC) inputs as these are high impedance
inputs (200 nA typical input current) that feed into on-chip
buffer amplifiers. The reference voltages for these inputs can be
derived using suitable resistor divider networks.
The analog reference available in the disk drive system can be
used to set the bias voltage of the AD7769, and could also be attenuated to provide the reference for the input and output swing
as shown in Figure 7. The same bias voltage would generally
(though not necessarily) be used for the ADC and the DACs,
though the input and output ranges might be different.
Figure 5. ADC Transfer Function
Figure 7. Typical Analog Connections to the AD7769
ADC Conversion Cycle
Figure 8 shows the operating waveforms for a conversion cycle.
On the rising edge of WR, the conversion cycle starts with the
acquisition and tracking of the selected ADC channel, VINA or
VINB. The analog input voltage is held 50 ns (typically) after the
fourth falling edge of the input CLK following a conversion
start. If tD in Figure 8 is greater than 150 ns, then the falling
edge of the input CLK will be seen as the first falling clock edge.
If tD is less than 150 ns, the first falling clock edge to be recognized will not occur until one cycle later.
Figure 6. DAC Transfer Function
–8–
REV. A
AD7769
Figure 8. Operating Waveforms Using External Clock
Following the “hold” on the analog input, the MSB decision is
made approximately 50 ns after the next falling edge of the input CLK. The succeeding bit decisions are made approximately 50 ns after a CLK edge until conversion is complete. At
the end of conversion, the INT line goes low 100 ns (typically)
after the LSB decision and the SAR contents are transferred to
the output latch. The SAR is then reset in readiness for a new
conversion.
Track-and-Hold
The track-and-hold (T/H) amplifier on the analog input to the
ADC of the AD7769 allows the ADC to accurately convert an
input sine wave of 5 V peak-to-peak amplitude up to a frequency of 200 kHz, the Nyquist frequency of the ADC when
operated at its maximum throughput rate of 400 kHz. This
maximum rate of conversion includes conversion time and time
between conversions. Because the input bandwidth of the trackand-hold is much greater than 200 kHz, the input signal should
be band limited to avoid folding unwanted signals into the band
of interest.
DAC Outputs
The D/A converter outputs are buffered with on-board, high
speed op amps that are capable of driving 5 kΩ and 100 pF
loads to AGND (DAC). Each output amplifier settles to within
1/2 LSB of its final output value in typically less than 2.5 µs.
See Figures 9 and 10 for waveforms of the typical output settling time performance.
The output noise from the amplifiers with full scale on the
DACs is typically 200 µV peak-to-peak.
Figure 10. Negative-Going Settling Time
Internal / External Clock Operation
The AD7769 can be operated on either its own internal clock or
with an externally applied clock signal. For internal clock operation the CLK input must be tied to VDD. No external components are required. The internal clock typically runs at 5 MHz
giving a typical conversion time of 2.5 µs. For external clock operation the CLK input must be driven with a TTL/ HCMOS
compatible input. The mark/space ratio of the clock signal can
vary from 30/70 to 70/30. For an input frequency of 5 MHz, the
conversion time is 2.5 µs.
Digital Inputs and Outputs
The AD7769 communicates over a standard, 8-bit microprocessor data bus and is controlled by standard mpu control lines,
CS, WR, RD, INT, plus two address lines, ADC/DAC and
CHA/CHB, which select the DAC or ADC function and Channel A or Channel B input/output channel. The Chip Select (CS)
line selects the device, Write (WR) is used to initiate ADC conversions or to write data to the DAC, depending on the state of
ADC/DAC. INT is a status flag that indicates completion of a
conversion, while RD is used to read ADC output data. The
8-bit data port (DB0–DB7) is a bidirectional port into which
data can be written to the two DAC registers, and from which
data can be read from the ADC register. ADC output data may
also be written directly into either of the DAC registers.
These logical operations are detailed in Table I and in the time
ing diagrams, Figures 11 to 13. Figures 12 and 13 show the
fairly straightforward operations of reading ADC data and writing data to the DACs, and need little explanation. Figure 11
shows the timing for ADC channel selection and conversion
start. This is more complicated as the state of the data outputs
during a conversion depends on CS and RD.
To initiate a conversion (or any other operation) the device
must be selected by taking CS low. A conversion is started by
taking WR low, then high again (conversion starts on rising edge
of WR). There are three possibilities for the state of the data
outputs during the conversion.
1. If RD is held high, the data outputs will be high impedance
throughout the conversion.
Figure 9. Positive-Going Settling Time
REV. A
2. If RD and CS are both held low until after INT goes low,
then DB0–DB7 will initially output data from the last conversion. After INT goes low the new conversion data will
appear on DB0–DB7.
–9–
AD7769
3. If RD is held low but CS is taken high during the conversion,
the device will be de-selected and DB0–DB7 will revert to
their high impedance state. This will not affect completion of
the conversion, but the data cannot be read, or any other
operation performed, until CS is taken low again.
4. Note that the state of RD should not be changed during a
conversion.
DIGITAL SIGNAL PROCESSING APPLICATIONS
In Digital Signal Processing (DSP) application areas like voice
recognition, echo cancellation and adaptive filtering, the dynamic characteristics (SNR, Harmonic Distortion, Intermodulation Distortion) of both the ADC and DACs are critical. The
AD7769 is specified dynamically as well as with standard dc
specifications. Because the track/hold amplifier has a wide bandwidth, an antialiasing filter should be placed on the VINA and
VINB inputs to avoid aliasing of high frequency noise back into
the bands of interest.
The dynamic performance of the ADC is evaluated by applying
a sine wave signal of very low distortion to the VINA or VINB
input which is sampled at a 409.6 kHz sampling rate. A Fast
Fourier Transform (FFT) plot or Histogram plot is then generated from which SNR, harmonic distortion and dynamic differential nonlinearity data can be obtained. For the DACs, the
codes for an ideal sine wave are stored in PROM and loaded
down to the DAC. The output spectrum is analyzed, using a
spectrum analyzer to evaluate SNR and harmonic distortion
performance. Similarly, for intermodulation distortion, an input
(either to VIN or DAC code) consisting of pure sine waves at
two frequencies is applied to the AD7769.
Figure 11. Timing for ADC Channel Select and Conversion
Start
Figure 14 shows a 2048 point FFT plot of the ADC with an input signal of 130 kHz. The SNR is 49.2 dB. It can be seen that
most of the harmonics are buried in the noise floor. It should be
noted that the harmonics are taken into account when calculating the SNR. The relationship between SNR and resolution (N)
is expressed by the following equation:
SNR = (6.02N + 1.76) dB
Figure 12. Timing for ADC Data Read
Figure 14. ADC FFT Plot
Figure 13. Timing for DAC Channel Select and Data Write
–10–
REV. A
AD7769
This is for an ideal part with no differential or integral linearity
errors. These errors will cause a degradation in SNR. By working backwards from the above equation, it is possible to get a
measure of ADC performance expressed in effective number of
bits (N). The effective number of bits is plotted versus frequency in Figure 15. The effective number of bits typically falls
between 7.7 and 7.9, corresponding to SNR Figures 48.1 and
49.7 dB.
where A is the peak amplitude of the sine wave and p (V) the
probability of occurrence at a voltage V. The histogram plot of
Figure 17 corresponds very well with this shape.
Figure 15. Effective Number of Bits vs. Frequency
Figure 16 shows a spectrum analyzer plot of the output spectrum from one of the DACs with an ideal sine wave table loaded
to the data inputs of the DAC. In this case, the SNR is 47 dB.
Figure 17. ADC Histogram Plot
In digital signal processing applications, where the AD7769 is
used to sample ac signals, it is essential that the signal sampling
occurs at exactly equal intervals. This minimizes errors due to
sampling uncertainty or jitter. A precise timer or clock source,
to start the conversion process, is the best method of generating
equidistant sampling intervals.
MICROPROCESSOR/MICROCOMPUTER INTERFACING
The AD7769 is designed for easy interfacing to microprocessors
and microcomputers as a memory mapped peripheral or an I/O
device. In addition, the AD7769 high speed bus timing allows
direct interfacing to many DSP processors such as the
TMS320C10 and ADSP-2101.
AD7769–TMS320C10 Interface
Figure 16. DAC Output Spectrum
Histogram Plot
A typical interface to the TMS320C10 is shown in Figure 18.
The AD7769 is mapped at a port address, and the interface is
designed for the maximum TMS320C10 clock frequency of
20 MHz.
When a sine wave of specified frequency is applied to the VINA
or VINB input of the AD7769 and several thousand samples are
taken, it is possible to plot a histogram showing the frequency of
occurrence of each of the 256 ADC codes. If a particular step is
wider than the ideal 1 LSB width, then the code associated with
that step will accumulate more counts than for the code for an
ideal step. Likewise, a step narrower than ideal width will have
fewer counts. Missing codes are easily seen because a missing
code means zero counts for a particular code. The absence of
large spikes in the plot indicates small differential nonlinearity.
Figure 17 shows a histogram plot for the ADC indicating very
small differential nonlinearity and no missing codes for an input
frequency of 204 kHz. For a sine wave input, a perfect ADC
would produce a probability density function described by the
equation:
p (V) =
1
π( A2 –V 2)1/2
Figure 18. AD7769 to TMS320C10 Interface
REV. A
–11–
AD7769
Conversion is initiated on the selected AD7769 ADC channel
using a single I/O instruction, <OUT ADC, A>. The processor
then polls INT until it goes low before reading the conversion
result using an <IN A, ADC> instruction. Writing data to the relevant AD7769 DAC consists of an <OUT DAC, A> instruction.
AD7769–ADSP-2101 Interface
Figure 19 shows a typical interface to the DSP microcomputer,
the ADSP-2101. The ADSP-2101 is optimized for high speed
numeric processing tasks.
Figure 20. AD7769 to 8051 (Processor Bus) Interface
Figure 19. AD7769 to ADSP-2101 Interface
Because the instruction cycle of the ADSP-2101 is very fast
(80 ns cycle), the WR and RD pulses must be stretched out to
suit the AD7769. This is easily achieved as the ADSP-2101
memory interface supports slower memories and memorymapped peripherals (i.e., AD7769) with a programmable wait
state generation capability. A number of wait states, from 0 to 7,
can be specified for each memory interface. One wait state is
sufficient for the interface to the AD7769.
AD7769–8051 Interface
A choice of two interface modes are available to the 8051
microcomputer.
Figure 20 shows a typical interface to the 8051 processor bus. It
is suitable for the maximum 8051 clock frequency of 12 MHz.
In this interface mode, Port 0 provides the multiplexed low order address and data bus and Port 2 provides the high order address bus (A8–A15).
Figure 21. AD7769 to 8051 (Parallel l/O Ports) Interface
AD7769–MC68HC11 Interface
Figure 22 shows a typical interface between the AD7769 and the
MC68HC11 microcomputer. This interface is designed for the
maximum MC68HC11 clock speed of 8.4 MHz. The microcomputer is operated in the expanded multiplexed mode, with the
AD7769 as a memory mapped peripheral. The expansion bus is
made up of Ports B and C, and control signals AS and R/W.
Figure 21 shows the AD7769 interfaced to the 8051 parallel I/O
ports. This interface circuit is simpler to implement than the
previous interface to the processor bus, but, in general, the
maximum data throughput rate is much slower (for the same
clock frequencies). In addition to its simplicity, the interface to
the parallel I/O ports versus the processor bus allows independent control of both the WR and RD inputs to the AD7769.
For example, the 8051 can set both WR and RD low at the
same time. This permits data from the last ADC conversion to
be written directly from the ADC register into the selected DAC
register (see Logic Truth Table). This allows very fast transfer
of data from the ADC to the DAC and is a useful feature for
some applications such as a fast, programmable, infinite sampleand-hold function.
Figure 22. AD7769 to MC68HC11 Interfaced
–12–
REV. A
AD7769
APPLICATIONS
The AD7769 analog I/O port is used to convert servo related
signals between the analog and digital domains. The input
structure of the two-channel ADC makes it very easy to convert
the typical output signals provided by a servo demodulator.
In a magnetic disk drive employing a dedicated servo surface,
the servo demodulator produces two, positive-only, quadrature
signals, generally sinusoidal or triangular, from the all-bit patterns read from the servo surface. The quadrature signals have
the form of VBIAS ± VSWING. The very fast conversion time of the
AD7769 ADC allows sequential conversion of these quadrature
signals without introducing significant phase delay errors. These
converted signals provide the servo microcontroller with position and track crossing information from which velocity information can be derived. In optical disk drives, analogous servo
signals can be derived from the quad photodiode detector to
provide position and focus information for the microcontroller.
The two DACs in the AD7769 accept servo data from the
microcontroller to position the head assembly. The DACs provide positive-only output signals of the form VBIAS ± VSWING,
which are ideal for driving voice coil motors. In magnetic disk
drives, a single voice coil motor is used to position the head assembly and one DAC is usually sufficient to drive the motor in
both the seek and track modes. In the seek mode, the DAC can
be used to generate directly the desired analog velocity trajectory which the head must travel in order to achieve minimum
access times. Alternatively, the DAC can generate a servo error
value (computed by the microcontroller) between the actual
head velocity and the desired head velocity. In the track mode,
the DAC can be used to provide a position error signal to keep
the head over the track or to detent the head off track, for such
purposes as thermal compensation and soft error retries. The
second DAC in the AD7769 may be employed in this fine positioning loop. Alternatively, the second DAC can be used to control the speed of the spindle motor via a pulse width modulator.
In optical disk drives two voice coil motors are used, requiring
both DACs of the AD7769–one for the focus servo loop and
one for the radial positioning servo loop.
A typical servo control loop using the AD7769 is shown in Figure 23. In this dedicated servo drive, the servo demodulator converts the servo information bit patterns from the disk into the
standard N and Q (normal and quadrature) servo signals. The
voice coil motor current, IL, is bidirectional and is supplied by the
power transconductance amplifier. One input to this amplifier is
held at VBIAS (DAC), while the other input is driven from a DAC
output, VOUT A/B. Typical input/output waveforms for this power
stage are shown in Figure 24. The transconductance, GO, of the
power stage is determined by external sense resistors.
REV. A
Figure 23. Typical Dedicated Servo Control Loop Using
the AD7769
Figure 24. Typical Relationship Between Input Voltage and
Output Current for Transconductance Amplifier
–13–
AD7769
Increased Resolution DAC Output
Since both VBIAS (DAC) and VSWING (DAC) are common to
both output channels, the full-scale output voltages of both
channels are nominally identical. However, by adding an external op amp and scaling resistors, it is possible to attenuate the
full-scale output voltage of one (or both) of the DAC outputs to
effectively increase the output voltage resolution. Figure 25
shows channel A being attenuated using a resistor scaling of
10:1. The attenuated output voltage, VOUTA', is
VOUTA' = VBIAS + (VSWING/10)(2DA–1).
DAC A can be programmed to produce an interpolation function between the 8-bit steps of DAC B to allow, for example,
very smooth velocity profile waveforms to be generated.
Servo Offset Facility
Most dedicated servo disk drives offer an offset facility whereby
some small voltage is injected into the track-following loop. The
purpose of the offset is to move the head to the right or left of its
current on-track position to permit reading of off-track data.
The circuit is shown in Figure 27. With the 10:1 resistor scaling
used in the circuit the output voltage, VOUT, is
VOUT = VPE + (VSWING/10) (2DA–1).
The output voltage of Channel B remains at
VOUTB = VBIAS + VSWING (2DB–1).
DA and DB are fractional representations of the DAC input
codes, e.g., DA = NA/256 and DB = NB/256. For example, with a
VSWING voltage level of 2 V, the Channel B output span is 4 V
with an LSB size of 15.6 mV and (attenuated) Channel A output span is 400 mV with an LSB size of 1.56 mV. Changing the
resistor scaling in Figure 25 obviously changes the attenuated
full-scale output.
Figure 27. Servo Offset Facility
Figure 25. Increasing the DAC Output Voltage Resolution
A single change to the circuit Figure 25 allows the two DAC
outputs to be combined to provide a single analog output with
resolution beyond the standard 8-bits. Figure 26 shows the rearranged circuit. The composite output, VOUT, is
VOUT = VOUTB + (VSWING/10)(2DA–1)
or
VOUT = VBIAS + VSWING (2DB–1) + (VSWING/10) (2DA–1).
With no offset added, VOUT = VPE, where VPE is the position
error voltage which the servo loop normally drives to its zero
level, VBIAS. When an offset voltage is supplied by DAC A, the
action of the servo is to move the head away from its current
on-track position until the position error voltage is equal and
opposite to the offset voltage. The position of the head about
the track centre is thus programmable.
Programmable Full-Scale Range
The output voltage span of both DACs is determined by the
VSWING (DAC) voltage level. This is normally supplied from
some fixed voltage source. However, it is possible to use one of
the DAC channels to generate a programmable VSWING voltage
level. The remaining channel will thus have a full-scale range
and LSB size which is software programmable. This circuit is
shown in Figure 28 where VOUTB is used in an implicit feedback
loop to generate a programmable swing voltage, VSWING (DAC),
for the AD7769 from an external fixed input swing voltage,
VSWING. Using the 5:1 resistor scaling shown in Figure 28, the
expression for the AD7669 input swing voltage is
VSWING (DAC) =
V SWING
.
(2DB –1)
1–
5
Figure 26. Combined VOUTA, VOUTB Circuit
–14–
REV. A
AD7769
Figure 28. Generating a Software Programmable VSWING
(DAC)
For example, with a fixed input swing voltage of 2.5 V, the programmable span via DAC B is as follows:
DB = 0:
Figure 29. Typical Closed-Loop Microstepping Circuit
with the AD7769
VSWING (DAC) = 2.08
DB = 1/2: VSWING (DAC) = 2.5 V = VSWING
DB ≈ 1:
VSWING (DAC) = 3.125 V
The AD7769 is specified for a VSWING (DAC) voltage range
from 2 V to 3 V, although in practice this range can be extended
while still maintaining monotonic operation.
Closed Loop Microstepping
Microstepping is a popular technique in low density disk drives
(both floppy and hard disk) that allows higher positional resolution of the disk drive head over that obtainable from a full-step
driven stepper motor. Typically, a two-phase stepper motor has
its phase currents driven with a sine-cosine relationship. These
cosinusoidal signals are generated by two DACs driven with the
appropriate data. The resolution of the DACs determines the
number of microsteps into which each full step can be divided.
For example, with a 1.8° full-step motor and a 4-bit DAC, a
microstep size of 0.11° (1.8°/2n) is obtainable.
The microstepping technique improves the positioning resolution possible in any control application. However, the positional
accuracy can be significantly worse than that offered by the original full-step accuracy specification due to load torque effects.
To ensure that the increased resolution is usable, it is therefore
necessary to use a closed-loop system where the position of the
disk drive head (or motor) is monitored. The closed-loop system
allows an error between the desired position and the actual position to be monitored and corrected. The correction is achieved
by adjusting the ratio of the phase currents in the motor windings until the required head position is reached.
The AD7769 is ideally suited for the closed-loop microstepping
technique with its dual DACs for positioning the disk drive
head and dual channel ADC for monitoring the position of the
head. A typical circuit for a closed-loop microstepping system is
shown in Figure 29. The DAC waveforms are shown in Figure
30 along with the direction information of clockwise rotation
supplied by the controller.
REV. A
Figure 30. Typical Control Waveforms for the Microstepping Circuit of Figure 29
A typical transducer would be a moire-fringe transducer which
consists of two gratings, one fixed and one moveable. The relative positions of these two gratings will modulate the amount of
light from a LED which can pass through. In order to derive
head direction information the stationary grating has two sets of
bars, with a 90° phase relationship, and two photo-transistors.
The quadrature sinusoidal output waveforms (N & Q) can be
converted directly by the AD7769.
–15–
AD7769
Multichannel Expansion
C1315a–0–6/97
In some applications, more than two analog input channels are
required to be converted by the ADC. Figure 31 shows a circuit
configuration for such an application. The ADG528A is a
latched, B-channel analog multiplexer that is ideally suited for
this application since it is specified for single supply operation
(+12 V ± 10%).
The CS, ADC/DAC and WR inputs of the AD7769 are gated to
drive the WR input of the ADG528A. The multiplexer input
signal is selected on the falling edge of the WR pulse while the
signal is latched on the rising edge. Also, on the rising edge of
WR, the AD7769 ADC starts conversion. Therefore, the output
signal of the multiplexer must have settled to within 8-bits over
the duration of the WR pulse (see ADC Conversion Cycle section for details). The tON (WR) and settling time of the
ADG528A thus determines the width of the WR pulse.
Figure 31. Multichannel Inputs
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Plastic DIP
(N-28)
PRINTED IN U.S.A.
28-Lead Plastic Leaded Chip Carrier
(P-28A)
–16–
REV. A