DRV8844 www.ti.com SLVSBA2 – JULY 2012 QUAD 1/2-H-BRIDGE DRIVER IC Check for Samples: DRV8844 FEATURES 1 • 2 • • • • Quad 1/2-H-Bridge DC Motor Driver – Can Drive Four Solenoids, Two DC Motors, One Stepper Motor, or Other Loads – Full Individual Half Bridge Control – Low MOSFET On-Resistance 2.5-A Maximum Drive Current at 24 V, 25°C Floating Input Buffers Allow Dual (Bipolar) Supplies (up to ±24 V) Built-In 3.3-V, 10-mA LDO Regulator Industry Standard IN/IN Digital Control Interface • • 8-V to 60-V Operating Supply Voltage Range Thermally Enhanced Surface Mount Package APPLICATIONS • • • • • Textile Machines Office Automation Machines Gaming Machines Factory Automation Robotics DESCRIPTION The DRV8844 provides four individually controllable 1/2-H-bridge drivers. It can be used to drive two DC motors, one stepper motor, four solenoids, or other loads. The output driver channel for each channel consists of Nchannel power MOSFET’s configured in a 1/2-H-bridge configuration. The DRV8844 can supply up to 2.5-A peak or 1.75-A RMS output current per channel (with proper PCB heatsinking at 24 V and 25°C) per H-bridge. Separate inputs to independently control each 1/2-H-bridge are provided. To allow operation with split supplies, the logic inputs and nFAULT output are referenced to a separate floating ground pin. Internal shutdown functions are provided for over current protection, short circuit protection, under voltage lockout and overtemperature. The DRV8844 is available in a 28-pin HTSSOP package with PowerPAD™ (Eco-friendly: RoHS & no Sb/Br). ORDERING INFORMATION (1) TA –40°C to 85°C (1) (2) ORDERABLE PART NUMBER PACKAGE (2) PowerPAD™ (HTSSOP) - PWP Reel of 2000 DRV8844PWPR Tube of 50 DRV8844PWP TOP-SIDE MARKING DRV8844 For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated DRV8844 SLVSBA2 – JULY 2012 www.ti.com DEVICE INFORMATION Functional Block Diagram VM Internal Reference & Regs VM Int. VCC CP1 LS Gate Drive 0.01uF Charge Pump V3P3OUT CP2 VM VCP Thermal Shut down 0.1uF HS Gate Drive nFAULT LGND VM IN1 VM EN1 VM IN2 VM 10uF EN2 OUT1 Control Logic IN3 EN3 Input Buffers OUT2 Output Stages IN4 EN4 VNEG OUT3 nRESET OUT4 nSLEEP VNEG LGND VNEG 2 VNEG Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8844 DRV8844 www.ti.com SLVSBA2 – JULY 2012 Table 1. TERMINAL FUNCTIONS NAME PIN I/O (1) EXTERNAL COMPONENTS OR CONNECTIONS DESCRIPTION POWER AND GROUND VNEG 6, 9, 14, 28, PPAD - Negative power supply (dual supplies) or ground (single supply) LGND 19 I Logic input reference ground Connect to logic ground. This may be any voltage between VNEG and VM - 8 V. 4, 11 - Main power supply Connect to motor supply (8 V - 60 V). Both pins must be connected to same supply. Bypass to VNEG with a 10-µF (minimum) capacitor. V3P3OUT 15 O 3.3-V regulator output Bypass to VNEG with a 0.47-μF 6.3-V ceramic capacitor. Can be used to supply VREF. CP1 1 IO Charge pump flying capacitor CP2 2 IO Charge pump flying capacitor VCP 3 IO High-side gate drive voltage Connect a 0.1-μF 16-V ceramic capacitor to VM. IN1 27 I Channel 1 input Logic input controls state of OUT1. Internal pulldown. EN1 26 I Channel 1 enable Logic high enables OUT1. Internal pulldown. IN2 25 I Channel 2 input Logic input controls state of OUT2. Internal pulldown. EN2 24 I Channel 2 enable Logic high enables OUT2. Internal pulldown. IN3 23 I Channel 3 input Logic input controls state of OUT3. Internal pulldown. EN3 22 I Channel 3 enable Logic high enables OUT3. Internal pulldown. IN4 21 I Channel 4 input Logic input controls state of OUT4. Internal pulldown. EN4 20 I Channel 4 enable Logic high enables OUT4. Internal pulldown. nRESET 16 I Reset input Active-low reset input initializes internal logic and disables the H-bridge outputs. Internal pulldown. nSLEEP 17 I Sleep mode input Logic high to enable device, logic low to enter low-power sleep mode. Internal pulldown. 18 OD Fault Logic low when in fault condition (overtemp, overcurrent, UVLO). Open-drain output. OUT1 5 O Output 1 OUT2 7 O Output 2 OUT3 10 O Output 3 OUT4 8 O Output 4 12, 13 - No connect VM Connect a 0.01-μF 100-V capacitor between CP1 and CP2. CONTROL STATUS nFAULT OUTPUT Connect to loads. NO CONNECT NC (1) No connection to these pins Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8844 3 DRV8844 SLVSBA2 – JULY 2012 www.ti.com CP1 CP2 VCP VM OUT1 VNEG OUT2 OUT3 VNEG OUT4 VM NC NC VNEG 1 2 3 4 5 6 7 GND (PPAD) 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VNEG IN1 EN1 IN2 EN2 IN3 EN3 IN4 EN4 LGND nFAULT nSLEEP nRESET V3P3OUT ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range, all voltages relative to VNEG terminal (unless otherwise noted) VM Power supply voltage range (1) (2) VALUE UNIT –0.3 to 65 V –0.5 to VM - 8 V LGND - 0.5 to LGND + 7 V Peak motor drive output current, t < 1 μS Internally limited A Continuous motor drive output current (3) 2.5 A Logic ground voltage range (LGND) Digital pin voltage range TJ Operating virtual junction temperature range –40 to 150 °C Tstg Storage temperature range –60 to 150 °C (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to VNEG terminal, unless otherwise specified. Power dissipation and thermal limits must be observed. THERMAL INFORMATION DRV8844 THERMAL METRIC (1) PWP UNITS 16 PINS θJA Junction-to-ambient thermal resistance (2) 31.6 θJCtop Junction-to-case (top) thermal resistance (3) 15.9 θJB Junction-to-board thermal resistance (4) 5.6 (5) ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter (6) 5.5 θJCbot Junction-to-case (bottom) thermal resistance (7) 1.4 (1) (2) (3) (4) (5) (6) (7) 4 0.2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8844 DRV8844 www.ti.com SLVSBA2 – JULY 2012 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range, all voltages relative to VNEG terminal (unless otherwise noted) MIN VM Motor power supply voltage range IV3P3 V3P3OUT load current (1) (1) NOM MAX UNIT 8 60 V 0 10 mA All VM pins must be connected to the same supply voltage. ELECTRICAL CHARACTERISTICS TA = 25°C, over operating free-air temperature range, all voltages relative to VNEG terminal (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1 5 mA POWER SUPPLIES IVM VM operating supply current VM = 24 V, fPWM < 50 kHz IVMQ VM sleep mode supply current VM = 24 V 500 800 μA VUVLO VM undervoltage lockout voltage VM rising 6.3 8 V 3.3 3.52 V V3P3OUT REGULATOR V3P3 V3P3OUT voltage IOUT = 0 to 1 mA 3.18 LOGIC-LEVEL INPUTS VIL Input low voltage VIH Input high voltage VHYS Input hysteresis IIL Input low current VIN = LGND IIH Input high current VIN = LGND + 3.3 V RPD Internal pulldown resistance LGND + 0.6 LGND + 0.7 V LGND + 2.2 5.25 V 50 600 mV –5 5 μA 100 μA 100 kΩ nFAULT OUTPUT (OPEN-DRAIN OUTPUT) VOL Output low voltage IO = 5 mA IOH Output high leakage current VO = LGND + 3.3 V LGND + 0.5 V 1 μA H-BRIDGE FETS HS FET on resistance RDS(ON) LS FET on resistance IOFF VM = 24 V, IO = 1 A, TJ = 25°C 0.24 VM = 24 V, IO = 1 A, TJ = 85°C 0.29 VM = 24 V, IO = 1 A, TJ = 25°C 0.24 VM = 24 V, IO = 1 A, TJ = 85°C Off-state leakage current 0.29 –2 0.39 Ω 0.39 2 μA PROTECTION CIRCUITS IOCP Overcurrent protection trip level tDEAD Output dead time tOCP Overcurrent protection deglitch time TTSD Thermal shutdown temperature 3 Die temperature 150 A 90 ns 5 µs 160 180 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8844 °C 5 DRV8844 SLVSBA2 – JULY 2012 www.ti.com SWITCHING CHARACTERISTICS (1) over operating free-air temperature range (unless otherwise noted) (1) NUMBER PARAMETER 1 t1 2 t2 3 TEST CONDITIONS MIN MAX UNIT Delay time, ENx high to OUTx high, INx = 1 130 330 ns Delay time, ENx low to OUTx low, INx = 1 275 475 ns t3 Delay time, ENx high to OUTx low, INx = 0 100 300 ns 4 t4 Delay time, ENx low to OUTx high, INx = 0 200 400 ns 5 t5 Delay time, INx high to OUTx high 300 500 ns 6 t6 Delay time, INx low to OUTx low 275 475 ns 7 tR Output rise time, resistive load to VNEG 30 150 ns 8 tF Output fall time, resistive load to VNEG 30 150 ns Not production tested – specified by design ENx 50% 50% 1 OUTx 3 2 50% 50% OUTx INx = 1, resistive load to GND INx 50% 5 50% 80% 80% OUTx 6 50% 4 INx = 0, resistive load to VM 50% 50% 50% 50% ENx 20% 50% 20% OUTx 7 8 ENx = 1 resistive load to GND Figure 1. DRV8844 Switching Characteristics 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8844 DRV8844 www.ti.com SLVSBA2 – JULY 2012 FUNCTIONAL DESCRIPTION Output Stage The DRV8844 contains four 1/2-H-bridge drivers using N-channel MOSFETs. A block diagram of the output circuitry is shown in Figure 2. VM VM VM Predrive IN1 EN1 OUT 1 OCP IN2 EN2 IN3 EN3 Predrive IN4 EN4 OUT2 OCP Logic Predrive OUT 3 OCP Predrive OUT4 OCP Figure 2. Motor Control Circuitry The output pins are driven between VM and VNEG. VNEG is normaly ground for single supply applications, and a negative voltage for dual supply applications. Note that there are multiple VM motor power supply pins. All VM pins must be connected together to the motor supply voltage. Logic Inputs The logic inputs and nFAULT output are referenced to the LGND pin. This pin would be connected to the logic ground of the source of the logic signals (e.g., microcontroller). This allows LGND to be at a different voltage than VNEG; for example, you could drive a load by with bipolar power supplies by driving VM with +24 V and VNEG with -24 V, and connect LGND to 0 V (ground). Bridge Control The INx input pins directly control the state (high or low) of the OUTx outputs; the ENx input pins enable or disable the OUTx driver. Table 2 shows the logic. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8844 7 DRV8844 SLVSBA2 – JULY 2012 www.ti.com Table 2. H-Bridge Logic INx ENx OUTx X 0 Z 0 1 L 1 1 H The inputs can also be used for PWM control of, for example, the speed of a DC motor. When controlling a winding with PWM, when the drive current is interrupted, the inductive nature of the motor requires that the current must continue to flow. This is called recirculation current. To handle this recirculation current, the Hbridge can operate in two different states, fast decay or slow decay. In fast decay mode, the H-bridge is disabled and recirculation current flows through the body diodes; in slow decay, the motor winding is shorted. To PWM using fast decay, the PWM signal is applied to the ENx pin; to use slow decay, the PWM signal is applied to the INx pin. Table 3 is an example of driving a DC motor using OUT1 and OUT2 as an H-bridge: Table 3. PWM Function IN1 EN1 IN2 EN2 FUNCTION PWM 0 1 0 1 Forward PWM, slow decay 1 PWM 1 Forward PWM, slow decay 1 PWM 0 PWM Reverse PWM, fast decay 0 PWM 1 PWM Reverse PWM, fast decay The drawings below show the current paths in different drive and decay modes: VM VM 1 Forward drive 1 OUT2 OUT1 1 Reverse drive 1 2 Fast decay 3 Slow decay 2 Fast decay OUT1 OUT2 2 2 3 3 FORWARD 3 Slow decay REVERSE Figure 3. Current Paths Charge Pump Since the output stages use N-channel FETs, a gate drive voltage higher than the VM power supply is needed to fully enhance the high-side FETs. The DRV8844 integrates a charge pump circuit that generates a voltage above the VM supply for this purpose. The charge pump requires two external capacitors for operation. Refer to the block diagram and pin descriptions for details on these capacitors (value, connection, etc.). The charge pump is shut down when SLEEPn is active low. 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8844 DRV8844 www.ti.com SLVSBA2 – JULY 2012 VM VM 10uF CP1 0.01uF 100V CP2 Charge Pump VCP 0.1uF 16V To pre-drivers Figure 4. Charge Pump nRESET and nSLEEP Operation The nRESET pin, when driven active low, resets the internal logic. It also disables the H-bridge drivers. All inputs are ignored while nRESET is active. Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the gate drive charge pump is stopped and all internal clocks are stopped. In this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time (approximately 1 ms) needs to pass before the motor driver becomes fully operational. Note that nRESET and nSLEEP have internal pulldown resistors of approximately 100 kΩ. These signals need to be driven to logic high for device operation. The V3P3OUT LDO regulator remains operational in sleep mode. Protection Circuits The DRV8844 is fully protected against undervoltage, overcurrent and overtemperature events. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP deglitch time, the channel experiencing the overcurrent will be disabled and the nFAULT pin will be driven low. The driver will remain off until either RESET is asserted or VM power is cycled. Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Thermal Shutdown (TSD) If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. Once the die temperature has fallen to a safe level operation will automatically resume. Undervoltage Lockout (UVLO) If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all outputs will be disabled, internal logic will be reset, and the nFAULT pin will be driven low. Operation will resume when VM rises above the UVLO threshold. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8844 9 DRV8844 SLVSBA2 – JULY 2012 www.ti.com THERMAL INFORMATION Thermal Protection The SDRV8844 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately 150°C, the device will be disabled until the temperature drops to a safe level. Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. Power Dissipation Power dissipation in the SDRV8844 is dominated by the power dissipated in the output FET resistance, or RDS(ON). Average power dissipation of each H-bridge when running a DC motor can be roughly estimated by Equation 1. P = 2 · RDS(ON) · (IOUT)2 (1) where P is the power dissipation of one H-bridge, RDS(ON) is the resistance of each FET, and IOUT is the RMS output current being applied to each winding. IOUT is equal to the average current drawn by the DC motor. Note that at start-up and fault conditions this current is much higher than normal running current; these peak currents and their duration also need to be taken into consideration. The factor of 2 comes from the fact that at any instant two FETs are conducting winding current (one high-side and one low-side). The total device dissipation will be the power dissipated in each of the two H-bridges added together. The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and heatsinking. Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must be taken into consideration when sizing the heatsink. Heatsinking The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers. For details about how to design the PCB, refer to TI application report SLMA002, " PowerPAD™ Thermally Enhanced Package" and TI application brief SLMA004, " PowerPAD™ Made Easy", available at www.ti.com. In general, the more copper area that can be provided, the more power can be dissipated. 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8844 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) DRV8844PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV8844PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DRV8844PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 28 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 16.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.2 1.8 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8844PWPR HTSSOP PWP 28 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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