AD AD5204BR10-REEL 4-/6-channel digital potentiometer Datasheet

4-/6-Channel
Digital Potentiometers
AD5204/AD5206
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
AD5204
CS
CLK
EN
SDO
DO
A2
A1
A0
D7
RDAC
LATCH
1
D0
The AD5204/AD5206 provide 4-/6-channel, 256-position
digitally controlled variable resistor (VR) devices. These
devices perform the same electronic adjustment function as a
potentiometer or variable resistor. Each channel of the AD5204/
AD5206 contains a fixed resistor with a wiper contact that taps
the fixed resistor value at a point determined by a digital code
loaded into the SPI-compatible serial-input register. The
resistance between the wiper and either endpoint of the fixed
resistor varies linearly with respect to the digital code transferred
into the VR latch. The variable resistor offers a completely
programmable value of resistance between the A terminal and
the wiper or the B terminal and the wiper. The fixed A-to-B
terminal resistance of 10 kΩ, 50 kΩ, or 100 kΩ has a nominal
temperature coefficient of 700 ppm/°C.
Each VR has its own VR latch that holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register that is loaded from a standard
3-wire serial-input digital interface. Eleven data bits make up
the data-word clocked into the serial input register. The first
three bits are decoded to determine which VR latch is loaded
with the last eight bits of the data-word when the CS strobe is
returned to logic high. A serial data output pin at the opposite
end of the serial register (AD5204 only) allows simple daisy
chaining in multiple VR applications without requiring
additional external decoding logic.
B1
R
A4
D7
D0
DI
8
GND
W4
RDAC
LATCH
4
B4
R
VSS
D0
POWER-ON
PRESET
SHDN
PR
06884-001
SDI
GENERAL DESCRIPTION
W1
SER
REG
APPLICATIONS
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, time constants
Line impedance matching
A1
D7
ADDR
DEC
VDD
Figure 1.
AD5206
CS
CLK
EN
A2
A1
A0
D7
A1
D7
RDAC
LATCH
1
ADDR
DEC
D0
VDD
W1
B1
R
SER
REG
A6
D7
SDI
DI
RDAC
LATCH
6
D0
8
GND
D0
POWER-ON
PRESET
W6
B6
R
VSS
06884-002
256 positions
Multiple independently programmable channels
AD5204—4-channel
AD5206—6-channel
Potentiometer replacement
Terminal resistance of 10 kΩ, 50 kΩ, 100 kΩ
3-wire SPI-compatible serial data input
+2.7 V to +5.5 V single-supply operation; ±2.7 V dual-supply
operation
Power-on midscale preset
Figure 2.
An optional reset (PR) pin forces all the AD5204 wipers to the
midscale position by loading 0x80 into the VR latch.
The AD5204/AD5206 are available in the 24-lead surfacemount SOIC, TSSOP, and PDIP packages. The AD5204 is also
available in a 32-lead, 5 mm × 5 mm LFCSP package. All parts are
guaranteed to operate over the extended industrial temperature
range of −40°C to +85°C. For additional single-, dual-, and quadchannel devices, see the AD8400/AD8402/AD8403 data sheets.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
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Fax: 781.461.3113 ©1999–2010 Analog Devices, Inc. All rights reserved.
AD5204/AD5206
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ........................................... 10
Applications....................................................................................... 1
Operation......................................................................................... 12
General Description ......................................................................... 1
Programming the Variable Resistor............................................. 13
Functional Block Diagrams............................................................. 1
Rheostat Operation .................................................................... 13
Revision History ............................................................................... 2
Programming the Potentiometer Divider ................................... 14
Specifications..................................................................................... 3
Voltage Output Operation......................................................... 14
Electrical Characteristics............................................................. 3
Digital Interfacing .......................................................................... 15
Timing Diagrams.............................................................................. 5
Test Circuits..................................................................................... 16
Absolute Maximum Ratings............................................................ 6
Outline Dimensions ....................................................................... 17
ESD Caution.................................................................................. 6
Ordering Guide .......................................................................... 18
Pin Configurations and Function Descriptions ........................... 7
REVISION HISTORY
7/10—Rev. B to Rev. C
Changes to Digital Input and Output Voltage to GND
Parameter, Table 2............................................................................. 6
Changes to Ordering Guide .......................................................... 18
5/09—Rev. A to Rev. B
Changes to Table 1............................................................................ 3
Changes to Absolute Maximum Ratings ....................................... 6
Changes to Figure 7.......................................................................... 8
Changes to Table 4............................................................................ 8
11/07—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Added 32-Lead LFCSP Package .......................................Universal
Changed RBA to RAB ............................................................Universal
Changes to Absolute Maximum Ratings........................................6
Changes to Operation Section...................................................... 12
Updated Outline Dimensions....................................................... 17
Changes to Ordering Guide .......................................................... 18
9/99—Revision 0: Initial Version
Rev. C | Page 2 of 20
AD5204/AD5206
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 5 V ± 10% or 3 V ± 10%, VSS = 0 V, VA = VDD, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS RHEOSTAT MODE 2
Resistor Differential NL 3
Resistor Nonlinearity Error3
Nominal Resistor Tolerance 4
Resistance Temperature Coefficient
Nominal Resistance Match
Wiper Resistance
DC CHARACTERISTICS POTENTIOMETER
DIVIDER MODE2
Resolution
Differential Nonlinearity 5
Integral Nonlinearity5
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range 6
Capacitance 7 Ax, Bx
Capacitance7 Wx
Shutdown Current 8
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Input Current
Input Capacitance7
POWER SUPPLIES
Power Single-Supply Range
Power Dual-Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation 9
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS7, 10
Bandwidth −3 dB
Total Harmonic Distortion
VW Settling Time (10 kΩ/50 kΩ/100 kΩ)
Resistor Noise Voltage
Symbol
Conditions
Min
Typ 1
Max
Unit
R-DNL
R-INL
ΔRAB
ΔRAB/ΔT
ΔR/RAB
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
VAB = VDD, wiper = no connect
Channel 1 to Channel 2, Channel 3, and
Channel 4, or to Channel 5 and Channel 6;
VAB = VDD
IW = 1 V/R, VDD = 5 V
−1
−2
−30
±0.25
±0.5
+1
+2
+30
RW
N
DNL
INL
ΔVW/ΔT
VWFSE
VWZSE
VA, VB, VW
CA, CB
CW
IA_SD
ICM
8
−1
−2
Code = 0x40
Code = 0x7F
Code = 0x00
−2
0
700
0.25
1.5
LSB
LSB
%
ppm/°C
%
50
100
Ω
±0.25
±0.5
15
−1
1
+1
+2
VSS
f = 1 MHz, measured to GND, code = 0x40
f = 1 MHz, measured to GND, code = 0x40
VDD
45
60
0.01
1
VA = VB = VW = 0, VDD = +2.7 V, VSS = −2.5 V
0
2
VIH
VIL
VOH
VOL
IIL
CIL
VDD = 5 V/3 V
VDD = 5 V/3 V
RPULL–UP = 1 kΩ to 5 V
IOL = 1.6 mA, VLOGIC = 5 V
VIN = 0 V or 5 V
VDD range
VDD/VSS range
IDD
ISS
PDISS
PSS
VSS = 0 V
VIH = 5 V or VIL = 0 V
VSS = −2.5 V, VDD = +2.7 V
VIH = 5 V or VIL = 0 V
ΔVDD = 5 V ± 10%
12
12
BW_10K
BW_50K
BW_100K
THDW
tS
eN_WB
RAB = 10 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
VA = 1.414 V rms, VB = 0 V dc, f = 1 kHz
VA = 5 V, VB = 0 V, ±1 LSB error band
RWB = 5 kΩ, f = 1 kHz, PR = 0
721
137
69
0.004
2/9/18
9
5
2.4/2.1
0.8/0.6
4.9
0.4
±1
5
Rev. C | Page 3 of 20
2.7
±2.3
0.0002
5.5
±2.7
60
60
0.3
0.005
Bits
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
μA
nA
V
V
V
V
μA
pF
V
V
μA
μA
mW
%/%
kHz
kHz
kHz
%
μs
nV/√Hz
AD5204/AD5206
Parameter
INTERFACE TIMING CHARACTERISTICS7, 11, 12
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK-to-SDO Propagation Delay 13
CS Setup Time
CS High Pulse Width
Reset Pulse Width
CLK Fall to CS Fall Setup
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
Symbol
Conditions
Min
tCH, tCL
tDS
tDH
tPD
tCSS
tCSW
tRS
tCSH0
tCSH1
tCS1
Clock level high or low
20
5
5
1
15
40
90
0
0
10
RL = 2 kΩ , CL < 20 pF
1
Typ 1
Max
150
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Typicals represent average readings at 25°C and VDD = 5 V.
Applies to all VRs.
3
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from the ideal position between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 28.
IW = VDD/R for both VDD = 3 V and VDD = 5 V.
4
VAB = VDD, wiper (VW) = no connect.
5
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic at operating conditions. See the test circuit in Figure 27.
6
Resistor Terminal A, Terminal B, and Wiper W have no limitations on polarity with respect to each other.
7
Guaranteed by design and not subject to production test.
8
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
9
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use VDD = 5 V.
11
Applies to all parts.
12
See the timing diagrams (Figure 3 to Figure 5) for the location of the measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V)
and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 5 V.
13
The propagation delay depends on the values of VDD, RL, and CL (see the Operation section).
2
Rev. C | Page 4 of 20
AD5204/AD5206
TIMING DIAGRAMS
SDI
1
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0
CLK
1
0
CS
RDAC LATCH LOAD
1
0
06884-003
VOUT
VDD
0V
Figure 3. Timing Diagram
SDI
(DATA IN)
SDO
(DATA OUT)
1
Ax OR Dx
Ax OR Dx
0
tDH
tDS
1
Ax OR Dx
Ax OR Dx
0
tPD_MAX
tCH
1
tCS1
CLK
0
CS
tCSH0
tCSS
1
tCSH1
tCL
tCSW
0
tS
0V
Figure 4. Detailed Timing Diagram
1
PR
VOUT
tRS
0
VDD
0V
tS
±1 LSB
±1 LSB ERROR BAND
Figure 5. AD5204 Preset Timing Diagram
Rev. C | Page 5 of 20
06884-004
±1 LSB
±1 LSB ERROR BAND
06884-005
VOUT
VDD
AD5204/AD5206
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 2.
Parameter
VDD to GND
VSS to GND
VDD to VSS
VA, VB, VW to GND
IA, IB, IW
Pulsed1
Continuous
10 kΩ End-to-End Resistance
50 kΩ and 100 kΩ End-to-End
Resistance
Digital Input and Output Voltage
to GND
Operating Temperature Range
Maximum Junction Temperature
(TJ max)
Storage Temperature
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Package Power Dissipation
Thermal Resistance, θJA2
PDIP (N-24-1)
SOIC (RW-24)
TSSOP (RU-24)
LFCSP (CP-32-3)
Rating
−0.3 V to +7 V
0 V to −7 V
7V
VSS, VDD
ESD CAUTION
±20 mA
±11 mA
±2.5 mA
−0.3 V to (VDD + 0.3 V) or 7 V
(whichever is less)
−40°C to +85°C
150°C
−65°C to +150°C
260°C
20 sec to 40 sec
(TJ max − TA)/θJA
63°C/W
52°C/W
50°C/W
32.5°C/W
1
Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Thermal resistance (JEDEC 4-layer (2S2P) board). Paddle soldered to board.
Rev. C | Page 6 of 20
AD5204/AD5206
NC
1
24
B4
NC
2
23
W4
GND
3
22
A4
CS
4
21
B2
PR
5
20
W2
VDD
6
19
A2
SHDN
7
18
A1
SDI
8
17
W1
CLK
9
16
B1
SDO 10
15
A3
VSS 11
14
W3
NC 12
13
B3
AD5204
TOP VIEW
(Not to Scale)
NC = NO CONNECT
06884-006
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 6. AD5204 SOIC/TSSOP/PDIP Pin Configuration
Table 3. AD5204 SOIC/TSSOP/PDIP Pin Function Descriptions
Pin No.
1, 2, 12
3
4
Name
NC
GND
CS
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
23
24
PR
VDD
SHDN
SDI
CLK
SDO
VSS
B3
W3
A3
B1
W1
A1
A2
W2
B2
A4
W4
B4
Description
Not Connected.
Ground.
Chip Select Input (Active Low). When CS returns high, data in the serial input register is decoded based on the address
bits, and then it is loaded into the target RDAC latch.
Preset to Midscale (Active Low). This pin sets the RDAC registers to 0x80.
Positive Power Supply. This pin is specified for operation at both 3 V and 5 V. It is the sum of |VDD| + |VSS| < 5.5 V.
Terminal A Open-Circuit Shutdown (Active Low Input). This pin controls VR 1 through VR 4.
Serial Data Input. Data is input MSB first.
Serial Clock Input. This pin is positive edge triggered.
Serial Data Output. This pin is an open-drain transistor and requires a pull-up resistor.
Negative Power Supply. This pin is specified for operation at both 0 V and −2.7 V. It is the sum of |VDD| + |VSS| < 5.5 V.
Terminal B RDAC 3.
Wiper RDAC 3. Address = 0102.
Terminal A RDAC 3.
Terminal B RDAC 1.
Wiper RDAC 1. Address = 0002.
Terminal A RDAC 1.
Terminal A RDAC 2.
Wiper RDAC 2. Address = 0012.
Terminal B RDAC 2.
Terminal A RDAC 4.
Wiper RDAC 4. Address = 0112.
Terminal B RDAC 4.
Rev. C | Page 7 of 20
GND
CS
VDD
PR
SHDN
SDI
CLK
SDO
AD5204/AD5206
32 31 30 29 28 27 26 25
24
NC
23
NC
22
NC
21
NC
20
B4
B3 6
19
W4
W3 7
18
A4
A3 8
17
NC
PIN 1
INDICATOR
NC 2
NC 3
AD5204
NC 4
TOP VIEW
(Not to Scale)
NC 5
B2
NC
W2
A2
A1
W1
10 11 12 13 14 15 16
B1
NC
9
NOTES
1. NC = NO CONNECT.
2. THE LFCSP PACKAGE HAS AN EXPOSED
PADDLE THAT SHOULD BE CONNECTED TO
GND AND THE ASSOCIATED PCB
GROUND PLATE.
06884-053
VSS 1
Figure 7. AD5204 LFCSP Pin Configuration
Table 4. AD5204 LFCSP Pin Function Descriptions
Pin No.
1
2 to 5, 9,
16, 17,
21 to 24
6
7
8
10
11
12
13
14
15
18
19
20
25
26
Name
VSS
NC
Description
Negative Power Supply. This pin is specified for operation at both 0 V and −2.7 V. It is the sum of |VDD| + |VSS| < 5.5 V.
Not Connected.
B3
W3
A3
B1
W1
A1
A2
W2
B2
A4
W4
B4
GND
CS
27
28
29
30
31
32
PR
VDD
SHDN
SDI
CLK
SDO
Terminal B RDAC 3.
Wiper RDAC 3. Address = 0102.
Terminal A RDAC 3.
Terminal B RDAC 1.
Wiper RDAC 1. Address = 0002.
Terminal A RDAC 1.
Terminal A RDAC 2.
Wiper RDAC 2. Address = 0012.
Terminal B RDAC 2.
Terminal A RDAC 4.
Wiper RDAC 4. Address = 0112.
Terminal B RDAC 4.
Ground.
Chip Select Input (Active Low). When CS returns high, data in the serial input register is decoded based on the address
bits, and then it is loaded into the target RDAC latch.
Preset to Midscale (Active Low). This pin sets the RDAC registers to 0x80.
Positive Power Supply. This pin is specified for operation at both 3 V and 5 V. It is the sum of |VDD| + |VSS| < 5.5 V.
Terminal A Open-Circuit Shutdown (Active Low Input). This pin controls VR 1 through VR 4.
Serial Data Input. Data is input MSB first.
Serial Clock Input. This pin is positive edge triggered.
Serial Data Output. This pin is an open-drain transistor and requires a pull-up resistor.
Rev. C | Page 8 of 20
A6
1
24
B4
W6
2
23
W4
B6
3
22
A4
GND
4
21
B2
CS
5
20
W2
VDD
6
19
A2
SDI
7
18
A1
CLK
8
17
W1
VSS
9
16
B1
B5 10
15
A3
W5 11
14
W3
A5 12
13
B3
AD5206
TOP VIEW
(Not to Scale)
NC = NO CONNECT
06884-019
AD5204/AD5206
Figure 8. AD5206 SOIC/TSSOP/PDIP Pin Configuration
Table 5. AD5206 Pin Function Descriptions
Pin No.
1
2
3
4
5
Name
A6
W6
B6
GND
CS
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDD
SDI
CLK
VSS
B5
W5
A5
B3
W3
A3
B1
W1
A1
A2
W2
B2
A4
W4
B4
Description
Terminal A RDAC 6.
Wiper RDAC 6. Address = 1012.
Terminal B RDAC 6.
Ground.
Chip Select Input (Active Low). When CS returns high, data in the serial input register is decoded based on the
address bits, and then it is loaded into the target RDAC latch.
Positive Power Supply. This pin is specified for operation at both 3 V and 5 V. It is the sum of |VDD| + |VSS| < 5.5 V.
Serial Data Input. Data is input MSB first.
Serial Clock Input. This pin is positive edge triggered.
Negative Power Supply. This pin is specified for operation at both 0 V and −2.7 V. It is the sum of |VDD| + |VSS| < 5.5 V.
Terminal B RDAC 5.
Wiper RDAC 5. Address = 1002.
Terminal A RDAC 5.
Terminal B RDAC 3.
Wiper RDAC 3. Address = 0102.
Terminal A RDAC 3.
Terminal B RDAC 1.
Wiper RDAC 1. Address = 0002.
Terminal A RDAC 1.
Terminal A RDAC 2.
Wiper RDAC 2. Address = 0012.
Terminal B RDAC 2.
Terminal A RDAC 4.
Wiper RDAC 4. Address = 0112.
Terminal B RDAC 4.
Rev. C | Page 9 of 20
AD5204/AD5206
TYPICAL PERFORMANCE CHARACTERISTICS
120
VDD/VSS = 2.7V/0V
100
NORMALIZED GAIN (dB)
SWITCH RESISTANCE (Ω)
110
90
80
70
VDD/VSS = 5.5V/0V
VDD/VSS = ±2.7V
60
10kΩ
0
VDD = ±2.7V
VSS = –2.7V
VA = 100mV rms
DATA = 0x80
–2
–4
50kΩ
VA
100kΩ
OP42
50
0
1.0
2.0
3.0
4.0
5.0
6.0
COMMON MODE (V)
1k
0
–6.00
–6
–6.01
–12
–18
–6.02
–6.03
–6.06
GAIN (dB)
GAIN (dB)
10kΩ
–6.05
50kΩ
100kΩ
–24
–30
VA
–48
OP42
–54
VB = 0V
1k
10k
100k
FREQUENCY (Hz)
–60
1k
06884-008
–6.09
100
1M
1M
DATA = 0x80
DATA = 0x40
DATA = 0x20
DATA = 0x10
DATA = 0x08
DATA = 0x04
–36
–42
–6.07
–6.08
1M
Figure 12. −3 dB Bandwidth vs. Terminal Resistance,
±2.7 V Dual-Supply Operation
–5.99
VDD = +2.7V
VSS = –2.7V
VA = 100mV rms
DATA = 0x80
TA = 25°C
100k
FREQUENCY (Hz)
Figure 9. Incremental On Resistance of the Wiper vs. Voltage
–6.04
10k
06884-010
–1.0
06884-011
–2.0
06884-012
30
–3.0
06884-007
40
DATA = 0x02
DATA = 0x01
VDD = +2.7V
VSS = –2.7V
VA = 100mV rms
TA = 25°C
VA
OP42
10k
100k
FREQUENCY (Hz)
Figure 10. Gain Flatness vs. Frequency
Figure 13. Bandwidth vs. Code, 10 kΩ Version
0
–6
10kΩ
VDD = 2.7V
VSS = 0V
VA = 100mV rms
DATA = 0x80
TA = 25°C
2.7V
–2
–4
–18
GAIN (dB)
0
50kΩ
100kΩ
OP42
–30
–36
–48
+1.5V
1k
–24
–42
–54
10k
100k
FREQUENCY (Hz)
1M
06884-009
NORMALIZED GAIN (dB)
–12
Figure 11. −3 dB Bandwidth vs. Terminal Resistance,
2.7 V Single-Supply Operation
–60
1k
DATA = 0x80
DATA = 0x40
DATA = 0x20
DATA = 0x10
DATA = 0x08
DATA = 0x04
DATA = 0x02
DATA = 0x01
VDD = +2.7V
VSS = –2.7V
VA = 100mV rms
TA = 25°C
VA
OP42
10k
100k
FREQUENCY (Hz)
Figure 14. Bandwidth vs. Code, 50 kΩ Version
Rev. C | Page 10 of 20
AD5204/AD5206
0
8
DATA = 0x80
DATA = 0x40
–12
DATA = 0x10
–24
DATA = 0x08
–30
DATA = 0x04
–36
DATA = 0x02
–42
DATA = 0x01
–48
–54
–60
1k
VA
VDD = +2.7V
VSS = –2.7V
VA = 100mV rms
TA = 25°C
6
5
4
3
2
1
OP42
10k
100k
1M
FREQUENCY (Hz)
IDD, VDD/VSS = 5.5V/0V, DATA = 0x55
ISS, VDD/VSS = ±2.7V, DATA = 0x55
IDD, VDD/VSS = 5V/0V, DATA = 0xFF
ISS, VDD/VSS = ±2.7V, DATA = 0xFF
IDD, VDD/VSS = 2.7V/0V, DATA = 0xFF
IDD, VDD/VSS = ±2.7V/0V, DATA = 0x55
0
10k
06884-013
GAIN (dB)
SUPPLY CURRENT (mA)
DATA = 0x20
–18
TA = 25°C
7
100k
1M
10M
FREQUENCY (Hz)
Figure 15. Bandwidth vs. Code, 100 kΩ Version
06884-016
–6
Figure 18. Supply Current vs. Clock Frequency
2.5
60
TA = 25°C
50
VSS = –3.0V ± 10%
40
1.5
SINGLE SUPPLY
VDD = VSS
PSRR (dB)
TRIP POINT (V)
2.0
DUAL SUPPLY
VSS = 0V
1.0
VDD = 5.0V ± 10%
30
VDD = 3.0V ± 10%
20
0.5
3
4
5
6
SUPPLY VOLTAGE VDD (V)
0
10
TA = 25°C
0.1
THD + NOISE (%)
IDD AT VDD/VSS = 5.5V/0V
1
IDD AT VDD/VSS = ±2.7V
0.01
100k
VDD = +2.7V
VSS = –2.7V
TA = 25°C
RAB = 10kΩ
NONINVERTING TEST CIRCUIT
0.001
0.01
INVERTING TEST CIRCUIT
IDD AT VDD/VSS = 2.7V/0V
0
1
2
3
4
5
INCREMENTAL INPUT LOGIC VOLTAGE (V)
6
06884-015
SUPPLY CURRENT (mA)
100k
Figure 19. Power Supply Rejection vs. Frequency
10
0.001
10k
1
ISS AT VDD/VSS = ±2.7V
0.1
1k
FREQUENCY (Hz)
Figure 16. Digital Input Trip Point vs. Supply Voltage
100
100
06884-017
2
06884-018
1
06884-014
0
10
Figure 17. Supply Current vs. Input Logic Voltage
0.0001
10
100
1k
10k
FREQUENCY (Hz)
Figure 20. Total Harmonic Distortion Plus Noise vs. Frequency
Rev. C | Page 11 of 20
AD5204/AD5206
OPERATION
connected to terminals Bx, resulting in only leakage currents
being consumed in the VR structure. In shutdown mode, the
VR latch settings are maintained so that the VR settings return
to their previous resistance values when the device is returned
to operational mode from power shutdown.
Table 6. Serial Data-Word Format
Address
B10 B9 B8
A2
A1 A0
MSB
LSB
210
28
B7
D7
MSB
27
B6
D6
B5
D5
Data
B4 B3
D4 D3
B2
D2
B1
D1
B0
D0
LSB
20
See Table 10 for the AD5204/AD5206 address assignments to
decode the location of the VR latch receiving the serial register
data in Bit B7 through Bit B0. The VR outputs can be changed
one at a time in random sequence. The AD5204 presets to
midscale by asserting the PR pin, simplifying fault condition
recovery at power up. Both parts have an internal power-on
preset that places the wiper in a preset midscale condition at
power on. In addition, the AD5204 contains a power shutdown pin
(SHDN) that places the RDAC in a zero power consumption
state, where terminals Ax are open circuited and wipers Wx are
Rev. C | Page 12 of 20
RS
SHDN
D7
D6
D5
D4
D3
D2
D1
D0
RDAC
LATCH
AND
DECODER
Ax
RS
RS
Wx
RS
Bx
06884-044
The AD5204 provides a 4-channel, 256-position digitally
controlled VR device, and the AD5206 provides a 6-channel,
256-position digitally controlled VR device. Changing the programmed VR settings is accomplished by clocking an 11-bit
serial data-word into the SDI pin. The format of this data-word
is three address bits, MSB first, followed by eight data bits, MSB
first. Table 6 provides the serial register data-word format.
Figure 21. AD5204/AD5206 Equivalent RDAC Circuit
AD5204/AD5206
PROGRAMMING THE VARIABLE RESISTOR
RHEOSTAT OPERATION
The nominal resistance of the RDAC between Terminal A and
Terminal B is available with values of 10 kΩ, 50 kΩ, and 100 kΩ.
The last digits of the part number determine the nominal
resistance value; for example, 10 kΩ = 10 and 100 kΩ = 100.
The nominal resistance (RAB) of the VR has 256 contact points
accessed by the wiper terminal, plus Terminal B contact. The
8-bit data-word in the RDAC latch is decoded to select one of
the 256 possible settings. The first connection of the wiper starts
at Terminal B for the 0x00 data. This Terminal B connection has a
wiper contact resistance of 45 Ω. The second connection (for a
10 kΩ part) is the first tap point, located at 84 Ω [= RAB (nominal
resistance)/256 + RW = 84 Ω + 45 Ω] for the 0x01 data. The
third connection is the next tap point, representing 78 + 45 =
123 Ω for the 0x02 data. Each LSB data value increase moves
the wiper up the resistor ladder until the last tap point is
reached at 10,006 Ω. The wiper does not directly connect to
Terminal A. See Figure 21 for a simplified diagram of the
equivalent RDAC circuit.
The general transfer equation determining the digitally
programmed output resistance between the Wx and Bx
terminals is
RWB (Dx) = (Dx)/256 × RAB + RW
(1)
where Dx is the data contained in the 8-bit RDACx latch, and
RAB is the nominal end-to-end resistance.
For example, when VB = 0 V and Terminal A is open circuited, the
output resistance values are set as outlined in Table 7 for the
RDAC latch codes (applies to the 10 kΩ potentiometer).
Table 7. Output Resistance Values for the RDAC Latch Codes—
VB = 0 V and Terminal A = Open Circuited
D (Dec)
255
128
1
0
RWB (Ω)
10006
5045
84
45
Output State
Full scale
Midscale (PR = 0 condition)
1 LSB
Zero scale (wiper contact resistance)
In the zero-scale condition, a finite total wiper resistance of 45 Ω
is present. Regardless of which setting the part is operating in,
care should be taken to limit the current between Terminal A to
Terminal B, Wiper W to Terminal A, and Wiper W to Terminal
B, to the maximum continuous current of ±5.65 mA(10 kΩ) or
±1.35 mA(50 kΩ and 100 kΩ) or pulse current of ±20 mA.
Otherwise, degradation or possible destruction of the internal
switch contact, can occur.
Like the mechanical potentiometer that the RDAC replaces,
the RDAC is completely symmetrical. The resistance between
Wiper W and Terminal A produces a digitally controlled
resistance, RWA. When these terminals are used, Terminal B
should be tied to the wiper. Setting the resistance value for RWA
starts at a maximum value of resistance and decreases as the
data loaded to the latch is increased in value. The general
transfer equation for this operation is
RWA (Dx) = (256 − Dx)/256 × RAB + RW
(2)
where Dx is the data contained in the 8-bit RDACx latch, and
RAB is the nominal end-to-end resistance.
For example, when VA = 0 V and Terminal B is tied to Wiper W,
the output resistance values outlined in Table 8 are set for the
RDAC latch codes.
Table 8. Output Resistance Values for the RDAC Latch Codes—
VA = 0 V and Terminal B Tied to Wiper W
D (DEC)
255
128
1
0
RWA (Ω)
84
5045
10006
10045
Output State
Full scale
Midscale (PR = 0 condition)
1 LSB
Zero scale
The typical distribution of RAB from channel to channel matches
to within ±1%. However, device-to-device matching is process
lot dependent, having a ±30% variation. The change in RAB in
terms of temperature has a 700 ppm/°C temperature coefficient.
Rev. C | Page 13 of 20
AD5204/AD5206
PROGRAMMING THE POTENTIOMETER DIVIDER
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example, connecting Terminal A to 5 V and Terminal B to
ground produces an output voltage at the wiper that can be any
value from 0 V up to 1 LSB less than +5 V. Each LSB of voltage
is equal to the voltage applied across Terminal A and Terminal B
divided by the 256-position resolution of the potentiometer
divider. The general equation defining the output voltage with
respect to ground for any given input voltage applied to
Terminal A and Terminal B is
VW (Dx) = Dx/256 × VAB + VB
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. In this
mode, the output voltage is dependent on the ratio of the
internal resistors, not the absolute value; therefore, the drift
improves to 15 ppm/°C.
VDD
CS
CLK
SDO*
DO
A2
A1
A0
D7
ADDR
DEC
DI
W1
RDAC
LATCH
1
B1
D0
R
AD5204/AD5206
SER
REG
SDI
A1
D7
EN
A4/A6
D7
D0
W4/W6
RDAC
LATCH
4/6
(3)
8
D0
B4/B6
R
SHDN*
DGND
PR
Figure 22. Block Diagram
Rev. C | Page 14 of 20
*AD5204 ONLY
06884-047
VOLTAGE OUTPUT OPERATION
AD5204/AD5206
DIGITAL INTERFACING
If a pull-up resistor is used to connect the SDI pin of the
next device in the series, the clock period must be increased.
Capacitive loading at the daisy-chain node (where SDO and
SDI are connected) between the devices must be accounted for
to successfully transfer data. When daisy chaining is used, the
CS should be kept low until all the bits of every package are
clocked into their respective serial registers, ensuring that the
address bits and data bits are in the proper decoding locations.
This requires 22 bits of address and data complying to the dataword format outlined in Table 6 if two AD5204 4-channel RDACs
are daisy-chained. During shutdown (SHDN), the SDO output
pin is forced to the off (logic high state) position to disable power
dissipation in the pull-up resistor. See Figure 24 for the equivalent
SDO output circuit schematic.
A2
0
0
0
0
1
1
CS
PR
SHDN
L
H
H
P
L
H
H
X
P
H
H
X
X
H
X
H
L
H
H
X
X
H
H
P
H
H
L
1
A0
0
1
0
1
0
1
Latch Decoded
RDAC 1
RDAC 2
RDAC 3
RDAC 4
RDAC 5 AD5206 only
RDAC 6 AD5206 only
The data setup and data hold times in the specification table
determine the data valid time requirements. The last 11 bits of
the data-word entered into the serial register are held when CS
returns high. When CS goes high, the address decoder is gated,
enabling one of four or six positive-edge-triggered RDAC
latches (see Figure 23 for details).
AD5204/AD5206
CS
ADDR
DECODE
RDAC 1
RDAC 2
RDAC 4/
RDAC 6
CLK
SERIAL
REGISTER
SDI
Figure 23. Equivalent Input Control Logic
The target RDAC latch is loaded with the last eight bits of the
serial data-word, completing one DAC update. Four separate
8-bit data-words must be clocked in to change all four VR
settings.
SHDN
CS
SDI
SDO
SERIAL
REGISTER
D
Q
GND
CK RS
CLK
PR
Figure 24. Detail SDO Output Schematic of the AD5204
All digital pins (CS, SDI, SDO, PR, SHDN, and CLK) are
protected with a series input resistor and a parallel Zener ESD
structure (see Figure 25).
Table 9. Input Logic Control Truth Table1
CLK
L
A1
0
0
1
1
0
0
06884-048
The serial data output (SDO) pin contains an open-drain
n-channel FET. This output requires a pull-up resistor to transfer
data to the SDI pin of the next package. The pull-up resistor
termination voltage can be larger than the VDD supply of the
AD5204. For example, the AD5204 can operate at VDD = 3.3 V,
and the pull-up for the interface to the next device can be set at
5 V. This allows for daisy chaining several RDACs from a
single-processor serial data line.
Table 10. Address Decode Table
06884-049
The AD5204/AD5206 each contain a standard 3-wire serial
input control interface. The three inputs are clock (CLK), chip
select input (CS), and serial data input (SDI). The positiveedge-sensitive CLK input requires clean transitions to avoid
clocking incorrect data into the serial input register. Standard
logic families work well. If mechanical switches are used for
product evaluation, they should be debounced by a flip-flop or
by other suitable means. Figure 22 shows more detail of the
internal digital circuitry. When CS is taken active low, the clock
loads data into the serial register on each positive clock edge
(see Table 9). When using a positive (VDD) and negative (VSS)
supply voltage, the logic levels are still referenced to digital
ground (GND).
Register Activity
No SR effect; enables SDO pin.
Shift one bit in from the SDI pin. The
11th bit entered is shifted out of the
SDO pin.
Load SR data into the RDAC latch
based on A2, A1, A0 decode (Table 10).
No operation.
Sets all RDAC latches to midscale;
wiper centered and SDO latch
cleared.
Latches all RDAC latches to 0x80.
Open circuits all A resistor terminals,
connects Wiper W to Terminal B, and
turns off the SDO output transistor.
P = positive edge, X = don’t care, SR = shift register.
Rev. C | Page 15 of 20
AD5204/AD5206
TEST CIRCUITS
VA
V+
~
V+ = VDD ± 10%
W
06884-050
LOGIC
B
PSRR (dB) = 20 log
VMS
DD
VSS
PSS (%/%) =
Figure 25. ESD Protection of Digital Pins
∆VMS%
∆VDD%
Figure 30. Power Supply Sensitivity Test Circuit (PSS, PSRR)
A, B, W
B
DUT
VOUT
OP279
OFFSET
GND
06884-051
5V
W
VIN
06884-040
A
VSS
∆V
( ∆VMS )
06884-039
340kΩ
A
VDD
OFFSET BIAS
Figure 26. ESD Protection of Resistor Terminals
Figure 31. Inverting Programmable Gain Test Circuit
5V
V+
V+ = VDD
1LSB = V+/256
VIN
W
B
VMS
Figure 27. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL)
W
A
OFFSET
GND
06884-036
A
VOUT
OP279
B
DUT
OFFSET BIAS
06884-041
DUT
Figure 32. Noninverting Programmable Gain Test Circuit
NO CONNECT
A
IW
VIN
B
Figure 33. Gain vs. Frequency Test Circuit
B
WHERE VW1 = VMS WHEN IW = 0
AND VW2 = VMS WHEN IW = 1/R
VMS
VDD
RSW =
W
VW2 – [VW1 + IW(RAWII RBW)]
RW =
IW
B
06884-052
V+
V+
06884-042
–15V
DUT
I = 1V/RNOMINAL
DUT W
A
VW
W
VOUT
OP42
B
2.5V
Figure 28. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
IMS
DUT
OFFSET
GND
06884-037
VMS
+15V
W
Figure 29. Wiper Resistance Test Circuit
0.1V
ISW
CODE = 0x00
+
ISW
VSS TO VDD
–
0.1V
06884-043
DUT
A
W
Figure 34. Incremental On-Resistance Test Circuit
Rev. C | Page 16 of 20
AD5204/AD5206
OUTLINE DIMENSIONS
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)
24
13
1
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
12
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
071006-A
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 35. 24-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-24-1)
Dimensions shown in inches and (millimeters)
15.60 (0.6142)
15.20 (0.5984)
13
24
7.60 (0.2992)
7.40 (0.2913)
12
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
10.65 (0.4193)
10.00 (0.3937)
1.27 (0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
0.75 (0.0295)
45°
0.25 (0.0098)
8°
0°
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 36. 24-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-24)
Dimensions shown in millimeters and (inches)
Rev. C | Page 17 of 20
1.27 (0.0500)
0.40 (0.0157)
06-07-2006-A
1
AD5204/AD5206
7.90
7.80
7.70
24
13
4.50
4.40
4.30
6.40 BSC
1
12
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.30
0.19
SEATING
PLANE
0.75
0.60
0.45
8°
0°
0.20
0.09
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 37. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
4.75
BSC SQ
0.50
BSC
0.50
0.40
0.30
12° MAX
SEATING
PLANE
0.80 MAX
0.65 TYP
0.30
0.23
0.18
32 1
EXPOSED
PAD
(BOTTOM VIEW)
17
16
9
3.45
3.30 SQ
3.15
8
0.25 MIN
3.50 REF
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
112408-A
TOP
VIEW
1.00
0.85
0.80
PIN 1
INDICATOR
25
24
Figure 38. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
AD5204BN10
AD5204BR10
AD5204BR10-REEL
AD5204BRZ10
AD5204BRZ10-REEL
AD5204BRU10
AD5204BRU10-REEL7
AD5204BRUZ10
AD5204BRUZ10-REEL7
AD5204BCPZ10-REEL
AD5204BCPZ10-REEL7
AD5204BN50
AD5204BR50
AD5204BR50-REEL
AD5204BRZ50
kΩ
10
10
10
10
10
10
10
10
10
10
10
50
50
50
50
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
24-Lead Plastic Dual In-Line Package [PDIP]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
32-Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Frame Chip Scale Package [LFCSP_VQ]
24-Lead Plastic Dual In-Line Package [PDIP]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
Rev. C | Page 18 of 20
Package Option
N-24-1
RW-24
RW-24
RW-24
RW-24
RU-24
RU-24
RU-24
RU-24
CP-32-3
CP-32-3
N-24-1
RW-24
RW-24
RW-24
AD5204/AD5206
Model1, 2
AD5204BRZ50-REEL
AD5204BRU50
AD5204BRU50-REEL
AD5204BRU50-REEL7
AD5204BRUZ50
AD5204BRUZ50-REEL7
AD5204BN100
AD5204BR100
AD5204BR100-REEL
AD5204BRZ100
AD5204BRZ100-REEL
AD5204BRU100
AD5204BRU100-REEL7
AD5204BRUZ100
AD5204BRUZ100-R7
AD5206BN10
AD5206BR10
AD5206BR10-REEL
AD5206BRZ10
AD5206BRZ10-REEL
AD5206BRU10
AD5206BRU10-REEL7
AD5206BRUZ10
AD5206BRUZ10-RL7
AD5206BN50
AD5206BR50
AD5206BR50-REEL
AD5206BRZ50
AD5206BRU50
AD5206BRU50-REEL
AD5206BRU50-REEL7
AD5206BRUZ50
AD5206BRUZ50-REEL7
AD5206BN100
AD5206BR100
AD5206BR100-REEL
AD5206BRZ100
AD5206BRU100
AD5206BRU100-REEL7
AD5206BRUZ100
AD5206BRUZ100-RL7
1
2
kΩ
50
50
50
50
50
50
100
100
100
100
100
100
100
100
100
10
10
10
10
10
10
10
10
10
50
50
50
50
50
50
50
50
50
100
100
100
100
100
100
100
100
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Plastic Dual In-Line Package [PDIP]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Plastic Dual In-Line Package [PDIP]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Plastic Dual In-Line Package [PDIP]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Plastic Dual In-Line Package [PDIP]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
The AD5204/AD5206 each contains 5,925 transistors. Die size is 92 mil × 114 mil, or 10,488 sq. mil.
Z = RoHS Compliant Part.
Rev. C | Page 19 of 20
Package Option
RW-24
RU-24
RU-24
RU-24
RU-24
RU-24
N-24-1
RW-24
RW-24
RW-24
RW-24
RU-24
RU-24
RU-24
RU-24
N-24-1
RW-24
RW-24
RW-24
RW-24
RU-24
RU-24
RU-24
RU-24
N-24-1
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
N-24-1
RW-24
RW-24
RW-24
RU-24
RU-24
RU-24
RU-24
AD5204/AD5206
NOTES
©1999–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06884-0-7/10(C)
Rev. C | Page 20 of 20

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