AMD AM186ED-33KI/W High performance, 80c186- and 80c188-compatible, 16-bit embedded microcontroller Datasheet

PRELIMINARY
Am186TMED/EDLV
High Performance, 80C186- and 80C188-Compatible,
16-Bit Embedded Microcontrollers
DISTINCTIVE CHARACTERISTICS
n E86TM family 80C186- and 80C188-compatible
microcontroller with enhanced bus interface
– Lower system cost with higher performance
– 3.3-V ± 0.3-V operation (Am186EDLV
microcontrollers)
n Programmable DRAM Controller
– Supports zero-wait-state operation with 50-ns
DRAM at 40 MHz, 60-ns @ 33 MHz, 70-ns @ 25
MHz
– Includes programmable CAS-before-RAS
refresh capability
n High performance
– 20-, 25-, 33-, and 40-MHz operating frequencies
– Zero-wait-state operation at 40 MHz with 70-ns
static memory
– 1-Mbyte memory address space
– 64-Kbyte I/O space
n Enhanced features provide improved memory
access and remove the requirement for a 2x clock
input
– Nonmultiplexed address bus
– Processor operates at the clock input frequency
– 8-bit or 16-bit programmable bus sizing including
8-bit boot option
n Enhanced integrated peripherals
– 32 programmable I/O (PIO) pins
– Two full-featured asynchronous serial ports allow
full-duplex, 7-bit, 8-bit, or 9-bit data transfers
D
GENERAL DESCRIPTION
R
The Am186TMED/EDLV microcontrollers are part of the
AMD E86TM family of embedded microcontrollers and microprocessors based on the x86 architecture. The
Am186ED/EDLV microcontrollers are the ideal upgrade
for 80C186/188 designs requiring 80C186/188 compatibility, increased performance, serial communications, a
direct bus interface, and more than 64K of memory.
The Am186ED/EDLV microcontrollers integrate a complete DRAM controller to take advantage of low DRAM
costs. This reduces memory subsystem costs while
maintaining SRAM performance.The Am186ED/EDLV
microcontrollers also integrate the functions of a CPU,
nonmultiplexed address bus, three timers, watchdog
timer, chip selects, interrupt controller, two DMA controllers, two asynchronous serial ports, programmable bus
n
– Serial port hardware handshaking with CTS,
RTS, ENRX, and RTR selectable for each port
– Improved serial port operation enhances 9-bit
DMA support
– Independent serial port baud rate generators
– DMA to and from the serial ports
– Watchdog timer can generate NMI or reset
– A pulse-width demodulation option
– A data strobe, true asynchronous bus interface
option included for DEN
– Reset configuration register
Familiar 80C186 peripherals
– Two independent DMA channels
– Programmable interrupt controller with up to 8 external and 8 internal interrupts
– Three programmable 16-bit timers
– Programmable memory and peripheral
chip-select logic
– Programmable wait state generator
– Power-save clock divider
Software-compatible with the 80C186 and
80C188 microcontrollers with widely available
native development tools, applications, and
system software
A compatible evolution of the Am186EM,
Am186ES, and Am186ER microcontrollers
Available in the following packages:
– 100-pin, thin quad flat pack (TQFP)
– 100-pin, plastic quad flat pack (PQFP)
A
n
n
n
T
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sizing, and programmable I/O (PIO) pins on one chip.
Compared to the 80C186/188 microcontrollers, the
Am186ED/EDLV microcontrollers enable designers to
reduce the size, power consumption, and cost of embedded systems, while increasing reliability, functionality, and performance.
The Am186ED/EDLV microcontrollers have been
designed to meet the most common requirements of
embedded products developed for the communications,
office automation, mass stor age, and general
embedded markets. Specific applications include
PBXs, multiplexers, modems, disk drives, hand-held
and desktop terminals, fax machines, printers,
photocopiers, and industrial controls.
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices,
Inc.
Publication# 21336 Rev: A Amendment/0
Issue Date: May 1997
P R E L I M I N A R Y
Am186ED/EDLV MICROCONTROLLERS BLOCK DIAGRAM
INT2/INTA0/PWD**
INT3/INTA1/IRQ
CLKOUTA
INT1/SELECT
TMROUT0 TMROUT1
PWD**
TMRIN0
TMRIN1
DRQ0/INT5** DRQ1/INT6**
NMI
INT6–INT4**
INT0
CLKOUTB
Timer Control
Unit
0
1
2
Max Count B
Registers
Max Count A
Registers
16-Bit Count
Registers
Control
Registers
X2
X1
VCC
GND
Clock and
Power
Management
Unit
Interrupt
Control Unit
Watchdog
Timer (WDT)
Control
Registers
Pulse
Width
Demodulator
(PWD)
RES
ARDY
Control
Registers
SRDY
S2/BTSEL
S1–S0
DT/R
DEN/DS
HOLD
HLDA
S6/CLKDIV2
UZI
0
1
20-Bit Source
Pointers
20-Bit Destination
Pointers
16-Bit Count
Registers
Control
Registers
T
F
Control
Registers
Control
Registers
DMA
Unit
Refresh
Control
Unit
R
Bus
Interface
Unit
D
A19–A0
Execution
Unit
Control
Registers
PIO31–
PIO0*
Control
Registers
Asynchronous
Serial Port 0
TXD0
RXD0
RTS0/RTR0
CTS0/ENRX0
Asynchronous
Serial Port 1
TXD1
RXD1
RTS1/RTR1**
CTS1/ENRX1**
Chip-Select
Unit
RD
LCS/ONCE0/RAS0
WHB
WLB
AD15–AD0
A
DRAM
Control
Unit
PIO
Unit
WR
BHE/ADEN
PCS6/A2
MCS3/RAS1
MCS2/LCAS
MCS1/UCAS
PCS5/A1
PCS3–PCS0**
MCS0 UCS/ONCE1
ALE
Notes:
*All PIO signals are shared with other physical pins. See the pin descriptions beginning on page 21 and Table 2 on page 29 for
information on shared functions.
** RTS1/RTR1 and CTS1/ENRX1 are multiplexed with PCS3 and PCS2, respectively. See the pin descriptions beginning on
page 21.
2
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed
by a combination of the elements below.
Am186TMED/EDLV
-40
K
C
\W
LEAD FORMING
\W=Trimmed and Formed
TEMPERATURE RANGE
C= ED Commercial (TC =0°C to +100°C)
C = EDLV Commercial (TC =0°C to +70°C)
I = ED Industrial (TA =–40°C to +85°C)
where: TC = case temperature
where: TA = ambient temperature
PACKAGE TYPE
V=100-Pin Thin Quad Flat Pack (TQFP)
K=100-Pin Plastic Quad Flat Pack (PQFP)
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SPEED OPTION
–20 = 20 MHz
–25 = 25 MHz
–33 = 33 MHz
–40 = 40 MHz
DEVICE NUMBER/DESCRIPTION
Am186ED = High-Performance, 80C186-Compatible,
16-Bit Embedded Microcontroller
A
Am186EDLV = High-Performance, 80L186-Compatible,
Low-Voltage, 16-Bit Embedded Microcontroller
R
Valid Combinations
Am186ED–20
Am186ED–25
Am186ED–33
Am186ED–40
D
Am186ED–20
Am186ED–25
Am186EDLV–20
Am186EDLV–25
VC\W or
KC\W
KI\W1
VC\W or
KC\W
Note:
The industrial version of the Am186ED is
offered only in the PQFP package.
Valid Combinations
Valid combinations list configurations planned to be
supported in volume for this device. Consult the
local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
Note: The industrial version of the Am186ED as
well as the Am186EDLV are available in 20 and 25
MHz operating frequencies only.
The Am186ED and Am186EDLV microcontrollers
are all functionally the same except for their DC
characteristics and available frequencies.
Note: There is no 188 version of the Am186ED/
EDLV. The same 8-bit external bus capabilities
can be achieved using the 8-bit boot capability and
programmable bus sizing options.
Am186ED/EDLV Microcontrollers
3
P R E L I M I N A R Y
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS ........................................................................................... 1
GENERAL DESCRIPTION .......................................................................................................... 1
AM186ED/EDLV MICROCONTROLLERS BLOCK DIAGRAM ................................................... 2
ORDERING INFORMATION ....................................................................................................... 3
Standard Products ........................................................................................................... 3
RELATED AMD PRODUCTS ...................................................................................................... 9
E86 Family Devices ...................................................................................................... 9
Related Documents ....................................................................................................... 10
Third-Party Development Support Products .................................................................. 10
Customer Service .......................................................................................................... 10
KEY FEATURES AND BENEFITS ............................................................................................ 10
Application Considerations .............................................................................................11
COMPARING THE AM186ED/EDLV TO THE AM186ES/ESLV MICROCONTROLLERS ........ 12
Integrated DRAM Controller ........................................................................................... 12
Enhanced Refresh Control Unit ..................................................................................... 13
Option to Overlap DRAM with PCS ............................................................................... 13
Additional Serial Port Mode for DMA Support of 9-bit Protocols .................................... 13
Option to Boot from 8- or 16-bit Memory ....................................................................... 13
Improved External Bus Master Support ......................................................................... 13
PSRAM Controller Removed ......................................................................................... 13
TQFP CONNECTION DIAGRAMS AND PINOUTS .................................................................. 14
Top Side View—100-Pin Thin Quad Flat Pack (TQFP) ................................................. 14
TQFP PIN DESIGNATIONS ....................................................................................................... 15
Sorted by Pin Number .................................................................................................... 15
Sorted by Pin Name ....................................................................................................... 16
PQFP CONNECTION DIAGRAMS AND PINOUTS .................................................................. 17
Top Side View—100-Pin Plastic Quad Flat Pack (PQFP) ............................................. 17
PQFP PIN DESIGNATIONS ....................................................................................................... 18
Sorted by Pin Number .................................................................................................... 18
Sorted by Pin Name ....................................................................................................... 19
LOGIC SYMBOL—AM186ED/EDLV MICROCONTROLLERS ................................................. 20
PIN DESCRIPTIONS ................................................................................................................. 21
Pins That Are Used by Emulators .................................................................................. 21
Pin Terminology ............................................................................................................. 21
A19–A0 (A19/PIO9, A18/PIO8, A17/PIO7) .................................................................... 21
AD15–AD8 ..................................................................................................................... 21
AD7–AD0 ....................................................................................................................... 21
ALE ................................................................................................................................ 21
ARDY ............................................................................................................................. 22
BHE/ADEN ..................................................................................................................... 22
CLKOUTA ...................................................................................................................... 22
CLKOUTB ...................................................................................................................... 22
CTS0/ENRX0/PIO21 ...................................................................................................... 22
DEN/DS/PIO5 ................................................................................................................ 23
DRQ0/INT5/PIO12 ......................................................................................................... 23
DRQ1/INT6/PIO13 ......................................................................................................... 23
DT/R/PIO4 ..................................................................................................................... 23
GND ............................................................................................................................... 23
HLDA ............................................................................................................................. 23
HOLD ............................................................................................................................. 23
INT0 ............................................................................................................................... 24
INT1/SELECT ................................................................................................................ 24
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Am186ED/EDLV Microcontrollers
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P R E L I M I N A R Y
INT2/INTA0/PWD/PIO31 ................................................................................................ 24
INT3/INTA1/IRQ ............................................................................................................. 24
INT4/PIO30 .................................................................................................................... 25
LCS/ONCE0/RAS0 ........................................................................................................ 25
MCS0/PIO14 .................................................................................................................. 25
MCS1/UCAS/PIO15 ....................................................................................................... 25
MCS2/LCAS/PIO24 ....................................................................................................... 25
MCS3/RAS1/PIO25 ....................................................................................................... 26
NMI ................................................................................................................................ 26
PCS1/PIO17, PCS0/PIO16 ............................................................................................ 26
PCS2/CTS1/ENRX1/PIO18 ........................................................................................... 27
PCS3/RTS1/RTR1/PIO19 .............................................................................................. 27
PCS5/A1/PIO3 ............................................................................................................... 27
PCS6/A2/PIO2 ............................................................................................................... 28
PIO31–PIO0 (Shared) .................................................................................................... 28
RD .................................................................................................................................. 28
RES ................................................................................................................................ 28
RTS0/RTR0/PIO20 ........................................................................................................ 30
RXD0/PIO23 .................................................................................................................. 30
RXD1/PIO28 .................................................................................................................. 30
S2/BTSEL ...................................................................................................................... 30
S1–S0 ............................................................................................................................ 30
S6/CLKDIV2/PIO29 ....................................................................................................... 30
SRDY/PIO6 .................................................................................................................... 30
TMRIN0/PIO11 ............................................................................................................... 31
TMRIN1/PIO0 ................................................................................................................ 31
TMROUT0/PIO10 .......................................................................................................... 31
TMROUT1/PIO1 ............................................................................................................ 31
TXD0/PIO22 ................................................................................................................... 31
TXD1/PIO27 ................................................................................................................... 31
UCS/ONCE1 .................................................................................................................. 31
UZI/PIO26 ...................................................................................................................... 31
VCC ................................................................................................................................ 31
WHB ............................................................................................................................... 31
WLB ............................................................................................................................... 32
WR ................................................................................................................................. 32
X1 ................................................................................................................................... 32
X2 ................................................................................................................................... 32
FUNCTIONAL DESCRIPTION .................................................................................................. 33
Memory Organization ..................................................................................................... 33
I/O Space ....................................................................................................................... 33
BUS OPERATION ..................................................................................................................... 34
BUS INTERFACE UNIT ............................................................................................................. 36
Nonmultiplexed Address Bus ......................................................................................... 36
DRAM Address Multiplexing .......................................................................................... 36
Programmable Bus Sizing ............................................................................................. 37
Byte-Write Enables ........................................................................................................ 37
Data Strobe Bus Interface Option .................................................................................. 37
DRAM INTERFACE ................................................................................................................... 37
PERIPHERAL CONTROL BLOCK ............................................................................................ 38
Reading and Writing the PCB ........................................................................................ 38
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Am186ED/EDLV Microcontrollers
T
F
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P R E L I M I N A R Y
CLOCK AND POWER MANAGEMENT .................................................................................... 40
Phase-Locked Loop ....................................................................................................... 40
Crystal-Driven Clock Source .......................................................................................... 40
External Source Clock ................................................................................................... 41
System Clocks ............................................................................................................... 41
Power-Save Operation ................................................................................................... 41
Initialization and Processor Reset .................................................................................. 41
Reset Configuration Register ......................................................................................... 41
CHIP-SELECT UNIT .................................................................................................................. 42
Chip-Select Timing ......................................................................................................... 42
Ready and Wait-State Programming ............................................................................. 42
Chip-Select Overlap ....................................................................................................... 42
Upper Memory Chip Select ............................................................................................ 43
Low Memory Chip Select ............................................................................................... 43
Midrange Memory Chip Selects ..................................................................................... 43
Peripheral Chip Selects ................................................................................................. 43
REFRESH CONTROL UNIT ...................................................................................................... 44
INTERRUPT CONTROL UNIT .................................................................................................. 44
TIMER CONTROL UNIT ............................................................................................................ 45
Watchdog Timer ............................................................................................................. 45
PULSE WIDTH DEMODULATION ............................................................................................ 45
DIRECT MEMORY ACCESS .................................................................................................... 46
DMA Operation .............................................................................................................. 46
DMA Channel Control Registers .................................................................................... 47
DMA Priority ................................................................................................................... 47
ASYNCHRONOUS SERIAL PORTS ......................................................................................... 47
DMA Transfers through the Serial Port .......................................................................... 48
PROGRAMMABLE I/O (PIO) PINS ........................................................................................... 48
ABSOLUTE MAXIMUM RATINGS ............................................................................................ 49
OPERATING RANGES ............................................................................................................. 49
DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES . 49
CAPACITANCE ......................................................................................................................... 50
POWER SUPPLY CURRENT ................................................................................................... 50
THERMAL CHARACTERISTICS ............................................................................................... 51
TQFP Package .............................................................................................................. 51
Typical Ambient Temperatures ....................................................................................... 52
COMMERCIAL AND INDUSTRIAL SWITCHING CHARACTERISTICS AND WAVEFORMS .. 57
Key to Switching Waveforms ......................................................................................... 57
Alphabetical Key to Switching Parameter Symbols ....................................................... 58
Numerical Key to Switching Parameter Symbols ........................................................... 61
SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL
OPERATING RANGES ............................................................................................... 64
Read Cycle (20 MHz and 25 MHz) ................................................................................ 64
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES ................. 65
Read Cycle (33 MHz and 40 MHz) ................................................................................ 65
READ CYCLE WAVEFORMS ................................................................................................... 66
SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL
OPERATING RANGES ............................................................................................... 67
Write Cycle (20 MHz and 25 MHz) ................................................................................ 67
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES ................. 68
Write Cycle (33 MHz and 40 MHz) ................................................................................ 68
WRITE CYCLE WAVEFORMS .................................................................................................. 69
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Am186ED/EDLV Microcontrollers
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P R E L I M I N A R Y
SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL
OPERATING RANGES ............................................................................................... 70
DRAM ............................................................................................................................ 70
DRAM Read Cycle Timing with No-Wait States ............................................................ 71
DRAM Read Cycle Timing with Wait State(s) ................................................................ 71
DRAM Write Cycle Timing with No-Wait States ............................................................. 72
DRAM Write Cycle Timing With Wait State(s) ............................................................... 72
DRAM CAS-before-RAS Cycle Timing .......................................................................... 73
SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL
OPERATING RANGES ............................................................................................... 74
Interrupt Acknowledge Cycle (20 MHz and 25 MHz) ..................................................... 74
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES ................. 75
Interrupt Acknowledge Cycle (33 MHz and 40 MHz) ..................................................... 75
INTERRUPT ACKNOWLEDGE CYCLE WAVEFORMS ........................................................... 76
SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL
OPERATING RANGES ............................................................................................... 77
Software Halt Cycle (20 MHz and 25 MHz) ................................................................... 77
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES ................. 77
Software Halt Cycle (33 MHz and 40 MHz) ................................................................... 77
SOFTWARE HALT CYCLE WAVEFORMS ............................................................................... 78
SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL
OPERATING RANGES ............................................................................................... 79
Clock (20 MHz and 25 MHz) .......................................................................................... 79
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES ................. 80
Clock (33 MHz and 40 MHz) .......................................................................................... 80
CLOCK WAVEFORMS .............................................................................................................. 81
Clock Waveforms—Active Mode ................................................................................... 81
Clock Waveforms—Power-Save Mode .......................................................................... 81
SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL
OPERATING RANGES ............................................................................................... 82
Ready and Peripheral (20 MHz and 25 MHz) ................................................................ 82
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES ................. 82
Ready and Peripheral (33 MHz and 40 MHz) ................................................................ 82
SYNCHRONOUS, ASYNCHRONOUS, AND PERIPHERAL WAVEFORMS ............................ 83
Synchronous Ready Waveforms ................................................................................... 83
Asynchronous Ready Waveforms .................................................................................. 83
Peripheral Waveforms ................................................................................................... 83
SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL
OPERATING RANGES ............................................................................................... 84
Reset and Bus Hold (20 MHz and 25 MHz) ................................................................... 84
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES ................ 84
Reset and Bus Hold (33 MHz and 40 MHz) ................................................................... 84
RESET AND BUS HOLD WAVEFORMS ................................................................................... 85
Reset Waveforms .......................................................................................................... 85
Signals Related to Reset Waveforms ............................................................................ 85
Bus Hold Waveforms—Entering .................................................................................... 86
Bus Hold Waveforms—Leaving ..................................................................................... 86
TQFP PHYSICAL DIMENSIONS ............................................................................................... 87
PQFP PHYSICAL DIMENSIONS .............................................................................................. 88
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Am186ED/EDLV Microcontrollers
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P R E L I M I N A R Y
LIST OF FIGURES
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Am186ED Microcontroller Example System Design .............................................. 11
80C186 Microcontroller Example System Design ................................................. 12
Two-Component Address ...................................................................................... 33
16-Bit Mode—Normal Read and Write Operation ................................................. 34
16-Bit Mode—Read and Write with Address Bus Disable In Effect ....................... 35
8-Bit Mode—Normal Read and Write Operation ................................................... 35
8-Bit Mode—Read and Write with Address Bus Disable in Effect ......................... 36
Am186ED/EDLV Microcontrollers Oscillator Configurations ................................. 40
Clock Organization ................................................................................................ 41
DMA Unit Block Diagram ....................................................................................... 47
Typical Icc Versus Frequency for Am186EDLV Microcontroller ............................. 50
Typical Icc Versus Frequency for Am186ED Microcontroller ................................. 50
Thermal Resistance(°C/Watt) ................................................................................ 51
Thermal Characteristics Equations ........................................................................ 51
Typical Ambient Temperatures for PQFP with a 2-Layer Board ............................ 53
Typical Ambient Temperatures for TQFP with a 2-Layer Board ............................ 54
Typical Ambient Temperatures for PQFP with a 4-Layer to 6-Layer Board .......... 55
Typical Ambient Temperatures for TQFP with a 4-Layer to 6-Layer Board ........... 56
LIST OF TABLES
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
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Data Byte Encoding ............................................................................................... 22
Numeric PIO Pin Designations .............................................................................. 29
Alphabetic PIO Pin Designations ........................................................................... 29
Bus Cycle Encoding ............................................................................................... 30
Segment Register Selection Rules ........................................................................ 33
DRAM Pin Interface ............................................................................................... 37
Programming the Bus Width of Am186ED/EDLV Microcontrollers ........................ 37
Peripheral Control Block Register Map .................................................................. 39
Am186ED/EDLV Microcontrollers Maximum DMA Transfer Rates ....................... 46
Typical Power Consumption Calculation for the Am186EDLV Microcontroller ...... 50
Thermal Characteristics (°C/Watt) ......................................................................... 51
Typical Power Consumption Calculation ............................................................... 52
Junction Temperature Calculation ......................................................................... 52
Typical Ambient Temperatures (°C) for PQFP with a 2-Layer Board .................... 53
Typical Ambient Temperatures (°C) for TQFP with a 2-Layer Board .................... 54
Typical Ambient Temperatures (°C) for PQFP with a 4-Layer to 6-Layer Board ... 55
Typical Ambient Temperatures (°C) for TQFP with a 4-Layer to 6-Layer Board ... 56
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Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
Microprocessors
Am486
Future
AT Peripheral
Microcontrollers
K86™
Future
186 Peripheral
Microcontrollers
Am486DX
Microprocessor
ÉlanSC410
Microcontroller
ÉlanSC400
Microcontroller
Am186ED
Microcontroller
Am386SX/DX
Microprocessors
ÉlanSC310
Microcontroller
ÉlanSC300
Microcontroller
80C186 and 80C188
Microcontrollers
80L186 and 80L188
Microcontrollers
32-bit Future
Am186 and
Am188 Future
Am186ER and
Am188ER
Microcontrollers
Am186ES and
Am188ES
Microcontrollers
Am186EM and
Am188EM
Microcontrollers
Am186ESLV &
Am188ESLV
Microcontrollers
Am186EMLV &
Am188EMLV
Microcontrollers
Time
T
F
The E86 Family of Embedded Microprocessors and Microcontrollers
RELATED AMD PRODUCTS
E86 Family Devices
Device
80C186
80C188
80L186
80L188
Am186EM
Am188EM
Am186EMLV
Am188EMLV
A
Description
16-bit microcontroller
16-bit microcontroller with 8-bit external data bus
Low-voltage, 16-bit microcontroller
Low-voltage, 16-bit microcontroller with 8-bit external data bus
High-performance, 80C186-compatible, 16-bit embedded microcontroller
High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus
High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller
High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit
external data bus
Am186ES
High-performance, 80C186-compatible, 16-bit embedded microcontroller
Am188ES
High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus
Am186ESLV High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller
Am188ESLV High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit
external data bus
Am186ED
High-performance, 80C186- and 80C188-compatible, 16-bit embedded microcontroller with 8- or 16bit external data bus
Am186EDLV High-performance, 80C186- and 80C188-compatible, low-voltage, 16-bit embedded microcontroller
with 8- or 16-bit external data bus
Am186ER
High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller with 32 Kbyte
of internal RAM
Am188ER
High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit
external data bus and 32 Kbyte of internal RAM
D
Élan™SC300
ÉlanSC310
ÉlanSC400
ÉlanSC410
Am386®DX
Am386®SX
Am486®DX
R
High-performance, highly integrated, low-voltage, 32-bit embedded microcontroller
High-performance, single-chip, 32-bit embedded PC/AT microcontroller
Single-chip, low-power, PC/AT-compatible microcontroller
Single-chip, PC/AT-compatible microcontroller
High-performance, 32-bit embedded microprocessor with 32-bit external data bus
High-performance, 32-bit embedded microprocessor with 16-bit external data bus
High-performance, 32-bit embedded microprocessor with 32-bit external data bus
Am186ED/EDLV Microcontrollers
9
P R E L I M I N A R Y
Related Documents
The following documents provide additional
i n f o r m a t i o n r e g a r d i n g t h e A m 1 8 6 E D / E D LV
microcontrollers:
n Am186ED/EDLV Microcontrollers User’s Manual,
order # 21335
n Am186 and Am188 Family Instruction Set Manual,
order # 21267
n FusionE86SM Catalog, order # 19255
n E86 Family Support Tools Brief, order # 20071
n FusionE86 Development Tools Reference CD,
order # 21058
Third-Party Development
Support Products
To d own lo ad do cu me nt s a nd s oft war e , ft p t o
ftp.amd.com and log on as anonymous using your
E-mail address as a password. Or via your web
browser, go to ftp://ftp.amd.com.
Questions, requests, and input concerning AMD’s
WWW pages can be sent via E-mail to
[email protected].
Documentation and Literature
Free E86 family information such as data books, user’s
man ual s , data sh eets , ap pl ic ati on n otes , th e
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The Am186ED/EDLV microcontrollers extend the AMD
family of microcontrollers based on the industry-standard x86 architecture. The Am186ED/EDLV microcontrollers are a higher-performance, highly integrated
version of the 80C186/188 microprocessors, offering
an attractive migration path. In addition, the Am186ED/
EDLV microcontrollers offer application-specific features that can enhance the system functionality of the
Am186ES/ESLV and Am188ES/ESLV microcontrollers. Upgrading to the Am186ED/EDLV microcontrollers is an attractive solution for several reasons:
n Programmable DRAM controller—Enables system designers to take advantage of low-cost DRAM
and fully utilize the performance and flexibility of the
x86 architecture. The DRAM controller supports
zero wait-state performance with 50-ns DRAM at 40
MHz, or, if required, can be programmed with wait
states. The Am186ED/EDLV microcontrollers provide a CAS-before-RAS refresh unit.
n Minimized total system cost—New and enhanced peripherals and on-chip system interface
logic on the Am186ED/EDLV microcontrollers reduce the cost of existing 80C186/188 designs.
n X86 software compatibility—80C186/188-compatible and upward-compatible with the other members of the AMD E86 family.
To access the AMD home page go to:
http://www.amd.com.
10
Toll-free for U.S. and Canada
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
n Enhanced performance—The Am186ED/EDLV
microcontrollers increase the performance of
80C186/188 systems, and the nonmultiplexed address bus offers unbuffered access to memory.
n Enhanced functionality—The enhanced on-chip
peripherals of the Am186ED/EDLV microcontrollers
include two asynchronous serial ports, 32 PIOs, a
watchdog timer, additional interrupt pins, a pulse
width demodulation option, DMA directly to and from
the serial ports, 8-bit and 16-bit programmable bus
sizing, a 16-bit reset configuration register, and enhanced chip-select functionality.
Clock Generation
The integrated clock generation circuitry of the
Am186ED/EDLV microcontrollers enables the use of a
1x crystal frequency. The Am186ED design in Figure 1
achieves 40-MHz CPU operation, while using a 40MHz crystal.
Application Considerations
The integration enhancements of the Am186ED/EDLV
microcontrollers provide a high-performance, low-system-cost solution for 16-bit embedded microcontroller
designs. The nonmultiplexed address bus eliminates
the need for system-support logic to interface memory
devices, while the multiplexed address/data bus maintains the value of previously engineered, customerspecific peripherals and circuits within the upgraded
design.
Figure 1 illustrates an example system design that
uses the integrated peripheral set to achieve high performance with reduced system cost.
Memory Interface
The Am186ED/EDLV microcontrollers integrate a versatile memory controller which supports direct memory
accesses to DRAM, SRAM, Flash, EPROM, and ROM.
No external glue logic is required and all required control signals are provided. The peripheral chip selects
have been enhanced to allow them to overlap the
DRAM. This allows a small 1.5K portion of the DRAM
memory space to be used for peripherals without bus
contention.
D
R
The improved memory timing specifications of the
Am186ED/EDLV microcontrollers allow for zero-waitstate operation at 40 MHz using 50-ns DRAM, 70-ns
SRAM, or 70-ns Flash memory. For 60-ns DRAM one
wait state is required at 40 MHz and zero wait states at
33 MHz and below. For 70-ns DRAM two wait states
are required at 40 MHz, one wait state at 33 MHz, and
zero wait states at 25 MHz and below. This reduces
overall system cost by enabling the use of commonly
available memory speeds and taking advantage of
DRAM’s lower cost per bit over SRAM.
A
T
F
0-6
Figure 1. Am186ED Microcontroller Example
System Design
Direct Memory Interface Example
Figure 1 illustrates the direct memory interface of the
Am186ED microcontroller. The processor’s A19–A0
bus connects to the memory address inputs, the AD
bus connects to the data inputs and outputs, and the
chip selects connect to the memory chip-select inputs.
The odd A1–A17 address pins connect to the DRAM
multiplexed address bus.
The RD output connects to the DRAM Output Enable
(OE) pin for read operations. Write operations use the
WR output connected to the DRAM Write Enable (WE)
pin. The UCAS and LCAS pins provide byte selection.
Figure 1 also shows an implementation of an RS-232
console or modem communications port. The RS-232
to CMOS voltage-level converter is required for the
electrical interface with the external device.
Am186ED/EDLV Microcontrollers
11
P R E L I M I N A R Y
COMPARING THE Am186ES/ESLV TO THE Am186ED/EDLV MICROCONTROLLERS
Compared to the Am186ES/ESLV microcontrollers, the
Am186ED/EDLV microcontrollers have the following
additional features:
n Integrated DRAM controller
n Enhanced refresh control unit
n Option to overlap DRAM with peripheral chip select
(PCS)
n Additional serial port mode for DMA support of 9-bit
protocols
n Option to boot from 8- or 16-bit memory
n Improved external bus master support
n PSRAM controller removed
Figure 1 shows an example system using a 40-MHz
Am 1 86 ED mi c r oc o nt r ol le r. F i gu r e 2 s ho ws a
comparable system implementation with an 80C186.
Because of its superior integration, the Am186ED/
EDLV system does not require the support devices that
are required on the 80C186 example system. In
addition, the Am186ED/EDLV microcontrollers provide
25
D
R
significantly better performance with its 40-MHz clock
rate.
Integrated DRAM Controller
The integrated DRAM controller directly interfaces
DRAM to support no-wait state DRAM interface up to
40 MHz. Wait states can be inserted to support slower
DRAM. All signals requir ed by the DRAM ar e
generated on the Am186ED/EDLV microcontrollers
and no external logic is r equired. The DRAM
multiplexed address pins are connected to the odd
address pins starting with A1 on the Am186ED/EDLV
microcontrollers to MA0 on the DRAM. The correct row
and column addresses are generated on these pins
during a DRAM access. The UCAS and LCAS are used
to select which byte of the DRAM is accessed during a
read or write. The RAS0 controls the lower bank of
DRAM which starts at 00000h in the address map and
is bounded by the lower memory size selected in the
LMCS register. RAS1 controls the upper bank of
DRAM which ends at FFFFFh and is bounded by the
upper memory size in the UMCS register. When RAS1
is enabled, UCS is automatically disabled. Neither,
either, or both DRAM banks can be activated.
A
T
F
Figure 2. 80C186 Microcontroller Example System Design
12
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
Enhanced Refresh Control Unit
The refresh control unit (RCU) is enhanced with two
additional bits in the refresh counter to allow for longer
refresh periods. The address generated during a
refresh has been fixed to FFFFFh. When either bank of
DRAM is enabled and the RCU is enabled, a CASbefore-RAS refresh will be generated based on the
time period coded into the refresh counter.
Option to Overlap DRAM with PCS
The peripheral chip selects (PCS0–PCS6) can overlap
DRAM blocks with different wait states without external
or internal bus contention. The RAS0 or RAS1 will
assert along with the appropriate PCS. The UCAS and
LCAS will not assert, preventing the DRAM from writing
erroneously or driving the data bus during a read. The
PCS must have the same or higher number of wait
states than the DRAM. The PCS bus width will be
determined by the LSIZ or USIZ bus widths as
programmed in the AUXCON register.
Additional Serial Port Mode for DMA
Support of 9-bit Protocols
A mode 7 was added to the serial port which enhances
the direct memory access (DMA) support for 9-bit
protocols. Using mode 2, the serial port can be
programmed to interrupt only if the 9th bit is set,
ignoring all 9th bit cleared byte receptions. Mode 3
receives all bytes, whether the 9th bit is set or cleared.
Mode 7 also receives all bytes whether the 9th bit is set
or cleared, but now an interrupt is generated when the
9th bit is set. This allows the DMA to service all
receptions, but also allows the CPU to intervene when
the trailer (9th bit set) is received. In all modes using
DMA, the interrupts other than transmitter ready and
character received interrupts can still be generated.
This allows the DMA to handle the standard sending
and receiving characters while the CPU can intervene
when a non-standard event (e.g., framing error)
occurs.
D
R
entire memory map can be set to 16-bit or 8-bit or
mixed between 8-bit and 16-bit based on the USIZ,
LSIZ, MSIZ, and IOSIZ bits in the AUXCON register.
Improved External Bus Master Support
When the bus is arbitrated away from the Am186ED/
EDLV microcontrollers using the HOLD pin, the chip
selects are driven High (negated) and then held High
with an internal ~10-kohm pullup. This allows external
bus masters to assert the chip selects by externally
pulling them Low, without having to combine the chip
selects from the Am186ED/EDLV microcontrollers and
the external bus master in logic external to the
Am186ED/EDLV microcontrollers. This internal pullup
is activated for any bus arbitration, even if the pin is
being used as a PIO input.
PSRAM Controller Removed
T
F
The PSRAM mode found on the Am186ES/ESLV
microcontrollers has been removed and replaced with
a DRAM controller. This includes removal of the variant
PSRAM LCS timing and refresh strobe on MCS3.
A
Option to Boot from 8- or 16-bit Memory
The Am186ED/EDLV microcontrollers can boot from 8or 16-bit-wide non-volatile memory, based on the state
of the S2/BTSEL pin. If S2/BTSEL is pulled High or left
floating, an internal pullup sets the boot mode option to
16-bit. If S2/BTSEL is pulled resistively Low during
reset, the boot mode option is for 8-bit. The status of
the S2/BTSEL pin is latched on the rising edge of reset.
If the 8-bit boot option is selected, the width of the
memory region associated with UCS can be changed
in the AUXCON register. This allows for cheaper 8-bitwide memory to be used for booting the
microcontroller, while speed-critical code and data can
be executed from 16-bit-wide lower memory. Eight-bit
or 16-bit-wide peripherals can be used in the memory
area between LCS and UCS or in the I/O space. The
Am186ED/EDLV Microcontrollers
13
P R E L I M I N A R Y
AD0
AD8
1
AD1
AD9
3
4
AD2
AD10
5
6
AD3
AD11
7
8
AD4
AD12
9
10
AD5
GND
11
12
AD13
AD6
13
14
V CC
AD14
15
16
AD7
AD15
17
18
S6/CLKDIV2
19
20
73
72
MCS0
DEN/DS
71
70
DT/R
NMI
69
68
SRDY
HOLD
67
66
HLDA
VCC
PCS 5/A1
PCS 6/A2
LCS / ONCE 0/RAS0
UCS / ONCE1
INT0
INT1/ SELECT
INT2/INTA 0/PWD
INT3/INTA 1/IRQ
84
83
82
81
80
79
78
77
76
MCS3/ RAS1
MCS2/LCAS
VCC
92
91
PCS2 /CTS1/ENRX1
PCS3 /RTS1/RTR1
RES
GND
94
93
86
85
TMROUT1
TMRIN1
96
95
PCS1
GND
TMRIN0
TMROUT0
98
97
88
87
DRQ0/INT5
DRQ1/INT6
100
99
PCS0
T
F
63
62
A0
A1
61
60
VCC
A2
59
58
A3
A4
57
56
A5
A6
55
54
A7
A8
23
24
53
52
A9
A10
25
51
A11
A
Am186ED/EDLV Microcontrollers
40
41
42
43
44
45
46
47
48
49
50
VCC
A17
A16
A15
A14
A13
A12
34
35
S0
CLKOUTB
GND
A19
A18
32
33
S2/BTSEL
S1
38
39
30
31
VCC
CLKOUTA
28
29
WR
RD
ALE
ARDY
36
37
R
GND
X1
X2
D
21
22
Note:
Pin 1 is marked for orientation.
14
INT4
MCS1/UCAS
WLB
WHB
GND
BHE/ADEN
TXD0
75
74
65
64
26
27
CTS0/ENRX0
RXD0
2
RTS0/RTR0
UZI
TXD1
RXD1
90
89
TQFP CONNECTION DIAGRAMS AND PINOUTS
Am186ED/EDLV Microcontrollers
Top Side View—100-Pin Thin Quad Flat Pack (TQFP)
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
TQFP PIN DESIGNATIONS—Am186ED/EDLV Microcontrollers
Sorted by Pin Number
Pin No.
Name
Pin No.
Name
Pin No.
Name
Pin No.
Name
1
AD0
26
RTS0/RTR0/
PIO20
51
A11
76
INT3/INTA1/IRQ
2
AD8
27
BHE/ADEN
52
A10
77
INT2/INTA0/PWD/
PIO31
3
AD1
28
WR
53
A9
78
INT1/SELECT
4
AD9
29
RD
54
A8
79
INT0
5
AD2
30
ALE
55
A7
80
UCS/ONCE1
6
AD10
31
ARDY
56
A6
81
LCS/ONCE0/
RAS0
7
AD3
32
S2/BTSEL
57
A5
82
PCS6/A2/PIO2
8
AD11
33
S1
58
A4
83
PCS5/A1/PIO3
9
AD4
34
S0
59
A3
84
VCC
10
AD12
35
GND
60
A2
85
PCS3/RTS1/
RTR1/
PIO19
11
AD5
36
X1
61
VCC
86
PCS2/CTS1/
ENRX1/PIO18
12
GND
37
X2
62
A1
87
GND
13
AD13
38
VCC
63
A0
88
PCS1/PIO17
14
AD6
39
CLKOUTA
64
GND
89
PCS0/PIO16
15
VCC
40
CLKOUTB
65
WHB
90
VCC
16
AD14
66
WLB
91
MCS2/LCAS/
PIO24
17
AD7
67
HLDA
92
MCS3/RAS1/
PIO25
18
AD15
19
S6/CLKDIV2/PIO29
20
UZI/PIO26
21
TXD1/PIO27
22
R
A
T
F
41
GND
42
A19/PIO9
43
A18/PIO8
68
HOLD
93
GND
44
VCC
69
SRDY/PIO6
94
RES
45
A17/PIO7
70
NMI
95
TMRIN1/PIO0
46
A16
71
DT/R/PIO4
96
TMROUT1/PIO1
RXD1/PIO28
47
A15
72
DEN/DS/PIO5
97
TMROUT0/PIO10
23
CTS0/ENRX0/PIO21
48
A14
73
MCS0/PIO14
98
TMRIN0/PIO11
24
RXD0/PIO23
49
A13
74
MCS1/UCAS/
PIO15
99
DRQ1/INT6/PIO13
25
TXD0/PIO22
50
A12
75
INT4/PIO30
100
DRQ0/INT5/PIO12
D
Am186ED/EDLV Microcontrollers
15
P R E L I M I N A R Y
TQFP PIN DESIGNATIONS—Am186ED/EDLV Microcontrollers
Sorted by Pin Name
Pin Name
No.
Pin Name
No.
Pin Name
No.
Pin Name
No.
A0
63
AD5
11
GND
87
RXD1
22
A1
62
AD6
14
GND
93
S0
34
A2
60
AD7
17
HLDA
67
S1
33
A3
59
AD8
2
HOLD
68
S2/BTSEL
32
A4
58
AD9
4
INT0
79
S6/CLKDIV2/
PIO29
19
A5
57
AD10
6
INT1/SELECT
78
SRDY/PIO6
69
A6
56
AD11
8
INT2/INTA0/PWD/
PIO31
77
TMRIN0/PIO11
98
A7
55
AD12
10
INT3/INTA1/IRQ
76
TMRIN1/PIO0
95
A8
54
AD13
13
INT4/PIO30
A9
53
AD14
16
LCS/ONCE0/RAS0
A10
52
AD15
18
MCS0/PIO14
A11
51
ALE
30
MCS1/UCAS/
PIO15
A12
50
ARDY
31
MCS2/LCAS/PIO24
A13
49
BHE/ADEN
27
A14
48
CLKOUTA
39
A15
47
CLKOUTB
40
A16
46
CTS0/ENRX0/
PIO21
23
A17/PIO7
45
DEN/DS/PIO5
72
A
A18/PIO8
43
DRQ0/INT5/PIO12
42
A19/PIO9
AD0
AD1
AD2
AD3
AD4
16
T
F
75
TMROUT0/
PIO10
97
81
TMROUT1/PIO1
96
73
TXD0/PIO22
25
74
TXD1
21
91
UCS/ONCE1
80
92
UZI/PIO26
20
70
VCC
15
89
VCC
38
PCS1/PIO17
88
VCC
44
PCS2/CTS1/
ENRX1/PIO18
86
VCC
61
100
PCS3/RTS1/RTR1/
PIO19
85
VCC
84
DRQ1/INT6/PIO13
99
PCS5/A1/PIO3
83
VCC
90
1
DT/R/PIO4
71
PCS6/A2/PIO2
82
WHB
65
3
GND
12
RD
29
WLB
66
5
GND
35
RES
94
WR
28
7
GND
41
RTS0/RTR0/PIO20
26
X1
36
9
GND
64
RXD0/PIO23
24
X2
37
D
R
MCS3/RAS1/PIO25
NMI
PCS0/PIO16
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
AD11
AD3
AD10
AD2
AD9
85
83
81
AD12
AD4
87
AD1
AD8
AD0
47
NMI
DT/R
50
46
SRDY
49
45
HOLD
DRQ0/INT5
DRQ1/INT6
TMRIN0
TMROUT0
TMROUT1
TMRIN1
RES
GND
MCS3/RAS1
MCS2/LCAS
VCC
PCS0
PCS1
GND
PCS2/CTS1/ENRX1
PCS3/RTS1/RTR1
VCC
PCS5/A1
PCS6/A2
LCS/ONCE0/RAS0
UCS/ONCE1
INT0
INT1/SELECT
INT2/INTA0/PWD
INT3/INTA1/IRQ
INT4
MCS1/UCAS
DEN/DS
MCS0
44
HLDA
48
43
WHB
WLB
42
41
40
VCC
A1
A0
GND
39
38
A2
82
GND
AD5
89
84
AD13
90
86
VCC
AD6
92
88
AD7
AD14
94
91
AD15
95
93
S6/CLKDIV2
96
97
98
CTS0/ENRX0
RXD1
TXD1
UZI
99
D
37
A9
R
36
A19
A18
V CC
A17
A16
A15
A14
A13
A12
A11
A10
A
A3
CLKOUTB
GND
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
T
F
Am186ED/EDLV Microcontrollers
A4
V CC
CLKOUTA
35
X1
X2
34
S0
GND
A5
S2/BTSEL
S1
33
ARDY
A6
RD
ALE
32
BHE/ADEN
WR
31
TXD0
RTS0/RTR0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A8
A7
RXD0
100
PQFP CONNECTION DIAGRAMS AND PINOUTS
Am186ED/EDLV Microcontrollers
Top Side View—100-Pin Plastic Quad Flat Pack (PQFP)
Note:
Pin 1 is marked for orientation.
Am186ED/EDLV Microcontrollers
17
P R E L I M I N A R Y
PQFP PIN DESIGNATIONS—Am186ED/EDLV Microcontrollers
Sorted by Pin Number
Pin No.
18
Name
Pin No.
Name
Pin No.
Name
Pin No.
Name
1
RXD0/PIO23
26
A13
51
MCS1/UCAS/PIO15
76
DRQ1/INT6/PIO13
2
TXD0/PIO22
27
A12
52
INT4/PIO30
77
DRQ0/INT5/PIO12
3
RTS0/RTR0/
PIO20
28
A11
53
INT3/INTA1/IRQ
78
AD0
4
BHE/ADEN
29
A10
54
INT2/INTA0/PWD/
PIO31
79
AD8
5
WR
30
A9
55
INT1/SELECT
80
AD1
6
RD
31
A8
56
INT0
81
AD9
7
ALE
32
A7
57
UCS/ONCE1
82
AD2
8
ARDY
33
A6
58
LCS/ONCE0/RAS0
83
AD10
9
S2/BTSEL
34
A5
59
PCS6/A2/PIO2
10
S1
35
A4
60
PCS5/A1/PIO3
11
S0
36
A3
61
VCC
12
GND
37
A2
62
13
X1
38
VCC
63
14
X2
39
A1
15
VCC
40
A0
16
CLKOUTA
41
GND
17
CLKOUTB
42
WHB
18
GND
43
19
A19/PIO9
44
20
A18/PIO8
45
HOLD
A
21
VCC
46
22
A17/PIO7
47
23
A16
48
24
A15
25
A14
D
T
F
84
AD3
85
AD11
86
AD4
PCS3/RTS1/RTR1/
PIO19
87
AD12
PCS2/CTS1/
ENRX1/PIO18
88
AD5
89
GND
90
AD13
91
AD6
64
GND
65
PCS1/PIO17
66
PCS0/PIO16
67
VCC
92
VCC
68
MCS2/LCAS/PIO24
93
AD14
69
MCS3/RAS1/PIO25
94
AD7
70
GND
95
AD15
SRDY/PIO6
71
RES
96
S6/CLKDIV2/PIO29
NMI
72
TMRIN1/PIO0
97
UZI/PIO26
DT/R/PIO4
73
TMROUT1/PIO1
98
TXD1/PIO27
49
DEN/DS/PIO5
74
TMROUT0/PIO10
99
RXD1/PIO28
50
MCS0/PIO14
75
TMRIN0/PIO11
100
CTS0/ENRX0/PIO21
R
WLB
HLDA
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
PQFP PIN DESIGNATIONS—Am186ED/EDLV Microcontrollers
Sorted by Pin Name
Pin Name
No.
Pin Name
No.
Pin Name
No.
Pin Name
No.
A0
40
AD5
88
GND
70
RXD1/PIO28
99
A1
39
AD6
91
GND
89
S0
11
A2
37
AD7
94
HLDA
44
S1
10
A3
36
AD8
79
HOLD
45
S2/BTSEL
9
A4
35
AD9
81
INT0
56
S6/CLKDIV2/
PIO29
96
A5
34
AD10
83
INT1/SELECT
55
SRDY/PIO6
46
A6
33
AD11
85
INT2/INTA0/
PWD/PIO31
54
TMRIN0/PIO11
75
A7
32
AD12
87
INT3/INTA1/IRQ
53
TMRIN1/PIO0
72
A8
31
AD13
90
INT4/PIO30
A9
30
AD14
93
LCS/ONCE0/RAS0
A10
29
AD15
95
MCS0/PIO14
A11
28
ALE
7
MCS1/UCAS/PIO15
A12
27
ARDY
8
MCS2/LCAS/PIO24
A13
26
BHE/ADEN
4
MCS3/RAS1/PIO25
A14
25
CLKOUTA
16
NMI
A15
24
CLKOUTB
17
PCS0/PIO16
A16
23
CTS0/ENRX0/
PIO21
100
PCS1/PIO17
A17/PIO7
22
DEN/DS/PIO5
49
A18/PIO8
20
DRQ0/INT5/PIO12
A19/PIO9
AD0
AD1
AD2
AD3
AD4
T
F
52
TMROUT0/
PIO10
74
58
TMROUT1/PIO1
73
50
TXD0/PIO22
2
51
TXD1/PIO27
98
68
UCS/ONCE1
57
69
UZI/PIO26
97
47
VCC
15
66
VCC
21
65
VCC
38
PCS2/CTS1/ENRX1/
PIO18
63
VCC
61
77
PCS3/RTS1/RTR1/
PIO19
62
VCC
67
A
19
DRQ1/INT6/PIO13
76
PCS5/A1/PIO3
60
VCC
92
78
DT/R/PIO4
48
PCS6/A2/PIO2
59
WHB
42
80
GND
R
12
RD
6
WLB
43
82
GND
18
RES
71
WR
5
84
GND
41
RTS0/RTR0/PIO20
3
X1
13
86
GND
64
RXD0/PIO23
1
X2
14
D
Am186ED/EDLV Microcontrollers
19
P R E L I M I N A R Y
LOGIC SYMBOL—Am186ED/EDLV MICROCONTROLLERS
RES
X1
DRQ1/INT6
X2
Clocks
DRQ0/INT5
CLKOUTA
CLKOUTB
INT4
*
INT3/INTA1/IRQ
Reset Control and
Interrupt Service
INT2/INTA0/PWD
*
20
A19–A0
16
AD15–AD0
*
INT1/SELECT
INT0
Address and
Address/Data Buses
*
S6/CLKDIV2
*
UZI
PCS6/A2
*
ALE
PCS5/A1
*
PCS3/RTS1/RTR1
*
S2/BTSEL
2
S1–S0
PCS1–PCS0
HLDA
LCS/ONCE0/RAS0
MCS3/RAS1
WR
DT/R
*
DEN/DS
*
ARDY
R
SRDY
*
BHE/ADEN
D
Timer Control
Programmable
I/O Control
A
*
2
*
Memory and
Peripheral Control
*
MCS2/LCAS
*
MCS1/UCAS
*
MCS0
*
UCS/ONCE1
DRQ1/INT6
*
DRQ0/INT5
*
TXD0
*
RXD0
*
CTS0/ENRX0
*
RTS0/RTR0
*
TXD1
*
RXD1
*
PCS2/CTS1/ENRX1
*
PCS3/RTS1/RTR1
*
DMA Control
WHB
WLB
*
TMRIN0
*
TMROUT0
*
TMRIN1
*
TMROUT1
32
shared
**
T
F
PCS2/CTS1/ENRX1
HOLD
RD
Bus Control
NMI
PIO32–PIO0
Asynchronous
Serial Port Control
Notes:
* These signals are the normal function of a pin that can be used as a PIO. See Pin Descriptions beginning on page 21 and
Table 2 on page 29 for information on shared function.
** All PIO signals are shared with other physical pins.
20
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
PIN DESCRIPTIONS
Pins That Are Used by Emulators
The following pins are used by emulators: A19–A0,
AD7–AD0, ALE, BHE/ADEN, CLKOUTA, RD, S2–S0,
S6/CLKDIV2, and UZI.
Many emulators require S6/CLKDIV2 and UZI to be
configured in their normal functionality as S6 and UZI,
not as PIOs. If BHE/ADEN is held Low during the rising
edge of RES, S6 and UZI are configured in their normal
functionality.
Pin Terminology
The following terms are used to describe the pins:
Input—An input-only pin.
Output—An output-only pin.
Input/Output—A pin that can be either input or output
(I/O).
Synchronous—Synchronous inputs must meet setup
and hold times in relation to CLKOUTA. Synchronous
outputs are synchronous to CLKOUTA.
Asynchronous—Inputs or outputs that are
asynchronous to CLKOUTA.
A19–A0
(A19/PIO9, A18/PIO8, A17/PIO7)
Address Bus (output, three-state, synchronous)
These pins supply nonmultiplexed memory or I/O
addresses to the system one half of a CLKOUTA period
earlier than the multiplexed address and data bus
(AD15–AD0). During a bus hold or reset condition, the
address bus is in a high-impedance state.
R
While the Am186ED/EDLV microcontrollers are directly
connected to DRAM, A19–A0 will serve as the
nonmultiplexed address bus for SRAM, FLASH,
PROM, EPROM, and peripherals. The odd address
pins (A17, A15, A13, A11, A9, A7, A5, A3, and A1) will
have both the row and column address during a DRAM
space access. The odd address signals connect
directly to the row and column multiplexed address bus
of the DRAM. The even address pins (A18, A16, A14,
A12, A10, A8, A6, A4, A2, and A0) and A19 will have
the initial address asserted during the full DRAM
access. These signals will not transition during a
DRAM access.
D
AD15–AD8
Address and Data Bus (input/output, three-state,
synchronous, level-sensitive)
AD15–AD8—These time-multiplexed pins supply
memory or I/O addresses and data to the system. This
bus can supply an address to the system during the
first period of a bus cycle (t1). It supplies data to the
system during the remaining periods of that cycle (t2,
t3, and t4).
The address phase of these pins can be disabled. See
the ADEN description with the BHE/ADEN pin. When
WHB is deasserted, these pins are three-stated during
t2, t3, and t4.
During a bus hold or reset condition, the address and
data bus is in a high-impedance state.
During a power-on reset, the address and data bus
pins (AD15–AD0) can also be used to load system
configuration information into the internal reset
configuration register.
When accesses are made to 8-bit-wide memory
regions, AD15–AD8 drive their corresponding address
signals throughout the access. If the disable address
phase and 8-bit mode are selected (see the ADEN
description with the BHE/ADEN pin), then AD15–AD8
are three-stated during t 1 and driven with their
corresponding address signal from t2 to t4.
AD7–AD0
T
F
Address and Data Bus (input/output, three-state,
synchronous, level-sensitive)
A
These time-multiplexed pins supply partial memory or
I/O addresses, as well as data, to the system. This bus
supplies the low-order 8 bits of an address to the
system during the first period of a bus cycle (t1), and it
supplies data to the system during the remaining
periods of that cycle (t2, t3, and t4). In 8-bit mode, AD7–
AD0 supplies the data for both high and low bytes.
The address phase of these pins can be disabled. See
the ADEN pin description with the BHE/ADEN pin.
When WLB is deasserted, these pins are three-stated
during t2, t3, and t4.
During a bus hold or reset condition, the address and
data bus is in a high-impedance state.
During a power-on reset, the address and data bus
pins (AD15–AD0) can also be used to load system
configuration information into the internal reset
configuration register.
ALE
Address Latch Enable (output, synchronous)
This pin indicates to the system that an address appears on the address and data bus (AD15–AD0). The
address is guaranteed to be valid on the trailing edge
of ALE. This pin is three-stated during ONCE mode.
ALE is three-stated and held resistively Low during a
bus hold condition. In addition, ALE has a weak internal
pulldown resistor that is active during reset, so that an
external device does not get a spurious ALE during
reset.
Am186ED/EDLV Microcontrollers
21
P R E L I M I N A R Y
ARDY
Asynchronous Ready (input, asynchronous,
level-sensitive)
This pin is a true asynchronous ready that indicates to
the microcontroller that the addressed memory space
or I/O device will complete a data transfer. The ARDY
pin is asynchronous to CLKOUTA and is active High.
To guarantee the number of wait states inserted, ARDY
or SRDY must be synchronized to CLKOUTA. If the
falling edge of ARDY is not synchronized to CLKOUTA
as specified, an additional clock period can be added.
To a l w a y s a s s e r t t h e r e a d y c o n d i t i o n t o t h e
microcontroller, tie ARDY High. If the system does not
use ARDY, tie the pin Low to yield control to SRDY.
not drive the address during t1. There is a weak internal
pullup resistor on BHE/ADEN so no external pullup is
required. Disabling the address phase reduces power
consumption.
If BHE/ADEN is held Low on power-on reset, the AD
bus drives both addresses and data, regardless of the
DA bit setting. The pin is sampled on the rising edge of
RE S . ( S 6 an d U Z I a l s o a s s u me th e i r n o r m al
functionality in this instance. See Table 2 on page 29.)
The internal pullup on ADEN is ~9 kohm.
Note: For 8-bit accesses, AD15–AD8 are driven with
addresses during the t2–t4 bus cycle, regardless of the
setting of the DA bit in the UMCS and LMCS registers.
CLKOUTA
BHE/ADEN
Clock Output A (output, synchronous)
Bus High Enable (three-state, output,
synchronous)
Address Enable (input, internal pullup)
This pin supplies the internal clock to the system.
Depending on the value of the system configuration
register (SYSCON), CLKOUTA operates at either the
PLL frequency (X1), the power-save frequency, or is
held Low. CLKOUTA remains active during reset and
bus hold conditions.
BHE—During a memory access, this pin and the leastsignificant address bit (AD0 or A0) indicate to the
system which bytes of the data bus (upper, lower, or
both) participate in a bus cycle. The BHE/ADEN and
AD0 pins are encoded as shown in Table 1.
CLKOUTB
Table 1. Data Byte Encoding
BHE
AD0
Type of Bus Cycle
0
0
Word Transfer
0
1
High Byte Transfer (Bits 15–8)
1
0
Low Byte Transfer (Bits 7–0)
1
1
Reserved
R
BHE is asserted during t 1 and remains asserted
through t3 and tW. BHE does not need to be latched.
BHE floats during bus hold and reset.
D
WLB and WHB implement the functionality of BHE and
AD0 for High and Low byte-write enables. UCAS and
LCAS implement High and Low-byte selection for
DRAM devices.
BHE/ADEN also signals DRAM refresh cycles when
using the multiplexed address and data (AD) bus. A
refresh cycle is indicated when both BHE/ADEN and
AD0 are High. During refresh cycles, the A bus is
indeterminate and the AD bus is driven to FFFFh
during the address phase of the AD bus cycle. For this
reason, the A0 signal cannot be used in place of the
AD0 signal to determine refresh cycles.
ADEN—If BHE/ADEN is held High or left floating
during power-on reset, the address portion of the AD
bus (AD15–AD0) is enabled or disabled during LCS
and UCS bus cycles based on the DA bit in the LMCS
and UMCS registers. If the DA bit is set, the AD bus will
22
T
F
All AC timing specs that use a clock relate to
CLKOUTA.
A
Clock Output B (output, synchronous)
This pin supplies an additional clock with a delayed
output compared to CLKOUTA. Depending upon the
value of the system configuration register (SYSCON),
CLKOUTB operates at either the PLL frequency (X1),
the power-save frequency, or is held Low. CLKOUTB
remains active during reset and bus hold conditions.
CLKOUTB is not used for AC timing specs.
CTS0/ENRX0/PIO21
Clear-to-Send 0 (input, asynchronous)
Enable-Receiver-Request 0 (input, asynchronous)
CTS0—This pin provides the Clear-to-Send signal for
asynchronous serial port 0 when the ENRX0 bit in the
AUXCON register is 0 and hardware flow control is
enabled for the port (FC bit in the serial port 0 control
register is set). The CTS0 signal gates the
transmission of data from the associated serial port
transmit register. When CTS0 is asserted, the
transmitter begins transmission of a frame of data, if
any is available. If CTS0 is deasserted, the transmitter
holds the data in the serial port transmit register. The
value of CTS0 is checked only at the beginning of the
transmission of the frame.
ENRX0—This pin provides the Enable Receiver
Request for asynchronous serial port 0 when the
ENRX0 bit in the AUXCON register is 1 and hardware
flow control is enabled for the port (FC bit in the serial
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
port 0 control register is set). The ENRX0 signal
enables the receiver for the associated serial port.
INT6 is edge-triggered only and must be held until the
interrupt is acknowledged.
DEN/DS/PIO5
DT/R/PIO4
Data Enable (output, three-state, synchronous)
Data Strobe (output, three-state, synchronous)
Data Transmit or Receive (output, three-state,
synchronous)
DEN—This pin supplies an output enable to an
external data-bus transceiver. DEN is asserted during
memory, I/O, and interrupt acknowledge cycles. DEN is
deasserted when DT/R changes state. DEN floats
during a bus hold or reset condition.
This pin indicates in which direction data should flow
through an external data-bus transceiver. When DT/R
is asserted High, the microcontroller transmits data.
When this pin is deasserted Low, the microcontroller
receives data. DT/R floats during a bus hold or reset
condition.
DS—The data strobe provides a signal where the write
cycle timing is identical to the read cycle timing. When
used with other control signals, DS provides an
interface for 68K-type peripherals without the need for
additional system interface logic.
When DS is asserted, addresses are valid. When DS is
asserted on writes, data is valid. When DS is asserted
on reads, data can be asserted on the AD bus.
Note: This pin resets to DEN.
DRQ0/INT5/PIO12
DMA Request 0 (input, synchronous,
level-sensitive)
Maskable Interrupt Request 5 (input,
asynchronous, edge-triggered)
DRQ0—This pin indicates to the microcontroller that an
external device is ready for DMA channel 0 to perform
a transfer. DRQ0 is level-triggered and internally
synchronized. DRQ0 is not latched and must remain
active until serviced.
R
INT5—If DMA 0 is not enabled or DMA 0 is not being
used with external synchronization, INT5 can be used
as an additional external interrupt request. INT5 shares
the DMA 0 interrupt type (0Ah) and register control bits.
D
INT5 is edge-triggered only and must be held until the
interrupt is acknowledged.
DRQ1/INT6/PIO13
DMA Request 1 (input, synchronous,
level-sensitive)
Maskable Interrupt Request 6 (input,
asynchronous, edge-triggered)
DRQ1—This pin indicates to the microcontroller that an
external device is ready for DMA channel 1 to perform
a transfer. DRQ1 is level-triggered and internally
synchronized. DRQ1 is not latched and must remain
active until serviced.
INT6—If DMA 1 is not enabled or DMA 1 is not being
used with external synchronization, INT6 can be used
as an additional external interrupt request. INT6 shares
the DMA 1 interrupt type (0Bh) and register control bits.
GND
Ground
Ground pins connect the microcontroller to the system
ground.
HLDA
T
F
Bus Hold Acknowledge (output, synchronous)
This pin is asserted High to indicate to an external bus
master that the microcontroller has released control of
the local bus. When an external bus master requests
control of the local bus (by asserting HOLD), the
microcontroller completes the bus cycle in progress. It
then relinquishes control of the bus to the external bus
master by asserting HLDA and floating DEN, RD, WR,
S2–S0, AD15–AD0, S6, A19–A0, BHE, WHB, WLB,
and DT/R. The following chip selects are three-stated
(then will be held High with an ~10-kohm resistor):
UCS, LCS, MCS3–MCS0, PCS6–PCS5, PCS3–PCS0,
RAS0, RAS1, UCAS, and LCAS. ALE is also threestated (then will be held Low with an ~10-kohm
resistor).
A
When the external bus master has finished using the
local bus, it indicates this to the microcontroller by
deasserting HOLD. The microcontroller responds by
deasserting HLDA.
If the microcontroller requires access to the bus (for
example, to refresh), it will deassert HLDA before the
external bus master deasserts HOLD. The external bus
master must be able to deassert HOLD and allow the
microcontroller access to the bus. See the timing
diagrams for bus hold on page 86.
HOLD
Bus Hold Request (input, synchronous,
level-sensitive)
This pin indicates to the microcontroller that an external
bus master needs control of the local bus.
The Am186ED/EDLV microcontrollers’ HOLD latency
time, that is, the time between HOLD request and
HOLD acknowledge, is a function of the activity occurring in the processor when the HOLD request is received. A HOLD request is second only to DRAM
Am186ED/EDLV Microcontrollers
23
P R E L I M I N A R Y
refresh requests in priority of activity requests received
by the processor.
For more information, see the HLDA pin description on
page 23.
INT0
Maskable Interrupt Request 0 (input,
asynchronous)
This pin indicates to the microcontroller that an
interrupt request has occurred. If the INT0 pin is not
masked, the microcontroller transfers program
execution to the location specified by the INT0 vector in
the microcontroller interrupt vector table.
Interrupt requests are synchronized internally and can
be edge-triggered or level-triggered. To guarantee
interrupt recognition, the requesting device must
continue asserting INT0 until the request is
acknowledged.
INT1/SELECT
Maskable Interrupt Request 1 (input,
asynchronous)
Slave Select (input, asynchronous)
INT1—This pin indicates to the microcontroller that an
interrupt request has occurred. If INT1 is not masked,
the microcontroller transfers program execution to the
location specified by the INT1 vector in the
microcontroller interrupt vector table.
Interrupt requests are synchronized internally and can
be edge-triggered or level-triggered. To guarantee
interrupt recognition, the requesting device must
continue asserting INT1 until the request is
acknowledged.
R
SELECT—When the microcontroller interrupt control
unit is operating as a slave to an external interrupt
controller, this pin indicates to the microcontroller that
an interrupt type appears on the address and data bus.
The INT0 pin must indicate to the microcontroller that
an interrupt has occurred before the SELECT pin
indicates to the microcontroller that the interrupt type
appears on the bus.
D
INT2/INTA0/PWD/PIO31
Maskable Interrupt Request 2 (input,
asynchronous)
Interrupt Acknowledge 0 (output, synchronous)
Pulse Width Demodulator (input, Schmitt trigger)
INT2—This pin indicates to the microcontroller that an
interrupt request has occurred. If the INT2 pin is not
masked, the microcontroller transfers program
execution to the location specified by the INT2 vector in
the microcontroller interrupt vector table.
Interrupt requests are synchronized internally and can
be edge-triggered or level-triggered. To guarantee
24
interrupt recognition, the requesting device must
continue asserting INT2 until the request is
acknowledged. INT2 becomes INTA0 when INT0 is
configured in cascade mode.
INTA0—When the microcontroller interrupt control unit
is operating in cascade mode, this pin indicates to the
system that the microcontroller needs an interrupt type
to process the interrupt request on INT0. The
peripheral issuing the interrupt request must provide
the microcontroller with the corresponding interrupt
type.
PWD—If pulse width demodulation is enabled, PWD
processes a signal through the Schmitt trigger. PWD is
used internally to drive TIMERIN0 and INT2, and PWD
is inverted internally to drive TIMERIN1 and INT4. If
INT2 and INT4 are enabled and timer 0 and timer 1 are
properly configured, the pulse width of the alternating
PWD signal can be calculated by comparing the values
in timer 0 and timer 1.
T
F
In PW D mo de, th e s i gn al s TIM ER IN0 /P IO 11 ,
TIMERIN1/PIO0, and INT4/PIO30 can be used as
PIOs. If they are not used as PIOs, they are ignored
internally. The level of INT2/INTA0/PWD/PIO31 is
reflected in the PIO data register for PIO31 as if it was
a PIO.
A
INT3/INTA1/IRQ
Maskable Interrupt Request 3
(input, asynchronous)
Interrupt Acknowledge 1 (output, synchronous)
Slave Interrupt Request (output, synchronous)
INT3—This pin indicates to the microcontroller that an
interrupt request has occurred. If the INT3 pin is not
masked, the microcontroller then transfers program
execution to the location specified by the INT3 vector in
the microcontroller interrupt vector table.
Interrupt requests are synchronized internally, and can
be edge-triggered or level-triggered. To guarantee
interrupt recognition, the requesting device must
continue asserting INT3 until the request is
acknowledged. INT3 becomes INTA1 when INT1 is
configured in cascade mode.
INTA1—When the microcontroller interrupt control unit
is operating in cascade mode, this pin indicates to the
system that the microcontroller needs an interrupt type
to process the interrupt request on INT1. The
peripheral issuing the interrupt request must provide
the microcontroller with the corresponding interrupt
type.
IRQ—When the microcontroller interrupt control unit is
operating as a slave to an external master interrupt
controller, this pin lets the microcontroller issue an
interrupt request to the external master interrupt
controller.
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
INT4/PIO30
MCS0/PIO14
Maskable Interrupt Request 4 (input,
asynchronous)
Midrange Memory Chip Select 0 (output,
synchronous, internal pullup)
This pin indicates to the microcontroller that an
interrupt request has occurred. If the INT4 pin is not
masked, the microcontroller then transfers program
execution to the location specified by the INT4 vector in
the microcontroller interrupt vector table.
This pin indicates to the system that a memory access
is in progress to the corresponding region of the
midrange memory block. The base address and size of
the midrange memory block are programmable. MCS0
can be programmed as the chip select for the entire
middle chip select address range. This mode is
recommended when using DRAM since the MCS1,
MCS2, and MCS3 chip selects function as RAS and
CAS signals for the DRAM interface and are not
available as chip selects.
Interrupt requests are synchronized internally, and can
be edge-triggered or level-triggered. To guarantee
interrupt recognition, the requesting device must
continue asserting INT4 until the request is
acknowledged.
When pulse width demodulation mode is enabled, the
INT4 signal is used internally to indicate a High-to-Low
transition on the PWD signal. When pulse width
demodulation mode is enabled, INT4/PIO30 can be
used as a PIO.
T
F
MCS1/UCAS/PIO15
LCS/ONCE0/RAS0
Lower Memory Chip Select (output, synchronous,
internal pullup)
ONCE Mode Request 0 (input)
Row Address Strobe 0
LCS—This pin indicates to the system that a memory
access is in progress to the lower memory block. The
base address and size of the lower memory block are
programmable up to 512 Kbytes. LCS is configured for
8-bit or 16-bit bus size by the auxiliary configuration
register.
R
LCS is three-stated and held resistively High during a
bus hold condition. In addition, LCS has an ~9-kohm
internal pullup resistor that is active during reset.
ONCE0—During reset, this pin and ONCE1 indicate to
the microcontroller the mode in which it should operate.
ONCE0 and ONCE1 are sampled on the rising edge of
RES. If both pins are asserted Low, the microcontroller
enters ONCE mode; otherwise, it operates normally.
D
MCS0 is configured for 8-bit or 16-bit bus size by the
auxiliary configuration register. MCS0 is three-stated
and held resistively High during a bus hold condition. In
addition, MCS0 has a weak internal pullup resistor that
is active during reset.
In ONCE mode, all pins assume a high-impedance
state and remain in that state until a subsequent reset
occurs. To guarantee that the microcontroller does not
inadvertently enter ONCE mode, ONCE0 has a weak
internal pullup resistor that is active only during reset.
RAS0—This pin is the row address strobe for the lower
DR A M b l o c k . T h e s el e c t i o n o f R A S 0 o r L C S
functionality, along with their configurations, are set
using the LMCS register.
RAS0 is three-stated and held resistively High during a
bus hold condition. In addition, RAS0 has a weak
internal pullup resistor that is active during reset.
Midrange Memory Chip Select (output,
synchronous, internal pullup)
Upper Column Address Strobe
This pin indicates to the system that a memory access
is in progress to the corresponding region of the
midrange memory block. The base address and size of
the midrange memory block are programmable. MCS1
is configured for 8-bit or 16-bit bus size via the auxiliary
configuration register.
A
MCS1 is three-stated and held resistively High during a
bus hold condition. In addition, MCS1 has a weak
internal pullup resistor that is active during reset.
If MCS0 is programmed to be active for the entire
middle chip-select range, then this signal is available
as a PIO or a DRAM control. If this signal is not
programmed as a PIO or DRAM control and if MCS0 is
programmed for the entire middle chip-select range,
this signal operates normally.
UCAS—When either bank of DRAM is activated, the
UCAS functionality is enabled. The UCAS activates
when the DRAM access is for the AD15–AD8 byte.
UCAS also activates at the start of a DRAM refresh
access.
UCAS is three-stated and held resistively High during a
bus hold condition. In addition, UCAS has a weak
internal pullup resistor that is active during reset.
MCS2/LCAS/PIO24
Midrange Memory Chip Select (output,
synchronous, internal pullup)
Lower Column Address Strobe
This pin indicates to the system that a memory access
is in progress to the corresponding region of the
midrange memory block. The base address and size of
Am186ED/EDLV Microcontrollers
25
P R E L I M I N A R Y
the midrange memory block are programmable. MCS2
is configured for 8-bit or 16-bit bus size via the auxiliary
configuration register.
NMI
MCS2 is three-stated and held resistively High during a
bus hold condition. In addition, it has a weak internal
pullup resistor that is active during reset.
This pin indicates to the microcontroller that an
interrupt request has occurred. The NMI signal is the
highest priority hardware interrupt and, unlike the
INT6–INT0 pins, cannot be masked. The
microcontroller always transfers program execution to
the location specified by the nonmaskable interrupt
vector in the microcontroller interrupt vector table when
NMI is asserted.
If MCS0 is programmed to be active for the entire
middle chip-select range, then this signal is available
as a PIO or a DRAM control. If this pin is not
programmed as a PIO or DRAM control and if MCS0 is
programmed for the whole middle chip-select range,
this signal operates normally.
LCAS—When either bank of DRAM is activated, the
LCAS functionality is enabled. The LCAS activates
when the DRAM access is for the AD7–AD0 byte.
LCAS also activates at the start of a DRAM refresh
access.
LCAS is three-stated and held resistively High during a
bus hold condition. In addition, LCAS has a weak
internal pullup resistor that is active during reset.
MCS3/RAS1/PIO25
Midrange Memory Chip Select 3
(output, synchronous, internal pullup)
Row Address Strobe 1 (output, synchronous)
MCS3—This pin indicates to the system that a memory
access is in progress to the fourth region of the
midrange memory block. The base address and size of
the mid-range memory block are programmable.
MCS3 is configured for 8-bit or 16-bit bus size by the
auxiliary configuration register.
R
MCS3 is three-stated and held resistively High during a
bus hold condition. In addition, this pin has a weak
internal pullup resistor that is active during reset.
D
If MCS0 is programmed for the entire middle chipselect range, then this signal is available as a PIO or a
DRAM control. If MCS3 is not programmed as a PIO or
DRAM control and if MCS0 is programmed for the
entire middle chip-select range, this signal operates
normally.
RAS1—This pin is the row address strobe for the upper
DR AM b l oc k . T h e se l ec t i on o f R A S 1 o r U CS
functionality, along with their configurations, are set
using the UMCS register. When RAS1 is activated, the
code activating RAS1 must not reside in the UCS
memory block. When RAS1 is activated, UCS is
automatically deactivated and remains negated.
RAS1 is three-stated and held resistively High during a
bus hold condition. In addition, RAS1 has a weak
internal pullup resistor that is active during reset.
26
Nonmaskable Interrupt (input, synchronous,
edge-sensitive)
Although NMI is the highest priority interrupt source, it
does not participate in the priority resolution process of
the maskable interrupts. There is no bit associated with
NMI in the interrupt in-service or interrupt request
registers. This means that a new NMI request can
interrupt an executing NMI interrupt service routine. As
with all hardware interrupts, the IF (interrupt flag) is
cleared when the processor takes the interrupt,
disabling the maskable interrupt sources. However, if
maskable interrupts are re-enabled by software in the
NMI interrupt service routine, via the STI instruction for
example, the fact that an NMI is currently in service
does not have any effect on the priority resolution of
maskable interrupt requests. For this reason, it is
strongly advised that the interrupt service routine for
NMI should not enable the maskable interrupts.
A
T
F
An NMI transition from Low to High is latched and
synchronized internally, and it initiates the interrupt at
the next instruction boundary. To guarantee that the
interrupt is recognized, the NMI pin must be asserted
for at least one CLKOUTA period.
PCS1/PIO17, PCS0/PIO16
Peripheral Chip Selects (output, synchronous)
These pins indicate to the system that a memory
access is in progress to the corresponding region of the
peripheral memory block (either I/O or memory
address space). The base address of the peripheral
memory block is programmable.
The PCS chip selects can overlap either block of
DRAM. The PCS chip selects must have the same or
greater number of wait states as the bank of DRAM
they overlap. The PCS signals take precedence over
DRAM accesses when DRAM and memory-mapped
peripherals overlap.
PCS1–PCS0 are three-stated and held resistively High
during a bus hold condition. In addition, PCS1–PCS0
each have a weak internal pullup resistor that is active
during reset.
Unlike the UCS and LCS chip selects, the PCS outputs
assert with the multiplexed AD address bus. Note also
that each peripheral chip select asserts over a 256byte address range, which is twice the address range
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
covered by peripheral chip selects in the 80C186 and
80C188 microcontrollers. PCS0–PCS1 also have
extended wait state options.
PCS2/CTS1/ENRX1/PIO18
Peripheral Chip Select 2 (output, synchronous)
Clear-to-Send 1 (input, asynchronous)
Enable-Receiver-Request 1 (input, asynchronous)
PCS2—This pin provides the Peripheral Chip Select 2
signal to the system when hardware flow control is not
enabled for asynchronous serial port 1. The PCS2
signal indicates to the system that a memory access is
in progress to the corresponding region of the
peripheral memory block (either I/O or memory
address space). The base address of the peripheral
memory block is programmable.
The PCS chip selects can overlap either block of
DRAM. The PCS chip selects must have the same or
greater number of wait states as the bank of DRAM
they overlap. The PCS signals take precedence over
DRAM accesses when DRAM and memory-mapped
peripherals overlap.
PCS2 is three-stated and held resistively High during a
bus hold condition. In addition, PCS2 has a weak
internal pullup resistor that is active during reset.
Unlike the UCS and LCS chip selects, the PCS outputs
assert with the multiplexed AD address bus. Note also
that each peripheral chip select asserts over a 256byte address range, which is twice the address range
covered by peripheral chip selects in the 80C186 and
80C188 microcontrollers. PCS2 also has extended
wait state options.
R
CTS1—This pin provides the Clear-to-Send signal for
asynchronous serial port 1 when the ENRX1 bit in the
AUXCON register is 0 and hardware flow control is
enabled for the port (FC bit in the serial port 1 control
register is set). The CTS1 signal gates the
transmission of data from the associated serial port
transmit register. When CTS1 is asserted, the
transmitter begins transmission of a frame of data, if
any is available. If CTS1 is deasserted, the transmitter
holds the data in the serial port transmit register. The
value of CTS1 is checked only at the beginning of the
transmission of the frame.
D
ENRX1—This pin provides the Enable Receiver
Request for asynchronous serial port 1 when the
ENRX1 bit in the AUXCON register is 1 and hardware
flow control is enabled for the port (FC bit in the serial
port 1 control register is set). The ENRX1 signal
enables the receiver for the associated serial port.
PCS3/RTS1/RTR1/PIO19
Peripheral Chip Select 3 (output, synchronous)
Ready-to-Send 1 (output, asynchronous)
Ready-to-Receive 1 (output, asynchronous)
PCS3—This pin provides the Peripheral Chip Select 3
signal to the system when hardware flow control is not
enabled for asynchronous serial port 1. The PCS3
signal indicates to the system that a memory access is
in progress to the corresponding region of the
peripheral memory block (either I/O or memory
address space). The base address of the peripheral
memory block is programmable.
The PCS chip selects can overlap either block of
DRAM. The PCS chip selects must have the same or
greater number of wait states as the bank of DRAM
they overlap. The PCS signals take precedence over
DRAM accesses when DRAM and memory-mapped
peripherals overlap.
T
F
PCS3 is three-stated and held resistively High during a
bus hold condition. In addition, PCS3 has a weak
internal pullup resistor that is active during reset.
Unlike the UCS and LCS chip selects, the PCS outputs
assert with the multiplexed AD address bus. Note also
that each peripheral chip select asserts over a 256byte address range, which is twice the address range
covered by peripheral chip selects in the 80C186 and
80C188 microcontrollers. PCS3 also has extended
wait state options.
A
RTS1—This pin provides the Ready-to-Send signal for
asynchronous serial port 1 when the RTS1 bit in the
AUXCON register is 1 and hardware flow control is
enabled for the port (FC bit in the serial port 1 control
register is set). The RTS1 signal is asserted when the
associated serial port transmit register contains data
which has not been transmitted.
RTR1—This pin provides the Ready-to-Receive signal
for asynchronous serial port 1 when the RTS1 bit in the
AUXCON register is 0 and hardware flow control is
enabled for the port (FC bit in the serial port 1 control
register is set). The RTR1 signal is asserted when the
associated serial port receive register does not contain
valid, unread data.
PCS5/A1/PIO3
Peripheral Chip Select 5 (output, synchronous)
Latched Address Bit 1 (output, synchronous)
PCS5—This pin indicates to the system that a memory
access is in progress to the sixth region of the
peripheral memory block (either I/O or memory
address space). The base address of the peripheral
memory block is programmable.
The PCS chip selects can overlap either block of
DRAM. The PCS chip selects must have the same or
greater number of wait states as the bank of DRAM
Am186ED/EDLV Microcontrollers
27
P R E L I M I N A R Y
they overlap. The PCS signals take precedence over
DRAM accesses when DRAM and memory-mapped
peripherals overlap.
PCS5 is three-stated and held resistively High during a
bus hold condition. In addition, PCS5 has a weak
internal pullup resistor that is active during reset.
Unlike the UCS and LCS chip selects, the PCS outputs
assert with the multiplexed AD address bus. Note also
that each peripheral chip select asserts over a 256byte address range, which is twice the address range
covered by peripheral chip selects in the 80C186 and
80C188 microcontrollers. PCS5 also has extended
wait state options.
A1—When the EX bit in the MCS and PCS auxiliary
register is 0, this pin supplies an internally latched
address bit 1 to the system. During a bus hold
condition, A1 retains its previously latched value.
PCS6/A2/PIO2
After power-on reset, the PIO pins default to various
configurations. The column titled Power-On Reset
Status in Table 2 and Table 3 lists the defaults for the
PIOs. Most of the PIO pins are configured as PIO
inputs with pullup after power-on reset. The system
initialization code must reconfigure any PIO pins as
required.
The A19–A17 address pins default to normal operation
on power-on reset, allowing the processor to correctly
begin fetching instructions at the boot address
FFFF0h. The DT/R, DEN, and SRDY pins also default
to normal operation on power-on reset. PIO15 and
PIO24 should be set to normal operation before
enabling either bank of DRAM. PIO25 should be set to
normal operation before enabling the upper bank of
DRAM.
RD
Peripheral Chip Select 6 (output, synchronous)
Latched Address Bit 2 (output, synchronous)
PCS6—This pin indicates to the system that a memory
access is in progress to the seventh region of the
peripheral memory block (either I/O or memory
address space). The base address of the peripheral
memory block is programmable.
The PCS chip selects can overlap either block of
DRAM. The PCS chip selects must have the same or
greater number of wait states as the bank of DRAM
they overlap. The PCS signals take precedence over
DRAM accesses when DRAM and memory-mapped
peripherals overlap.
R
PCS6 is three-stated and held resistively High during a
bus hold condition. In addition, PCS6 has a weak
internal pullup resistor that is active during reset.
D
pullup or pulldown. The pins that are multiplexed with
PIO31–PIO0 are listed in Table 2 and Table 3.
Unlike the UCS and LCS chip selects, the PCS outputs
assert with the multiplexed AD address bus. Note also
that each peripheral chip select asserts over a 256byte address range, which is twice the address range
covered by peripheral chip selects in the 80C186 and
80C188 microcontrollers. PCS6 also has extended
wait state options.
A2—When the EX bit in the MCS and PCS auxiliary
register is 0, this pin supplies an internally latched
address bit 2 to the system. During a bus hold
condition, A2 retains its previously latched value.
RD—This pin indicates to the system that the
microcontroller is performing a memory or I/O read
cycle. RD is guaranteed to not be asserted before the
address and data bus is floated during the address-todata transition. RD floats during a bus hold condition.
A
RES
Reset (input, asynchronous, level-sensitive)
This pin requires the microcontroller to perform a reset.
When RES is asserted, the microcontroller
immediately terminates its present activity, clears its
internal logic, and transfers CPU control to the reset
address, FFFF0h.
RES must be held Low for at least 1 ms.
RES can be asserted asynchronously to CLKOUTA
because RES is synchronized internally. For proper
initialization, VCC must be within specifications, and
CLK O UTA mu st b e s tab le fo r m or e th an fo ur
CLKOUTA periods during which RES is asserted.
The microcontroller begins fetching instructions
approximately 6.5 CLKOUTA periods after RES is
deasserted. This input is provided with a Schmitt
trigger to facilitate power-on RES generation via an RC
network.
PIO31–PIO0 (Shared)
Programmable I/O Pins (input/output,
asynchronous, open-drain)
The Am186ED/EDLV microcontrollers provide 32
individually programmable I/O pins. Each PIO can be
programmed with the following attributes: PIO function
(enabled/disabled), direction (input/output), and weak
28
T
F
Read Strobe (output, synchronous, three-state)
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
Table 2. Numeric PIO Pin Designations
PIO No
Associated Pin
Power-On Reset Status
Table 3.
Alphabetic PIO Pin Designations
Associated Pin
PIO No Power-On Reset Status
(1)
7
Normal operation(3)
0
TMRIN1
Input with pullup
A17
1
TMROUT1
Input with pulldown
A18(1)
8
Normal operation(3)
(1)
9
Normal operation(3)
CTS0/ENRX0
21
Input with pullup
2
PCS6/A2
Input with pullup
3
PCS5/A1
Input with pullup
A19
4
DT/R
Normal operation
DEN/DS
5
Normal operation(3)
5
DEN/DS
Normal operation(3)
DRQ0/INT5
12
Input with pullup
(4)
DRQ1/INT6
13
Input with pullup
(3)
6
SRDY
(3)
Normal operation
(1)
A17
Normal operation
DT/R
4
Normal operation(3)
8(1)
A18
Normal operation(3)
INT2/INTA0/PWD
31
Input with pullup
9(1)
A19
Normal operation(3)
INT4
30
Input with pullup
10
TMROUT0
Input with pulldown
MCS0
14
Input with pullup
11
TMRIN0
Input with pullup
MCS1/UCAS
15
Input with pullup
12
DRQ0/INT5
Input with pullup
MCS2/LCAS
13
DRQ1/INT6
Input with pullup
MCS3/RAS1
14
MCS0
Input with pullup
PCS0
15
MCS1/UCAS
Input with pullup
PCS1
16
PCS0
Input with pullup
17
PCS1
Input with pullup
18
PCS2/CTS1/ENRX1 Input with pullup
PCS5/A1
19
PCS3/RTS1/RTR1
Input with pullup
7
Input with pullup
25
Input with pullup
16
Input with pullup
17
Input with pullup
PCS2/CTS1/ENRX1
18
Input with pullup
PCS3/RTS1/RTR1
19
Input with pullup
3
Input with pullup
2
Input with pullup
20
Input with pullup
23
Input with pullup
28
Input with pullup
S6/CLKDIV2
29
Input with pullup
SRDY
6
Normal operation(4)
TMRIN0
11
Input with pullup
TMRIN1
0
Input with pullup
Input with pullup
TMROUT0
10
Input with pulldown
20
RTS0/RTR0
Input with pullup
21
CTS0/ENRX0
Input with pullup
22
TXD0
Input with pullup
R
23
RXD0
Input with pullup
24
MCS2/LCAS
Input with pullup
25
MCS3/RAS1
Input with pullup
UZI
Input with pullup
(1,2)
26
D
T
F
24
A
PCS6/A2
RTS0/RTR0
RXD0
RXD1
(1,2)
27
TXD1
28
RXD1
Input with pullup
TMROUT1
1
Input with pulldown
S6/CLKDIV2
Input with pullup
TXD0
22
Input with pullup
INT4
Input with pullup
TXD1
27
Input with pullup
26
Input with pullup
29(1,2)
30
31
Notes:
INT2/INTA0/PWD
Input with pullup
UZI
(1,2)
The following notes apply to both tables.
1. These pins are used by many emulators. (Emulators also use S2–S0, RES, NMI, CLKOUTA, BHE, ALE, AD15–
AD0, and A16–A0.)
2. These pins revert to normal operation if BHE/ADEN is held Low during power-on reset.
3. When used as a PIO, input with pullup option available.
4. When used as a PIO, input with pulldown option available.
Am186ED/EDLV Microcontrollers
29
P R E L I M I N A R Y
RTS0/RTR0/PIO20
S1–S0
Ready-to-Send 0 (output, asynchronous)
Ready-to-Receive 0 (output, asynchronous)
Bus Cycle Status (output, three-state,
synchronous)
RTS0—This pin provides the Ready-to-Send signal for
asynchronous serial port 0 when the RTS0 bit in the
AUXCON register is 1 and hardware flow control is
enabled for the port (FC bit in the serial port 0 control
register is set). The RTS0 signal is asserted when the
associated serial port transmit register contains data
that has not been transmitted.
These pins indicate to the system the type of bus cycle
in progress. S1 can be used as a data transmit or
receive indicator. S1–S0 float during bus hold and hold
acknowledge conditions. The S2–S0 pins are encoded
as shown in Table 4.
RTR0—This pin provides the Ready-to-Receive signal
for asynchronous serial port 0 when the RTS0 bit in the
AUXCON register is 0 and hardware flow control is
enabled for the port (FC bit in the serial port 0 control
register is set). The RTR0 signal is asserted when the
associated serial port receive register does not contain
valid, unread data.
Table 4.
Bus Cycle Encoding
S2/BTSEL
S1
S0
0
0
0
Interrupt acknowledge
0
0
1
Read data from I/O
0
1
0
Write data to I/O
0
1
1
Halt
RXD0/PIO23
1
0
0
Instruction fetch
Receive Data 0 (input, asynchronous)
1
0
1
Read data from memory
This pin supplies asynchronous serial receive data
from the system to asynchronous serial port 0.
1
1
0
Write data to memory
1
1
1
None (passive)
RXD1/PIO28
Receive Data 1 (input, asynchronous)
This pin supplies asynchronous serial receive data
from the system to asynchronous serial port 1.
S2/BTSEL
Bus Cycle Status (output, three-state,
synchronous)
Boot Mode Select
R
S2—This pin indicates to the system the type of bus
cycle in progress. S2 can be used as a logical memory or
I/O indicator. S2–S0 float during bus hold and hold
acknowledge conditions. The S2–S0 pins are encoded as
shown in Table 4.
D
BTSEL—The Am186ED/EDLV microcontrollers can
boot from 8- or 16-bit wide nonvolatile memory, based
on the state of the BTSEL pin. If BTSEL is pulled High
or left floating, an internal pullup sets the boot mode
option to 16-bit. If BTSEL is pulled resistively Low
during reset, the 8-bit boot mode option is selected.
The status of the BTSEL pin is latched on the rising
edge of reset. If 8-bit mode is selected, the width of the
memory region associated with UCS can be changed
in the AUXCON register.
This signal should never be tied to VCC or VSS directly
since this pin is driven during normal operation. This
signal should be tied Low with an external resistor if the
8-bit boot mode is to be used. The internal pullup
resistor on BTSEL is ~9 kohm.
30
Bus Cycle
T
F
S6/CLKDIV2/PIO29
A
Bus Cycle Status Bit 6 (output, synchronous)
Clock Divide by 2 (input, internal pullup)
S6—During the second and remaining periods of a
cycle (t2, t3, and t4), this pin is asserted High to indicate
a DMA-initiated bus cycle. During a bus hold or reset
condition, S6 floats.
CLKDIV2—If S6/CLKDIV2/PIO29 is held Low during
power-on reset, the chip enters clock divided by 2
mode where the processor clock is derived by dividing
the external clock input by 2. If this mode is selected,
the PLL is disabled. The pin is sampled on the rising
edge of RES.
If S6 is to be used as PIO29 in input mode, the device
driving PIO29 must not drive the pin Low during poweron reset. S6/CLKDIV2/PIO29 defaults to a PIO input
with pullup, so the pin does not need to be driven High
externally.
SRDY/PIO6
Synchronous Ready (input, synchronous,
level-sensitive)
This pin indicates to the microcontroller that the
addressed memory space or I/O device will complete a
data transfer. The SRDY pin accepts an active High
input synchronized to CLKOUTA.
Using SRDY instead of ARDY allows a relaxed system
timing because of the elimination of the one-half clock
period required to internally synchronize ARDY. To
always assert the ready condition to the
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
microcontroller, tie SRDY High. If the system does not
use SRDY, tie the pin Low to yield control to ARDY.
TMRIN0/PIO11
Timer Input 0 (input, synchronous, edge-sensitive)
This pin supplies a clock or control signal to the internal
microcontroller timer 0. After internally synchronizing a
Low-to-High transition on TMRIN0, the microcontroller
increments the timer. TMRIN0 must be tied High if not
being used. When PIO11 is enabled, TMRIN0 is pulled
High internally.
TMRIN0 is driven internally by INT2/INTA0/PWD when
pulse width demodulation mode is enabled. The
TMRIN0/PIO11 pin can be used as a PIO when pulse
width demodulation mode is enabled.
TMRIN1/PIO0
Timer Input 1 (input, synchronous, edge-sensitive)
This pin supplies a clock or control signal to the internal
microcontroller timer 1. After internally synchronizing a
Low-to-High transition on TMRIN1, the microcontroller
increments the timer. TMRIN1 must be tied High if not
being used. When PIO0 is enabled, TMRIN1 is pulled
High internally.
TMRIN1 is driven internally by INT2/INTA0/PWD when
pulse width demodulation mode is enabled. The
TMRIN1/PIO0 pin can be used as a PIO when pulse
width demodulation mode is enabled.
TMROUT0/PIO10
Timer Output 0 (output, synchronous)
R
This pin supplies the system with either a single pulse
or a continuous waveform with a programmable duty
cycle. TMROUT0 is floated during a bus hold or reset.
UCS/ONCE1
Upper Memory Chip Select (output, synchronous)
ONCE Mode Request 1 (input, internal pullup)
UCS—This pin indicates to the system that a memory
access is in progress to the upper memory block. The
base address and size of the upper memory block are
programmable up to 512 Kbytes.
UCS is three-stated and held resistively High during a
bus hold condition. In addition, UCS has an ~9-kohm
internal pullup resistor that is active during reset.
After reset, UCS is active for the 64 Kbyte memory
range from F0000h to FFFFFh, including the reset
address of FFFF0h.
When RAS1 is activated, the code activating RAS1
must not reside in the UCS memory block. When RAS1
is activated, UCS is automatically deactivated and
remains negated. This allows code to boot from UCS,
copy its code to another memory device, then activate
a DRAM bank in place of the UCS memory block.
T
F
ONCE1—During reset, this pin and LCS/ONCE0 indicate to the microcontroller the mode in which it should
operate. ONCE0 and ONCE1 are sampled on the rising edge of RES. If both pins are asserted Low, the microcontroller enters ONCE mode. Otherwise, it
operates normally. In ONCE mode, all pins assume a
high-impedance state and remain in that state until a
subsequent reset occurs. To guarantee that the microcontroller does not inadvertently enter ONCE mode,
ONCE1 has a weak internal pullup resistor that is active only during a reset.
A
UZI/PIO26
Upper Zero Indicate (output, synchronous)
This pin supplies the system with either a single pulse
or a continuous waveform with a programmable duty
cycle. TMROUT1 floats during a bus hold or reset.
This pin lets the designer determine if an access to the
interrupt vector table is in progress by ORing it with bits
15–10 of the address and data bus (AD15–AD10). UZI
is the logical AND of the inverted A19–A16 bits. It asserts
in the first period of a bus cycle and is held throughout the
cycle.
TXD0/PIO22
VCC
Transmit Data 0 (output, asynchronous)
Power Supply (input)
This pin supplies asynchronous serial transmit data to
the system from serial port 0.
These pins supply power (+5 V) to the microcontroller.
TXD1/PIO27
Write High Byte (output, three-state, synchronous)
Transmit Data 1 (output, asynchronous)
This pin and WLB indicate to the system which bytes of
the data bus (upper, lower, or both) participate in a write
cycle. In 80C186 microcontroller designs, information
is provided by BHE, AD0, and WR. However, by using
WHB and WLB, the standard system interface logic
and external address latch that were required are
eliminated.
TMROUT1/PIO1
D
Timer Output 1 (output, synchronous)
This pin supplies asynchronous serial transmit data to
the system from serial port 1.
WHB
Am186ED/EDLV Microcontrollers
31
P R E L I M I N A R Y
WHB is asserted with AD15–AD8. WHB is the logical
OR of BHE and WR. This pin floats during reset.
WLB
Write Low Byte (output, three-state, synchronous)
WLB—This pin and WHB indicate to the system which
bytes of the data bus (upper, lower, or both) participate
in a write cycle. In 80C186 microcontroller designs, this
information is provided by BHE, AD0, and WR.
However, by using WHB and WLB, the standard
system interface logic and external address latch that
were required are eliminated.
WLB is asserted with AD7–AD0. WLB is the logical OR
of AD0 and WR. This pin floats during reset.
WR
Write Strobe (output, synchronous)
WR—This pin indicates to the system that the data on
the bus is to be written to a memory or I/O device. WR
floats during a bus hold or reset condition. WR should
be used for DRAM write enable.
X1
Crystal Input (input)
This pin and the X2 pin provide connections for a
fundamental mode or third-overtone, parallel-resonant
crystal used by the internal oscillator circuit. To provide
the microcontroller with an external clock source,
connect the source to the X1 pin and leave the X2 pin
unconnected.
X2
Crystal Output (output)
R
This pin and the X1 pin provide connections for a
fundamental mode or third-overtone, parallel-resonant
crystal used by the internal oscillator circuit. To provide
the microcontroller with an external clock source, leave
the X2 pin unconnected and connect the source to the
X1 pin.
D
32
A
Am186ED/EDLV Microcontrollers
T
F
P R E L I M I N A R Y
FUNCTIONAL DESCRIPTION
The Am186ED/EDLV microcontrollers are based on
the architecture of the 80C186 and 80C188 microcontrollers. The Am186ED/EDLV microcontrollers function
in the enhanced mode of earlier generations of 80C186
and 80C188 microcontrollers. Enhanced mode includes system features such as power-save control.
ment register used for physical address generation is
implied by the addressing mode used (see Table 5).
Shift
Left
4 Bits
Each of the 8086, 8088, 80186, and 80188 microcontrollers contains the same basic set of registers, instructions, and addressing modes. The Am186ED/
EDLV microcontrollers are backward-compatible with
the 80C186 and 80C188 microcontrollers.
A full description of all the Am186ED/EDLV microcontroller registers and instructions is included in the
Am186ED/EDLV Microcontrollers User’s Manual, order# 21335A.
1
All instructions that address operands in memory must
specify the segment value and the 16-bit offset value.
For speed and compact instruction encoding, the seg-
D
R
Table 5.
A
4
19
2
A
0
15
0
2
4 Segment
Logical
0 Base
Address
2 Offset
0
0
0
0
0
15
0
1
2
A
Memory Organization
Memory is organized in sets of segments. Each segment is a linear contiguous sequence of 64K (216) 8-bit
bytes. Memory is addressed using a two-component
address that consists of a 16-bit segment value and a
16-bit offset. The 16-bit segment values are contained
in one of four internal segment registers (CS, DS, SS,
or ES). The physical address is calculated by shifting
the segment value left by 4 bits and adding the 16-bit
offset value to yield a 20-bit physical address (see Figure 3). This allows for a 1-Mbyte physical address size.
2
1
15
19
2
2
0
T
F
6
2
Physical Address
0
To Memory
Figure 3. Two-Component Address
I/O Space
A
The I/O space consists of 64K 8-bit or 32K 16-bit ports.
Separate instructions (IN, INS and OUT, OUTS) address the I/O space with either an 8-bit port address
specified in the instruction, or a 16-bit port address in
the DX register. Eight-bit port addresses are zero-extended such that A15–A8 are Low. I/O port addresses
00F8h through 00FFh are reserved.
Segment Register Selection Rules
Memory Reference
Needed
Segment Register Used
Instructions
Code (CS)
Instructions (including immediate data)
Local Data
Data (DS)
All data references
Stack
Stack (SS)
All stack pushes and pops;
any memory references that use BP Register
External Data (Global)
Extra (ES)
All string instruction references that use the DI Register as an index
Implicit Segment Selection Rule
Am186ED/EDLV Microcontrollers
33
P R E L I M I N A R Y
BUS OPERATION
for all accesses, thus preserving the industry-standard
80C186 and 80C188 microcontrollers’ multiplexed address bus and providing support for existing emulation
tools.
The industry-standard 80C186 and 80C188 microcontrollers use a multiplexed address and data (AD) bus.
The address is present on the AD bus only during the
t1 clock phase. The Am186ED/EDLV microcontrollers
continue to provide the multiplexed AD bus and, in addition, provides a nonmultiplexed address (A) bus. The
A bus provides an address to the system for the complete bus cycle (t1–t4).
The following diagrams show the bus cycles of the
Am186ED/EDLV microcontrollers when the address
bus disable feature is in effect:
Figure 4 shows the affected signals during a normal
read or write operation for 16-bit mode. The address
and data are multiplexed onto the AD bus.
For systems where power consumption is a concern, it
is possible to disable the address from being driven on
the AD bus during the normal address portion of the
bus cycle for accesses to RAS0, RAS1, UCS, and/or
LCS address spaces. In this mode, the affected bus is
placed in a high-impedance state during the address
portion of the bus cycle. This feature is enabled
through the DA bits in the UMCS and LMCS registers.
When address disable is in effect, the number of signals that assert on the bus during all normal bus cycles
to the associated address space is reduced, decreasing power consumption and reducing processor switching noise. In 8-bit mode, the address is driven on
AD15–AD8 during the data portion of the bus cycle regardless of the setting of the DA bits.
If the ADEN pin is pulled Low during processor reset,
the value of the DA bits in the UMCS and LMCS registers is ignored and the address is driven on the AD bus
R
t1
Address
Phase
D
CLKOUTA
A19–A0
Figure 5 shows a 16-bit mode bus cycle when address
bus disable is in effect. This results in the AD bus operating in a nonmultiplexed address/data mode. The A
bus has the address during a read or write operation.
Figure 6 shows the affected signals during a normal
read or write operation for 8-bit mode. The multiplexed
address/data mode is compatible with the 80C186 and
80C188 microcontrollers and might be used to take advantage of existing logic or peripherals.
A
AD15–AD0
(Read)
Address
AD15–AD0
(Write)
Address
T
F
Figure 7 shows an 8-bit mode bus cycle when address
bus disable is in effect. The address and data are not
multiplexed. The AD7–AD0 signals have only data on
the bus, while the AD bus has the address during a
read or write operation.
t2
t3
t4
Data
Phase
Address
Data
Data
LCS or UCS
or
MCSx, PCSx
Note: For a detailed description of DRAM control signals, see DRAM switching characteristics
beginning on page 70.
Figure 4.
34
16-Bit Mode—Normal Read and Write Operation
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
t1
Address
Phase
t2
t3
Data
Phase
t4
CLKOUTA
Address
A19–A0
AD15–AD0
(Read)
Data
AD15–AD0
(Write)
Data
LCS, or UCS
or
MCSx, PCSx
T
F
Note: For a detailed description of DRAM control signals, see DRAM switching characteristics
beginning on page 70.
Figure 5.
16-Bit Mode—Read and Write with Address Bus Disable In Effect
t1
Address
Phase
CLKOUTA
A19–A0
D
AD7–AD0
(Read)
R
A
t3
t4
Data
Phase
Address
Address
AD15–AD8
(Read or Write)
AD7–AD0
(Write)
t2
Data
Address
Address
Data
LCS or UCS
or
MCSx, PCSx
Figure 6.
8-Bit Mode—Normal Read and Write Operation
Am186ED/EDLV Microcontrollers
35
P R E L I M I N A R Y
t1
t2
Address
Phase
t3
t4
Data
Phase
CLKOUTA
A19–A0
Address
AD7–AD0
(Read)
Data
AD15–AD8
Address
AD7–AD0
(Write)
Data
LCS, or UCS
or
MCSx, PCSx
T
F
Figure 7. 8-Bit Mode—Read and Write with Address Bus Disable in Effect
BUS INTERFACE UNIT
The bus interface unit controls all accesses to external
peripherals and memory devices. External accesses
include those to memory devices, as well as those to
memory-mapped and I/O-mapped peripherals and the
peripheral control block. The Am186ED/EDLV microcontrollers provide an enhanced bus interface unit with
the following features:
n A nonmultiplexed address bus
D
n DRAM address multiplexing
R
n A static bus-sizing option for 8-bit and 16-bit memory and I/O
n Separate byte write enables and CAS for High and
Low bytes
n Data strobe bus interface option
The standard 80C186/188 microcontroller multiplexed
address and data bus requires system interface logic
and an external address latch. On the Am186ED/EDLV
microcontrollers, new byte write enables, DRAM control logic, and a new nonmultiplexed address bus can
reduce design costs by eliminating this external logic.
The standard 80C186/188 microcontroller required external DRAM controller logic and DRAM address multiplex circuitry for interfacing to DRAM. On the
Am186ED/EDLV microcontrollers, the integrated
DRAM controller and internal address multiplexing can
reduce design costs by eliminating this external logic.
36
A
Further, system costs can be reduced for systems
using more than 64K of RAM by replacing SRAM with
less expensive DRAM.
Nonmultiplexed Address Bus
The nonmultiplexed address bus (A19–A0) is valid
one-half CLKOUTA cycle in advance of the address on
the AD bus. When used in conjunction with the modified UCS and LCS outputs and the byte-write enable
signals, the A19–A0 bus provides a seamless interface
to SRAM, and Flash EPROM memory systems.
DRAM Address Multiplexing
The A19–A0 address bus also provides the addresses
for the DRAM. When RAS0 or RAS1 asserts for a read
or write, all the address signals are valid. This allows
the DRAM to latch the odd addresses into the row address. Before the UCAS and/or LCAS asserts, the odd
addresses A17–A1 change to reflect the even addresses. This allows the DRAM to latch in the even addresses into the column address. During a refresh
cycle, the entire A19–A0 address bus is stable but undefined. The internal address and that reflected on the
AD bus is all 1s. The DRAM pin interface is shown in
Table 6.
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
Table 6.
DRAM Pin Interface
AM186ED/EDLV
Microcontroller Pins
DRAM Pin
A1
MA0
A3
MA1
A5
MA2
A7
MA3
A9
MA4
A11
MA5
A13
MA6
A15
MA7
A17
MA8
The byte-write enables are driven in conjunction with
the nonmultiplexed address bus as required for the
write timing requirements of common SRAMs.
Data Strobe Bus Interface Option
RAS (Bank 0)
RAS1
RAS (Bank 1)
UCAS
UCAS (AD15–AD8 Byte)
LCAS
LCAS (AD7–AD0 Byte)
OE
WR
WE
The Am186ED/EDLV microcontrollers provide the
WHB (Write High Byte) and WLB (Write Low Byte) signals, which act as byte-write enables.
WHB is the logical OR of BHE and WR. WHB is Low
when BHE and WR are both Low. WLB is the logical
OR of A0 and WR. WLB is Low when A0 and WR are
both Low.
RAS0
RD
Byte-Write Enables
The Am186ED/EDLV microcontrollers provide an
asynchronous bus interface that allows the use of 68Ktype peripherals. This implementation combines a DS
data strobe signal (multiplexed with DEN) with an asynchronous ARDY ready input. When DS is asserted, the
data and address signals are valid.
T
F
A chip select signal, ARDY, DS, and other control signals (RD/WR) can control the interface of 68K-type external peripherals to the AD bus.
Programmable Bus Sizing
DRAM INTERFACE
The Am186ED/EDLV microcontrollers allow programmability for data bus widths through fields in the Auxiliary Configuration Register (AUXCON) , as shown in
Table 7. The USIZ bit in AUXCON is only configurable
if the boot mode is 8-bit at reset.
The Am186ED/EDLV microcontrollers support up to
two banks of DRAM. The use of DRAM can significantly reduce the memory costs for applications using
more than 64K of RAM. No performance is lost except
for the slight overhead of periodically refreshing the
DRAM. The lower bank of DRAM uses the LCS space.
The upper bank of DRAM uses the UCS space. Either,
neither, or both banks can be activated. When either
bank is activated, the UCAS and LCAS are enabled,
and the DRAM address multiplexing is enabled on the
A19–A0 bus. When DRAM is activated, the corresponding memory bus size should be set to 16-bit. The
use of 8-bit-wide DRAM is not supported. All refreshes
to DRAM are 7 clocks long. The refreshes must be separately enabled in the RCU.
The width of the data access should not be modified
while the processor is fetching instructions from the associated address space.
R
Table 7. Programming the Bus Width of
Am186ED/EDLV Microcontrollers
Space
AUXCON
Field
Value
UCS
D
Bus
Width
USIZ
0
16 bits
1
8 bits
0
16 bits
1
8 bits
IOSIZ
0
16 bits
1
8 bits
0
16 bits
1
8 bits
LCS
I/O
Other
LSIZ
MSIZ
Comments
Dependent
on boot
option1
Default
Default
Default
A
The improved memory timing specifications of the
Am186ED/EDLV microcontrollers allow for zero-waitstate operation using 50-ns DRAM at a 40-MHz clock
speed. 60-ns DRAM requires one wait state at 40 MHz
and zero wait states at 33 MHz and below. 70-ns
DRAM requires two wait states at 40 MHz, one wait
state at 33 MHz, and zero wait states at 25 MHz and
below. This reduces overall system cost by enabling
the use of commonly available memory speeds and
taking advantage of DRAM’s lower cost per bit over
SRAM.
Note:
1. UCS width on reset is determined by the S2/BTSEL
pin. If UCS boots as a 16-bit space, it is not re-configurable to 8-bit.
Am186ED/EDLV Microcontrollers
37
P R E L I M I N A R Y
PERIPHERAL CONTROL BLOCK
The integrated peripherals of the Am186ED/EDLV microcontrollers are controlled by 16-bit read/write registers. The peripheral registers are contained within an
internal 256-byte peripheral control block (PCB). The
registers are physically located in the peripheral devices they control, but they are addressed as a single
256-byte block. Table 8 shows a map of these registers.
Reading and Writing the PCB
Code written for the Am186ED/EDLV microcontrollers
should perform all writes to the PCB registers as byte
writes. These writes transfer 16 bits of data to the PCB
register even if an 8-bit register is named in the instruction. For example, out dx, al results in the value of
ax being written to the port address in dx. Reads to the
PCB should be done as word reads. Code written in
this manner runs correctly on the Am186ED/EDLV microcontrollers with the PCB overlayed on either 8- or
16-bit address spaces.
Unaligned reads and writes to the PCB result in unpredictable behavior.
For a complete description of all the registers in the
PCB, see the Am186ED/EDLV Microcontrollers User’s
Manual, order# 21335A.
D
38
R
A
Am186ED/EDLV Microcontrollers
T
F
P R E L I M I N A R Y
Table 8. Peripheral Control Block Register Map
Register Name
Register Name
Timer 2 max count compare A register
62h
Timer 2 count register
60h
Offset
Processor Control Registers:
Offset
Peripheral control block relocation register
FEh
Timer 1 mode/control register
5Eh
Reset configuration register
F6h
Timer 1 max count compare B register
5Ch
F4h
Timer 1 max count compare A register
5Ah
Processor release level register1
1
F2h
Timer 1 count register
58h
System configuration register1
F0h
Timer 0 mode/control register
56h
Watchdog timer control register
E6h
Timer 0 max count compare B register
54h
E4h
Timer 0 max count compare A register
52h
E2h
Timer 0 count register
50h
Auxiliary configuration register
1
Enable RCU register
Clock prescaler register
1
(See note 2.)
Interrupt Registers:
DMA Registers:
Serial port 0 interrupt control register
44h
42h
DMA 1 control register
DAh
Serial port 1 interrupt control register
DMA 1 transfer count register
D8h
INT4 interrupt control register
DMA 1 destination address high register
D6h
INT3 control register
3Eh
DMA 1 destination address low register
D4h
INT2 control register
3Ch
DMA 1 source address high register
D2h
INT1 control register
3Ah
DMA 1 source address low register
D0h
INT0 control register
38h
DMA 0 control register
CAh
DMA1/INT6 interrupt control register
36h
DMA 0 transfer count register
C8h
DMA0/INT5 interrupt control register
34h
DMA 0 destination address high register
C6h
Timer interrupt control register
32h
Interrupt status register
30h
DMA 0 destination address low register
C4h
DMA 0 source address high register
C2h
DMA 0 source address low register
C0h
Chip-Select Registers:
PCS and MCS auxiliary register
Interrupt request register
2Eh
Interrupt in-service register
2Ch
Interrupt priority mask register
2Ah
Interrupt mask register
28h
Interrupt poll status register
26h
Interrupt poll register
24h
A2h
End-of-interrupt register
22h
A0h
Interrupt vector register
20h
R
A8h
Midrange memory chip-select register
A6h
Peripheral chip-select register
A4h
1
Low memory chip-select register
D
Upper memory chip-select register
Serial Port 0 Registers:
1
A
T
F
40h
Serial Port 1 Registers:
Serial port 0 baud rate divisor register
88h
Serial port 1 baud rate divisor register
18h
Serial port 0 receive register
86h
Serial port 1 receive register
16h
Serial port 0 transmit register
84h
Serial port 1 transmit register
14h
Serial port 0 status register
82h
Serial port 1 status register
12h
Serial port 0 control register
80h
Serial port 1 control register
10h
PIO Registers:
PIO data 1 register
7Ah
PIO direction 1 register
78h
PIO mode 1 register
76h
PIO data 0 register
74h
PIO direction 0 register
72h
PIO mode 0 register
70h
Timer Registers:
Timer 2 mode/control register
All unused addresses are reserved and should not be
accessed.
Notes:
1. The register has been modified from the Am186ES/
Am188ES microcontrollers.
2. The previous Memory Partition Register (MDRAM)
has been removed and its functionality replaced
with the CAS-before-RAS refresh mode.
66h
Am186ED/EDLV Microcontrollers
39
P R E L I M I N A R Y
CLOCK AND POWER MANAGEMENT
The clock and power management unit of the
Am186ED/EDLV microcontrollers includes a phaselocked loop (PLL) and a second programmable system
clock output (CLKOUTB).
the output of the amplifier and negatively affects the operation of the clock generator. Values for the loading on
X1 and X2 must be chosen to provide the necessary
phase shift and crystal operation.
Phase-Locked Loop
Selecting a Crystal
In a traditional 80C186/188 microcontroller design, the
crystal frequency is twice that of the desired internal
clock. Because of the PLL on the Am186ED/EDLV microcontrollers, the internal clock generated by the
Am186ED/EDLV microcontrollers (CLKOUTA) is the
same frequency as the crystal. The PLL takes the crystal inputs (X1 and X2) and generates a 45–55% (worst
case) duty cycle intermediate system clock of the same
frequency. This removes the need for an external 2x
oscillator, reducing system cost. The PLL is reset during power-on reset by an on-chip power-on reset
(POR) circuit.
When selecting a crystal, the load capacitance should
always be specified (CL). This value can cause variance in the oscillation frequency from the desired specified value (resonance). The load capacitance and the
loading of the feedback network have the following relationship:
(C1 ⋅ C2)
CL =
+ CS
(C1 + C2)
Crystal-Driven Clock Source
The internal oscillator circuit of the Am186ED/EDLV
microcontrollers is designed to function with a parallel
resonant fundamental or third overtone crystal. Because of the PLL, the crystal frequency should be
equal to the processor frequency. Do not replace a
crystal with an LC or RC equivalent.
The X1 and X2 signals are connected to an internal inverting amplifier (oscillator) that provides, along with
the external feedback loading, the necessary phase
shift (Figure 8). In such a positive feedback circuit, the
inverting amplifier has an output signal (X2) 180 degrees out of phase of the input signal (X1).
R
The external feedback network provides an additional
180-degree phase shift. In an ideal system, the input to
X1 will have 360 or zero degrees of phase shift. The external feedback network is designed to be as close to
ideal as possible. If the feedback network is not providing necessary phase shift, negative feedback dampens
D
where CS is the stray capacitance of the circuit. Placing
the crystal and CL in series across the inverting amplifier and tuning these values (C1, C2) allows the crystal
to oscillate at resonance. This relationship is true for
both fundamental and third-overtone operation. Finally,
there is a relationship between C1 and C2. To enhance
the oscillation of the inverting amplifier, these values
need to be offset with the larger load on the output (X2).
Equal values of these loads tend to balance the poles
of the inverting amplifier.
A
The characteristics of the inverting amplifier set limits
on the following parameters for crystals:
ESR (Equivalent Series Resistance) ......60 Ω max
Drive Level ..............................................1 mW max
The recommended range of values for C1 and C2 are
as follows:
C1 ..................................................................15 pF ± 20%
C2 ..................................................................22 pF ± 20%
The specific values for C1 and C2 must be determined
by the designer and are dependent on the characteristics of the chosen crystal and board design.
C1
X1
Crystal
X2
Crystal
C1
C2
C2
a. Inverting Amplifier Configuration
Figure 8.
40
T
F
Note 1
Note 1: Use for Third Overtone Mode
XTAL Frequency L1 Value (Max)
20 MHz
12 µH ±20%
25 MHz
8.2 µH ±20%
33 MHz
4.7 µH ±20%
40 MHz
3.0 µH ±20%
200 pF
b. Crystal Configuration
Am186ED/EDLV Microcontrollers Oscillator Configurations
Am186ED/EDLV Microcontrollers
Am186ED/EDLV
Microcontrollers
P R E L I M I N A R Y
External Source Clock
Initialization and Processor Reset
Alternately, the internal oscillator can be driven from an
external clock source. This source should be connected to the input of the inverting amplifier (X1), with
the output (X2) not connected.
Processor initialization or startup is accomplished by
driving the RES input pin Low. RES must be held Low
for 1 ms during power-up to ensure proper device initialization. RES forces the Am186ED/EDLV microcontrollers to terminate all execution and local bus activity.
No instruction or bus activity occurs as long as RES is
active. After RES becomes inactive and an internal
processing interval elapses, the microcontroller begins
execution with the instruction at physical location
FFFF0h, with UCS asserted with three wait states.
RES also sets some registers to predefined values and
resets the watchdog timer.
System Clocks
The base system clock of AMD’s original 80C186 and
80C188 microcontrollers is renamed CLKOUTA and
the additional output is called CLKOUTB. CLKOUTA
and CLKOUTB operate at either the processor frequency or the PLL frequency. The output drivers for
both clocks are individually programmable for disable.
Figure 9 shows the organization of the clocks.
Reset Configuration Register
The second clock output (CLKOUTB) allows one clock
to run at the PLL frequency and the other clock to run
at the power-save frequency. Individual drive enable
bits allow selective enabling of just one or both of these
clock outputs.
When the RES input is asserted Low, the contents of
the address/data bus (AD15–AD0) are written into the
reset configuration register. The system can place configuration information on the address/data bus using
weak external pullup or pulldown resistors, or using an
external driver that is enabled during reset. The processor does not drive the address/data bus during reset.
Power-Save Operation
The power-save mode of the Am186ED/EDLV microcontrollers reduces power consumption and heat dissipation, thereby extending battery life in portable
systems. In power-save mode, operation of the CPU
and internal peripherals continues at a slower clock frequency. When an interrupt occurs, the microcontroller
automatically returns to its normal operating frequency
on the internal clock’s next rising edge of t3.
Note: Power-save operation requires that clock-dependent devices be reprogrammed for clock frequency
changes. Software drivers must be aware of clock frequency. The power-save divisor should not be set to
operate the processor core below 100 kHz.
D
R
PLL
X1, X2
Mux
/2
T
F
For example, the reset configuration register could be
used to provide the software with the position of a configuration switch in the system. Using weak external
pullup and pulldown resistors on the address and data
bus, the system can provide the microcontroller with a
value corresponding to the position of the jumper during a reset.
A
Power-Save
Divisor
/1 to /128
PSEN
Mux
Processor Clock
CAF
CLKDIV2
CLKOUTA
Mux
CAD
CBF
Mux
Note: For frequencies under 16 MHz, use PLL bypass.
Time
Delay
6 ns ±
CLKOUTB
CBD
Figure 9. Clock Organization
Am186ED/EDLV Microcontrollers
41
P R E L I M I N A R Y
CHIP-SELECT UNIT
The Am186ED/EDLV microcontrollers contain logic
that provides programmable chip-select generation for
both memories and peripherals. The logic can be programmed to provide ready and wait-state generation
and latched address bits A1 and A2. The chip-select
lines are active for all memory and I/O cycles in their
programmed areas, whether they are generated by the
CPU or by the integrated DMA unit.
The Am186ED/EDLV microcontrollers provide six chipselect outputs for use with memory devices and six
more for use with peripherals in either memory space
or I/O space. The six memory chip selects can be used
to address three memory ranges. Each peripheral chip
select addresses a 256-byte block that is offset from a
programmable base address. A write to a chip select
register will enable the corresponding chip select logic
even if the actual pin has another function (e.g., PIO).
Chip-Select Timing
The timing for the UCS and LCS outputs is modified
from the original 80C186 microcontroller. These outputs now assert in conjunction with the nonmultiplexed
address bus for normal memory timing. To allow these
outputs to be available earlier in the bus cycle, the
number of programmable memory size selections has
been reduced.
Ready and Wait-State Programming
The Am186ED/EDLV microcontrollers can be programmed to sense a ready signal for each of the
peripheral or memory chip-select lines. The ready signal can be either the ARDY or SRDY signal. Each chipselect control register (UMCS, LMCS, MMCS, PACS,
and MPCS) contains a single-bit field that determines
whether the external ready signal is required or
ignored.
D
R
The number of wait states to be inserted for each access to a peripheral or memory region is programmable. The chip-select control registers for UCS, LCS,
MCS3–MCS0, PCS6, and PCS5 contain a two-bit field
that determines the number of wait states from zero to
three to be inserted. PCS3–PCS0 use three bits to provide additional values of 5, 7, 9, and 15 wait states.
When external ready is required, internally programmed wait states will always complete before external ready can terminate or extend a bus cycle. For
example, if the internal wait states are set to insert two
wait states, the processor samples the external ready
pin during the first wait cycle. If external ready is asserted at that time, the access completes after six cycles (four cycles plus two wait states). If external ready
is not asserted during the first wait cycle, the access is
extended until ready is asserted, and one more wait
state occurs followed by t4.
42
The ARDY signal on the Am186ED/EDLV microcontrollers is a true asynchronous ready signal. The ARDY
pin accepts a rising edge that is asynchronous to CLKOUTA and is active High. If the falling edge of ARDY is
not synchronized to CLKOUTA as specified, an additional clock period may be added.
Chip-Select Overlap
Although programming the various chip selects on the
Am186ED/EDLV microcontrollers so that multiple chip
select signals are asserted for the same physical address is not recommended, it may be unavoidable in
some systems. In such systems, the chip selects
whose assertions overlap must have the same configuration for ready (external ready required or not required) and the number of wait states to be inserted
into the cycle by the processor. The one exception to
this is PCS overlapping DRAM.
T
F
The peripheral control block (PCB) is accessed using
internal signals. These internal signals function as chip
selects configured with zero wait states and no external
ready. Therefore, the PCB can be programmed to addresses that overlap external chip-select signals only if
those external chip selects are programmed to zero
wait states with no external ready required.
A
When overlapping an additional chip select with either
the LCS or UCS chip selects, it must be noted that setting the Disable Address (DA) bit in the LMCS or UMCS
register disables the address from being driven on the
AD bus for all accesses for which the associated chip
select is asserted, including any accesses for which
multiple chip selects assert.
The MCS and PCS chip-select pins can be configured
as either chip selects (normal function) or as PIO inputs
or outputs. It should be noted, however, that the ready
and wait state generation logic for these chip selects is
in effect regardless of their configurations as chip selects or PIOs. This means that if these chip selects are
enabled (by a write to the MMCS and MPCS for the
MCS chip selects, or by a write to the PACS and MPCS
registers for the PCS chip selects), the ready and wait
state programming for these signals must agree with
the programming for any other chip selects with which
their assertion would overlap if they were configured as
chip selects.
Although the PCS4 signal is not available on an external pin, the ready and wait state logic for this signal still
exists internal to the part. For this reason, the PCS4 address space must follow the rules for overlapping chip
selects. The ready and wait-state logic for PCS6–
PCS5 is disabled when these signals are configured as
address bits A2–A1.
Failure to configure overlapping chip selects with the
same ready and wait state requirements may cause
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
the processor to hang with the appearance of waiting
for a ready signal. This behavior may occur even in a
system in which ready is always asserted (ARDY or
SRDY tied High).
Configuring PCS in I/O space with LCS or any other
chip select configured for memory address 0 is not considered overlapping of the chip selects. Overlapping
chip selects refers to configurations where more than
one chip select asserts for the same physical address.
The PCS can overlap DRAM blocks with different wait
states and without external or internal bus contention.
The RAS will assert along with the appropriate PCS.
The UCAS and LCAS will not assert, preventing the
DRAM from writing erroneously or driving the data bus
during a read. The PCS must have the same or higher
number of wait states than the DRAM. The PCS bus
width will be determined by the LSIZ or USIZ bus
widths. This will make a 1785-byte block of the DRAM
inaccessible. In its place, the peripherals associated
with the PCS can be accessed. This is especially useful when the entire memory space is used with two
banks of DRAM or a bank of DRAM and a 512K Flash.
Upper Memory Chip Select
The Am186ED/EDLV microcontrollers provide a UCS
chip select for the top of memory. On reset the
Am186ED/EDLV microcontrollers begin fetching and
executing instructions at memory location FFFF0h.
Therefore, upper memory is usually used as instruction
memory. To facilitate this usage, UCS defaults to active
on reset, with a default memory range of 64 Kbytes
from F0000h to FFFFFh, with external ready required
and three wait states automatically inserted. The UCS
memory range always ends at FFFFFh. The UCS
lower boundary is programmable.
R
The bus width associated with UCS is determined on
reset by the S2/BTSEL. If S2/BTSEL is pulled High or
left floating, an internal pullup sets the boot mode option to 16-bit. If S2/BTSEL is pulled resistively Low during reset, the boot mode option is for 8-bit. The status
of the S2/BTSEL pin is latched on the rising edge of reset. If 8-bit mode is selected, the width of the memory
region associated with UCS can be changed in the
AUXCON register. If UCS boots as a 16-bit space, it is
not re-configurable to 8-bit. This allows for cheaper 8bit-wide memory to be used for booting the Am186ED/
EDLV microcontrollers, while speed-critical code and
data can be executed from 16-bit-wide lower memory.
Eight-bit or 16-bit-wide peripherals can be used in the
memory area between LCS and UCS or in the I/O
space. The entire memory map can be set to 16-bit or
8-bit or mixed between 8-bit and 16-bit based on the
USIZ, LSIZ, MSIZ, and IOSIZ bits in the AUXCON register.
D
Low Memory Chip Select
The Am186ED/EDLV microcontrollers provide an LCS
chip select for lower memory. The AUXCON register
can be used to configure LCS for 8-bit or 16-bit accesses. Since the interrupt vector table is located at the
bottom of memory starting at 00000h, the LCS pin is
usually used to control data memory. The LCS pin is
not active on reset.
The LCS signal is multiplexed with the RAS0 signal
when the DRAM mode is enabled in the LMCS register.
Midrange Memory Chip Selects
The Am186ED/EDLV microcontrollers provide four
chip selects, MCS3–MCS0, for use in a user-locatable
memory block. With some exceptions, the base address of the memory block can be located anywhere
within the 1-Mbyte memory address space. The areas
associated with the UCS and LCS chip selects are excluded. If they are mapped to memory, the address
range of the peripheral chip selects, PCS6, PCS5, and
PCS3–PCS0, are also excluded. The MCS address
range can overlap the PCS address range if the PCS
chip selects are mapped to I/O space.
T
F
MCS0 can be configured to be asserted for the entire
MCS range. When configured in this mode, the MCS3–
MCS1 pins can be used as PIOs or DRAM control signals.
A
The AUXCON register can be used to configure MCS
for 8-bit or 16-bit accesses. The bus width of the MCS
range is determined by the width of the non-UCS/nonLCS memory range.
Unlike the UCS and LCS chip selects, the MCS outputs
assert with the same timing as the multiplexed AD address bus.
Activating either bank of DRAM will change the MCS1
and MCS2 functionality to UCAS and LCAS. Activating
the upper DRAM bank will change the MCS3 functionality to RAS1. It is recommended that when either bank
of DRAM is activated, either MCS0 be configured to assert for the entire MCS range or that MCS space be unused. If the lower bank of DRAM is activated, but not
the upper bank of DRAM, MCS3 can still be used as a
chip select or PIO. The MCS2 and MCS1 portion of the
middle chip select address space will not have a chip
select signal asserted, but the wait states will still be
valid.
Peripheral Chip Selects
The Am186ED/EDLV microcontrollers provide six chip
selects, PCS6–PCS5 and PCS3–PCS0, for use within
a user-configured memory or I/O block. PCS4 is not
available on the Am186ED/EDLV microcontrollers. The
base address of the memory block can be located anywhere within the 1-Mbyte memory address space, exclusive of the areas associated with the UCS, LCS, and
Am186ED/EDLV Microcontrollers
43
P R E L I M I N A R Y
MCS chip selects, or they can be configured to access
the 64-Kbyte I/O space.
The PCS pins are not active on reset. PCS6–PCS5 can
be programmed for zero to three wait states. PCS3–
PCS0 can be programmed for four additional wait-state
values: 5, 7, 9, and 15.
The AUXCON register can be used to configure PCS
for 8-bit or 16-bit accesses. The bus width of the PCS
range is determined by the width of the non-UCS/nonLCS memory range or by the width of the I/O area.
Unlike the UCS and LCS chip selects, the PCS outputs
assert with the multiplexed AD address bus. Each
peripheral chip select asserts over a 256-byte address
range, which is twice the address range covered by
peripheral chip selects in the 80C186/188 microcontrollers.
The PCS allows for overlap in memory space with the
DRAM (RAS0, RAS1) space. Overlap of the PCS with
LCS, MCS, or UCS in a non-DRAM mode is not recommended. If overlap of the PCS with MCS, LCS, or UCS
occurs, the same number of wait states and external
ready must be used. If overlap of PCS with DRAM
space occurs, the DRAM controller will assert RAS and
stop the CAS signal from asserting. This will not modify
the contents of the DRAM and the access will continue
as a normal PCS access. When overlapping the PCS
with DRAM, the number of wait states can be different
for PCS space. PCS wait states must be greater than
or equal to DRAM wait states. The ready and wait
states will be determined by the PCS programming in
the MPCS and PACS registers.
R
PCS space should not contain the address FFFFFh,
which is the address used for a refresh cycle. The
AD15–AD0 bus will drive FFFFh during a refresh cycle
for the address portion of cycle.
D
REFRESH CONTROL UNIT
The refresh control unit (RCU) automatically generates
refresh bus cycles when enabled. After a programmable period of time, the RCU generates a CAS-beforeRAS refresh bus cycle. The RCU should not be enabled if at least one bank of DRAM is not enabled. All
refreshes will be 7 clocks, no matter how the DRAM
wait states are programmed. During a refresh cycle,
the A19–A0 bus is undefined; the AD15–AD0 bus is
driven with all 1s (FFFFh). The PCS and MCS chip selects are decoded by the processor using a 20-bit version of the AD bus. The highest four bits of this internal
bus are not available externally; however, internally
these bits are set to all 1s during a refresh cycle, resulting in the 20-bit address FFFFFh. For this reason, the
MCS and PCS chip selects should not contain the address FFFFFh while DRAM is enabled.
44
INTERRUPT CONTROL UNIT
The Am186ED/EDLV microcontrollers can receive interrupt requests from a variety of sources, both internal
and external. The internal interrupt controller arranges
these requests by priority and presents them one at a
time to the CPU.
There are up to eight external interrupt sources on the
Am186ED/EDLV microcontrollers—seven maskable
interrupt pins and one nonmaskable interrupt (NMI)
pin. In addition, there are eight internal interrupt
sources (three timers, two DMA channels, two asynchronous serial ports, and the Watchdog Timer NMI)
that are not connected to external pins. INT5 and INT6
are multiplexed with DRQ0 and DRQ1. These two interrupts are available if the associated DMA is not enabled or is being used with internal synchronization.
The Am186ED/EDLV microcontrollers provide up to six
interrupt sources not present on the 80C186 and
80C188 microcontrollers. There are up to three additional external interrupt pins—INT4, INT5, and INT6.
These pins operate much like the INT3–INT0 interrupt
pins on the 80C186 and 80C188 microcontrollers.
There are also two internal interrupts from the serial
ports and the watchdog timer can generate interrupts.
T
F
INT5 and INT6 are multiplexed with the DMA request
signals, DRQ0 and DRQ1. If a DMA channel is not enabled, or if it is not using external synchronization, then
the associated pin can be used as an external interrupt.
INT5 and INT6 can also be used in conjunction with the
DMA terminal count interrupts.
A
The seven maskable interrupt request pins can be
used as direct interrupt requests. INT4–INT0 can be either edge-triggered or level-triggered. INT6 and INT5
are edge-triggered only. In addition, INT0 and INT1 can
be configured in cascade mode for use with an external
82C59A-compatible interrupt controller. When INT0 is
configured in cascade mode, the INT2 pin is automatically configured in its INTA0 function. When INT1 is
configured in cascade mode, the INT3 pin is automatically configured in its INTA1 function. An external interrupt controller can be used as the system master by
programming the internal interrupt controller to operate
in slave mode. INT6–INT4 are not available in slave
mode.
Interrupts are automatically disabled when an interrupt
is taken. Interrupt-service routines (ISRs) may
re-enable interrupts by setting the IF flag. This allows
interrupts of greater or equal priority to interrupt the
currently executing ISR. Interrupts from the same
source are disabled as long as the corresponding bit in
the interrupt in-service register is set. INT1 and INT0
provide a special bit to enable special fully nested
mode. When configured in special fully nested mode,
the interrupt source may generate a new interrupt
regardless of the setting of the in-service bit.
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
TIMER CONTROL UNIT
There are three 16-bit programmable timers and a
watchdog timer on the Am186ED/EDLV microcontrollers.
Timer 0 and timer 1 are connected to four external pins
(each one has an input and an output). These two timers can be used to count or time external events, or to
generate nonrepetitive or variable-duty-cycle waveforms. When pulse width demodulation is enabled,
timer 0 and timer 1 are used to measure the width of
the High and Low pulses on the PWD pin. (See the
Pulse Width Demodulation section on page 45.)
Timer 2 is not connected to any external pins. It can be
used for real-time coding and time-delay applications.
It can also be used as a prescaler to timers 0 and 1 or
to synchronize DMA transfers.
The programmable timers are controlled by eleven 16bit registers in the peripheral control block. A timer’s
timer-count register contains the current value of that
timer. The timer-count register can be read or written
with a value at any time, whether the timer is running or
not. The microcontroller increments the value of the
timer-count register each time a timer event occurs.
Each timer also has a maximum-count register that defines the maximum value the timer can reach. When
the timer reaches the maximum value, it resets to 0
during the same clock cycle. The value in the maximum-count register is never stored in the timer-count
register. Also, timers 0 and 1 have a secondary maximum-count register. Using both the primary and secondary maximum-count registers lets the timer
alternate between two maximum values.
R
If the timer is programmed to use only the primary maximum-count register, the timer output pin switches Low
for one clock cycle after the maximum value is
reached. If the timer is programmed to use both of its
maximum-count registers, the output pin indicates
which maximum-count register is currently in control,
thereby creating a waveform. The duty cycle of the
waveform depends on the values in the maximumcount registers.
D
Each timer is serviced every fourth clock cycle, so a
timer can operate at a speed of up to one-quarter of the
internal clock frequency. A timer can be clocked externally at this same frequency; however, because of internal synchronization and pipelining of the timer
circuitry, the timer output can take up to six clock cycles
to respond to the clock or gate input.
Watchdog Timer
The Am186ED/EDLV microcontrollers provide a true
watchdog timer function. The Watchdog Timer (WDT)
can be used to regain control of the system when software fails to respond as expected. The WDT is active
after reset. It can only be modified a single time by a
keyed sequence of writes to the watchdog timer control
register (WDTCON) following reset. This single write
can either disable the timer or modify the timeout period and the action taken upon timeout. A keyed sequence is also required to reset the current WDT count.
This behavior ensures that randomly executing code
will not prevent a WDT event from occurring.
The WDT supports up to a 1.67-second timeout period
in a 40-MHz system. After reset, the WDT is enabled
and the timeout period is set to its maximum value.
The WDT can be configured to cause either an NMI interrupt or a system reset upon timeout. If the WDT is
configured for NMI, the NMIFLAG in the WDTCON register is set when the NMI is generated. The NMI interrupt service routine (ISR) should examine this flag to
determine if the interrupt was generated by the WDT or
by an external source. If the NMIFLAG is set, the ISR
should clear the flag by writing the correct keyed sequence to the WDTCON register. If the NMIFLAG is set
when a second WDT timeout occurs, a WDT system
reset is generated rather than a second NMI event.
T
F
When the processor takes a WDT reset, either due to
a single WDT event with the WDT configured to generate resets or due to a WDT event with the NMIFLAG
set, the RSTFLAG in the WDTCON register is set. This
allows system initialization code to differentiate between a hardware reset and a WDT reset and take appropriate action. The RSTFLAG is cleared when the
WDTCON register is read or written. The processor
does not resample external pins during a WDT reset.
This means that the clocking, the reset configuration
register, and any other features that are user-selectable during reset do not change when a WDT system
reset occurs. All other activities are identical to those of
a normal system reset.
A
Note: The Watchdog Timer (WDT) is active after reset.
PULSE WIDTH DEMODULATION
For many applications, such as bar-code reading, it is
necessary to measure the width of a signal in both its
High and Low phases. The Am186ED/EDLV microcontrollers provide a pulse-width demodulation (PWD) option to fulfill this need. The PWD bit in the System
Configuration Register (SYSCON) enables the PWD
option. Analog-to-digital conversion is not supported.
In PWD mode, TMRIN0, TMRIN1, INT2, and INT4 are
configured internal to the microcontroller to support the
detection of rising and falling edges on the PWD input
pin (INT2/INTA0/PWD) and to enable either timer 0
when the signal is High or timer 1 when the signal is
Low. The INT4, TMRIN0, and TMRIN1 pins are not
used in PWD mode and so are available for use as
PIOs.
Am186ED/EDLV Microcontrollers
45
P R E L I M I N A R Y
The following diagram shows the behavior of a system
for a typical waveform.
the event of a simultaneous DMA request or if there is
a need to interrupt transfers on the other channel.
DMA Operation
INT2
INT4
INT2 Ints generated
TMR1 enabled
TMR0 enabled
The interrupt service routine (ISR) for the INT2 and
INT4 interrupts should examine the current count of the
associated timer, timer 1 for INT2, and timer 0 for INT4,
in order to determine the pulse width. The ISR should
then reset the timer count register in preparation for the
next pulse.
Since the timers count at one quarter of the processor
clock rate, this determines the maximum resolution that
can be obtained. Further, in applications where the
pulse width may be short, it may be necessary to poll
the INT2 and INT4 request bits in the interrupt request
register in order to avoid the overhead involved in taking and returning from an interrupt. Overflow conditions, where the pulse width is greater than the
maximum count of the timer, can be detected by monitoring the Maximum Count (MC) bit in the associated
timer or by setting the INT bit to enable timer interrupt
requests.
DIRECT MEMORY ACCESS
Direct memory access (DMA) permits transfer of data
between memory and peripherals without CPU involvement. The DMA unit shown in Figure 10, provides two
high-speed DMA channels. Data transfers can occur
between memory and I/O spaces (e.g., memory to I/O)
or within the same space (e.g., memory to memory or
I/O to I/O). Table 9 shows maximum DMA transfer
rates.
D
R
Each channel has six registers in the peripheral control
block that define specific channel operations. The DMA
registers consist of a 20-bit source address (two registers), a 20-bit destination address (two registers), a 16bit transfer count register, and a 16-bit control register.
The DMA Transfer Count Register (DTC) specifies the
number of DMA transfers to be performed. Up to 64K
of byte or word transfers can be performed with automatic termination. The DMA control registers define the
channel operation. All registers can be modified during any DMA activity. Any changes made to the DMA
registers are reflected immediately in DMA operation.
Table 9. Am186ED/EDLV Microcontrollers
Maximum DMA Transfer Rates
40
MHz
33
MHz
25
MHz
20
MHz
Unsynchronized
10
8.25
6.25
5
Source Synchronized
10
8.25
6.25
5
Destination Synchronized
(CPU needs bus)
6.6
5.5
4.16
3.3
Destination Synch
(CPU does not need bus)
8
6.6
5
4
A
The DMA channels can be directly connected to the
asynchronous serial ports. DMA and serial port transfer
is accomplished by programming the DMA controller to
perform transfers between a data source in memory or
I/O space and a serial port transmit or receive register.
The two DMA channels can support one serial port in
full-duplex mode or two serial ports in half-duplex
mode.
Either bytes or words can be transferred to or from
even or odd addresses. However, word DMA transfers
to or from memory configured for 8-bit accesses are
not supported. Only two bus cycles (a minimum of eight
clocks) are necessary for each data transfer.
Each channel accepts a DMA request from one of four
sources: the channel request pin (DRQ1–DRQ0),
Timer 2, a serial port, or the system software. The
channels can be programmed with different priorities in
46
T
F
Type of
Synchronization
Selected
Maximum DMA
Transfer Rate (Mbytes)
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
Adder Control
Logic
20-bit Adder/Subtractor
Timer Request
DRQ1/Serial Port
20
Request
Selection
Logic
Transfer Counter Ch. 1
Destination Address Ch. 1
Source Address Ch. 1
Transfer Counter Ch. 0
Destination Address Ch. 0
Source Address Ch. 0
DMA
Control
Logic
Interrupt
Request
Channel Control Register 1
Channel Control Register 0
20
16
Internal Address/Data Bus
Figure 10.
Each DMA control register determines the mode of operation for the particular DMA channel. The DMA control registers specify the following:
R
n Whether bytes or words are transferred
D
A
T
F
DMA Unit Block Diagram
DMA Channel Control Registers
n The mode of synchronization
DRQ0/Serial Port
n Whether an interrupt is generated after the last
transfer
n Whether the DRQ pins are configured as INT pins
DMA Priority
The DMA channels can be programmed so that one
channel is always given priority over the other, or they
can be programmed to alternate cycles when both
have DMA requests pending. DMA cycles always have
priority over internal CPU cycles except between
locked memory accesses or word accesses to odd
memory locations. However, an external bus hold
takes priority over an internal DMA cycle.
n The relative priority of the DMA channel with respect to the other DMA channel
Because an interrupt request cannot suspend a DMA
operation and the CPU cannot access memory during
a DMA cycle, interrupt latency time suffers during sequences of continuous DMA cycles. An NMI request,
however, causes all internal DMA activity to halt. This
allows the CPU to respond quickly to the NMI request.
n Whether the source address is incremented, decremented, or maintained constant after each transfer
ASYNCHRONOUS SERIAL PORTS
n Whether DMA activity ceases after a programmed
number of DMA cycles
n Whether the source address addresses memory or
I/O space
n Whether the destination address is incremented,
decremented, or maintained constant after transfers
The Am186ED/EDLV microcontrollers provide two independent asynchronous serial ports. These ports provide full-duplex, bidirectional data transfer using
several industry-standard communications protocols.
The serial ports can be used as sources or destinations
of DMA transfers.
n Whether the destination address addresses memory or I/O space
Am186ED/EDLV Microcontrollers
47
P R E L I M I N A R Y
The asynchronous serial ports support the following
features:
n Full-duplex operation
n Direct memory access (DMA) from the serial ports
n 7-bit, 8-bit, or 9-bit data transfers
n Odd, even, or no parity
n One stop bit
n Long or short break character recognition
n Error detection
— Parity errors
— Framing errors
— Overrun errors
— Break character recognition
n Hardware handshaking with the following selectable control signals:
— Clear-to-send (CTS)
— Enable-receiver-request (ENRX)
— Ready-to-send (RTS)
— Ready-to-receive (RTR)
n DMA to and from the serial ports
n Separate maskable interrupts for each port
n Multidrop protocol (9-bit) support
n Independent baud rate generators
n Maximum baud rate of 1/16th of the CPU clock
R
n Double-buffered transmit and receive
n Programmable interrupt generation for transmit, receive, and/or error detection
DMA Transfers through the Serial Port
D
The DMA channels can be directly connected to the
asynchronous serial ports. DMA and serial port transfer
is accomplished by programming the DMA controller to
perform transfers between a memory or I/O space and
a serial port transmit or receive register. The two DMA
channels can support one serial port in full-duplex
mode or two serial ports in half-duplex mode. See the
DMA Control register descriptions in the Am186ED/
EDLV Microcontrollers User’s Manual, order# 21335A
for more information.
48
PROGRAMMABLE I/O (PIO) PINS
There are 32 pins on the Am186ED/EDLV microcontrollers that are available as user-programmable I/O
signals. Table 2 on page 29 and Table 3 on page 29 list
the PIO pins. Each of these pins can be used as a userprogrammable input or output signal if the normal
shared function is not needed.
If a pin is enabled to function as a PIO signal, the preassigned signal function is disabled and does not affect
the level on the pin. A PIO signal can be configured to
operate as an input or output with or without a weak
pullup or pulldown, or as an open-drain output.
After power-on reset, the PIO pins default to various
configurations. The column titled Power-On Reset Status in Table 2 on page 29 and Table 3 on page 29 lists
the defaults for the PIOs. The system initialization code
must reconfigure the PIOs as required.
T
F
The A19–A17 address pins default to normal operation
on power-on reset, allowing the processor to correctly
begin fetching instructions at the boot address
FFFF0h. The DT/R, DEN, and SRDY pins also default
to normal operation on power-on reset.
Note that emulators use A19, A18, A17, S6, and UZI.
In environments where an emulator is needed, these
pins must be configured for normal function—not as
PIOs.
A
If the AD15–AD0 bus override is enabled on power-on
reset, then S6/CLKDIV2 and UZI revert to normal operation instead of PIO input with pullup. If BHE/ADEN is
held Low during power-on reset, the AD15–AD0 bus
override is enabled.
When the PCS or MCS are used as PIO inputs (only)
and the bus is arbitrated, an internal pullup of ~10
kohms is activated, even if the pullup option for the PIO
is not selected.
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage temperature
Am186ED........................................ –65°C to +125°C
Am186EDLV.................................... –65°C to +125°C
Am186ED Microcontroller
Commercial (TC) .................................0°C to +100°C
Industrial* (TA)...................................–40°C to +85°C
Supply voltage (VCC) .................................5 V ± 10%
Voltage on any pin with respect to ground
Am186ED................................... –0.5 V to Vcc +0.5 V
Am186EDLV............................... –0.5 V to Vcc +0.5 V
Note: Stresses above those listed under Absolute
Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied.
Exposure to absolute maximum ratings for extended
periods may affect device reliability.
Am186EDLV Microcontroller
Commercial (TA) ................................... 0°C to +70°C
VCC up to 25 MHz................................. 3.3 V ± 0.3 V
Where:
TC = case temperature
TA = ambient temperature
*Industrial versions of Am186ED microcontrollers are
available in 20 and 25 MHz operating frequencies only.
DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES
T
F
Preliminary
Symbol
Parameter Description
VIL
Input Low Voltage (Except X1)
VIL1
Clock Input Low Voltage (X1)
VIH
Input High Voltage (Except RES and X1)
VIH 1
Input High Voltage (RES)
VIH 2
Clock Input High Voltage (X1)
Test Conditions
VOH
0.2VCC –0.3
V
0.8
V
2.0
VCC +0.5
V
2.4
VCC +0.5
V
VCC –0.8
VCC +0.5
V
0.45
V
0.45
V
2.4
VCC +0.5
V
IOH = –200 µA @ VCC –0.5
VCC –0.5
VCC
V
IOH = –200 µA @ VCC –0.5
VCC –0.5
VCC
V
5.9
mA/MHz
Am186EDLV
IOL = 1.5 mA (S2–S0)
IOL = 1.0 mA (others)
Am186EDLV
ICC
A
IOL = 2.5 mA (S2–S0)
IOL = 2.0 mA (others)
Am186ED
D
R
IOH = –2.4 mA @ 2.4 V
Power Supply Current @ 0°C
VCC
= 5.5 V (b)
VCC
= 3.6 V (b)
Input Leakage Current @ 0.5 MHz
0.45 V≤VIN ≤ VCC
Output Leakage Current @ 0.5 MHz
0.45 V≤VOUT ≤VCC
VCLO
Clock Output Low
ICLO = 4.0 mA
VCHO
Clock Output High
ICHO = –500 µA
ILI
ILO
Unit
–0.5
Am186ED
Output High Voltage(a)
Max
–0.5
Output Low Voltage
VOL
Min
4.0
(c)
VCC –0.5
±10
µA
±10
µA
0.45
V
V
Notes:
a The LCS/ONCE0/RAS0 and UCS/ONCE1 pins have weak internal pullup resistors. Loading the LCS/ONCE0/RAS0 and
UCS/ONCE1 pins in excess of IOH = –200 µA during reset can cause the device to go into ONCE mode.
b
Current is measured with the device in RESET with X1 and X2 driven and all other non-power pins open but held High or Low.
c
Testing is performed with the pins floating, either during HOLD or by invoking the ONCE mode.
Am186ED/EDLV Microcontrollers
49
P R E L I M I N A R Y
CAPACITANCE
Preliminary
Symbol
Max
Unit
CIN
Input Capacitance
Parameter Description
@ 1 MHz
Test Conditions
Min
10
pF
CIO
Output or I/O Capacitance
@ 1 MHz
20
pF
Note:
Capacitance limits are guaranteed by characterization.
POWER SUPPLY CURRENT
Table 10 shows the variables that are used to calculate
t he t y p i c a l p o we r c o n s um p t i o n v a l u e f o r t h e
Am186EDLV microcontroller.
For the following typical system specification shown in
Figure 11, ICC has been measured at 4.0 mA per MHz
of system clock. For the following typical system
specification shown in Figure 12, I CC has been
measured at 5.9 mA per MHz of system clock. The
typical system is measured while the system is
executing code in a typical application with nominal
voltage and maximum case temperature. Actual power
supply current is dependent on system design and may
be greater or less than the typical ICC figure presented
here.
Table 10. Typical Power Consumption Calculation
for the Am186EDLV Microcontroller
R
n Output capacitive load set to 35 pF
D
Typical Power
in Watts
20
4.0
3.6
0.288
4.0
3.6
0.360
A
120
n No DC loads on the output buffers
n PIOs are disabled
Volts
140
Please note that dynamic ICC measurements are dependent upon chip activity, operating frequency, output
buffer logic, and capacitive/resistive loading of the outputs. For these ICC measurements, the devices were
set to the following modes:
n AD bus set to data only
Typical ICC
25
Typical current in Figure 11 is given by:
ICC = 4.0 mA ⋅ freq(MHz)
Typical current in Figure 12 is given by:
ICC = 5.9 mA ⋅ freq(MHz)
T
F
MHz ⋅ ICC ⋅ Volts / 1000 = P
MHz
100
80
ICC (mA)
25 MHz
20 MHz
60
40
20
0
10
20
Clock Frequency (MHz)
n Timer, serial port, refresh, and DMA are enabled
Figure 11. Typical Icc Versus Frequency for
Am186EDLV Microcontroller
280
240
40 MHz
200
33 MHz
160
ICC (mA)
25 MHz
120
20 MHz
80
40
0
10
20
30
40
50
Clock Frequency (MHz)
Figure 12. Typical Icc Versus Frequency for Am186ED Microcontroller
50
30
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
THERMAL CHARACTERISTICS
TQFP Package
The variable P is power in watts. Power supply current
(ICC) is in mA per MHz of clock frequency.
The Am186ED microcontroller is specified for
operation with case temperature ranges from 0°C to
+100°C for a commercial device. Case temperature is
measured at the top center of the package as shown in
Figure 13. The various temperatures and thermal
resistances can be determined using the equations in
Figure 14 with information given in Table 11.
θJA
TC θ
JC
The total thermal resistance is θJA; θJA is the sum of
θJC, the internal thermal resistance of the assembly,
and θCA, the case to ambient thermal resistance.
θJA = θJC + θCA
Figure 13.
θJA = θJC + θCA
P=ICC ⋅ freq (MHz) ⋅ VCC
TC =TJ –( P ⋅ θJC )
TC =TA +( P ⋅ θCA )
TA =TJ –( P ⋅ θJA )
TA =TC –( P ⋅ θCA )
A
Thermal Resistance(°C/Watt)
T
F
TJ =TC +( P ⋅ θJC )
TJ =TA + ( P ⋅ θJA )
Figure 14.
θCA
Thermal Characteristics Equations
Table 11. Thermal Characteristics (°C/Watt)
R
Package/Board
PQFP/2-Layer
D
TQFP/2-Layer
PQFP/4-Layer
to 6-Layer
TQFP/4-Layer
to 6-Layer
Airflow
(Linear Feet
per Minute)
θJA
θJC
θCA
0 fpm
45
7
38
200 fpm
39
7
32
400 fpm
35
7
28
600 fpm
33
7
26
0 fpm
56
10
46
200 fpm
46
10
36
400 fpm
40
10
30
600 fpm
38
10
28
0 fpm
23
5
18
200 fpm
21
5
16
400 fpm
19
5
14
600 fpm
17
5
12
0 fpm
30
6
24
200 fpm
28
6
22
400 fpm
26
6
20
600 fpm
24
6
18
Am186ED/EDLV Microcontrollers
51
P R E L I M I N A R Y
Typical Ambient Temperatures
Table 13. Junction Temperature Calculation
The typical ambient temperature specifications are
based on the following assumptions and calculations:
The commercial operating range of the Am186ED
microcontroller is a case temperature TC of 0 to 100
degrees Centigrade. TC is measured at the top center
of the package. An increase in the ambient temperature
causes a proportional increase in TC.
Microcontrollers up to 40 MHz are specified as 5.0 V
plus or minus 10%. Therefore, 5.0 V is used for
calculating typical power consumption up to 40 MHz.
Typical power supply current (ICC) in normal usage is
estimated at 5.9 mA per MHz of microcontroller clock
rate.
Typical power consumption (watts) = (5.9 mA/MHz)
times microcontroller clock rate times VCC divided by
1000.
Table 12 shows the variables that are used to calculate
the typical power consumption value for each version
of the Am186ED microcontroller.
Table 12.
Typical Power Consumption Calculation
Typical
Power (P) in
Watts
P = MHz ⋅ ICC ⋅ VCC/1000
MHz
Typical ICC
Volts
40
5.9
5.0
1.2
33
5.9
5.0
1.0
25
5.9
5.0
0.7
20
5.9
5.0
0.6
D
R
Speed/
Pkg/
Board
TJ(°C)
TC
P
θJC
40/P2
108.3
100
1.2
7
40/T2
111.8
100
1.2
10
TJ = TC + (P ⋅ θJC)
40/P4-6
105.9
100
1.2
5
40/T4-6
107.1
100
1.2
6
33/P2
106.8
100
1.0
7
33/T2
109.7
100
1.0
10
33/P4-6
104.9
100
1.0
5
33/T4-6
105.8
100
1.0
6
25/P2
105.2
100
0.7
7
25/T2
107.4
100
0.7
10
25/P4-6
103.7
100
0.7
5
25/T4-6
104.4
100
0.7
6
20/P2
104.1
100
0.6
7
20/T2
105.9
100
0.6
10
T
F
20/P4-6
103.0
100
0.6
5
20/T4-6
103.5
100
0.6
6
By using T J from Table 13, the typical power
consumption value from Table 12, and a θJA value from
Table 11, the typical ambient temperature TA can be
calculated using the following formula from Figure 14:
A
TA = TJ – (P ⋅ θJA)
For example, TA for a 40-MHz PQFP design with a 2layer board and 0 fpm airflow is calculated as follows:
TA = 108.3 – (1.2 ⋅ 45)
TA = 55.2
Thermal resistance is a measure of the ability of a
package to remove heat from a semiconductor device.
A safe operating range for the device can be calculated
using the formulas from Figure 14 and the variables in
Table 11.
In this calculation, TJ comes from Table 13, P comes
from Table 12, and θJA comes from Table 11. See Table
14.
By using the maximum case rating T C , the typical
power consumption value from Table 12, and θJC from
Table 11, the junction temperature TJ can be calculated
by using the following formula from Figure 14.
TA = 105.8 – (1.0 ⋅ 28)
TA = 78.6
TJ = TC + (P ⋅ θJC)
Table 14 through Table 17 and Figure 15 through
F i g u r e 1 8 s h o w TA b a s e d o n t h e p r e c e d i n g
assumptions and calculations for a range of θJA values
with airflow from 0 linear feet per minute to 600 linear
feet per minute.
Table 13 shows TJ values for the various versions of
the Am186ED microcontroller. The column titled
Speed/Pkg/Board in Table 13 indicates the clock speed
in MHz, the type of package (P for PQFP and T for
TQFP), and the type of board (2 for 2-layer and 4-6 for
4-layer to 6-layer).
52
TA for a 33-MHz TQFP design with a 4-layer to 6-layer
board and 200 fpm airflow is calculated as follows:
See Table 17 for the result of this calculation.
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
Table 14 shows typical maximum ambient temperatures in degrees Centigrade for a PQFP package used on a 2layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature.
Figure 15 graphically illustrates the typical temperatures in Table 14.
Table 14.
Typical Ambient Temperatures (°C) for PQFP with a 2-Layer Board
Linear Feet per Minute Airflow
Microcontroller
Speed
Typical Power
(Watts)
0 fpm
200 fpm
400 fpm
600 fpm
40 MHz
1.2
55.2
62.2
67.0
69.3
33 MHz
1.0
63.0
68.8
72.7
74.7
25 MHz
0.7
72.0
76.4
79.4
80.8
20 MHz
0.6
77.6
81.1
83.5
84.7
Typical Ambient Temperature (Degrees C)
90
Legend:
● 40 MHz
✵ 33 MHz
◆ 25 Mhz
■ 20 MHz
T
F
■
■
80
◆
■
◆
■
◆
✶
✶
◆
70
●
✶
✶
●
60
●
50
D
40
0 fpm
R
200 fpm
●
A
400 fpm
600 fpm
Airflow (Linear Feet Per Minute)
Figure 15. Typical Ambient Temperatures for PQFP with a 2-Layer Board
Am186ED/EDLV Microcontrollers
53
P R E L I M I N A R Y
Table 15 shows typical maximum ambient temperatures in degrees Centigrade for a TQFP package used on a 2layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature.
Figure 16 graphically illustrates the typical temperatures in Table 15.
Table 15. Typical Ambient Temperatures (°C) for TQFP with a 2-Layer Board
Linear Feet per Minute Airflow
Microcontroller
Speed
Typical Power
(Watts)
0 fpm
200 fpm
400 fpm
600 fpm
40 MHz
1.2
45.7
57.5
64.6
67.0
33 MHz
1.0
55.2
65.0
70.8
72.7
25 MHz
0.7
66.1
73.5
77.9
79.4
20 MHz
0.6
72.9
78.8
82.3
83.5
85
Typical Ambient Temperature (Degrees C)
■
Legend:
● 40 MHz
✵ 33 MHz
◆ 25 Mhz
■ 20 MHz
T
F
◆
■
◆
75
■
◆
✶
✶
65
◆
●
✶
●
55
✶
45
●
D
35
0 fpm
Figure 16.
54
■
R
200 fpm
●
A
400 fpm
Airflow (Linear Feet Per Minute)
Typical Ambient Temperatures for TQFP with a 2-Layer Board
Am186ED/EDLV Microcontrollers
600 fpm
P R E L I M I N A R Y
Table 16 shows typical maximum ambient temperatures in degrees Centigrade for a PQFP package used on a 4layer to 6-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case
temperature. Figure 17 graphically illustrates the typical temperatures in Table 16.
Table 16. Typical Ambient Temperatures (°C) for PQFP with a 4-Layer to 6-Layer Board
Linear Feet per Minute Airflow
Microcontroller
Speed
Typical Power
(Watts)
0 fpm
200 fpm
400 fpm
600 fpm
40 MHz
1.2
78.8
81.1
83.5
85.8
33 MHz
1.0
82.5
84.4
86.4
88.3
25 MHz
0.7
86.7
88.2
89.7
91.2
20 MHz
0.6
89.4
90.6
91.7
92.9
95
Typical Ambient Temperature (Degrees C)
■
Legend:
● 40 MHz
✵ 33 MHz
◆ 25 Mhz
■ 20 MHz
T
F
■
90
■
◆
■
✶
◆
◆
85
◆
✶
✶
●
●
✶
●
80
●
75
D
70
0 fpm
Figure 17.
R
200 fpm
A
400 fpm
600 fpm
Airflow (Linear Feet Per Minute)
Typical Ambient Temperatures for PQFP with a 4-Layer to 6-Layer Board
Am186ED/EDLV Microcontrollers
55
P R E L I M I N A R Y
Table 17 shows typical maximum ambient temperatures in degrees Centigrade for a TQFP package used on a 4layer to 6-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case
temperature. Figure 18 graphically illustrates the typical temperatures in Table 17.
Table 17. Typical Ambient Temperatures (°C) for TQFP with a 4-Layer to 6-Layer Board
Linear Feet per Minute Airflow
Microcontroller
Speed
Typical Power
(Watts)
0 fpm
200 fpm
400 fpm
600 fpm
40 MHz
1.2
71.7
74.0
76.4
78.8
33 MHz
1.0
76.6
78.6
80.5
82.5
25 MHz
0.7
82.3
83.8
85.3
86.7
20 MHz
0.6
85.8
87.0
88.2
89.4
90
■
Typical Ambient Temperature (Degrees C)
■
Legend:
● 40 MHz
✵ 33 MHz
◆ 25 Mhz
■ 20 MHz
T
F
■
◆
■
◆
85
◆
✶
◆
✶
80
●
✶
✶
75
●
●
70
D
65
0 fpm
R
A
200 fpm
●
400 fpm
600 fpm
Airflow (Linear Feet Per Minute)
Figure 18. Typical Ambient Temperatures for TQFP with a 4-Layer to 6-Layer Board
56
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
COMMERCIAL AND INDUSTRIAL SWITCHING CHARACTERISTICS AND WAVEFORMS
In the switching waveforms that follow, several
abbreviations are used to indicate the specific periods
of a bus cycle. These periods are referred to as time
states. A typical bus cycle is composed of four
consecutive time states: t1, t2, t3, and t4. Wait states,
which represent multiple t3 states, are referred to as tw
states. When no bus cycle is pending, an idle (ti) state
occurs.
In t h e s w i tc h i n g pa r a m e te r de s c r i p t i on s , t h e
multiplexed address is referred to as the AD address
bus; the demultiplexed address is referred to as the A
address bus.
Key to Switching Waveforms
WAVEFORM
D
R
INPUT
OUTPUT
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
Off State
Invalid
Invalid
A
Am186ED/EDLV Microcontrollers
T
F
57
P R E L I M I N A R Y
Alphabetical Key to Switching Parameter Symbols
Parameter Symbol
No.
tARYCH
49
ARDY Resolution Transition Setup Time
tARYCHL
51
ARDY Inactive Holding Time
tARYHDSH(a)
tARYHDV(a)
95
ARDY High to DS High
89
ARDY Assert to Data Valid
tARYLCL
52
ARDY Setup Time
tARYLDSH(a)
96
ARDY Low to DS High
tAVBL
87
A Address Valid to WHB, WLB Low
tAVCH
14
AD Address Valid to Clock High
tAVLL
12
AD Address Valid to ALE Low
tAVRL
66
A Address Valid to RD Low
tAVWL
65
A Address Valid to WR Low
tAZRL
24
AD Address Float to RD Active
tCH1CH2
45
CLKOUTA Rise Time
tCHAV
68
CLKOUTA High to A Address Valid
T
F
tCHCA
104
CLKOUTA High to CAS Active
tCHCAV
101
CLKOUTA Low to Column Address Valid
tCHCK
38
X1 High Time
tCHCL
44
CLKOUTA High Time
tCHCSV
67
CLKOUTA High to LCS/UCS Valid
tCHCSX
18
MCS/PCS Inactive Delay
tCHCTV
22
Control Active Delay 2
tCHCV
64
Command Lines Valid Delay (after Float)
Command Lines Float Delay
tCHCZ
63
tCHDX
8
tCHLH
9
tCHLL
11
tCHRA
106
D
58
Description
R
A
Status Hold Time
ALE Active Delay
ALE Inactive Delay
CLKOUTA High to RAS Active
tCHSV
3
Status Active Delay
tCICOA
69
X1 to CLKOUTA Skew
tCICOB
70
X1 to CLKOUTB Skew
tCHRX
103
CLKOUTA High to RAS Inactive
tCKHL
39
X1 Fall Time
tCKIN
36
X1 Period
tCKLH
40
X1 Rise Time
tCL2CL1
46
CLKOUTA Fall Time
tCLARX
50
ARDY Active Hold Time
tCLAV
5
AD Address Valid Delay and BHE
tCLAX
6
Address Hold
tCLAZ
15
AD Address Float Delay
tCLCH
43
CLKOUTA Low Time
tCLCK
37
X1 Low Time
tCLCL
42
CLKOUTA Period
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
Alphabetical Key to Switching Parameter Symbols (continued)
Parameter Symbol
No.
Description
tCLCSV
16
MCS/PCS Active Delay
tCLCX
105
CLKOUTA Low to CAS Inactive
tCLRX
107
CLKOUTA Low to RAS Inactive
tCLDOX
30
Data Hold Time
tCLDV
7
Data Valid Delay
tCLDX
2
Data in Hold
tCLHAV
62
HLDA Valid Delay
tCLRA
102
CLKOUTA Low to RAS Active
tCLRH
27
RD Inactive Delay
tCLRL
25
RD Active Delay
tCLSH
4
Status Inactive Delay
tCLSRY
48
SRDY Transition Hold Time
tCLTMV
55
Timer Output Delay
tCOAOB(a)
tCSHARYL(a)
83
CLKOUTA to CLKOUTB Skew
88
Chip Select to ARDY Low
tCVCTV
20
Control Active Delay 1
tCVCTX
31
Control Inactive Delay
tCVDEX
21
DEN Inactive Delay
T
F
tCXCSX
17
MCS/PCS Hold from Command Inactive
tDSHDIR(a)
92
DS High to Data Invalid—Read
tDSHDIW
98
DS High to Data Invalid—Write
tDSHDX(a)
93
DS High to Data Bus Turn-off Time
tDSHLH
41
DS Inactive to ALE Inactive
tDSLDD(a)
tDSLDV(a)
tDVCL
tDVDSL(a)
D
tDXDL
tHVCL
tINVCH
tINVCL
R
A
90
DS Low to Data Driven
91
DS Low to Data Valid
1
Data in Setup
97
Data Valid to DS Low
19
DEN Inactive to DT/R Low
58
HOLD Setup
53
Peripheral Setup Time
54
DRQ Setup Time
tLHAV
23
ALE High to Address Valid
tLHLL
10
ALE Width
tLLAX
13
AD Address Hold from ALE Inactive
tLOCK
61
Maximum PLL Lock Time
tPLAL
99
PCS Active to ALE Inactive
tRD0W
110
RAS To Column Address Delay Time with 0 Wait States
tRD1W
111
RAS to Column Address Delay Time with 1 or More Wait States
tRESIN
57
RES Setup Time
tRHAV
29
RD Inactive to AD Address Active
tRHDX
59
RD High to Data Hold on AD Bus
94
RD High to Data Bus Turn-off Time
28
RD Inactive to ALE High
tRHDZ
(a)
tRHLH
Am186ED/EDLV Microcontrollers
59
P R E L I M I N A R Y
Alphabetical Key to Switching Parameter Symbols (continued)
Parameter Symbol
No.
Description
tRLRH
26
RD Pulse Width
tRP0W
108
RAS Inactive Pulse Width (0 Wait States)
tRP1W
109
RAS Inactive Pulse Width (1 Wait State)
tSRYCL
47
SRDY Transition Setup Time
tWHDEX
35
WR Inactive to DEN Inactive
tWHDX
34
Data Hold after WR
tWHLH
33
WR Inactive to ALE High
tWLWH
32
WR Pulse Width
Note:
a Specs 83 and 88–97 are defined but not used at this time. Additionally, the following parameters are not defined nor used at
this time: 56, 60, and 71–78.
D
60
R
A
Am186ED/EDLV Microcontrollers
T
F
P R E L I M I N A R Y
Numerical Key to Switching Parameter Symbols
No.
Parameter Symbol
Description
1
tDVCL
Data in Setup
2
tCLDX
Data in Hold
3
tCHSV
Status Active Delay
4
tCLSH
Status Inactive Delay
5
tCLAV
AD Address Valid Delay and BHE
6
tCLAX
Address Hold
7
tCLDV
Data Valid Delay
8
tCHDX
Status Hold Time
9
tCHLH
ALE Active Delay
10
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
12
tAVLL
AD Address Valid to ALE Low
13
tLLAX
AD Address Hold from ALE Inactive
14
tAVCH
AD Address Valid to Clock High
15
tCLAZ
AD Address Float Delay
16
tCLCSV
MCS/PCS Active Delay
17
tCXCSX
MCS/PCS Hold from Command Inactive
18
tCHCSX
MCS/PCS Inactive Delay
19
tDXDL
DEN Inactive to DT/R Low
20
tCVCTV
Control Active Delay 1
21
tCVDEX
DEN Inactive Delay
22
tCHCTV
Control Active Delay 2
23
tLHAV
24
tAZRL
25
tCLRL
26
tRLRH
27
tCLRH
28
29
30
31
32
33
34
35
D
tRHLH
tRHAV
tCLDOX
tCVCTX
A
ALE High to Address Valid
R
T
F
AD Address Float to RD Active
RD Active Delay
RD Pulse Width
RD Inactive Delay
RD Inactive to ALE High
RD Inactive to AD Address Active
Data Hold Time
Control Inactive Delay
tWLWH
WR Pulse Width
tWHLH
WR Inactive to ALE High
tWHDX
Data Hold after WR
tWHDEX
WR Inactive to DEN Inactive
36
tCKIN
X1 Period
37
tCLCK
X1 Low Time
38
tCHCK
X1 High Time
39
tCKHL
X1 Fall Time
40
tCKLH
X1 Rise Time
41
tDSHLH
DS Inactive to ALE Inactive
42
tCLCL
CLKOUTA Period
Am186ED/EDLV Microcontrollers
61
P R E L I M I N A R Y
Numerical Key to Switching Parameter Symbols (continued)
No.
Parameter Symbol
43
tCLCH
CLKOUTA Low Time
44
tCHCL
CLKOUTA High Time
45
tCH1CH2
CLKOUTA Rise Time
46
tCL2CL1
CLKOUTA Fall Time
47
tSRYCL
SRDY Transition Setup Time
48
tCLSRY
SRDY Transition Hold Time
49
tARYCH
ARDY Resolution Transition Setup Time
50
tCLARX
ARDY Active Hold Time
51
tARYCHL
ARDY Inactive Holding Time
52
tARYLCL
ARDY Setup Time
53
tINVCH
Peripheral Setup Time
54
tINVCL
DRQ Setup Time
55
tCLTMV
Timer Output Delay
57
tRESIN
RES Setup Time
58
tHVCL
HOLD Setup
59
tRHDX
RD High to Data Hold on AD Bus
61
tLOCK
Maximum PLL Lock Time
62
tCLHAV
HLDA Valid Delay
63
tCHCZ
Command Lines Float Delay
64
tCHCV
Command Lines Valid Delay (after Float)
65
tAVWL
A Address Valid to WR Low
66
tAVRL
A Address Valid to RD Low
67
tCHCSV
68
tCHAV
69
tCICOA
70
tCICOB
83(a)
tCOAOB
87
88(a)
89(a)
90(a)
91(a)
92(a)
93(a)
62
D
tAVBL
tCSHARYL
tARYHDV
tDSLDD
Description
A
CLKOUTA High to LCS/UCS Valid
R
CLKOUTA High to A Address Valid
X1 to CLKOUTA Skew
X1 to CLKOUTB Skew
CLKOUTA to CLKOUTB Skew
A Address Valid to WHB, WLB Low
Chip Select to ARDY Low
ARDY Assert to Data Valid
DS Low to Data Driven
tDSLDV
DS Low to Data Valid
tDSHDIR
DS High to Data Invalid—Read
tDSHDX
DS High to Data Bus Turn-off Time
Am186ED/EDLV Microcontrollers
T
F
P R E L I M I N A R Y
Numerical Key to Switching Parameter Symbols (continued)
No.
Parameter Symbol
94(a)
Description
tRHDZ
95(a)
tARYHDSH
ARDY High to DS High
96(a)
tARYLDSH
ARDY Low to DS High
97(a)
tDVDSL
Data Valid to DS Low
98
tDSHDIW
DS High to Data Invalid—Write
99
tPLAL
101
tCHCAV
102
tCLRA
CLKOUTA Low to RAS Active
103
tCHRX
CLKOUTA High to RAS Inactive
104
tCHCA
CLKOUTA High to CAS Active
105
tCLCX
CLKOUTA Low to CAS Inactive
106
tCHRA
CLKOUTA High to RAS Active
107
tCLRX
CLKOUTA Low to RAS Inactive
108
tRP0W
RAS Inactive Pulse Width (0 Wait States)
109
tRP1W
RAS Inactive Pulse Width (1 Wait State)
110
tRD0W
RAS To Column Address Delay Time with 0 Wait States
111
tRD1W
RAS to Column Address Delay Time with 1 or More Wait States
RD High to Data Bus Turn-off Time
PCS Active to ALE Inactive
CLKOUTA Low to Column Address Valid
T
F
Note:
a Specs 83 and 88–97 are defined but not used at this time. Additionally, the following parameters are not defined nor used at
this time: 56, 60, and 71–78.
D
R
A
Am186ED/EDLV Microcontrollers
63
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
Read Cycle (20 MHz and 25 MHz)
Preliminary
Parameter
No.
Symbol
20 MHz
Description
Min
25 MHz
Max
Min
Max
Unit
General Timing Requirements
1
tDVCL
Data in Setup
10
10
ns
2
tCLDX
Data in Hold(c)
3
3
ns
General Timing Responses
3
tCHSV
Status Active Delay
4
tCLSH
Status Inactive Delay
0
25
0
20
ns
5
tCLAV
AD Address Valid Delay and BHE
0
25
0
20
ns
6
tCLAX
Address Hold
0
25
0
20
8
tCHDX
Status Hold Time
0
9
tCHLH
ALE Active Delay
10
tLHLL
ALE Width
0
20
ns
0
20
ns
0
25
0
20
ns
0
25
0
20
ns
28
15
24
ns
AD Address Valid to ALE Low(a)
tCLCH –2
13
tLLAX
AD Address Hold from ALE Inactive(a)
tCHCL –2
14
tAVCH
AD Address Valid to Clock High
15
tCLAZ
AD Address Float Delay
tCLAX =0
16
tCLCSV
MCS/PCS Active Delay
0
17
tCXCSX
MCS/PCS Hold from Command Inactive(a)
18
tCHCSX
MCS/PCS Inactive Delay
19
tDXDL
DEN Inactive to DT/R Low(a)
20
tCVCTV
Control Active Delay 1(b)
21
tCVDEX
DEN Inactive Delay
22
tCHCTV
Control Active Delay 2(b)
23
tLHAV
ALE High to Address Valid
99
tPLAL
PCS Active to ALE Inactive
tCLCL –10=30
25
0
tCLCH –2
A
0
0
20
tCLCH –2
AD Address Float to RD Active
25
tCLRL
RD Active Delay
0
26
tRLRH
RD Pulse Width
2tCLCL –15=85
27
tCLRH
RD Inactive Delay
28
tRHLH
RD Inactive to ALE High(a)
ns
ns
ns
0
ns
25
tCLAX =0
20
ns
25
0
20
ns
20
ns
tCLCH –2
25
0
0
15
0
0
ns
tCHCL –2
20
15
tAZRL
Active(a)
ns
ns
25
ALE Inactive Delay
tAVLL
D
0
ns
0
tCHLL
R
20
T
F
11
24
0
25
tCLCL –10=40
12
Read Cycle Timing Responses
25
0
ns
20
2tCLCL –15=65
25
0
ns
ns
0
25
ns
ns
ns
20
ns
tCLCH –3
tCLCH –3
ns
tCLCL –10=40
tCLCL –10=30
ns
tCLCH –2=21
tCLCH –2=16
ns
0
0
ns
tCLCL + tCHCL–3
tCLCL + tCHCL–3
ns
29
tRHAV
RD Inactive to AD Address
41
tDSHLH
DS Inactive to ALE Active
59
tRHDX
RD High to Data Hold on AD Bus(c)
66
tAVRL
A Address Valid to RD Low(a)
67
tCHCSV
CLKOUTA High to LCS/UCS Valid
0
25
0
20
ns
68
tCHAV
CLKOUTA High to A Address Valid
0
25
0
20
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
Equal loading on referenced pins.
b
This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals.
c
If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
64
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Read Cycle (33 MHz and 40 MHz)
Preliminary
Parameter
No.
Symbol
33 MHz
Description
Min
40 MHz
Max
Min
Max
Unit
General Timing Requirements
1
tDVCL
Data in Setup
8
5
ns
2
tCLDX
Data in Hold(c)
3
2
ns
General Timing Responses
3
tCHSV
Status Active Delay
0
4
tCLSH
Status Inactive Delay
0
15
0
12
ns
5
tCLAV
AD Address Valid Delay and BHE
0
15
0
12
ns
6
tCLAX
Address Hold
0
15
0
12
ns
8
tCHDX
Status Hold Time
0
9
tCHLH
ALE Active Delay
10
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
12
tAVLL
AD Address Valid to ALE Low(a)
15
0
0
15
tCLCL –10=20
Inactive(a)
12
T
F
12
tCLCH –2
ns
ns
ns
ns
13
tLLAX
AD Address Hold from ALE
14
tAVCH
AD Address Valid to Clock High
15
tCLAZ
AD Address Float Delay
tCLAX =0
15
tCLAX =0
12
ns
16
tCLCSV
MCS/PCS Active Delay
0
15
0
12
ns
17
tCXCSX
MCS/PCS Hold from Command Inactive(a)
18
tCHCSX
MCS/PCS Inactive Delay
Low(a)
19
tDXDL
DEN Inactive to DT/R
20
tCVCTV
Control Active Delay 1(b)
21
tCVDEX
DEN Inactive Delay
22
tCHCTV
Control Active Delay 2(b)
23
tLHAV
ALE High to Address Valid
99
tPLAL
PCS Active to ALE Inactive
Read Cycle Timing Responses
D
R
tAZRL
AD Address Float to RD Active
25
tCLRL
RD Active Delay
26
tRLRH
RD Pulse Width
24
tCHCL –2
ns
ns
tCLCL –5=20
15
tCLCH –2
12
0
tCLCH –2
A
0
0
0
tCHCL –2
ns
0
ns
tCLCH –2
15
0
12
0
15
0
12
ns
ns
ns
ns
0
15
0
12
ns
0
15
0
12
ns
18
ns
10
12
7.5
20
10
0
0
0
15
2tCLCL –15=45
0
ns
0
ns
10
2tCLCL –10=40
15
27
tCLRH
RD Inactive Delay
28
tRHLH
RD Inactive to ALE High(a)
29
tRHAV
RD Inactive to AD Address Active(a)
41
tDSHLH
DS Inactive to ALE Active
59
tRHDX
RD High to Data Hold on AD Bus(c)
66
tAVRL
A Address Valid to RD Low(a)
67
tCHCSV
CLKOUTA High to LCS/UCS Valid
0
15
0
10
ns
68
tCHAV
CLKOUTA High to A Address Valid
0
15
0
10
ns
tCLCH –3
0
ns
ns
12
ns
tCLCH –2
ns
tCLCL –10=20
tCLCL –5=20
ns
tCLCH –2=11.5
tCLCH –2=9.25
0
0
ns
tCLCL + tCHCL–3
tCLCL + tCHCL–1.25
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
Equal loading on referenced pins.
b
This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals.
c
If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
Am186ED/EDLV Microcontrollers
65
P R E L I M I N A R Y
READ CYCLE WAVEFORMS
t1
t2
t3
t4
tW
CLKOUTA
66
Address
A19–A0
8
68
S6
S6
INVALID
S6
14
1
6
(a)
AD15–AD0 ,
AD7–AD0(b)
Address
Data
2
Address
AD15–AD8(b)
23
11
59
ALE
15
10
RD
28
24
26
12
5
25
BHE(a)
67
13
LCS, UCS
99
16
DEN, DS
D
19
DT/R
22
S2–S0
A
BHE
MCS1–MCS0,
PCS6–PCS5,
PCS3–PCS0
R
(c)
20
4
Status
3
UZI
Notes:
a Am186ED/EDLV microcontrollers in 16-bit mode
b
Am186ED/EDLV microcontrollers in 8-bit mode
c
Changes in t phase preceding next bus cycle if followed by read, INTA, or halt.
66
T
F
29
9
Am186ED/EDLV Microcontrollers
27
41
18
17
21
22
(c)
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
Write Cycle (20 MHz and 25 MHz)
Preliminary
Parameter
No.
Symbol
20 MHz
Description
Min
25 MHz
Max
Min
Max
Unit
General Timing Responses
3
tCHSV
Status Active Delay
0
25
0
20
ns
4
tCLSH
Status Inactive Delay
0
25
0
20
ns
5
tCLAV
AD Address Valid Delay and BHE
0
25
0
20
ns
6
tCLAX
Address Hold
0
25
0
20
ns
7
tCLDV
Data Valid Delay
0
15
0
15
8
tCHDX
Status Hold Time
0
9
tCHLH
ALE Active Delay
10
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
12
tAVLL
AD Address Valid to ALE Low(a)
0
25
tCLCL –10=40
20
tCLCL –10=30
25
ns
ns
20
T
F
ns
15
28
15
24
ns
25
0
20
ns
tCLCH –2
Inactive(a)
ns
ns
ns
13
tLLAX
AD Address Hold from ALE
14
tAVCH
AD Address Valid to Clock High
16
tCLCSV
MCS/PCS Active Delay
17
tCXCSX
MCS/PCS Hold from Command Inactive(a)
18
tCHCSX
MCS/PCS Inactive Delay
0
19
tDXDL
DEN Inactive to DT/R Low(a)
0
20
tCVCTV
Control Active Delay 1(b)
0
15
0
15
ns
21
tCVDEX
DS Inactive Delay
0
25
0
20
ns
22
tCHCTV
Control Active Delay 2
0
25
0
20
ns
23
tLHAV
ALE High to Address Valid
99
tPLAL
PCS Active to ALE Inactive
Write Cycle Timing Responses
30
tCLDOX
Data Hold Time
31
tCVCTX
Control Inactive
R
Delay(b)
tCHCL–2
20
tCLCH –2
0
0
tCLCH –2
A
25
ns
0
ns
0
20
tCLCH –2
25
0
20
0
15
0
0
tCHCL–2
0
ns
ns
ns
ns
ns
ns
32
tWLWH
WR Pulse Width
33
tWHLH
WR Inactive to ALE High(a)
34
tWHDX
Data Hold after WR(a)
35
tWHDEX
WR Inactive to DEN Inactive(a)
41
tDSHLH
DS Inactive to ALE Active
65
tAVWL
A Address Valid to WR Low
67
tCHCSV
CLKOUTA High to LCS/UCS Valid
0
25
0
20
ns
68
tCHAV
CLKOUTA High to A Address Valid
0
25
0
20
ns
87
tAVBL
A Address Valid to WHB, WLB Low
tCHCL –3
25
tCHCL –3
20
ns
98
tDSHDIW
D
DS High to Data Invalid—Write
2tCLCL –10=90
2tCLCL –10=70
ns
tCLCH –2
tCLCH –2
ns
tCLCL –10=40
tCLCL –10=30
ns
tCLCH –3
tCLCH –3
ns
tCLCH –2=21
tCLCH –2=16
ns
tCLCL+tCHCL –3
tCLCL +tCHCL –3
ns
35
30
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL =0.45 V and VIH = 2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals.
Am186ED/EDLV Microcontrollers
67
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Write Cycle (33 MHz and 40 MHz)
Preliminary
Parameter
No.
Symbol
33 MHz
Description
Min
40 MHz
Max
Min
Max
Unit
General Timing Responses
3
tCHSV
Status Active Delay
0
15
0
12
ns
4
tCLSH
Status Inactive Delay
0
15
0
12
ns
5
tCLAV
AD Address Valid Delay and BHE
0
15
0
12
ns
6
tCLAX
Address Hold
0
7
tCLDV
Data Valid Delay
0
8
tCHDX
Status Hold Time
0
9
tCHLH
ALE Active Delay
10
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
12
tAVLL
AD Address Valid to ALE Low(a)
0
15
0
12
0
15
tCLCL –10=20
ns
ns
12
tCLCL –5=20
15
ns
ns
10
T
F
ns
12
20
10
18
ns
15
0
12
ns
tCLCH –2
Inactive(a)
ns
ns
13
tLLAX
AD Address Hold from ALE
14
tAVCH
AD Address Valid to Clock High
16
tCLCSV
MCS/PCS Active Delay
17
tCXCSX
MCS/PCS Hold from Command Inactive(a)
18
tCHCSX
MCS/PCS Inactive Delay
0
19
tDXDL
DEN Inactive to DT/R Low(a)
0
20
tCVCTV
Control Active Delay 1(b)
0
15
0
12
ns
21
tCVDEX
DS Inactive Delay
0
15
0
12
ns
22
tCHCTV
Control Active Delay 2
0
15
0
12
ns
23
tLHAV
ALE High to Address Valid
99
tPLAL
PCS Active to ALE Inactive
Write Cycle Timing Responses
30
tCLDOX
Data Hold Time
R
Delay(b)
31
tCVCTX
Control Inactive
32
tWLWH
WR Pulse Width
33
tWHLH
WR Inactive to ALE High(a)
D
tCHCL–2
12
tCLCH –2
0
0
tCLCH –2
A
WR(a)
15
ns
0
ns
0
12
tCLCH –2
15
0
12
0
7.5
0
0
tCHCL–2
0
ns
ns
ns
ns
ns
ns
2tCLCL –10=50
2tCLCL –10=40
ns
tCLCH –2
tCLCH –2
ns
tCLCL –10=20
tCLCL –10=15
ns
tCLCH –3
tCLCH –3
ns
34
tWHDX
Data Hold after
35
tWHDEX
WR Inactive to DEN Inactive(a)
41
tDSHLH
DS Inactive to ALE Active
tCLCH –2=11.5
tCLCH –2=9.25
ns
65
tAVWL
A Address Valid to WR Low
tCLCL +tCHCL –3
tCLCL +tCHCL –1.25
ns
67
tCHCSV
CLKOUTA High to LCS/UCS Valid
0
15
0
10
ns
68
tCHAV
CLKOUTA High to A Address Valid
0
15
0
10
ns
87
tAVBL
A Address Valid to WHB, WLB Low
tCHCL –3
15
tCHCL –1.25
12
ns
98
tDSHDIW
DS High to Data Invalid—Write
20
15
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals.
68
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
WRITE CYCLE WAVEFORMS
t1
t2
t3
t4
tW
CLKOUTA
65
A19–A0
Address
68
8
S6
S6
INVALID
S6
14
AD15–AD0(a)
7
,
30
Address
Data
AD7–AD0(b)
6
AD15–AD8(b)
T
F
Address
23
11
9
34
13
ALE
31
10
33
32
WR
12
20
WHB, WLB
87
5
BHE
67
LCS, UCS
R
16
MCS3–MCS0,
PCS6–PCS5,
PCS3–PCS0
DEN
DS
DT/R
S2–S0
D
22
41
20
A
31
BHE
99
18
17
35
20
31
98
21
20
19
(c)
(c)
22
Status
3
4
UZI
Notes:
a Am186ED/EDLV microcontrollers in 16-bit mode
b
Am186ED/EDLV microcontrollers in 8-bit mode
c
Changes in t phase preceding next bus cycle if followed by read, INTA, or halt
Am186ED/EDLV Microcontrollers
69
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
DRAM
Parameter
No. Symbol
Description
General Timing Responses
101
tCHCAV CLKOUTA Low to Column
Address Valid
CLKOUTA Low to RAS Active
102
tCLRA
103
tCHRX
CLKOUTA High to RAS Inactive
CLKOUTA High to CAS Active
104
tCHCA
105
tCLCX
CLKOUTA Low to CAS Inactive
106
tCHRA
CLKOUTA High to RAS Active
CLKOUTA Low to RAS Inactive
107
tCLRX
108
tRP0W
RAS Inactive Pulse Width with 0
Wait States
RAS Inactive Pulse Width with 1 or
109
tRP1W
More Wait States
RAS To Column Address Delay
110
tRD0W
Time with 0 Wait States
RAS to Column Address Delay
111
tRD1W
Time with 1 or More Wait States
20 MHz
Min
Max
Preliminary
25 MHz
33 MHz
Min
Max
Min
Max
40 MHz
Min
Max
Unit
0
25
0
20
0
15
0
12
ns
3
3
3
3
3
3
60
25
25
25
25
25
25
—
3
3
3
3
3
3
50
20
20
20
20
20
20
—
3
3
3
3
3
3
40
15
15
15
15
15
15
—
3
3
3
3
3
3
30
12
12
12
12
12
12
—
ns
ns
ns
ns
ns
ns
ns
70
—
60
—
25
—
20
—
30
—
25
—
T
F
50
—
40
—
ns
15
—
15
—
ns
20
—
15
—
ns
Frequency
As guaranteed by design, the following table shows the minimum time for RAS assertion to RAS assertion. These
minimums correlate to DRAM spec tRC.
40 MHz
33 MHz
25 MHz
20 MHz
0
90
110
130
150
D
70
Wait States
1
2
110
130
130
150
150
170
170
190
3
150
170
190
210
R
A
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
DRAM Read Cycle Timing with No-Wait States
t3
t4
t1
t2
t3
t4
t1
CLKOUTA
5
15
AD[15:0]
1
Data
Addr.
2
68
101
A[17:1]
Column
Row
110
103
102
RAS
108
104
CAS
25
T
F
105
27
RD(a)
Note:
a The RD output connects to the DRAM output enable (OE) pin for read operations.
A
DRAM Read Cycle Timing with Wait State(s)
t4
CLKOUTA
AD[15:0]
A[17:1]
RAS
D
R
t1
5
t2
t3
tw
t4
15
1
Addr.
68
t1
Data
2
101
Row
Column
110
107
102
109
104
105
CAS
RD(a)
25
27
Note:
a The RD output connects to the DRAM output enable (OE) pin for read operations.
Am186ED/EDLV Microcontrollers
71
P R E L I M I N A R Y
DRAM Write Cycle Timing with No-Wait States
t4
t1
t2
t3
t4
t1
CLKOUTA
5
7
30
Addr.
AD[15:0]
Data
68
101
Row
A[17:1]
Column
110
103
102
RAS
108
T
F
105
104
CAS
20
31
WR(a)
Note:
a Write operations use the WR output connected to the DRAM write enable (WE) pin.
A
DRAM Write Cycle Timing With Wait State(s)
t4
CLKOUTA
D
AD[15:0]
A[17:1]
RAS
R
t1
5
t2
t3
tw
t4
t1
7
30
Addr.
68
Data
101
Row
102
Column
110
107
109
104
105
CAS
WR(a)
20
Note:
a Write operations use the WR output connected to the DRAM write enable (WE) pin.
72
Am186ED/EDLV Microcontrollers
31
P R E L I M I N A R Y
DRAM CAS-before-RAS Cycle Timing
t4
t1
t2
tW
tW
tW
t3
t4
t1
CLKOUTA
5
AD[15:0]
15
FFFF
68
A[17:1]
101
X
X
107
106
RAS
T
F
109
104
105
CAS(a)
25
27
RD(b)
Notes:
a CAS before RAS cycle timing is always 7 clocks, independent of wait state timing.
b
A
The RD output connects to the DRAM output enable (OE) pin for read operations.
D
R
Am186ED/EDLV Microcontrollers
73
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
Interrupt Acknowledge Cycle (20 MHz and 25 MHz)
Preliminary
Parameter
No.
Symbol
20 MHz
Description
Min
25 MHz
Max
Min
Max
Unit
General Timing Requirements
1
tDVCL
Data in Setup
10
10
ns
2
tCLDX
Data in Hold
3
3
ns
General Timing Responses
3
tCHSV
Status Active Delay
0
25
0
20
ns
4
tCLSH
Status Inactive Delay
0
25
0
20
ns
7
tCLDV
Data Valid Delay
0
25
0
20
ns
8
tCHDX
Status Hold Time
0
9
tCHLH
ALE Active Delay
10
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
0
25
tCLCL –10=40
tCLCL –10=30
T
F
25
12
tAVLL
AD Address Invalid to ALE
15
tCLAZ
AD Address Float Delay
Low(a)
tCLCH –2
tCLAX =0
Low(a)
ns
20
20
tCLCH –2
25
20
ns
ns
ns
19
tDXDL
DEN Inactive to DT/R
tCVCTV
Control Active Delay 1(b)
21
tCVDEX
DEN Inactive Delay
0
25
0
20
ns
22
tCHCTV
Control Active Delay 2(c)
0
25
0
20
ns
ALE High to Address Valid
20
23
tLHAV
tCVCTX
Control Inactive Delay(b)
68
tCHAV
CLKOUTA High to A Address Valid
0
A
0
ns
20
31
0
tCLAX =0
ns
25
0
20
15
ns
ns
ns
0
25
0
20
ns
0
25
0
20
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
R
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the INTA1–INTA0 signals.
c
This parameter applies to the DEN and DT/R signals.
74
D
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Interrupt Acknowledge Cycle (33 MHz and 40 MHz)
Preliminary
Parameter
No.
Symbol
33 MHz
Description
Min
40 MHz
Max
Min
Max
Unit
General Timing Requirements
1
tDVCL
Data in Setup
8
5
ns
2
tCLDX
Data in Hold
3
2
ns
General Timing Responses
3
tCHSV
Status Active Delay
0
15
0
12
ns
4
tCLSH
Status Inactive Delay
0
15
0
12
ns
7
tCLDV
Data Valid Delay
0
15
0
12
ns
8
tCHDX
Status Hold Time
0
9
tCHLH
ALE Active Delay
10
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
0
15
tCLCL –10=20
tCLCL –5=20
T
F
15
12
tAVLL
AD Address Invalid to ALE
15
tCLAZ
AD Address Float Delay
Low(a)
tCLCH
tCLAX =0
Low(a)
ns
12
12
tCLCH
15
12
ns
ns
ns
19
tDXDL
DEN Inactive to DT/R
tCVCTV
Control Active Delay 1(b)
21
tCVDEX
DEN Inactive Delay
0
15
0
12
ns
22
tCHCTV
Control Active Delay 2(c)
0
15
0
12
ns
ALE High to Address Valid
10
23
tLHAV
tCVCTX
Control Inactive Delay(b)
68
tCHAV
CLKOUTA High to A Address Valid
0
A
0
ns
20
31
0
tCLAX =0
ns
15
0
12
7.5
ns
ns
ns
0
15
0
12
ns
0
15
0
10
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
R
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the INTA1–INTA0 signals.
c
This parameter applies to the DEN and DT/R signals.
D
Am186ED/EDLV Microcontrollers
75
P R E L I M I N A R Y
INTERRUPT ACKNOWLEDGE CYCLE WAVEFORMS
t1
t2
t3
t4
tW
CLKOUTA
68
Address
A19–A0
7
S6
8
Invalid
S6
S6
1
2
12
AD15–AD0
Ptr
15
T
F
23
9
ALE
10
11
4
BHE
BHE
INTA1–INTA0
20
DEN
22
DT/R
S2–S0
(b)
D
R
19 (c)
A
31
21
22
4 (a)
3
22 (d)
Status
Notes:
a The status bits become inactive in the state preceding t4.
76
b
The data hold time lasts only until the interrupt acknowledge signal deasserts, even if the interrupt acknowledge
transition occurs prior to tCLDX (min).
c
This parameter applies for an interrupt acknowledge cycle that follows a write cycle.
d
If followed by a write cycle, this change occurs in the state preceding that write cycle.
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
Software Halt Cycle (20 MHz and 25 MHz)
Preliminary
Parameter
No.
Symbol
20 MHz
Description
Min
25 MHz
Max
Min
Max
Unit
General Timing Responses
3
tCHSV
Status Active Delay
0
25
0
20
ns
4
tCLSH
Status Inactive Delay
0
25
0
20
ns
5
tCLAV
AD Address Invalid Delay and BHE
0
25
0
9
tCHLH
ALE Active Delay
10
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
19
tDXDL
DEN Inactive to DT/R Low(a)
0
22
tCHCTV
Control Active Delay 2(b)
0
25
68
tCHAV
CLKOUTA High to A Address Invalid
0
25
20
ns
20
ns
20
ns
0
20
ns
0
20
ns
25
tCLCL –10=40
tCLCL –10=30
25
ns
0
ns
T
F
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN signal.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Software Halt Cycle (33 MHz and 40 MHz)
Parameter
No.
Symbol
General Timing Responses
A
33 MHz
Description
R
Min
Preliminary
40 MHz
Max
3
tCHSV
Status Active Delay
4
tCLSH
Status Inactive Delay
5
tCLAV
AD Address Invalid Delay and BHE
9
tCHLH
ALE Active Delay
10
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
19
tDXDL
DEN Inactive to DT/R Low(a)
0
22
tCHCTV
Control Active Delay 2(b)
0
15
68
tCHAV
CLKOUTA High to A Address Invalid
0
15
D
Min
Max
Unit
0
15
0
12
ns
0
15
0
12
ns
15
0
0
12
ns
12
ns
12
ns
0
12
ns
0
10
ns
15
tCLCL –10=20
tCLCL –5=20
15
ns
0
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN signal.
Am186ED/EDLV Microcontrollers
77
P R E L I M I N A R Y
SOFTWARE HALT CYCLE WAVEFORMS
t1
t2
ti
ti
CLKOUTA
68
A19–A0
Invalid Address
5
Invalid Address
S6, AD15–AD0
10
ALE
9
11
DEN
19
DT/R
22
4
Status
S2–S0
3
D
78
R
A
Am186ED/EDLV Microcontrollers
T
F
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
Clock (20 MHz and 25 MHz)
Preliminary
Parameter
No.
Symbol
20 MHz
Description
25 MHz
Min
Max
60
Min
Max
40
60
Unit
CLKIN Requirements
36
tCKIN
X1 Period(a)
50
37
tCLCK
X1 Low Time (1.5 V)(a)
15
38
tCHCK
X1 High Time (1.5 V)(a)
15
39
tCKHL
X1 Fall Time (3.5 to 1.0 V)(a)
40
tCKLH
X1 Rise Time (1.0 to 3.5
V)(a)
15
ns
ns
15
ns
5
5
ns
5
5
ns
CLKOUT Timing
42
tCLCL
CLKOUTA Period
50
40
ns
43
tCLCH
CLKOUTA Low Time (CL =50 pF)
0.5tCLCL –2=23
0.5tCLCL –2=18
ns
44
tCHCL
CLKOUTA High Time (CL =50 pF)
0.5tCLCL –2=23
45
tCH1CH2
CLKOUTA Rise Time
(1.0 to 3.5 V)
3
46
tCL2CL1
CLKOUTA Fall Time
(3.5 to 1.0 V)
3
0.5tCLCL –2=18
61
tLOCK
Maximum PLL Lock Time
1
69
tCICOA
X1 to CLKOUTA Skew
15
70
tCICOB
X1 to CLKOUTB Skew
25
T
F
ns
3
ns
3
ns
1
ms
15
ns
25
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
A
The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes.
The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2
mode should be used.
R
Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should
be used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation.
D
Am186ED/EDLV Microcontrollers
79
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over Commercial operating ranges
Clock (33 MHz and 40 MHz)
Preliminary
Parameter
No.
Symbol
33 MHz
Description
40 MHz
Min
Max
60
Min
Max
Unit
25
60
ns
CLKIN Requirements
36
tCKIN
X1 Period(a)
30
37
tCLCK
X1 Low Time (1.5 V)(a)
10
38
tCHCK
X1 High Time (1.5
V)(a)
10
39
tCKHL
X1 Fall Time (3.5 to 1.0 V)(a)
5
5
ns
40
tCKLH
X1 Rise Time (1.0 to 3.5 V)(a)
5
5
ns
7.5
ns
7.5
ns
CLKOUT Timing
42
tCLCL
CLKOUTA Period
30
25
ns
43
tCLCH
CLKOUTA Low Time (CL =50 pF)
0.5tCLCL –1.5 =13.5
0.5tCLCL –1.25 =11.25
ns
44
tCHCL
CLKOUTA High Time (CL =50 pF)
0.5tCLCL –1.5 =13.5
45
tCH1CH2
CLKOUTA Rise Time (1.0 to 3.5 V)
46
tCL2CL1
CLKOUTA Fall Time (3.5 to 1.0 V)
3
61
tLOCK
Maximum PLL Lock Time
1
69
tCICOA
X1 to CLKOUTA Skew
15
15
ns
70
tCICOB
X1 to CLKOUTB Skew
25
25
ns
0.5tCLCL –1.25 =11.25
3
T
F
3
ns
ns
3
ns
1
ms
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
A
The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes.
The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2
mode should be used.
Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should
used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation.
D
80
R
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
CLOCK WAVEFORMS
Clock Waveforms—Active Mode
X2
37
36
38
X1
39
40
45
46
CLKOUTA
(Active, F=000)
69
42
43
44
CLKOUTB
70
Clock Waveforms—Power-Save Mode
X2
X1
CLKOUTA
(Power-Save, F=010)
CLKOUTB
(Like X1, CBF=1)
D
CLKOUTB
(Like CLKOUTA, CBF=0)
R
A
Am186ED/EDLV Microcontrollers
T
F
81
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
Ready and Peripheral (20 MHz and 25 MHz)
Preliminary
Preliminary
20 MHz
25 MHz
Parameter
No.
Symbol
Description
Min
Max
Min
Max
Unit
Ready and Peripheral Timing Requirements
47
tSRYCL
SRDY Transition Setup Time(a)
10
10
ns
48
tCLSRY
SRDY Transition Hold Time(a)
3
3
ns
49
tARYCH
ARDY Resolution Transition Setup Time(b)
10
10
ns
50
tCLARX
ARDY Active Hold Time(a)
4
4
ns
51
tARYCHL
ARDY Inactive Holding Time
6
6
ns
52
tARYLCL
ARDY Setup Time(a)
15
15
ns
53
tINVCH
Peripheral Setup Time(b)
10
10
ns
54
tINVCL
DRQ Setup Time(b)
10
10
ns
Peripheral Timing Responses
55
tCLTMV
Timer Output Delay
T
F
25
20
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
This timing must be met to guarantee proper operation.
b
This timing must be met to guarantee recognition at the clock edge.
A
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Ready and Peripheral (33 MHz and 40 MHz)
Parameter
No.
Symbol
R
Description
Ready and Peripheral Timing Requirements
47
tSRYCL
SRDY Transition Setup Time(a)
48
tCLSRY
SRDY Transition Hold Time(a)
D
Preliminary
33 MHz
Min
Time(b)
40 MHz
Max
Min
Max
Unit
8
5
ns
3
2
ns
8
5
ns
4
3
ns
49
tARYCH
ARDY Resolution Transition Setup
50
tCLARX
ARDY Active Hold Time(a)
51
tARYCHL
ARDY Inactive Holding Time
6
5
ns
52
tARYLCL
ARDY Setup Time(a)
10
5
ns
53
tINVCH
Peripheral Setup Time(b)
8
5
ns
54
tINVCL
DRQ Setup Time(b)
8
5
ns
Peripheral Timing Responses
55
tCLTMV
Timer Output Delay
15
12
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
This timing must be met to guarantee proper operation.
b
This timing must be met to guarantee recognition at the clock edge.
82
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
SYNCHRONOUS, ASYNCHRONOUS, and PERIPHERAL WAVEFORMS
Synchronous Ready Waveforms
Case 1
tW
tW
tW
t4
Case 2
t3
tW
tW
t4
Case 3
t2
t3
tW
t4
Case 4
t1
t2
t3
t4
CLKOUTA
47
SRDY
48
Asynchronous Ready Waveforms
Case 1
tW
tW
Case 2
t3
tW
Case 3
t2
t3
Case 4
t1
t2
A
CLKOUTA
ARDY (Normally NotReady System)
ARDY (Normally
Ready System)
D
49
R
T
F
tW
t4
tW
t4
tW
t4
t3
t4
50
49
50
51
52
Peripheral Waveforms
CLKOUTA
53
INT4–INT0, NMI,
TMRIN1–TMRIN0
54
DRQ1–DRQ0
55
TMROUT1–
TMROUT0
Am186ED/EDLV Microcontrollers
83
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
Reset and Bus Hold (20 MHz and 25 MHz)
Preliminary
Parameter
No.
Symbol
20 MHz
Description
25 MHz
Min
Max
Min
Max
Unit
Reset and Bus Hold Timing Requirements
5
tCLAV
AD Address Valid Delay and BHE
0
25
0
20
ns
15
tCLAZ
AD Address Float Delay
0
25
0
20
ns
57
tRESIN
RES Setup Time
10
10
ns
58
tHVCL
HOLD Setup(a)
10
10
ns
Reset and Bus Hold Timing Responses
tCLHAV
HLDA Valid Delay
63
tCHCZ
Command Lines Float Delay
64
tCHCV
Command Lines Valid Delay (after Float)
62
0
25
0
20
ns
25
20
ns
25
20
ns
T
F
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Reset and Bus Hold (33 MHz and 40 MHz)
Preliminary
Parameter
No.
Symbol
33 MHz
Description
Min
Reset and Bus Hold Timing Requirements
5
tCLAV
AD Address Valid Delay and BHE
15
tCLAZ
AD Address Float Delay
57
tRESIN
RES Setup Time
58
tHVCL
HOLD Setup(a)
A
0
0
8
8
Reset and Bus Hold Timing Responses
R
62
tCLHAV
HLDA Valid Delay
63
tCHCZ
Command Lines Float Delay
64
tCHCV
Command Lines Valid Delay (after Float)
0
40 MHz
Max
Min
Max
Unit
15
0
12
ns
15
0
12
15
ns
5
ns
5
ns
12
ns
15
0
12
ns
15
12
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
84
D
This timing must be met to guarantee recognition at the next clock.
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
RESET and BUS HOLD WAVEFORMS
Reset Waveforms
X1
57
57
RES
CLKOUTA
Signals Related to Reset Waveforms
RES
S2/BTSEL,
CLKOUTA
BHE/ADEN,
S6/CLKDIV2, and
UZI
AD15–AD0
D
R
A
T
F
Three-State
Three-State
Am186ED/EDLV Microcontrollers
85
P R E L I M I N A R Y
Bus Hold Waveforms—Entering
Case 1
ti
ti
ti
Case 2
t4
ti
ti
CLKOUTA
58
HOLD
62
HLDA
15
AD15–AD0, DEN
63
A19–A0, S6, RD,
WR, BHE,
DT/R, S2–S0
WHB, WLB
Bus Hold Waveforms—Leaving
CLKOUTA
Case 1
ti
Case 2
ti
R
58
HOLD
HLDA
D
A
ti
ti
T
F
ti
t1
t4
t1
62
5
AD15–AD0, DEN
64
A19–A0, S6, RD,
WR, BHE,
DT/R, S2–S0
WHB, WLB
86
Am186ED/EDLV Microcontrollers
P R E L I M I N A R Y
TQFP PHYSICAL DIMENSIONS
PQL 100, Trimmed and Formed
Thin Quad Flat Pack
100
1
15.80
16.20
13.80
14.20
13.80
14.20
15.80
16.20
1.35
1.45
D
1.00 REF.
0.17
0.27
R
A
0.50 BSC
T
F
11° – 13°
1.60 MAX
11° – 13°
16-038-PQT-2_AI
PQL100
9.3.96 lv
Notes:
1. All measurements are in millimeters, unless otherwise noted.
2. Not to scale; for reference only.
Am186ED/EDLV Microcontrollers
87
P R E L I M I N A R Y
PQFP PHYSICAL DIMENSIONS
PQR 100, Trimmed and Formed
Plastic Quad Flat Pack
Pin 100
13.90
14.10
12.35
REF
17.00
17.40
Pin 80
Pin 1 I.D.
T
F
18.85
REF
19.90
20.10
23.00
23.40
Pin 30
2.70
2.90
D
0.25
MIN
R
A
Pin 50
0.65 BASIC
3.35
MAX
SEATING PLANE
16-038-PQR-1_AH
PQR100
DP92
6-20-96 lv
Notes:
1. All measurements are in millimeters, unless otherwise noted.
2. Not to scale; for reference only.
Trademarks
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Am386 and Am486 are registered trademarks of Advanced Micro Devices, Inc.
Am186, Am188, E86, K86, Élan, and AMD Facts-On-Demand are trademarks of Advanced Micro Devices, Inc.
FusionE86 is a service mark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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Am186ED/EDLV Microcontrollers