Cypress CY29949AXIT 2.5v or 3.3v 200 mhz 1:15 clock distribution buffer Datasheet

CY29949
2.5V or 3.3V 200 MHz 1:15
Clock Distribution Buffer
Features
Description
■
2.5V or 3.3V operation
The CY29949 is a low voltage 200 MHz clock distribution
buffer with the capability to select either a differential LVPECL
or LVCMOS/LVTTL compatible input clocks. These clock
sources are used to provide for test clocks and primary system
clocks. All other control inputs are LVCMOS/LVTTL
compatible. The 15 outputs are LVCMOS or LVTTL compatible
and can drive 50Ω series or parallel terminated transmission
lines. For series terminated transmission lines, each output
can drive one or two traces giving the device an effective
fanout of 1:30.
■
200-MHz clock support
■
LVPECL or LVCMOS/LVTTL clock input
■
LVCMOS/LVTTL compatible outputs
■
15 clock outputs: drive up to 30 clock lines
■
1X and 1/2X configurable outputs
■
Output three-state control
■
350 ps maximum output-to-output skew
■
Pin compatible with MPC949, MPC9449
■
Available in Commercial and Industrial temperature range
■
52-pin TQFP package
The CY29949 is capable of generating 1X and 1/2X signals
from a 1X source. These signals are generated and retimed
internally to ensure minimal skew between the 1X and 1/2X
signals. SEL(A:D) inputs allow flexibility in selecting the ratio
of 1X to1/2X outputs.
The CY29949 outputs can also be three-stated via the
MR/OE# input. When MR/OE# is set HIGH, it resets the
internal flip-flops and three-states the outputs.
Logic Block Diagram
TCLK_SEL
0
1
PECL_CLK
PECL_CLK#
PECL_SEL
0
1
1
R
2
0
2
QA(0:1)
3
QB(0:2)
4
QC(0:3)
6
QD(0:5)
1
DSELA
DSELB
R
1
0
2
1
1
0
2
1
1
0
R 2
1
R
DSELC
DSELD
MR/OE#
Cypress Semiconductor Corporation
Document #: 38-07289 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 22, 2008
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CY29949
Pin Configuration
Figure 1. Pin Diagram - CY29949
NC
VDDC
QB2
VSS
QB1
VDDC
QB0
VSS
VSS
QA1
VDDC
QA0
VSS
52 51 50 49 48 47 46 45 44 43 42 41 40
MR/OE#
TCLK_SEL
VDD
TCLK0
TCLK1
PECL_CLK
PECL_CLK#
PCLK_SEL
DSELA
DSELB
DSELC
DSELD
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
CY29949
39
38
37
36
35
34
33
32
31
30
29
28
27
NC
VSS
QC0
VDDC
QC1
VSS
QC2
VDDC
QC3
VSS
VSS
QD5
NC
14 15 16 17 18 19 20 21 22 23 24 25 26
NC
VDDC
QD4
VSS
QD3
VDDC
QD2
VSS
QD1
VDDC
QD0
VSS
NC
Pin Description
Pin
Name
PWR
I/O[1]
Description
6
PECL_CLK
I, PD PECL Input Clock
7
PECL_CLK#
I, PU PECL Input Clock
4, 5
TCLK(0,1)
49, 51
QA(1,0)
I, PU External Reference/Test Clock Input
VDDC
O
Clock Outputs
42, 44, 46
QB(2:0)
VDDC
O
Clock Outputs
31, 33, 35, 37
QC(3:0)
VDDC
O
Clock Outputs
16, 18, 20, 22, 24, 28 QD(5:0)
VDDC
O
Clock Outputs
9, 10, 11, 12
DSEL(A:D)
I, PD Divider Select Inputs. When HIGH, selects ÷2 input divider. When LOW,
selects ÷1 input divider.
2
TCLK_SEL
I, PD TCLK Select Input. When LOW, TCLK0 clock is selected and when
HIGH TCLK1 is selected.
8
PCLK_SEL
I, PD PECL Select Input. When HIGH, PECL clock is selected and when LOW
TCLK(0,1) is selected
1
MR/OE#
I, PD Output Enable Input. When asserted LOW, the outputs are enabled and
when asserted HIGH, internal flip-flops are reset and the outputs are
three-stated. If more than one bank is used in /2 mode, a reset must be
performed (MR/OE# asserted high) after power up to ensure that all
internal flip-flops are set to the same state.
17, 21, 25, 32, 36,
41, 45, 50
VDDC
2.5V or 3.3V Power Supply for Output Clock Buffers
3
VDD
2.5V or 3.3V Power Supply
13, 15, 19, 23, 29,
30, 34, 38, 43, 47,
48, 52
VSS
Common Ground
14, 26, 27, 39, 40,
NC
Not Connected
Note
1. PD = internal pull-down, PU = internal pull-up.
Document #: 38-07289 Rev. *E
Page 2 of 7
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CY29949
Maximum Ratings[2]
Maximum Input Voltage Relative to VSS:............. VSS – 0.3V
Maximum Input Voltage Relative to VDD:............. VDD + 0.3V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature:................................ –40°C to +85°C
Maximum ESD Protection .............................................. 2 kV
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions must be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, Vin and Vout should be constrained to the range:
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
Maximum Power Supply:................................................ 5.5V
Maximum Input Current: ............................................ ±20 mA
DC Parameters (VDD = VDDC = 3.3V ±10% or 2.5V ±5%, over the specified temperature range)
Parameter
VIL
VIH
Description
Input Low Voltage
Input High Voltage
Conditions
Min
Typ
Max
Unit
VDD = 3.3V, PECL_CLK single ended
1.49
–
1.825
V
VDD = 2.5V, PECL_CLK single ended
1.10
–
1.45
All other inputs
VSS
–
0.8
VDD = 3.3V, PECL_CLK single ended
2.135
–
2.42
VDD = 2.5V, PECL_CLK single ended
1.75
–
2.0
All other inputs
V
2.0
–
VDD
IIL
Input Low
Current[3]
–
–
–100
IIH
Input High Current[3]
–
–
100
VPP
Peak-to-Peak Input Voltage
PECL_CLK
300
–
1000
mV
VCMR
Common Mode Range[4]
PECL_CLK
VDD = 3.3V
VDD – 2.0
–
VDD – 0.6
V
VDD = 2.5V
VDD – 1.2
–
VDD – 0.6
IOL = 20 mA
–
–
0.4
V
IOH = –20 mA, VDD = 3.3V
2.5
–
–
V
IOH = –20 mA, VDD = 2.5V
1.8
VOL
VOH
Output Low
Voltage[5]
Output High
Voltage[5]
IDDQ
Quiescent Supply Current
IDD
Dynamic Supply Current
Zout
Output Impedance
Cin
Input Capacitance
µA
–
–
5
7
mA
VDD = 3.3V, Outputs at 100 MHz,
CL = 30 pF
–
200
–
mA
VDD = 3.3V, Outputs at 160 MHz,
CL = 30 pF
–
330
–
VDD = 2.5V, Outputs at 100 MHz,
CL = 30 pF
–
140
–
VDD = 2.5V, Outputs at 160 MHz,
CL = 30 pF
–
235
–
VDD = 3.3V
12
15
18
VDD = 2.5V
14
18
22
–
4
–
Ω
pF
Notes
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR
range and the input lies within the VPP specification.
5. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.
Document #: 38-07289 Rev. *E
Page 3 of 7
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CY29949
AC Parameters (VDD = VDDC = 3.3V ±10% or 2.5V ±5%, over the specified temperature range)[6]
Parameter
Description
Fmax
Input Frequency[7]
Tpd
PECL_CLK to Q Delay[7]
TCLK to Q
Conditions
Typ
Max
Unit
–
–
200
MHz
VDD = 2.5V
–
–
170
VDD = 3.3V
4.0
–
8.6
4.2
–
10.5
6.0
–
10.6
6.2
–
10.5
45
–
55
%
Delay[7]
PECL_CLK to Q Delay[7]
TCLK to Q
Min
VDD = 3.3V
VDD = 2.5V
Delay[7]
ns
FoutDC
Output Duty Cycle[7, 8]
tpZL, tpZH
Output Enable Time (all outputs)
2
–
10
ns
tpLZ, tpHZ
Output Disable Time (all outputs)
2
–
10
ns
–
250
350
ps
–
1.5
2.75
ns
Measured at VDD/2
Skew[7, 9]
Tskew
Output-to-Output
Tskew(pp)
Part-to-Part Skew[10]
Tr/Tf
Output Clocks Rise/Fall Time[9]
PECL_CLK to Q
TCLK to Q
–
2.0
4.0
0.8V to 2.0V,
VDD = 3.3V
0.10
–
1.0
0.6V to 1.8V,
VDD = 2.5V
0.10
–
1.3
ns
Figure 2. LVCMOS_CLK CY29949 Test Reference for VCC = 3.3V and VCC = 2.5V
CY29949 DUT
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
R T = 50 ohm
R T = 50 ohm
VTT
VTT
Figure 3. PECL_CLK CY29949 Test Reference for VCC = 3.3V and VCC = 2.5V
Zo = 50 ohm
Differential
Pulse
Generator
Z = 50 ohm
CY29949 DUT
Zo = 50 ohm
Zo = 50 ohm
R T = 50 ohm
R T = 50 ohm
VTT
VTT
Notes
6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
7. Outputs driving 50Ω transmission lines.
8. 50% input duty cycle.
9. See Figure 2 and Figure 3.
10. Part-to-part skew at a given temperature and voltage.
Document #: 38-07289 Rev. *E
Page 4 of 7
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CY29949
Figure 4. Propagation Delay (TPD) Test Reference
PECL_CLK
VCMR
VPP
PECL_CLK
VCC
Q
VCC /2
tPD
GND
Figure 5. LVCMOS Propagation Delay (TPD) Test Reference
VCC
LVCMOS_CLK
VCC /2
GND
VCC
Q
VCC /2
tPD
GND
Figure 6. Output Duty Cycle (FoutDC)
VCC
VCC /2
tP
GND
T0
DC = tP / T0 x 100%
Figure 7. Output-to-Output Skew tsk(0)
VCC
VCC /2
GND
VCC
VCC /2
tSK(0)
Document #: 38-07289 Rev. *E
GND
Page 5 of 7
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CY29949
Ordering Information
Part Number
Package Type
CY29949AXI
CY29949AXIT
CY29949AXC
CY29949AXCT
Production Flow
52-Pin TQFP
Industrial, –40°C to +85°C
52-Pin TQFP - Tape and Reel
Industrial, –40°C to +85°C
52-Pin TQFP
Commercial, 0°C to +70°C
52-Pin TQFP - Tape and Reel
Commercial, 0°C to +70°C
Package Drawing and Dimensions
Figure 8. 52-Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A52B
51-85158-**
Document #: 38-07289 Rev. *E
Page 6 of 7
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CY29949
Document History Page
Document Title: CY29949 2.5V or 3.3V 200 MHz 1:15 Clock Distribution Buffer
Document Number: 38-07289
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
111100
02/01/02
BRK
Description of Change
New data sheet
*A
116783
08/14/02
HWT
Added commercial temperature range to the Ordering Information table
*B
118463
09/09/02
HWT
Corrected the package diagram from 52 LQFP to 52 TQFP
*C
122881
12/22/02
RBI
Added power-up requirements to Maximum Ratings
*D
130132
11/07/03
RGL
Fixed block diagram and MR/OE# description in the Pin Description table
*E
2595534
10/23/08
CXQ/PYRS Changed to Pb-Free device code in Ordering Information
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Document #: 38-07289 Rev. *E
Revised October 22, 2008
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