ADS5240 ¨ SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 4-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface FEATURES • • • • • • • • • • • • • • • Maximum Sample Rate: 40MSPS 12-Bit Resolution No Missing Codes Power Dissipation: 607mW CMOS Technology Simultaneous Sample-and-Hold 70.5dBFS SNR at 10MHz IF Internal and External References 3.3V Digital/Analog Supply Serialized LVDS Outputs Integrated Frame and Bit Patterns MSB and LSB First Modes Option to Double LVDS Clock Output Currents Pin- and Format-Compatible Family HTQFP-64 PowerPAD™ Package APPLICATIONS • • • • Portable Ultrasound Systems Tape Drives Test Equipment Optical Networking An integrated phase lock loop multiplies the incoming ADC sampling clock by a factor of 12. This 12x clock is used in the process of serializing the data output from each channel. The 12x clock is also used to generate a 1x and a 6x clock, both of which are transmitted as LVDS clock outputs. The 6x clock is denoted by the differential pair LCLKP and LCLKN, while the 1x clock is denoted by ADCLKP and ADCLKN. The word output of each ADC channel can be transmitted either as MSB or LSB first. The bit coinciding with the rising edge of the 1x clock output is the first bit of the word. Data is to be latched by the receiver on both the rising and falling edges of the 6x clock. The ADS5240 provides internal references, or can optionally be driven with external references. Best performance can be achieved through the internal reference mode. The device is available in an HTQFP-64 PowerPAD package and is specified over a -40°C to +85°C operating range. LCLK P 6X ADCLK LCLK N PLL ADC LK P 1X ADCLK ADCLK DESCRIPTION ADC LK N IN1 P The ADS5240 is a high-performance, 4-channel, 40MSPS analog-to-digital converter (ADC). Internal references are provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS (low-voltage differential signaling) outputs reduce the number of interface lines and package size. RELATED PRODUCTS IN1 N S/H IN2 P IN2 N S/H IN3 P IN3 N S/H IN4 P IN4 N MODEL RESOLUTION (BITS) SAMPLE RATE (MSPS) CHANNELS ADS5242(1) 12 65 4 S/H 12− Bit ADC Serializer 12− Bit ADC Serializer 12− Bit ADC Serializer 12− Bit ADC Serializer OUT 1 N OUT 2 P OUT 2 N OUT 3 P OUT 3 N OUT 4 P OUT 4 N Registers Reference OUT 1 P Control PD RESET SCLK SDATA CS INT/EXT REF T VC M REF B (1) Available Q1 2005. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR ADS5240 HTQFP-64 (2) PAP (1) (2) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING -40°C to +85°C ADS5240I ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS5240IPAP Tray, 160 ADS5240IPAPT Tape and Reel, 1000 For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. Thermal pad size: 5.29mm × 5.29mm (min), 6.50mm × 6.50mm (max). ABSOLUTE MAXIMUM RATINGS (1) Supply Voltage Range, AVDD -0.3V to +3.8V Supply Voltage Range, LVDD -0.3V to +3.8V Voltage Between AVSS and LVSS -0.3V to +0.3V Voltage Between AVDD and LVDD -0.3V to +0.3V Voltage Applied to External REF Pins -0.3V to +2.4V All LVDS Data and Clock Outputs Analog Input Pins Peak Total Input Current (all inputs) Junction Temperature Operating Free-Air Temperature Range, TA Lead Temperature, 1.6mm (1/16" from case for 10s) (1) 2 -0.3V to +2.4V -0.15V to +3.0V 30mA +105°C -40°C to +85°C 220°C Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 RECOMMENDED OPERATING CONDITIONS ADS5240 MIN TYP MAX UNITS Analog Supply Voltage, AVDD 3.0 3.3 3.6 V Output Driver Supply Voltage, LVDD 3.0 3.3 3.6 V 40 MSPS 0.6 V SUPPLIES AND REFERENCES CLOCK INPUT AND OUTPUTS ADCLK Input Sample Rate (low-voltage TTL) 20 Low-Level Voltage Clock Input High-Level Voltage Clock Input 2.2 ADCLKP and ADCLKN Outputs (LVDS) 20 40 MHz V LCLKP and LCLKN Outputs (LVDS) (1) 120 240 MHz Operating Free-Air Temperature, TA -40 +85 °C Thermal Characteristics: (1) θJA 24 °C/W θJC 15 °C/W 6 × ADCLK. REFERENCE SELECTION MODE Internal Reference External Reference INT/EXT DESCRIPTION 1 Full-scale range = 2.0VPP. Default with internal pull-up. 0 Internal reference is powered down. Common mode of external reference should be within 50mV of VCM. VCM is derived from the internal bandgap voltage. 3 ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 ELECTRICAL CHARACTERISTICS TMIN = -40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V differential, transformer coupled inputs, -1dBFS, ISET = 56.2kΩ, internal voltage reference, and LDVS buffer current at 3.5mA per channel, unless otherwise noted. ADS5240 PARAMETER TEST CONDITIONS MIN TYP MAX UNITS LSB DC ACCURACY No Missing Codes Assured DNL Differential Nonlinearity INL Integral Nonlinearity fIN = 5MHz -0.9 ±0.4 +0.9 fIN = 5MHz -2.0 ±0.75 +2.0 LSB -0.75 ±0.2 +0.75 %FS Offset Error (1) Offset Temperature Coefficient Fixed Attenuation in Channel (2) ppm/°C 1 %FS ±0.2 Variable Attenuation in Channel (3) Gain Error (4) 14 REFT - REFB -5 Attenuation Temperature Coefficient (5) ±1.0 %FS +5 %FS 44 ppm/°C VIN = FS, FIN = 5MHz 184 mA I(AVDD) Analog Supply Current VIN = FS, FIN = 5MHz 142 mA I(LVDD) Digital Output Driver Supply Current VIN = FS, FIN = 5MHz, LVDS into 100Ω Load 42 mA POWER SUPPLY ICC Total Supply Current Power Dissipation Power-Down 607 Clock Running 650 95 mW mW REFERENCE VOLTAGES VREFT Reference Top (internal) 1.95 2.0 2.05 V VREFB Reference Bottom (internal) 0.95 1.0 1.05 V VCM Common-Mode Voltage 1.45 1.5 1.55 VCM Output Current (6) ±50mV Change in Voltage VREFT Reference Top (external) ±2 1.875 V VREFB Reference Bottom (external) 1.125 External Reference Input Current (7) V mA V 1.0 mA 4.0 pF VCM ± 0.05 V ANALOG INPUT Differential Input Capacitance Analog Input Common-Mode Range Differential Input Voltage Range Voltage Overhead Recovery Time Input Bandwidth 1.5 2.02 VPP Differential Input Signal at 4VPP Recovery to Within 1% of Code 4.0 CLK Cycles -3dBFS 300 MHz DIGITAL DATA OUTPUTS Data Bit Rate (1) (2) (3) (4) (5) (6) (7) 4 240 480 MBPS Offset error is the deviation of the average code from mid-code for a zero input. Offset error is expressed in terms of % of full-scale. Fixed attenuation in the channel arises due to a fixed attenuation of about 1% in the sample-and-hold amplifier. When the differential voltage at the analog input pins are changed from -VREF to +VREF, the swing of the output code is expected to deviate from the full-scale code (4096LSB) by the extent of this fixed attenuation. NOTE: VREF is defined as (REFT - REFB). Variable attenuation in the channel refers to the attenuation of the signal in the channel over and above the fixed attenuation. The reference voltages are trimmed at production so that (VREFT - VREFB) is within ± 50mV of the ideal value of 1V. It does not include fixed attenuation. The attenuation temperature coefficient refers to the temperature coefficient of the attenuation in the channel. It does not account for the variation of the reference voltages with temperature. VCM provides the common-mode current for the inputs of all four channels when the inputs are AC-coupled. The VCM output current specified is the additional drive of the VCM buffer if loaded externally. Average current drawn from the reference pins in the external reference mode. ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 AC CHARACTERISTICS TMIN = -40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V differential, transformer coupled inputs, -1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. ADS5240 PARAMETER CONDITIONS MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS fIN = 1MHz SFDR Spurious-Free Dynamic Range HD2 2nd-Order Harmonic Distortion HD3 3rd-Order Harmonic Distortion SNR Signal-to-Noise Ratio SINAD Signal-to-Noise and Distortion fIN = 5MHz 85 dBc 85 dBc fIN = 1MHz 95 dBc 95 dBc fIN = 10MHz 90 dBc fIN = 1MHz 87 dBc 85 dBc fIN = 5MHz ENOB Effective Number of Bits Crosstalk 85 78 fIN = 10MHz 85 dBc fIN = 1MHz 70.5 dBFS 70.5 dBFS fIN = 10MHz 70 dBFS fIN = 1MHz 70 dBFS 70 dBFS 69.5 dBFS fIN = 5MHz fIN = 5MHz fIN = 10MHz IMD Two-Tone Intermodulation Distortion dBc fIN = 10MHz fIN = 5MHz 78 87 f1 = 9.5MHz at -7dBFS f2 = 10.2MHz at -7dBFS 68 67 -88 dBc fIN = 5MHz 11.3 Bits Signal Applied to 3 Channels; Measurement Taken on the Channel with No Input Signal -90 dBc 5 ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 LVDS DIGITAL DATA AND CLOCK OUTPUTS Test conditions at IO = 3.5mA, RLOAD = 100Ω, and CLOAD = 6pF. IO refers to the current setting for the LVDS buffer. RLOAD is the differential load resistance between the LVDS pair. CLOAD is the effective single-ended load capacitance between each of the LVDS pins and ground. CLOAD includes the receiver input parasitics as well as the routing parasitics. Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load. All LVDS specifications are characterized, but not tested at production. PARAMETER DC SPECIFICATIONS VOH CONDITIONS MIN TYP MAX UNITS (1) Output Voltage High, OUTP or OUTN VOL Output Voltage Low, OUTP or OUTN |VOD| Output Differential Voltage, |OUTP - OUTN| VOS Output Offset Voltage (2) CO Output Capacitance (3) |∆VOD| Change in |VOD| Between 0 and 1 RLOAD = 100Ω± 1% See LVDS Timing Diagram, Page 7 1375 1500 mV mV RLOAD = 100Ω± 1% 900 1025 RLOAD = 100Ω± 1% 300 350 400 mV RLOAD = 100Ω± 1% See LVDS Timing Diagram, Page 7 1100 1200 1300 mV VCM = 1.5V 4 pF RLOAD = 100Ω± 1% 25 mV ∆VOS Change Between 0 and 1 RLOAD = 100Ω± 1% 25 mV ISOUT Output Short-Circuit Current Drivers Shorted to Ground 40 mA Drivers Shorted Together 12 mA ISOUTNP Output Current DRIVER AC SPECIFICATIONS Clock LVDS Clock Duty Cycle 6 × ADCLK (LCLKP, LCLKN) 45 Minimum Data Setup Time (4) (5) Minimum Data Hold Time (4) (5) tRISE/tFALL VOD Rise Time or VOD Fall Time (1) (2) (3) (4) (5) 50 55 % 650 ps 650 ps IO = 2.5mA 400 ps IO = 3.5mA 250 ps IO = 4.5mA 200 ps IO = 6mA 150 ps The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1. VOS refers to the common-mode of OUTP and OUTN. Output capacitance inside the device, from either OUTP or OUTN to ground. Refer to the LVDS application note (SBAA118) for a description of data setup and hold times. Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as reduced timing margins. SWITCHING CHARACTERISTICS TMIN = -40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, -1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. ADS5240 PARAMETER CONDITIONS MIN TYP MAX UNITS 50 ns SWITCHING SPECIFICATIONS tSAMPLE tD(A) Aperture Delay Aperture Jitter (uncertainty) tD(pipeline) Latency tPROP Propagation Delay 6 25 3.1 ns 1 ps rms 6.5 Cycles 5 ns ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 LVDS TIMING DIAGRAM (PER ADC CHANNEL) Sample n Sample n+6 Input tSAMPLE ADCLK tS 2 ; tS = tSAMPLE 12 LCLKP 6X ADCLK LCLKN OUTP SERIAL DATA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 OUTN Sample n data ADCLKP 1X ADCLK ADCLKN tD(A) tPROP 6.5 Clock Cycles RESET TIMING t1 +AVDD Power Supply t 1 > 10ms t 2 > 100ns t 3 > 100ns 0V +AVDD RESET 0V t2 t3 Register Write Enable POWER-DOWN TIMING 1µs 10µs PD Device Fully Powers Down Device Fully Powers Up 7 ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 SERIAL INTERFACE TMIN = -40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, -1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. ADS5240 PARAMETER TEST CONDITIONS MIN TYP SCLK Serial Clock Input Frequency VIN LOW Input Low Voltage 0 VIN HIGH Input High Voltage 2.2 MAX UNITS 20 MHz 0.6 V AVDD V Input Current ±10 µA Input Pin Capacitance 5.0 pF SERIAL INTERFACE TIMING Data is shifted in MSB first. Outputs change on next rising clock edge after CS goes high. ADCLK Start Sequence CS t1 Data latched on each rising edge of SCLK. t2 SCLK t3 SDATA MSB D6 D5 D4 D3 D2 D1 D0 t4 t5 8 PARAMETER DESCRIPTION MIN t1 Serial CLK Period 50 TYP MAX UNIT t2 Serial CLK High Time 25 ns t3 Serial CLK Low Time 25 ns t4 Minimum Data Setup Time 5 ns t5 Minimum Data Hold Time 5 ns ns ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 SERIAL INTERFACE REGISTERS ADDRESS DATA D7 D6 D5 D4 0 0 0 0 0 0 0 0 0 0 0 DESCRIPTION D3 D2 D1 0 0 Normal ADC Output 0 1 Deskew Pattern 1 0 Sync Pattern 1 1 D0 LVDS BUFFERS (register 0) 0 Output Current in LVDS = 3.5mA 0 1 Output Current in LVDS = 2.5mA 1 0 Output Current in LVDS = 4.5mA 1 1 Output Current in LVDS = 6.0mA Patterns Get Reversed in MSB First Mode of LVDS (default after reset) LSB/MSB MODE (register 1) 0 X X 0 Default LVDS Clock Output Current 0 X X 1 2X LVDS Clock Output Current IOUT = 7.0mA 0 0 X X LSB First Mode (default after reset) 0 1 X X 0 1 (default after reset) Custom Pattern 0 1 1 REMARKS IOUT = 3.5mA MSB First Mode POWER-DOWN ADC CHANNELS (register 2) 0 1 0 X D2: Power-Down for Channel 2 0 X 0 1 D0: Power-Down for Channel 1 1 Logic 1 = Channel Powered Down POWER-DOWN ADC CHANNELS (register 3) 1 0 X 0 D3: Power-Down for Channel 4 X 0 1 0 D1: Power-Down for Channel 3 Logic 1 = Channel Powered Down CUSTOM PATTERN (registers 4-6) D3 D2 D1 D0 0 1 0 0 X X X X 0 1 0 1 X X X X 0 1 1 0 X X X X Bits for Custom Pattern See Test Patterns TEST PATTERNS (1) Deskew 101010101010 Sync 000000111111 Custom (1) Any 12-bit pattern that is defined in the custom pattern registers 4 to 6. The output comes out in the following order: D0(4) D1(4) D2(4) D3(4) D0(5) D1(5) D2(5) D3(5) D0(6) D1(6) D2(6) D3(6) where, for example, D0(4) refers to the D0 bit of register 4, etc. Default is LSB first. If MSB first is selected, the above patterns will be reversed. 9 ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 PIN CONFIGURATION SCLK SDATA CS AVDD AVSS AVSS AVSS ADCLK AVDD INT/EXT REFT REFB VCM ISET AVSS HTQFP AVSS Top View 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD 1 48 AVDD IN1P 2 47 IN4N IN1N 3 46 IN4P AVSS 4 45 AVSS AVDD 5 44 AVDD AVSS 6 43 AVSS IN2P 7 42 IN3N IN2N 8 AVSS 41 IN3P ADS5240 9 40 AVSS AVDD 10 39 AVDD LVSS 11 38 LVSS 37 RESET PD 12 10 LVSS 13 36 LVSS LVSS 14 35 LVSS 24 25 26 27 28 29 30 31 32 LVDD LVSS OUT4P OUT4N NC NC 23 OUT3N 22 OUT3P 21 OUT2N 20 OUT2P 19 LVSS 18 LVDD 17 OUT1N 33 ADCLKP OUT1P LCLKN 16 NC 34 ADCLKN NC LCLKP 15 ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 PIN DESCRIPTIONS NAME PIN # I/O DESCRIPTION AVDD 1, 5, 10, 39, 44, 48, 55, 60 I Analog Power Supply IN1P 2 I Channel 1 Differential Analog Input High IN1N 3 I Channel 1 Differential Analog Input Low AVSS 4, 6, 9, 40, 43, 45, 49, 57-59, 64 I Analog Ground IN2P 7 I Channel 2 Differential Analog Input High IN2N 8 I Channel 2 Differential Analog Input Low LVSS 11, 13, 14, 22, 28, 35, 36, 38 I LVDS Ground PD 12 I Power-Down; 0 = Normal, 1 = Power-Down LCLKP 15 O Positive LVDS Clock LCLKN 16 O Negative LVDS Clock NC 17, 18, 31, 32 — No Connection OUT1P 19 O Channel 1 Positive LVDS Data Output OUT1N 20 O Channel 1 Negative LVDS Data Output LVDD 21, 27 I LVDS Power Supply OUT2P 23 O Channel 2 Positive LVDS Data Output OUT2N 24 O Channel 2 Negative LVDS Data Output OUT3P 25 O Channel 3 Positive LVDS Data Output OUT3N 26 O Channel 3 Negative LVDS Data Output OUT4P 29 O Channel 4 Positive LVDS Data Output OUT4N 30 O Channel 4 Negative LVDS Data Output ADCLKP 33 O Positive LVDS ADC Clock Output ADCLKN 34 O Negative LVDS ADC Clock Output RESET 37 I Reset Registers to Default; 0 = Reset, 1 = Normal IN3P 41 I Channel 3 Differential Analog Input High IN3N 42 I Channel 3 Differential Analog Input Low IN4P 46 I Channel 4 Differential Analog Input High IN4N 47 I Channel 4 Differential Analog Input Low ISET 50 I/O Bias Current Setting Resistor of 56.2kΩ to Ground VCM 51 O Common-Mode Output Voltage REFB 52 I/O Reference Bottom Voltage (2Ω resistor in series with 0.1µF capacitor to ground) Reference Top Voltage (2Ω resistor in series with 0.1µF capacitor to ground) REFT 53 I/O INT/EXT 54 I Internal/External Reference Select; 0 = External, 1 = Internal ADCLK 56 I Data Converter Clock Input CS 61 I Chip-Select; 0 = Select, 1 = No Select SDATA 62 I Serial Data Input SCLK 63 I Serial Data Clock 11 ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3dB. Aperture Delay The delay in time between one of the edges of the input sampling clock and the actual time at which the sampling occurs. Integral Nonlinearity (INL) INL is the deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line or best fit determined by a least square curve fit. INL is independent from effects of offset, gain or quantization errors. Maximum Conversion Rate Aperture Uncertainty (Jitter) The encode rate at which parametric testing is performed. This is the maximum sampling rate where certified operation is given. The sample-to-sample variation in aperture delay. Minimum Conversion Rate Clock Pulse Width/Duty Cycle This is the minimum sampling rate where the ADC still works. Pulse width high is the minimum amount of time that the ENCODE pulse should be left in logic '1' state to achieve rated performance. Pulse width low is the minimum time that the ENCODE pulse should be left in a low state (logic '0'). At a given clock rate, these specifications define an acceptable clock duty cycle. Nyquist Sampling When the sampled frequencies of the analog input signal are below fCLOCK/2, it is called Nyquist sampling. The Nyquist frequency is fCLOCK/2, which can vary depending on the sample rate (fCLOCK). Differential Nonlinearity (DNL) Offset Error An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation of any single LSB transition at the digital output from an ideal 1 LSB step at the analog input. If a device claims to have no missing codes, it means that all possible codes (for a 12-bit converter, 4096 codes) are present over the full operating range. Offset error is the deviation of output code from mid-code when both inputs are tied to common-mode. Effective Number of Bits (ENOB) The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula: ENOB SINAD 1.76 6.02 If SINAD is not known, SNR can be used exceptionally to calculate ENOB (ENOBSNR). 12 Propagation Delay This is the delay between the input clock of one of the edges and the time when all data bits are within valid logic levels. Signal-to-Noise and Distortion (SINAD) The RMS value of the sine wave fIN (input sine wave for an ADC) to the RMS value of the noise of the converter from DC to the Nyquist frequency, including harmonic content. It is typically expressed in decibels (dB). SINAD includes harmonics, but excludes DC. Input(VS ) SINAD 20Log (10) Noise Harmonics ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 Signal-to-Noise Ratio (without harmonics) Temperature Drift SNR is a measure of signal strength relative to background noise. The ratio is usually measured in dB. If the incoming signal strength in µV is VS and the noise level (also in µV) is VN, then the SNR in dB is given by the formula: V SNR 20Log (10) S VN Temperature drift (for offset error and gain error) specifies the maximum change from the initial temperature value to the value at TMIN or TMAX. This is the ratio of the RMS signal amplitude, VS (set 1dB below full-scale), to the RMS value of the sum of all other spectral components, VN, excluding harmonics and DC. Spurious-Free Dynamic Range (SFDR) The ratio of the RMS value of the analog input sine wave to the RMS value of the peak spur observed in the frequency domain. It may be reported in dBc (that is, it degrades as signal levels are lowered), or in dBFS (always related back to converter full-scale). The peak spurious component may or may not be a harmonic. Total Harmonic Distortion (THD) THD is the ratio of the RMS signal amplitude of the input sine wave to the RMS value of distortion appearing at multiples (harmonics) of the input, typically given in dBc. Two-Tone Intermodulation Distortion Rejection The ratio of the RMS value of either input tone (f1, f2) to the RMS value of the worst third-order intermodulation product (2f1 - f2; 2f2 - f1). It is reported in dBc. 13 ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS TMIN = -40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, -1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE 0 0 f IN = 1MHz (−1dBFS) SNR = 70.9dBFS SINAD = 70.8dBFS SFDR = 87.1dBFS −40 Amplitude (dB) Amplitude (dB) −20 −60 −80 fIN = 5MHz (−1dBFS) SNR = 70.5dBFS SINAD = 70.3dBFS SFDR = 84.9dBFS −20 −40 −60 −80 −100 −100 −120 −120 0 4 8 12 16 0 20 4 Figure 1. SPECTRAL PERFORMANCE 20 TWO-TONE INTERMODULATION fIN = 10MHz (−1dBFS) SNR = 70.3dBFS SINAD = 70.2dBFS SFDR = 85.4dBFS −40 −60 −80 f 1 = 9.5MHz (−7dBFS) f1 = 10.2MHz (−7dBFS) IMD = −88.2dBc −20 Amplitude (dB) Amplitude (dB) 16 0 −20 −40 −60 −80 −100 −100 −120 −120 0 4 8 12 16 0 20 4 Figure 3. 16 20 INTEGRAL NONLINEARITY ERROR 2.0 fIN = 5MHz 0.8 12 Figure 4. DIFFERENTIAL NONLINEARITY ERROR 1.0 8 Input Frequency (MHz) Input Frequency (MHz) fIN = 5MHz 1.5 0.6 1.0 0.4 INL Error (LSBs) DNL Error (LSB) 12 Figure 2. 0 0.2 0 −0.2 −0.4 −0.6 0.5 0 −0.5 −1.0 −1.5 −0.8 −2.0 −1.0 0 14 8 Input Frequency (MHz) Input Frequency (MHz) 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 Code Code Figure 5. Figure 6. 3072 3584 4096 ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) TMIN = -40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, -1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. SWEPT INPUT POWER SWEPT INPUT POWER 100 100 fIN = 5MHz 90 80 80 SNR (dBFS) 70 60 SNR (dBc, dBFS) SNR (dBc, dBFS) f IN = 10MHz 90 SFDR (dBc) 50 40 SNR (dBc) 30 60 50 SFDR (dBc) 40 SNR (dBc) 30 20 20 10 10 0 SNR (dBFS) 70 0 −70 −60 −50 −40 −30 −20 −10 −70 0 −40 −30 −20 Figure 7. Figure 8. IAVDD, IDVDD vs SAMPLE RATE −10 0 DYNAMIC PERFORMANCE vs SAMPLE RATE 90 fIN = 5MHz fIN = 5MHz SFDR, SNR, SINAD (dBFS) 0.25 IAVDD, IDVDD (A) −50 Input Amplitude (A) 0.30 0.20 0.15 IAVDD 0.10 0.05 IDVDD 0 SFDR 85 80 SNR 75 70 65 SINAD 60 55 20 25 30 35 40 45 20 25 30 35 40 Sample Rate (MSPS) Sample Rate (MSPS) Figure 9. Figure 10. DYNAMIC PERFORMANCE vs SAMPLE RATE 45 POWER DISSIPATION vs TEMPERATURE 620 90 f IN = 10MHz 618 85 616 SFDR 80 614 Power (mW) SFDR, SNR, SINAD (dBFS) −60 Input Amplitude (A) 75 SNR 70 SINAD 612 610 608 606 65 604 60 602 55 600 20 25 30 35 Sample Rate (MSPS) Figure 11. 40 45 −40 −20 0 20 40 60 80 Temperature ( C) Figure 12. 15 ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) TMIN = -40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, -1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. OUTPUT NOISE HISTOGRAM 120k 100k Counts 80k 60k 40k 20k 0k N−2 N− 1 N Code Figure 13. 16 N+1 N+2 ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 THEORY OF OPERATION OVERVIEW DRIVING THE ANALOG INPUTS The ADS5240 is a 4-channel, high-speed, CMOS ADC. It consists of a high-performance sample-and-hold circuit at the input, followed by a 12-bit ADC. The 12 bits given out by each channel are serialized and sent out on a single pair of pins in LVDS format. All four channels of the ADS5240 operate from a single clock referred to as ADCLK. The sampling clocks for each of the four channels are generated from the input clock using a carefully matched clock buffer tree. The 12x clock required for the serializer is generated internally from ADCLK using a phase lock loop (PLL). A 6x and a 1x clock are also output in LVDS format along with the data to enable easy data capture. The ADS5240 operates from internally-generated reference voltages that are trimmed to improve matching across multiple devices on a board. This feature eliminates the need for external routing of reference lines and also improves matching of the gain across devices. The nominal values of REFT and REFB are 2V and 1V, respectively. These values imply that a differential input of -1V corresponds to the zero code of the ADC, and a differential input of +1V corresponds to the full-scale code (4095 LSB). VCM (common-mode voltage of REFT and REFB) is also made available externally through a pin, and is nominally 1.5V. The analog input biasing is shown in Figure 14. The recommended method to drive the inputs is through AC coupling. AC coupling removes the worry of setting the common-mode of the driving circuit, since the inputs are biased internally using two 600Ω resistors. The ADC employs a pipelined converter architecture consisting of a combination of multi-bit and single-bit internal stages. Each stage feeds its data into the digital error correction logic, ensuring excellent differential linearity and no missing codes at the 12-bit level. The pipeline architecture results in a data latency of 6.5 clock cycles. The output of the ADC goes to a serializer that operates from a 12x clock generated by the PLL. The 12 data bits from each channel are serialized and sent LSB first. In addition to serializing the data, the serializer also generates a 1x clock and a 6x clock. These clocks are generated in the same way the serialized data is generated, so these clocks maintain perfect synchronization with the data. The data and clock outputs of the serializer are buffered externally using LVDS buffers. Using LVDS buffers to transmit data externally has multiple advantages, such as reduced number of output pins (saving routing space on the board), reduced power consumption, and reduced effects of digital noise coupling to the analog circuit inside the ADS5240. The ADS5240 operates from two sets of supplies and grounds. The analog supply/ground set is denoted as AVDD/AVSS, while the digital set is denoted by LVDD/LVSS. ADS5240 IN+ 600Ω Input Circuitry 600Ω IN− VCM CM Buffer Internal Voltage Reference Figure 14. Analog Input Bias Circuitry The sampling capacitor used to sample the inputs is 4pF. The choice of the external AC coupling capacitor is dictated by the attenuation at the lowest desired input frequency of operation. The attenuation resulting from using a 10nF AC coupling capacitor is 0.04%. If the input is DC-coupled, then the output common-mode voltage of the circuit driving the ADS5240 should match the VCM (which is provided as an output pin) to within ±50mV. It is recommended that the output common-mode of the driving circuit be derived from VCM provided by the device. The sampling circuit consists of a low-pass RC filter at the input to filter out noise components that might be differentially coupled on the input pins. The inputs are sampled on two 4pF capacitors, see Figure 15. The sampling on the capacitors is done with respect to an internally-generated common-mode voltage (INCM). The switches connecting the sampling capacitors to the INCM are opened out first (before the switches connecting them to the analog inputs). This ensures that the charge injection arising out of the switches opening is independent of the input signal amplitude to a first-order of approximation. SP refers to a sampling clock whose falling edge comes an instant before the SAMPLE clock. The falling edge of SP determines the sampling instant. 17 ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 INCM (internally−generated voltage) 15Ω IN+ 1.5pF Sample 4pF SP (defines sampling instant) 1.7pF SP 4pF 15Ω IN− 1.5pF Sample SP thereby scales down the device operating power. However, it is recommended that the external resistor be within 10% of the specified value of 56.2kΩ so that the internal bias margins for the various blocks are proper. Buffering the internal bandgap voltage also generates a voltage called VCM, which is set to the midlevel of REFT and REFB, and is accessible on a pin. The internal buffer driving VCM has a drive of ±2mA. It is meant as a reference voltage to derive the input common-mode in case the input is directly coupled. When using the internal reference mode, a resistor of 2Ω should be added between the reference pins (REFT and REFB) and the decoupling capacitor, as shown in Figure 16. INCM ADS5240 ISET Figure 15. Input Circuitry REFT INPUT OVER-VOLTAGE RECOVERY The differential full-scale input peak-to-peak supported by the ADS5240 is 2V. For a nominal value of VCM (1.5V), INP and INN can swing from 1V to 2V. The ADS5240 is specially designed to handle an over-voltage differential peak-to-peak voltage of 4V (2.5V and 0.5V swings on INP and INN). If the input common-mode is not considerably off from VCM during overload (less than 300mV), recovery from an over-voltage input condition is expected to be within 4 clock cycles. All of the amplifiers in the SHA and ADC are specially designed for excellent recovery from an overload signal. REFERENCE CIRCUIT DESIGN The digital beam-forming algorithm relies on gain matching across all receiver channels. (A typical system would have about 128 ADCs on the board.) In such a case, it is critical to ensure that the gain is matched, essentially requiring the reference voltages seen by all the ADCs to be the same. Matching references within the four channels of a chip is done by using a single internal reference voltage buffer. Trimming the reference voltages on each chip during production ensures the reference voltages are well-matched across different chips. All bias currents required for the internal operation of the device are set using an external resistor to ground at pin ISET. Using a 56.2kΩ resistor on ISET generates an internal reference current of 20µA. This current is mirrored internally to generate the bias current for the internal blocks. Using a larger external resistor at ISET reduces the reference bias current and 18 VCM REFB 2Ω 0.1µF + 2.2µF 56.2kΩ 2Ω + 2.2µF 0.1µF Figure 16. Internal Reference Mode The device also supports the use of external reference voltages. This mode involves forcing REFT and REFB externally. In this mode, the internal reference buffer is tri-stated. Since the switching current for the four ADCs come from the externally-forced references, it is possible for the performance to be slightly less than when the internal references are used. It should be noted that in this mode, VCM and ISET continue to be generated from the internal bandgap voltage, as in the internal reference mode. It is therefore important to ensure that the common-mode voltage of the externally-forced reference voltages matches to within 50mV of VCM. CLOCKING The four channels on the chip run off a single ADCLK input. To ensure that the aperture delay and jitter are same for all the channels, a clock tree network is used to generate individual sampling clocks to each channel. The clock paths for all the channels are matched from the source point all the way to the sample-and-hold. This ensures that the performance and timing for all the channels are identical. The use ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 of the clock tree for matching introduces an aperture delay, which is defined as the delay between the rising edge of ADCLK and the actual instant of sampling. The aperture delays for all the channels are matched. The aperture delays for all channels are matched. However, across conditions of temperature, supply voltage, and devices, the aperture delay averages 3.1ns. The input ADCLK should ideally have a 50% duty cycle. However, while routing ADCLK to different components on board, the duty cycle of the ADCLK reaching the ADS5240 could deviate from 50%. A smaller (or larger) duty cycle eats into the time available for sample or hold phases of each circuit, and is therefore not optimal. For this reason, the internal PLL is used to generate an internal clock that has 50% duty cycle. The use of the PLL automatically dictates the minimum sampling rate to be about 20MSPS. LVDS BUFFERS The LVDS buffer has two current sources, as shown in Figure 17. OUTP and OUTN are loaded externally by a resistive load that is ideally about 100Ω. Depending on the data being 0 or 1, the currents are directed in one or the other direction through the resistor. While the lower side current source is a constant current source, the higher side current source is controlled through a feedback loop to maintain the output common mode constant. The LVDS buffer has four current settings. The default current setting is 3.5mA, and gives a differential drop of about ±350mV across the 100Ω resistor. High External Termination Resistor Low OUTP OUTN Low High Figure 17. LVDS Buffer The LVDS buffer gets data from a serializer that takes the output data from each channel and serializes it into a single data stream. For a clock frequency of 40MHz, the data rate output by the serializer is 480MBPS. The data comes out LSB first, with a register programmability to revert to MSB first. The serializer also gives out a 1x clock and a 6x clock. The 6x clock (denoted as LCLKP/LCLKN) is meant to synchronize the capture of the LVDS data. The deskew mode can be enabled as well, using a register setting. This mode gives out a data stream of alternate 0s and 1s and can be used determine the relative delay between the 6x clock and the output data for optimum capture. A 1x clock is also generated by the serializer and transmitted by the LVDS buffer. The 1x clock (referred to as ADCLKP/ADCLKN) is used to determine the start of the 12-bit data frame. The sync mode (enabled through a register setting) gives out a data of six 0s followed by six 1s. Using this mode, the 1x clock can be used to determine the start of the data frame. In addition to the deskew mode pattern and the sync pattern, a custom pattern can be defined by the user and output from the LVDS buffer. NOISE COUPLING ISSUES High-speed mixed signals are sensitive to various types of noise coupling. One of the main sources of noise is the switching noise from the serializer and the output buffers. Maximum care is taken to isolate these noise sources from the sensitive analog blocks. As a starting point, the analog and digital domains of the chip are clearly demarcated. AVDD and AVSS are used to denote the supplies for the analog sections, while LVDD and LVSS are used to denote the digital supplies. Care is taken to ensure that there is minimal interaction between the supply sets within the device. The extent of noise coupled and transmitted from the digital to the analog sections depends on the following: 1. The effective inductances of each of the supply/ground sets. 2. The isolation between the digital and analog supply/ground sets. Smaller effective inductance of the supply/ground pins leads to better suppression of the noise. For this reason, multiple pins are used to drive each supply/ground. It is also critical to ensure that the impedances of the supply and ground lines on board are kept to the minimum possible values. Use of ground planes in the board as well as large decoupling capacitors between the supply and ground lines are necessary to get the best possible SNR from the device. 19 ADS5240 SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 It is recommended that the isolation be maintained onboard by using separate supplies to drive AVDD and LVDD, as well as separate ground planes for AVSS and LVSS. The use of LVDS buffers reduces the injected noise considerably, compared to CMOS buffers. The current in the LVDS buffer is independent of the direction of switching. Also, the low output swing as well as the differential nature of the LVDS buffer results in low-noise coupling. POWER-DOWN MODE The ADS5240 has a power-down pin, PD. Pulling PD high causes the device to enter the power-down mode. In this mode, the reference and clock circuitry as well as all the channels are powered down. Device power consumption drops to less than 100mW in this mode. Individual channels can also be selectively powered down by programming registers. The ADS5240 also has an internal circuit that monitors the state of stopped clocks. If ADCLK is stopped (or if it runs at a speed < 3MHz), this monitoring circuit generates a logic signal that puts the device in a power-down state. As a result, the power consumption of the device is reduced when ADCLK is stopped. This circuit can also be disabled using register options. SUPPLY SEQUENCE The following supply sequence is recommended for powering up the device: 1. AVDD is powered up. 2. LVDD is powered up. During the power-up ramp, the AVDD and LVDD supplies should track each other to within 0.6V. 20 www.ti.com If this sequencing is not possible, then it is recommended that AVDD and LVDD be powered up simultaneously. After the supplies have stabilized, it is required to give the device an active RESET pulse. This results in all internal registers getting reset to their default value of 0 (inactive). Without RESET, it is possible that some registers might be in their non-default state on power-up. This could cause the device to malfunction. LAYOUT OF PCB WITH PowerPAD THERMALLY-ENHANCED PACKAGES The ADS5240 is housed in an 64-lead PowerPAD thermally-enhanced package. To make optimum use of the thermal efficiencies designed into the PowerPAD package, the printed circuit board (PCB) must be designed with this technology in mind. Please refer to PowerPAD brief SLMA004 PowerPAD Made Easy (refer to our web site at www.ti.com), which addresses the specific considerations required when integrating a PowerPAD package into a PCB design. For more detailed information, including thermal modeling and repair procedures, please see technical brief SLMA002, PowerPAD Thermally-Enhanced Package (available for download at www.ti.com). CONNECTING HIGH-SPEED, MULTI-CHANNEL ADCs TO XILINX FPGAs A separate application note (XAPP774) describing how to connect TI's high-speed, multi-channel ADCs with serial LVDS outputs to XILINX FPGAs can be downloaded directly from the XILINX website (http://www.xilinx.com). THERMAL PAD MECHANICAL DATA www.ti.com PAP (S-PQFP-G64) THERMAL INFORMATION This PowerPAD™ package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. When the thermal pad is soldered directly to the printed circuit board (PCB), the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to a ground plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC). For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities, refer to Technical Brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 and Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004. Both documents are available at www.ti.com. The exposed thermal pad dimensions for this package are shown in the following illustration. 48 33 49 32 Exposed Thermal Pad 6,50 5,29 64 17 1 16 6,50 5,29 Top View NOTE: All linear dimensions are in millimeters PPTD012 Exposed Thermal Pad Dimensions PowerPAD is a trademark of Texas Instruments PACKAGE OPTION ADDENDUM www.ti.com 12-May-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS5240IPAP ACTIVE HTQFP PAP 64 160 ADS5240IPAPG4 ACTIVE HTQFP PAP 64 160 TBD Call TI ADS5240IPAPT ACTIVE HTQFP PAP 64 250 Green (RoHS & no Sb/Br) CU NIPDAU ADS5240IPAPTG4 ACTIVE HTQFP PAP 64 250 TBD Call TI Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-3-260C-168 HR Call TI Level-3-260C-168 HR Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated