Cypress CY8C24794-SPI Psoctm mixed-signal array Datasheet

PSoC™ Mixed-Signal Array
Final Data Sheet
CY8C24794
Features
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ Two 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 3.0 to 5.25V Operating Voltage
❐ Industrial Temperature Range: -40°C to +85°C
❐ USB Temperature Range: -10°C to +85°C
■ Advanced Peripherals (PSoC Blocks)
❐ 6 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
❐ 4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Full-Duplex UART
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
❐ Capacitive Sensing Application Capability
Port 5
System Bus
Port 7
Port 4
Port 3
Global Digital Interconnect
Port 2
■ Full-Speed USB (12 Mbps)
❐ Four Uni-Directional Endpoints
❐ One Bi-Directional Control Endpoint
❐ USB 2.0 Compliant
❐ Dedicated 256 Byte Buffer
❐ No External Crystal Required
■ Flexible On-Chip Memory
❐ 16K Flash Program Storage 50,000 Erase/
Write Cycles
❐ 1K SRAM Data Storage
❐ In-System Serial Programming (ISSP™)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
❐ Up to 48 Analog Inputs on GPIO
❐ Two 33 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO
Port 1
Port 0
Analog
Drivers
Global Analog Interconnect
PSoC CORE
SRAM
1K
SROM
Flash 16K
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
ANALOG SYSTEM
Analog
Ref .
Digital
Block
Array
Digital
Clocks
2
Decimator
MACs
Type 2
Internal
POR and LVD
Voltage
System Resets
Ref.
USB
❐ I2C™ Slave, Master, and Multi-Master to
400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■ Complete Development Tools
❐ Free Development Software
(PSoC™ Designer)
❐ Full-Featured, In-Circuit Emulator and
Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
PSoC™ Functional Overview
The PSoC™ family consists of many Mixed-Signal Array with
On-Chip Controller devices. All PSoC family devices are
designed to replace traditional MCUs, system ICs, and the
numerous discrete components that surround them. The PSoC
CY8C24794 device is a unique member of the PSoC family
because it includes a full-featured, full-speed (12 Mbps) USB
port. Configurable analog, digital, and interconnect circuitry
enable a high level of integration in a host of industrial, consumer, and communication applications.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources including a full-speed USB port. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C24794
device can have up to seven IO ports that connect to the global
digital and analog interconnects, providing access to 4 digital
blocks and 6 analog blocks.
Analog
Block
Array
I2C
■ Additional System Resources
This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program
memory, SRAM data memory, and configurable IO are included
in a range of convenient pinouts and packages.
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
■ Precision, Programmable Clocking
❐ Internal ±4% 24/48 MHz Oscillator
❐ Internal Oscillator for Watchdog and Sleep
❐ .25% Accuracy for USB with no External
Components
Analog
Input
Muxing
SYSTEM RESOURCES
April 14, 2005
© Cypress Semiconductor Corp. 2004-2005 — Document No. 38-12018 Rev. *F
1
CY8C24794 Final Data Sheet
PSoC™ Overview
The PSoC Core
Digital peripheral configurations include those listed below.
The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with up to 20
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompasses 16K of Flash for program storage, 1K of
SRAM for data storage, and up to 2K of EEPROM emulated
using the Flash. Program Flash utilizes four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate
to 8% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low
power 32 kHz ILO (internal low speed oscillator) is provided for
the Sleep timer and WDT. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC
device. In USB systems, the IMO will self-tune to ± 0.25% accuracy for USB communication.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read.
The Digital System
The Digital System is composed of 4 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references.
Port 7
Port 5
Port 3
Port 4
Port 1
Port 2
To System Bus
DigitalClocks
FromCore
■
Full-Speed USB (12 Mbps)
■
PWMs (8 to 32 bit)
■
PWMs with Dead band (8 to 24 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity
■
SPI master and slave
■
I2C slave and multi-master
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA
■
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device Characteristics” on page 3.
The Analog System
The Analog System is composed of 6 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and
can be customized to support specific application requirements.
Some of the more common PSoC analog functions (most available as user modules) are listed below.
■
Analog-to-digital converters (up to 2, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR)
■
Filters (2 and 4 pole band-pass, low-pass, and notch)
■
Amplifiers (up to 2, with selectable gain to 48x)
■
Instrumentation amplifiers (1 with selectable gain to 93x)
■
Comparators (up to 2, with 16 selectable thresholds)
■
DACs (up to 2, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 2, with 6- to 9-bit resolution)
■
High current output drivers (two with 30 mA drive as a PSoC
Core Resource)
■
1.3V reference (as a System Resource)
■
DTMF Dialer
■
Modulators
■
Correlators
■
Peak Detectors
■
Many other topologies possible
Port 0
To Analog
System
DIGITAL SYSTEM
8
Row 0
DBB00
DBB01
DCB02
4
Row Output
Configuration
8
Row Input
Configuration
Digital PSoC Block Array
DCB03
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
8
8
GOO[7:0]
Digital System Block Diagram
April 14, 2005
Document No. 38-12018 Rev. *F
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CY8C24794 Final Data Sheet
PSoC™ Overview
Analog blocks are arranged in a column of three, which
includes one CT (Continuous Time) and two SC (Switched
Capacitor) blocks, as shown in the figure below.
All IO
(Except Port 7)
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
Analog
Mux Bus
AGNDIn RefIn
P0[7]
P2[3]
Additional System Resources
System Resources, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, low voltage detection, and power on reset. Brief
statements describing the merits of each resource follow.
■
Full-Speed USB (12 Mbps) with 5 configurable endpoints and
256 bytes of RAM. No external components required except
two series resistors. Wider than commercial temperature
USB operation (-10°C to +85°C).
■
Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to
both the digital and analog systems. Additional clocks can be
generated using digital PSoC blocks as clock dividers.
■
Two multiply accumulates (MACs) provide fast 8-bit multipliers with 32-bit accumulate, to assist in both general math as
well as digital filters.
■
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
■
Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
Versatile analog multiplexer system.
P2[6]
P2[4]
P2[1]
P2[2]
P2[0]
ACI0[1:0]
ACI1[1:0]
Array Input
Configuration
AnalogReference
Reference
Generators
PSoC Device Characteristics
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Analog System Block Diagram
The Analog Multiplexer System
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources
available for specific PSoC device groups. The device covered
by this data sheet is shown in the highlighted row of the table.
PSoC Device Characteristics
The Analog Mux Bus can connect to every GPIO pin in ports 05. Pins can be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. It can be
split into two sections for simultaneous dual-channel processing. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array.
Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other
multiplexer applications include:
Flash
Size
RefHi
RefLo
AGND
SRAM
Size
Interface to
Digital System
Analog
Blocks
ASC21
Analog
Columns
ASD20
Analog
Outputs
ASD11
Analog
Inputs
ASC10
Digital
Blocks
ACB01
Digital
Rows
ACB00
Digital
IO
Block
Array
CY8C29x66
up to
64
4
16
12
4
4
12
2K
32K
CY8C27x43
up to
44
2
8
12
4
4
12
256
Bytes
16K
CY8C24794
50
1
4
48
2
2
6
1K
16K
CY8C24x23
up to
24
1
4
12
2
2
6
256
Bytes
4K
CY8C24x23A
up to
24
1
4
12
2
2
6
256
Bytes
4K
PSoC Part
Number
■
Track pad, finger sensing.
CY8C21x34
up to
28
1
4
28
0
2
4a
512
Bytes
8K
■
Chip-wide mux that allows analog input from up to 48 IO
pins.
CY8C21x23
16
1
4
8
0
2
4a
256
Bytes
4K
■
Crosspoint connection between any IO pin combinations.
April 14, 2005
a. Limited analog functionality.
Document No. 38-12018 Rev. *F
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CY8C24794 Final Data Sheet
PSoC™ Overview
Getting Started
Development Tools
The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin,
register, and electrical specifications. For in-depth information,
along with detailed programming information, reference the
PSoC™ Mixed-Signal Array Technical Reference Manual.
PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable System-onChip (PSoC) devices. The PSoC Designer IDE and application
runs on Windows NT 4.0, Windows 2000, Windows Millennium
(Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.)
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest PSoC device data sheets on
the web at http://www.cypress.com/psoc.
To determine which PSoC device meets your requirements,
navigate through the PSoC Decision Tree in the Application
Note AN2209 at http://www.cypress.com and select Application
Notes under the Design Resources.
PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Development Kits
Technical Training
Free PSoC technical training is available for beginners and is
taught by a marketing or application engineer over the phone.
PSoC training classes cover designing, debugging, advanced
analog, as well as application-specific classes covering topics
such as PSoC and the LIN bus. Go to http://www.cypress.com,
click on Design Support located on the left side of the web
page, and select Technical Training for more details.
Context
Sensitive
Help
Graphical Designer
Interface
Commands
PSoC TM
Designer
Results
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com, click the Online Store shopping cart
icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items.
Importable
Design
Database
PSoC
Configuration
Sheet
Device
Database
PSoC TM
Designer
Core
Engine
Application
Database
Manufacturing
Information
File
Project
Database
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Design
Support located on the left side of the web page, and select
CYPros Consultants.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.
User
Modules
Library
Emulation
Pod
In-Circuit
Emulator
Device
Programmer
PSoC Designer Subsystems
Application Notes
A long list of application notes will assist you in every aspect of
your design effort. To view the PSoC application notes, go to
the http://www.cypress.com web site and select Application
Notes under the Design Resources list located in the center of
the web page. Application notes are listed by date as default.
April 14, 2005
Document No. 38-12018 Rev. *F
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CY8C24794 Final Data Sheet
PSoC™ Overview
PSoC Designer Software Subsystems
Device Editor
Debugger
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time.
PSoC Designer sets up power-on initialization tables for
selected PSoC block configurations and creates source code
for an application framework. The framework contains software
to operate the selected components and, if the project uses
more than one operating configuration, contains routines to
switch between different sets of PSoC block configurations at
run time. PSoC Designer can print out a configuration sheet for
a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the
framework is generated, the user can add application-specific
code to flesh out the framework. It’s also possible to change the
selected components and regenerate the framework.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
Design Browser
The Design Browser allows users to select and import preconfigured designs into the user’s project. Users can easily browse
a catalog of preconfigured designs to facilitate time-to-design.
Examples provided in the tools include a 300-baud modem, LIN
Bus master and slave, fan controller, and magnetic card reader.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble, compile, link, and build.
A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability
to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and will operate
with all PSoC devices. Emulation pods for each device family
are available separately. The emulation pod takes the place of
the PSoC device in the target board and performs full speed (24
MHz) operation.
Assembler. The macro assembler allows the assembly code
to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available
that supports the PSoC family of devices. Even if you have
never worked in the C language before, the product quickly
allows you to create complete C programs for the PSoC family
devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
April 14, 2005
Document No. 38-12018 Rev. *F
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CY8C24794 Final Data Sheet
PSoC™ Overview
Designing with User Modules
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture
a unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk
of having to select a different part to meet the final design
requirements.
Device Editor
User
Module
Selection
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this
stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to developing code for the project, you
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specification and provides the high-level user
module API functions.
April 14, 2005
Source
Code
Generator
Generate
Application
Application Editor
To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters
that allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8
bits of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides highlevel functions to control and respond to hardware events at
run-time. The API also provides optional interrupt service routines that you can adapt as needed.
Placement
and
Parameter
-ization
Project
Manager
Source
Code
Editor
Build
Manager
Build
All
Debugger
Interface
to ICE
Storage
Inspector
Event &
Breakpoint
Manager
User Module and Source Code Development Flows
The next step is to write your main program, and any sub-routines using PSoC Designer’s Application Editor subsystem.
The Application Editor includes a Project Manager that allows
you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor
provides syntax coloring and advanced edit features for both C
and assembly language. File search capabilities include simple
string searches and recursive “grep-style” patterns. A single
mouse click invokes the Build Manager. It employs a professional-strength “makefile” system to automatically analyze all
file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in
a console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it
runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
Document No. 38-12018 Rev. *F
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CY8C24794 Final Data Sheet
PSoC™ Overview
Document Conventions
Table of Contents
Acronyms Used
For an in depth discussion and more information on your PSoC
device, obtain the PSoC Mixed-Signal Array Technical Reference Manual. This document encompasses and is organized
into the following chapters and sections.
The following table lists the acronyms that are used in this document.
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only memory
FSR
full scale range
GPIO
general purpose IO
GUI
graphical user interface
HBM
human body model
ICE
in-circuit emulator
ILO
internal low speed oscillator
IMO
internal main oscillator
IO
input/output
IPOR
imprecise power on reset
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
PC
program counter
PLL
phase-locked loop
POR
power on reset
PPOR
precision power on reset
PSoC™
Programmable System-on-Chip™
PWM
pulse width modulator
SC
switched capacitor
SRAM
static random access memory
1.
Pin Information ............................................................. 8
1.1 56-Pin Part Pinout .................................................. 8
2.
Register Reference ....................................................... 9
2.1 Register Conventions ............................................. 9
2.1.1 Abbreviations Used .................................... 9
2.2 Register Mapping Tables ....................................... 9
3.
Electrical Specifications ............................................ 12
3.1 Absolute Maximum Ratings ................................. 13
3.2 Operating Temperature ........................................ 13
3.3 DC Electrical Characteristics ................................ 13
3.3.1 DC Chip-Level Specifications ................... 13
3.3.2 DC General Purpose IO Specifications .... 14
3.3.3 DC Full-Speed USB Specifications .......... 14
3.3.4 DC Operational Amplifier Specifications ... 15
3.3.5 DC Analog Output Buffer Specifications ... 17
3.3.6 DC Analog Reference Specifications ....... 18
3.3.7 DC Analog PSoC Block Specifications ..... 19
3.3.8 DC POR and LVD Specifications ............. 19
3.3.9 DC Programming Specifications ............... 20
3.4 AC Electrical Characteristics ................................ 21
3.4.1 AC Chip-Level Specifications ................... 21
3.4.2 AC General Purpose IO Specifications .... 22
3.4.3 AC Full-Speed USB Specifications ........... 22
3.4.4 AC Operational Amplifier Specifications ... 23
3.4.5 AC Digital Block Specifications ................. 25
3.4.6 AC External Clock Specifications ............. 25
3.4.7 AC Analog Output Buffer Specifications ... 26
3.4.8 AC Programming Specifications ............... 27
3.4.9 AC I2C Specifications ............................... 28
4.
Packaging Information ............................................... 29
4.1 Packaging Dimensions ......................................... 29
4.2 Thermal Impedance ............................................. 30
4.3 Solder Reflow Peak Temperature ........................ 30
5.
Ordering Information .................................................. 31
5.1 Ordering Code Definitions .................................... 31
6.
Sales and Company Information ............................... 32
6.1 Revision History ................................................... 32
6.2 Copyrights and Code Protection .......................... 32
Units of Measure
A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 12 lists all the abbreviations
used to measure the PSoC devices.
Numeric Naming
Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.
April 14, 2005
Document No. 38-12018 Rev. *F
7
1. Pin Information
This chapter describes, lists, and illustrates the CY8C24794 PSoC device pins and pinout configuration.
1.1
56-Pin Part Pinout
The CY8C24794 PSoC device is available in a 56-pin package which is listed and illustrated in the following table. Every port pin
(labeled with a “P”) is capable of Digital IO. However, Vss and Vdd are not capable of Digital IO.
Table 1-1. 56-Pin Part Pinout (MLF*)
M
I, M
I, M
M
P2[5], M
P2[7], M
P0[1], A, I, M
P0[3], A, IO, M
P0[5], A, IO, M
P0[7], A, I, M
Vss
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
P2[6], M
P2[4], M
P4[6]
P2[0]
P2[2]
P2[4]
IO
IO
IO
IO
Direct switched capacitor block input.
Direct switched capacitor block input.
A, I, M, P2[3]
A, I, M, P2[1]
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
I2C Serial Clock (SCL), ISSP-SCLK.
Ground connection.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
56
55
54
53
52
51
50
49
48
47
46
45
44
43
40
41
42
43
CY8C24794 56-Pin PSoC Device
Description
MLF
(Top View )
15
16
17
18
19
20
21
22
23
24
25
26
27
28
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
D+
DVdd
P7[7]
P7[0]
P1[0]
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
P4[0]
P4[2]
P4[4]
Name
Supply voltage.
42
41
40
39
38
37
36
35
34
33
32
31
30
29
P2[2], A, I, M
P2[0], A, I, M
P4[6], M
P4[4], M
P4[2], M
P4[0], M
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
M, I2C SCL, P1[7]
M, I2C SDA, P1[5]
M, P1[3]
M, I2C SCL, P1[1]
Vss
D+
DVdd
P7[7]
P7[0]
M, I2C SDA, P1[0]
M, P1[2]
M, P1[4]
M, P1[6]
Type
Pin
No. Digital Analog
1
IO
I, M
2
IO
I, M
3
IO
M
4
IO
M
5
IO
M
6
IO
M
7
IO
M
8
IO
M
9
IO
M
10
IO
M
11
IO
M
12
IO
M
13
IO
M
14
IO
M
15
IO
M
16
IO
M
17
IO
M
18
IO
M
19
Power
20
USB
21
USB
22
Power
23
IO
24
IO
25
IO
M
26
IO
M
27
IO
M
28
IO
M
29
IO
M
30
IO
M
31
IO
M
32
IO
M
33
IO
M
34
IO
M
35
IO
M
36
IO
M
37
IO
M
38
IO
M
39
IO
M
I2C Serial Data (SDA), ISSP-SDATA.
Type
Pin
No. Digital Analog
44
IO
M
45
IO
I, M
46
IO
I, M
47
IO
I, M
48
IO
I, M
49
Power
50
Power
51
IO
I, M
52
IO
IO, M
53
Direct switched capacitor block input.
54
Direct switched capacitor block input.
55
External Analog Ground (AGND) input. 56
IO
IO
IO
IO
IO, M
I, M
M
M
Name
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Vss
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
Description
External Voltage Reference (VREF) input.
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
Ground connection.
Analog column mux input, integration input #1.
Analog column mux input and column output,
integration input #2.
Analog column mux input and column output.
Analog column mux input.
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* The MLF package has a center pad that must be connected to ground (Vss).
April 14, 2005
Document No. 38-12018 Rev. *F
8
2. Register Reference
This chapter lists the registers of the CY8C24794 PSoC device. For detailed register information, reference the
PSoC™ Mixed-Signal Array Technical Reference Manual.
2.1
2.1.1
Register Conventions
2.2
Abbreviations Used
The register conventions specific to this section are listed in the
following table.
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
April 14, 2005
Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI
bit is set the user is in Bank 1.
Note In the following register mapping tables, blank fields are
Reserved and should not be accessed.
Document No. 38-12018 Rev. *F
9
CY8C24794 Final Data Sheet
2. Register Reference
Register Map Bank 0 Table: User Space
RW
RW
RW
RW
RW
RW
RW
RW
W
W
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
CPU_F
DAC_D
CPU_SCR1
CPU_SCR0
Document No. 38-12018 Rev. *F
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
RW
RW
Addr
(0,Hex)
Name
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
ASD20CR0
91
ASD20CR1
92
ASD20CR2
93
ASD20CR3
94
ASC21CR0
95
ASC21CR1
96
ASC21CR2
97
ASC21CR3
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
MUL1_X
A9
MUL1_Y
AA
MUL1_DH
AB
MUL1_DL
AC
ACC1_DR1
AD
ACC1_DR0
AE
ACC1_DR3
AF
ACC1_DR2
B0
RDI0RI
B1
RDI0SYN
B2
RDI0IS
B3
RDI0LT0
B4
RDI0LT1
B5
RDI0RO0
B6
RDI0RO1
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Access
Addr
(0,Hex)
April 14, 2005
Name
Access
Addr
(0,Hex)
Name
Access
Addr
(0,Hex)
Name
00
RW
PMA0_DR
40
RW
01
RW
PMA1_DR
41
RW
02
RW
PMA2_DR
42
RW
03
RW
PMA3_DR
43
RW
04
RW
PMA4_DR
44
RW
05
RW
PMA5_DR
45
RW
06
RW
PMA6_DR
46
RW
07
RW
PMA7_DR
47
RW
08
RW
USB_SOF0
48
R
09
RW
USB_SOF1
49
R
0A
RW
USB_CR0
4A
RW
0B
RW
USBIO_CR0
4B
#
0C
USBIO_CR1
4C
RW
RW
0D
4D
RW
0E
EP1_CNT1
4E
#
RW
0F
EP1_CNT
4F
RW
RW
10
EP2_CNT1
50
#
RW
11
EP2_CNT
51
RW
RW
12
EP3_CNT1
52
#
RW
13
EP3_CNT
53
RW
RW
14
EP4_CNT1
54
#
RW
15
EP4_CNT
55
RW
RW
16
EP0_CR
56
#
RW
17
EP0_CNT
57
#
RW
18
EP0_DR0
58
RW
19
EP0_DR1
59
RW
1A
EP0_DR2
5A
RW
1B
EP0_DR3
5B
RW
1C
EP0_DR4
5C
RW
RW
PRT7DR
1D
EP0_DR5
5D
RW
RW
PRT7IE
1E
EP0_DR6
5E
RW
RW
PRT7GS
1F
EP0_DR7
5F
RW
RW
PRT7DM2
60
20
RW
DBB00DR0
#
AMX_IN
61
21
DBB00DR1
W
AMUXCFG
RW
62
22
DBB00DR2
RW
63
23
RW
DBB00CR0
#
ARF_CR
64
24
#
DBB01DR0
#
CMP_CR0
65
25
#
DBB01DR1
W
ASY_CR
66
26
RW
DBB01DR2
RW
CMP_CR1
67
27
DBB01CR0
#
68
28
DCB02DR0
#
69
29
DCB02DR1
W
6A
2A
DCB02DR2
RW
6B
2B
DCB02CR0
#
6C
2C
RW
DCB03DR0
#
TMP_DR0
6D
2D
RW
DCB03DR1
W
TMP_DR1
6E
2E
RW
DCB03DR2
RW
TMP_DR2
6F
2F
RW
DCB03CR0
#
TMP_DR3
70
30
RW
ACB00CR3
71
31
RW
ACB00CR0
72
32
RW
ACB00CR1
73
33
RW
ACB00CR2
74
34
RW
ACB01CR3
75
35
RW
ACB01CR0
76
36
RW
ACB01CR1
77
37
RW
ACB01CR2
78
38
79
39
7A
3A
7B
3B
7C
3C
7D
3D
7E
3E
7F
3F
Blank fields are Reserved and should not be accessed.
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
PRT5GS
PRT5DM2
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
RW
#
#
10
CY8C24794 Final Data Sheet
2. Register Reference
Register Map Bank 1 Table: Configuration Space
RW
RW
RW
RW
RW
RW
RW
EP1_CR0
EP2_CR0
EP3_CR0
EP4_CR0
C0
C1
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
GDI_O_IN
D1
GDI_E_IN
D2
GDI_O_OU
D3
GDI_E_OU
D4
D5
D6
D7
D8
MUX_CR0
D9
MUX_CR1
DA
MUX_CR2
DB
MUX_CR3
DC
OSC_GO_EN DD
DE
OSC_CR4
DF
OSC_CR3
E0
OSC_CR0
E1
OSC_CR1
E2
OSC_CR2
E3
VLT_CR
E4
VLT_CMP
E5
E6
E7
E8
IMO_TR
E9
ILO_TR
EA
BDG_TR
EB
ECO_TR
EC
MUX_CR4
ED
MUX_CR5
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
CPU_F
F8
F9
FA
FB
FC
FD
DAC_CR
FE
CPU_SCR1
CPU_SCR0
FF
Document No. 38-12018 Rev. *F
Access
RW
RW
RW
RW
RW
RW
RW
USBIO_CR2
USB_CR1
Addr
(1,Hex)
RW
RW
RW
RW
RW
RW
RW
RW
Name
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
ASD20CR1
92
ASD20CR2
93
ASD20CR3
94
ASC21CR0
95
ASC21CR1
96
ASC21CR2
97
ASC21CR3
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
RDI0RI
B1
RDI0SYN
B2
RDI0IS
B3
RDI0LT0
B4
RDI0LT1
B5
RDI0RO0
B6
RDI0RO1
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Access
Addr
(1,Hex)
April 14, 2005
Name
Access
Addr
(1,Hex)
Name
Access
Addr
(1,Hex)
Name
40
00
RW
RW
PMA0_WA
41
01
RW
RW
PMA1_WA
42
02
RW
RW
PMA2_WA
43
03
RW
RW
PMA3_WA
44
04
RW
RW
PMA4_WA
45
05
RW
RW
PMA5_WA
46
06
RW
RW
PMA6_WA
47
07
RW
RW
PMA7_WA
48
08
RW
49
09
RW
4A
0A
RW
4B
0B
RW
4C
0C
RW
4D
0D
RW
4E
0E
RW
4F
0F
RW
50
10
RW
RW
PMA0_RA
51
11
RW
RW
PMA1_RA
52
12
RW
RW
PMA2_RA
53
13
RW
RW
PMA3_RA
54
14
RW
RW
PMA4_RA
55
15
RW
RW
PMA5_RA
16
56
RW
RW
PMA6_RA
17
57
RW
RW
PMA7_RA
18
58
19
59
1A
5A
1B
5B
1C
5C
RW
PRT7DM0
1D
5D
RW
PRT7DM1
1E
5E
RW
PRT7IC0
1F
5F
RW
PRT7IC1
20
60
RW
RW
DBB00FN
CLK_CR0
21
61
RW
RW
DBB00IN
CLK_CR1
22
62
RW
RW
DBB00OU
ABF_CR0
23
63
RW
AMD_CR0
64
24
DBB01FN
RW
CMP_GO_EN
RW
65
25
DBB01IN
RW
CMP_GO_EN1
RW
66
26
RW
DBB01OU
RW
AMD_CR1
27
67
RW
ALT_CR0
68
28
DCB02FN
RW
69
29
DCB02IN
RW
6A
2A
DCB02OU
RW
2B
6B
6C
2C
RW
DCB03FN
RW
TMP_DR0
6D
2D
RW
DCB03IN
RW
TMP_DR1
6E
2E
RW
DCB03OU
RW
TMP_DR2
2F
6F
RW
TMP_DR3
70
30
RW
ACB00CR3
71
31
RW
ACB00CR0
72
32
RW
ACB00CR1
33
73
RW
ACB00CR2
74
34
RW
ACB01CR3
75
35
RW
ACB01CR0
76
36
RW
ACB01CR1
37
77
RW
ACB01CR2
78
38
79
39
7A
3A
3B
7B
7C
3C
7D
3D
7E
3E
3F
7F
Blank fields are Reserved and should not be accessed.
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
PRT5DM1
PRT5IC0
PRT5IC1
RW
#
#
#
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
W
W
RW
W
RW
RW
RL
RW
#
#
11
3. Electrical Specifications
This chapter presents the DC and AC electrical specifications of the CY8C24794 PSoC device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. Specifications for devices running at greater
than 12 MHz are valid for -40oC ≤ TA ≤ 70oC and TJ ≤ 82oC.
5.25
Vdd Voltage
lid ng
Va rati n
e io
Op Reg
4.75
3.00
93 kHz
12 MHz
24 MHz
CPUFrequency
Figure 3-1a. Voltage versus CPU Frequency
The following table lists the units of measure that are used in this chapter.
Table 3-1: Units of Measure
Symbol
Unit of Measure
Symbol
Unit of Measure
degree Celsius
µW
microwatts
dB
decibels
mA
milli-ampere
fF
femto farad
ms
milli-second
Hz
hertz
mV
milli-volts
KB
1024 bytes
nA
nanoampere
Kbit
1024 bits
ns
nanosecond
kHz
kilohertz
nV
nanovolts
kΩ
kilohm
Ω
ohm
MHz
megahertz
pA
picoampere
MΩ
megaohm
pF
picofarad
µA
microampere
pp
peak-to-peak
µF
microfarad
ppm
µH
microhenry
ps
picosecond
µs
microsecond
sps
samples per second
µV
microvolts
σ
sigma: one standard deviation
microvolts root-mean-square
V
volts
o
C
µVrms
April 14, 2005
parts per million
Document No. 38-12018 Rev. *F
12
CY8C24794 Final Data Sheet
3.1
3. Electrical Specifications
Absolute Maximum Ratings
Table 3-2. Absolute Maximum Ratings
Symbol
Description
Min
Typ
Max
Units
TSTG
Storage Temperature
-55
–
+100
oC
TA
Ambient Temperature with Power Applied
-40
–
+85
o
Vdd
Supply Voltage on Vdd Relative to Vss
-0.5
–
+6.0
V
VIO
DC Input Voltage
Vss - 0.5
–
Vdd + 0.5
V
VIO2
DC Voltage Applied to Tri-state
Vss - 0.5
–
Vdd + 0.5
V
IMIO
Maximum Current into any Port Pin
-25
–
+50
mA
IMAIO
Maximum Current into any Port Pin Configured as Analog
Driver
-50
–
+50
mA
ESD
Electro Static Discharge Voltage
2000
–
–
V
LU
Latch-up Current
–
–
200
mA
3.2
Notes
Higher storage temperatures will reduce data
retention time.
C
Human Body Model ESD.
Operating Temperature
Table 3-3. Operating Temperature
Symbol
Description
Min
Typ
Max
Units
TA
Ambient Temperature
-40
–
+85
oC
TAUSB
Ambient Temperature using USB
-10
–
+85
o
TJ
Junction Temperature
-40
–
+100
oC
3.3
3.3.1
Notes
C
The temperature rise from ambient to junction is
package specific. See “Thermal Impedance” on
page 30. The user must limit the power consumption to comply with this requirement.
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-4. DC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd
Supply Voltage
3.0
–
5.25
V
See DC POR and LVD specifications, Table 314 on page 19.
IDD5
Supply Current, IMO = 24 MHz (5V)
–
14
27
mA
Conditions are Vdd = 5.0V, TA = 25 oC, CPU = 3
MHz, SYSCLK doubler disabled, VC1 = 1.5
MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off.
IDD3
Supply Current, IMO = 24 MHz (3.3V)
–
8
14
mA
Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3
MHz, SYSCLK doubler disabled, VC1 = 1.5
MHz, VC2 = 93.75 kHz, VC3 = 0.367 kHz, analog power = off.
ISB
Sleep (Mode) Current with POR, LVD, Sleep Timer, and
WDT.a
–
3
6.5
µA
Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC ≤ TA ≤ 55 oC, analog
power = off.
ISBH
Sleep (Mode) Current with POR, LVD, Sleep Timer, and
WDT at high temperature.a
–
4
25
µA
Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA ≤ 85 oC, analog
power = off.
a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions
enabled.
April 14, 2005
Document No. 38-12018 Rev. *F
13
CY8C24794 Final Data Sheet
3.3.2
3. Electrical Specifications
DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-5. DC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
kΩ
RPU
Pull-Up Resistor
RPD
Pull-Down Resistor
4
5.6
8
kΩ
VOH
High Output Level
Vdd - 1.0
–
–
V
IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads,
4 on even port pins (for example, P0[2], P1[4]),
4 on odd port pins (for example, P0[3], P1[5])).
80 mA maximum combined IOH budget.
VOL
Low Output Level
–
–
0.75
V
IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads,
4 on even port pins (for example, P0[2], P1[4]),
4 on odd port pins (for example, P0[3], P1[5])).
150 mA maximum combined IOL budget.
VIL
Input Low Level
–
–
0.8
VIH
Input High Level
2.1
–
VH
Input Hysterisis
–
60
–
mV
IIL
Input Leakage (Absolute Value)
–
1
–
nA
Gross tested to 1 µA.
CIN
Capacitive Load on Pins as Input
–
3.5
10
pF
Package and pin dependent. Temp = 25oC.
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent. Temp = 25oC.
3.3.3
4
5.6
8
V
Vdd = 3.0 to 5.25.
V
Vdd = 3.0 to 5.25.
DC Full-Speed USB Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -10°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -10°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-6. DC Full-Speed (12 Mbps) USB Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
USB Interface
VDI
Differential Input Sensitivity
0.2
–
–
V
VCM
Differential Input Common Mode Range
0.8
–
2.5
V
VSE
Single Ended Receiver Threshold
0.8
–
2.0
V
CIN
Transceiver Capacitance
–
–
20
pF
IIO
High-Z State Data Line Leakage
-10
–
10
µA
0V < VIN < 3.3V.
REXT
External USB Series Resistor
23
–
25
Ω
In series with each USB pin.
VUOH
Static Output High, Driven
2.8
–
3.6
V
15 kΩ ± 5% to Ground. Internal pull-up enabled.
VUOHI
Static Output High, Idle
2.7
–
3.6
V
15 kΩ ± 5% to Ground. Internal pull-up enabled.
VUOL
Static Output Low
–
–
0.3
V
15 kΩ ± 5% to Ground. Internal pull-up enabled.
ZO
USB Driver Output Impedance
28
–
44
Ω
Including REXT Resistor.
VCRS
D+/D- Crossover Voltage
1.3
–
2.0
V
April 14, 2005
Document No. 38-12018 Rev. *F
| (D+) - (D-) |
14
CY8C24794 Final Data Sheet
3.3.4
3. Electrical Specifications
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor
PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.
Table 3-7. 5V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Min
Typ
Max
Units
Notes
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
–
1.6
10
mV
Power = Medium, Opamp Bias = High
–
1.3
8
mV
Power = High, Opamp Bias = High
–
1.2
7.5
mV
TCVOSOA
Average Input Offset Voltage Drift
–
7.0
35.0
µV/oC
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
20
–
pA
Gross tested to 1 µA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent. Temp = 25oC.
VCMOA
Common Mode Voltage Range
0.0
–
Vdd
V
Common Mode Voltage Range (high power or high
opamp bias)
0.5
–
Vdd - 0.5
The common-mode input voltage range is measured through an analog output buffer. The
specification includes the limitations imposed
by the characteristics of the analog output
buffer.
–
–
dB
GOLOA
VOHIGHOA
VOLOWOA
ISOA
PSRROA
Open Loop Gain
Power = Low, Opamp Bias = High
60
Power = Medium, Opamp Bias = High
60
Power = High, Opamp Bias = High
80
High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
Vdd - 0.2
–
–
V
Power = Medium, Opamp Bias = High
Vdd - 0.2
–
–
V
Power = High, Opamp Bias = High
Vdd - 0.5
–
–
V
Power = Low, Opamp Bias = High
–
–
0.2
V
Power = Medium, Opamp Bias = High
–
–
0.2
V
Power = High, Opamp Bias = High
–
–
0.5
V
Power = Low, Opamp Bias = Low
–
400
800
µA
Power = Low, Opamp Bias = High
–
500
900
µA
Power = Medium, Opamp Bias = Low
–
800
1000
µA
Power = Medium, Opamp Bias = High
–
1200
1600
µA
Power = High, Opamp Bias = Low
–
2400
3200
µA
Power = High, Opamp Bias = High
–
4600
6400
µA
Supply Voltage Rejection Ratio
65
80
–
dB
Low Output Voltage Swing (internal signals)
Supply Current (including associated AGND buffer)
April 14, 2005
Document No. 38-12018 Rev. *F
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN
≤ Vdd.
15
CY8C24794 Final Data Sheet
3. Electrical Specifications
Table 3-8. 3.3V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Min
Typ
Max
Units
Notes
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
–
1.65
10
mV
Power = Medium, Opamp Bias = High
–
1.32
8
mV
High Power is 5 Volts Only
TCVOSOA
Average Input Offset Voltage Drift
–
7.0
35.0
µV/oC
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
20
–
pA
Gross tested to 1 µA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent. Temp = 25oC.
VCMOA
Common Mode Voltage Range
0.2
–
Vdd - 0.2
V
The common-mode input voltage range is
measured through an analog output buffer.
The specification includes the limitations
imposed by the characteristics of the analog
output buffer.
GOLOA
Open Loop Gain
–
–
dB
VOHIGHOA
VOLOWOA
ISOA
PSRROA
Power = Low, Opamp Bias = Low
60
Power = Medium, Opamp Bias = Low
60
Power = High, Opamp Bias = Low
80
High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Vdd - 0.2
–
–
V
Power = Medium, Opamp Bias = Low
Vdd - 0.2
–
–
V
Power = High is 5V only
Vdd - 0.2
–
–
V
Power = Low, Opamp Bias = Low
–
–
0.2
V
Power = Medium, Opamp Bias = Low
–
–
0.2
V
Power = High, Opamp Bias = Low
–
–
0.2
V
Power = Low, Opamp Bias = Low
–
400
800
µA
Power = Low, Opamp Bias = High
–
500
900
µA
Power = Medium, Opamp Bias = Low
–
800
1000
µA
Power = Medium, Opamp Bias = High
–
1200
1600
µA
Power = High, Opamp Bias = Low
–
2400
3200
µA
Power = High, Opamp Bias = High
–
4600
6400
µA
Supply Voltage Rejection Ratio
65
80
–
dB
Low Output Voltage Swing (internal signals)
Supply Current (including associated AGND buffer)
April 14, 2005
Document No. 38-12018 Rev. *F
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤
VIN ≤ Vdd.
16
CY8C24794 Final Data Sheet
3.3.5
3. Electrical Specifications
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-9. 5V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
VOSOB
Input Offset Voltage (Absolute Value)
–
3
12
mV
TCVOSOB
Average Input Offset Voltage Drift
–
+6
–
µV/°C
VCMOB
Common-Mode Input Voltage Range
0.5
–
Vdd - 1.0
V
ROUTOB
Output Resistance
Power = Low
–
0.6
–
Ω
Power = High
–
0.6
–
Ω
High Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
0.5 x Vdd + 1.1 –
–
V
0.5 x Vdd + 1.1 –
–
V
VOHIGHOB
Power = High
VOLOWOB
ISOB
PSRROB
Notes
Low Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
–
–
0.5 x Vdd - 1.3
V
Power = High
–
–
0.5 x Vdd - 1.3
V
Power = Low
–
1.1
5.1
mA
Power = High
–
2.6
8.8
mA
Supply Voltage Rejection Ratio
53
64
–
dB
Supply Current Including Bias Cell (No Load)
(0.5 x Vdd - 1.3) ≤ VOUT ≤ (Vdd 2.3).
Table 3-10. 3.3V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
VOSOB
Input Offset Voltage (Absolute Value)
–
3
12
mV
TCVOSOB
Average Input Offset Voltage Drift
–
+6
–
µV/°C
VCMOB
Common-Mode Input Voltage Range
0.5
-
Vdd - 1.0
V
ROUTOB
Output Resistance
Power = Low
–
1
–
Ω
Power = High
–
1
–
Ω
Power = Low
0.5 x Vdd + 1.0 –
–
V
Power = High
0.5 x Vdd + 1.0 –
–
V
Power = Low
–
–
0.5 x Vdd - 1.0
V
Power = High
–
–
0.5 x Vdd - 1.0
V
VOHIGHOB
VOLOWOB
ISOB
High Output Voltage Swing (Load = 1K ohms to Vdd/2)
Low Output Voltage Swing (Load = 1K ohms to Vdd/2)
Supply Current Including Bias Cell (No Load)
Power = Low
PSRROB
Notes
0.8
2.0
mA
Power = High
–
2.0
4.3
mA
Supply Voltage Rejection Ratio
34
64
–
dB
April 14, 2005
Document No. 38-12018 Rev. *F
(0.5 x Vdd - 1.0) ≤ VOUT ≤ (0.5 x
Vdd + 0.9).
17
CY8C24794 Final Data Sheet
3.3.6
3. Electrical Specifications
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 3-11. 5V DC Analog Reference Specifications
Symbol
Description
Min
Typ
Max
Units
BG
Bandgap Voltage Reference
1.28
1.30
1.32
V
–
AGND = Vdd/2a
Vdd/2 - 0.04
Vdd/2 - 0.01
Vdd/2 + 0.007
V
2 x BG - 0.048
2 x BG - 0.030
2 x BG + 0.024
V
P2[4] - 0.011
P2[4]
P2[4] + 0.011
V
BG - 0.009
BG + 0.008
BG + 0.016
V
1.6 x BG - 0.022
1.6 x BG - 0.010
1.6 x BG + 0.018
V
0.000
0.034
V
–
a
AGND = 2 x BandGap
–
AGND = P2[4] (P2[4] =
–
AGND = BandGapa
–
Vdd/2)a
a
AGND = 1.6 x BandGap
–
AGND Block to Block Variation (AGND = Vdd/2)
-0.034
–
RefHi = Vdd/2 + BandGap
Vdd/2 + BG - 0.10
Vdd/2 + BG
Vdd/2 + BG + 0.10
V
–
RefHi = 3 x BandGap
3 x BG - 0.06
3 x BG
3 x BG + 0.06
V
–
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
2 x BG + P2[6] - 0.113
2 x BG + P2[6] - 0.018
2 x BG + P2[6] + 0.077
V
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
P2[4] + BG - 0.130
P2[4] + BG - 0.016
P2[4] + BG + 0.098
V
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
P2[4] + P2[6] - 0.133
P2[4] + P2[6] - 0.016
P2[4] + P2[6]+ 0.100
V
–
RefHi = 3.2 x BandGap
3.2 x BG - 0.112
3.2 x BG
3.2 x BG + 0.076
V
–
RefLo = Vdd/2 – BandGap
Vdd/2 - BG - 0.04
Vdd/2 - BG + 0.024
Vdd/2 - BG + 0.04
V
–
RefLo = BandGap
BG - 0.06
BG
BG + 0.06
V
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
2 x BG - P2[6] - 0.084
2 x BG - P2[6] + 0.025
2 x BG - P2[6] + 0.134
V
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
P2[4] - BG - 0.056
P2[4] - BG + 0.026
P2[4] - BG + 0.107
V
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
P2[4] - P2[6] - 0.057
P2[4] - P2[6] + 0.026
P2[4] - P2[6] + 0.110
V
a
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
Table 3-12. 3.3V DC Analog Reference Specifications
Symbol
Description
Min
Typ
Max
Units
BG
Bandgap Voltage Reference
1.28
1.30
1.32
V
–
AGND = Vdd/2a
Vdd/2 - 0.03
Vdd/2 - 0.01
Vdd/2 + 0.005
V
–
AGND = 2 x BandGapa
Not Allowed
–
AGND = P2[4] (P2[4] = Vdd/2)
P2[4] - 0.008
P2[4] + 0.001
P2[4] + 0.009
V
–
AGND = BandGapa
BG - 0.009
BG + 0.005
BG + 0.015
V
–
AGND = 1.6 x BandGapa
1.6 x BG - 0.027
1.6 x BG - 0.010
1.6 x BG + 0.018
V
-0.034
0.000
0.034
V
P2[4] + P2[6] - 0.009
P2[4] + P2[6] + 0.057
V
P2[4]- P2[6] + 0.022
P2[4] - P2[6] + 0.092
V
–
AGND Column to Column Variation (AGND =
–
RefHi = Vdd/2 + BandGap
Not Allowed
–
RefHi = 3 x BandGap
Not Allowed
–
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
Not Allowed
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
Not Allowed
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
P2[4] + P2[6] - 0.075
–
RefHi = 3.2 x BandGap
Not Allowed
–
RefLo = Vdd/2 - BandGap
Not Allowed
–
RefLo = BandGap
Not Allowed
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
Not Allowed
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
Not Allowed
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
P2[4] - P2[6] - 0.048
Vdd/2)a
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
April 14, 2005
Document No. 38-12018 Rev. *F
18
CY8C24794 Final Data Sheet
3.3.7
3. Electrical Specifications
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-13. DC Analog PSoC Block Specifications
Symbol
Description
Min
Typ
Max
Units
RCT
Resistor Unit Value (Continuous Time)
–
12.2
–
kΩ
CSC
Capacitor Unit Value (Switched Capacitor)
–
80
–
fF
3.3.8
Notes
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V or 3.3V at 25°C and are
for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Mixed-Signal Array Technical
Reference Manual for more information on the VLT_CR register.
Table 3-14. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd Value for PPOR Trip (positive ramp)
VPPOR0R
PORLEV[1:0] = 00b
VPPOR1R
PORLEV[1:0] = 01b
VPPOR2R
PORLEV[1:0] = 10b
2.91
–
4.39
V
–
4.55
V
V
Vdd Value for PPOR Trip (negative ramp)
VPPOR0
PORLEV[1:0] = 00b
VPPOR1
PORLEV[1:0] = 01b
VPPOR2
PORLEV[1:0] = 10b
2.82
–
4.39
V
–
4.55
V
V
PPOR Hysteresis
VPH0
PORLEV[1:0] = 00b
–
92
–
mV
VPH1
PORLEV[1:0] = 01b
–
0
–
mV
VPH2
PORLEV[1:0] = 10b
–
0
–
mV
Vdd Value for LVD Trip
VLVD0
VM[2:0] = 000b
2.86
2.92
2.98a
V
VLVD1
VM[2:0] = 001b
2.96
3.02
3.08
VLVD2
VM[2:0] = 010b
3.07
3.13
3.20
VLVD3
VM[2:0] = 011b
3.92
4.00
4.08
VLVD4
VM[2:0] = 100b
4.39
4.48
4.57
VLVD5
VM[2:0] = 101b
4.55
4.64
4.74b
VLVD6
VM[2:0] = 110b
4.63
4.73
VLVD7
VM[2:0] = 111b
4.72
4.81
V
V
V
V
V
V
V
V
4.82
4.91
a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
April 14, 2005
Document No. 38-12018 Rev. *F
19
CY8C24794 Final Data Sheet
3.3.9
3. Electrical Specifications
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-15. DC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
IDDP
Supply Current During Programming or Verify
–
15
30
mA
VILP
Input Low Voltage During Programming or Verify
–
–
0.8
V
VIHP
Input High Voltage During Programming or Verify
2.1
–
–
V
IILP
Input Current when Applying Vilp to P1[0] or P1[1] During
Programming or Verify
–
–
0.2
mA
Driving internal pull-down resistor.
IIHP
Input Current when Applying Vihp to P1[0] or P1[1] During
Programming or Verify
–
–
1.5
mA
Driving internal pull-down resistor.
VOLV
Output Low Voltage During Programming or Verify
–
–
Vss + 0.75
V
VOHV
Output High Voltage During Programming or Verify
Vdd - 1.0
–
Vdd
V
FlashENPB
Flash Endurance (per block)
50,000
–
–
–
Erase/write cycles per block.
1,800,000
–
–
–
Erase/write cycles.
10
–
–
Years
FlashENT
Flash Endurance
FlashDR
Flash Data Retention
(total)a
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of
25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than
50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to
the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
April 14, 2005
Document No. 38-12018 Rev. *F
20
CY8C24794 Final Data Sheet
3.4
3. Electrical Specifications
AC Electrical Characteristics
3.4.1
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-16. AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FIMO245V
Internal Main Oscillator Frequency for 24 MHz (5V)
23.04
24
24.96
a,b
MHz
Trimmed for 5V operation using factory trim
values.
FIMO243V
Internal Main Oscillator Frequency for 24 MHz (3.3V)
22.08
24
25.92a,c
MHz
Trimmed for 3.3V operation using factory
trim values.
FIMOUSB
Internal Main Oscillator Frequency with USB
Frequency locking enabled and USB traffic present.
23.94
24
24.06b
MHz
-10°C ≤ TA ≤ 85°C
FCPU1
CPU Frequency (5V Nominal)
0.93
24
24.96a,b
MHz
FCPU2
CPU Frequency (3.3V Nominal)
0.93
12
12.96b,c
MHz
FBLK5
Digital PSoC Block Frequency (5V Nominal)
0
48
49.92a,b,d
MHz
FBLK3
Digital PSoC Block Frequency (3.3V Nominal)
0
24
25.92
F32K1
Internal Low Speed Oscillator Frequency
15
32
64
Jitter32k
32 kHz Period Jitter
–
100
Step24M
24 MHz Trim Step Size
–
50
–
kHz
Fout48M
48 MHz Output Frequency
46.08
48.0
49.92a,c
MHz
Jitter24M1
24 MHz Period Jitter (IMO) Peak-to-Peak
–
300
FMAX
Maximum frequency of signal on row input or row output.
–
–
12.96
MHz
TRAMP
Supply Ramp Time
0
–
–
µs
a.
b.
c.
d.
b, d
Refer to the AC Digital Block Specifications.
MHz
kHz
ns
Trimmed. Utilizing factory trim values.
ps
4.75V < Vdd < 5.25V.
Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.
See the individual user module data sheets for information on maximum frequencies for user modules.
Jitter24M1
F 24M
Figure 3-2. 24 MHz Period Jitter (IMO) Timing Diagram
April 14, 2005
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CY8C24794 Final Data Sheet
3.4.2
3. Electrical Specifications
AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-17. AC GPIO Specifications
Symbol
FGPIO
Description
Min
Typ
Max
Units
Notes
GPIO Operating Frequency
0
–
12
MHz
Normal Strong Mode
TRiseF
Rise Time, Normal Strong Mode, Cload = 50 pF
3
–
18
ns
Vdd = 4.5 to 5.25V, 10% - 90%
TFallF
Fall Time, Normal Strong Mode, Cload = 50 pF
2
–
18
ns
Vdd = 4.5 to 5.25V, 10% - 90%
TRiseS
Rise Time, Slow Strong Mode, Cload = 50 pF
10
27
–
ns
Vdd = 3 to 5.25V, 10% - 90%
TFallS
Fall Time, Slow Strong Mode, Cload = 50 pF
10
22
–
ns
Vdd = 3 to 5.25V, 10% - 90%
90%
GPIO
Pin
O u tp u t
V o l ta g e
10%
TRi se F
TRi se S
TFallF
TFallS
Figure 3-3. GPIO Timing Diagram
3.4.3
AC Full-Speed USB Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -10°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -10°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-18. AC Full-Speed (12 Mbps) USB Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
TRFS
Transition Rise Time
4
–
20
ns
TFSS
Transition Fall Time
4
–
20
ns
For 50 pF load.
TRFMFS
Rise/Fall Time Matching: (TR/TF)
90
–
111
%
For 50 pF load.
12 - 0.25%
12
12 + 0.25% Mbps
TDRATEFS Full-Speed Data Rate
April 14, 2005
Document No. 38-12018 Rev. *F
For 50 pF load.
22
CY8C24794 Final Data Sheet
3.4.4
3. Electrical Specifications
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 3-19. 5V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Min
Typ
Max
Units
Notes
Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
–
–
3.9
µs
Power = Medium, Opamp Bias = High
–
–
0.72
µs
Power = High, Opamp Bias = High
–
–
0.62
µs
Power = Low, Opamp Bias = Low
–
–
5.9
µs
Power = Medium, Opamp Bias = High
–
–
0.92
µs
Power = High, Opamp Bias = High
–
–
0.72
µs
Power = Low, Opamp Bias = Low
0.15
–
–
V/µs
Power = Medium, Opamp Bias = High
1.7
–
–
V/µs
Power = High, Opamp Bias = High
6.5
–
–
V/µs
Power = Low, Opamp Bias = Low
0.01
–
–
V/µs
Power = Medium, Opamp Bias = High
0.5
–
–
V/µs
Power = High, Opamp Bias = High
4.0
–
–
V/µs
Power = Low, Opamp Bias = Low
0.75
–
–
MHz
Power = Medium, Opamp Bias = High
3.1
–
–
MHz
Power = High, Opamp Bias = High
5.4
–
–
MHz
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Gain Bandwidth Product
Table 3-20. 3.3V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Min
Typ
Max
Units
Notes
Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
–
–
3.92
µs
Power = Medium, Opamp Bias = High
–
–
0.72
µs
Power = Low, Opamp Bias = Low
–
–
5.41
µs
Power = Medium, Opamp Bias = High
–
–
0.72
µs
Power = Low, Opamp Bias = Low
0.31
–
–
V/µs
Power = Medium, Opamp Bias = High
2.7
–
–
V/µs
Power = Low, Opamp Bias = Low
0.24
–
–
V/µs
Power = Medium, Opamp Bias = High
1.8
–
–
V/µs
Power = Low, Opamp Bias = Low
0.67
–
–
MHz
Power = Medium, Opamp Bias = High
2.8
–
–
MHz
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Gain Bandwidth Product
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23
CY8C24794 Final Data Sheet
3. Electrical Specifications
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
Figure 3-4. Typical AGND Noise with P2[4] Bypass
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level.
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
0.01
0.1
Freq (kHz)
1
10
100
Figure 3-5. Typical Opamp Noise
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24
CY8C24794 Final Data Sheet
3.4.5
3. Electrical Specifications
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-21. AC Digital Block Specifications
Function
Timer
Counter
Dead Band
Description
Min
Typ
Max
Units
Capture Pulse Width
50a
–
–
ns
Maximum Frequency, No Capture
–
–
49.92
MHz
Maximum Frequency, With Capture
–
–
25.92
MHz
Enable Pulse Width
50a
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.92
MHz
Maximum Frequency, Enable Input
–
–
25.92
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50a
–
–
ns
a
–
–
ns
Notes
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
Kill Pulse Width:
Disable Mode
50
–
–
49.92
MHz
4.75V < Vdd < 5.25V.
CRCPRS
Maximum Input Clock Frequency
(PRS Mode)
Maximum Frequency
–
–
49.92
MHz
4.75V < Vdd < 5.25V.
CRCPRS
Maximum Input Clock Frequency
(CRC Mode)
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
SPIS
Maximum Input Clock Frequency
–
–
4.1
MHz
Width of SS_ Negated Between Transmissions
50a
–
–
ns
Transmitter
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
Receiver
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
Maximum data rate at 4.1 MHz due to 2 x over
clocking.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
3.4.6
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-22. AC External Clock Specifications
Symbol
FOSCEXT
Description
Frequency for USB Applications
Min
Typ
Max
23.94
24
24.06
Units
–
Duty Cycle
47
50
53
%
–
Power up to IMO Switch
150
–
–
µs
April 14, 2005
Document No. 38-12018 Rev. *F
Notes
MHz
25
CY8C24794 Final Data Sheet
3.4.7
3. Electrical Specifications
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-23. 5V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOBSS
BWOBLS
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
–
–
2.5
µs
Power = High
–
–
2.5
µs
Power = Low
–
–
2.2
µs
Power = High
–
–
2.2
µs
Power = Low
0.65
–
–
V/µs
Power = High
0.65
–
–
V/µs
Power = Low
0.65
–
–
V/µs
Power = High
0.65
–
–
V/µs
Power = Low
0.8
–
–
MHz
Power = High
0.8
–
–
MHz
Power = Low
300
–
–
kHz
Power = High
300
–
–
kHz
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Table 3-24. 3.3V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOBSS
BWOBLS
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
–
–
3.8
µs
Power = High
–
–
3.8
µs
Power = Low
–
–
2.6
µs
Power = High
–
–
2.6
µs
Power = Low
0.5
–
–
V/µs
Power = High
0.5
–
–
V/µs
Power = Low
0.5
–
–
V/µs
Power = High
0.5
–
–
V/µs
Power = Low
0.7
–
–
MHz
Power = High
0.7
–
–
MHz
Power = Low
200
–
–
kHz
Power = High
200
–
–
kHz
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
April 14, 2005
Document No. 38-12018 Rev. *F
26
CY8C24794 Final Data Sheet
3.4.8
3. Electrical Specifications
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-25. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
TRSCLK
Rise Time of SCLK
1
–
20
ns
TFSCLK
Fall Time of SCLK
1
–
20
ns
TSSCLK
Data Set up Time to Falling Edge of SCLK
40
–
–
ns
THSCLK
Data Hold Time from Falling Edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
TERASEB
Flash Erase Time (Block)
–
10
–
ms
TWRITE
Flash Block Write Time
–
30
–
ms
TDSCLK
Data Out Delay from Falling Edge of SCLK
–
–
45
ns
Vdd > 3.6
TDSCLK3
Data Out Delay from Falling Edge of SCLK
–
–
50
ns
3.0 ≤ Vdd ≤ 3.6
April 14, 2005
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27
CY8C24794 Final Data Sheet
3.4.9
3. Electrical Specifications
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-26. AC Characteristics of the I2C SDA and SCL Pins for Vdd
Standard Mode
Symbol
Description
Min
Fast Mode
Max
Min
Max
Units
FSCLI2C
SCL Clock Frequency
0
100
0
400
kHz
THDSTAI2C
Hold Time (repeated) START Condition. After this period,
the first clock pulse is generated.
4.0
–
0.6
–
µs
TLOWI2C
LOW Period of the SCL Clock
4.7
–
1.3
–
µs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
0.6
–
µs
TSUSTAI2C
Set-up Time for a Repeated START Condition
4.7
–
0.6
–
µs
THDDATI2C
Data Hold Time
0
–
0
–
µs
TSUDATI2C
Data Set-up Time
250
–
100
–
ns
TSUSTOI2C
Set-up Time for STOP Condition
4.0
–
0.6
–
µs
TBUFI2C
Bus Free Time Between a STOP and START Condition
4.7
–
1.3
–
µs
TSPI2C
Pulse Width of spikes are suppressed by the input filter.
–
–
0
50
ns
a
Notes
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if
the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Figure 3-6. Definition for Timing for Fast/Standard Mode on the I2C Bus
April 14, 2005
Document No. 38-12018 Rev. *F
28
4. Packaging Information
This chapter illustrates the package specification for the CY8C24794 PSoC device, along with the thermal impedance for the package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/support/link.cfm?mr=poddim.
4.1
Packaging Dimensions
Dimensions in MM[Inches]
51-85144 - *D
Figure 4-1. 56-Lead (8x8 mm) MLF
Important Note For information on the preferred dimensions for mounting MLF packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
April 14, 2005
Document No. 38-12018 Rev. *F
29
CY8C24794 Final Data Sheet
4.2
4. Packaging Information
Thermal Impedance
Table 4-1. Thermal Impedance for the Package
Package
Typical θJA *
56 MLF
20 oC/W
* TJ = TA + POWER x θJA
4.3
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 4-2. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature*
Maximum Peak Temperature
56 MLF
240oC
260oC
*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220+/-5oC
with Sn-Pb or 245+/-5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
April 14, 2005
Document No. 38-12018 Rev. *F
30
5. Ordering Information
The following table lists the CY8C24794 PSoC device’s key package features and ordering codes.
SRAM
(Bytes)
Temperature
Range
Digital Blocks
Analog Blocks
Digital IO Pins
Analog Inputs
Analog Outputs
XRES Pin
CY8C24794-24LFXI
16K
1K
-40C to +85C
4
6
50
48
2
No
56 Pin (8x8 mm) MLF
(Tape and Reel)
CY8C24794-24LFXIT
16K
1K
-40C to +85C
4
6
50
48
2
No
5.1
Ordering
Code
56 Pin (8x8 mm) MLF
Package
Flash
(Bytes)
Table 5-1. CY8C24794 PSoC Device Key Features and Ordering Information
Ordering Code Definitions
CY 8 C 24 xxx-SPxx
Package Type:
PX = PDIP Pb-Free
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
LFX = MLF Pb-Free
AX = TQFP Pb-Free
Thermal Rating:
C = Commercial
I = Industrial
E = Extended
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress MicroSystems
Company ID: CY = Cypress
April 14, 2005
Document No. 38-12018 Rev. *F
31
6. Sales and Company Information
To obtain information about Cypress Semiconductor or PSoC sales and technical support, reference the following information.
Cypress Semiconductor
2700 162nd Street SW, Building D
Lynnwood, WA 98037
Phone:
800.669.0557
Web Sites:
6.1
Facsimile:
425.787.4641
Company Information – http://www.cypress.com
Sales – http://www.cypress.com/aboutus/sales_locations.cfm
Technical Support – http://www.cypress.com/support/login.cfm
Revision History
Table 6-1. CY8C24794 Data Sheet Revision History
Document Title:
CY8C24794 PSoC Mixed-Signal Array Final Data Sheet
Document Number: 38-12018
ECN #
Issue Date
Origin of Change
**
Revision
133189
01.27.2004
NWJ
New silicon and new document – Advance Data Sheet.
*A
251672
See ECN
SFV
First Preliminary Data Sheet. Changed title to encompass only the CY8C24794 because the CY8C24494
and CY8C24694 are not being offered by Cypress MicroSystems.
*B
289742
See ECN
HMT
Add standard DS items from SFV memo. Add Analog Input Mux on pinouts. 2 MACs. Change 512 bytes of
SRAM to 1K. Add dimension key to package. Remove HAPI. Update diagrams, registers and specs.
*C
335236
See ECN
HMT
Add CY logo. Update CY copyright. Update new CY.com URLs. Re-add ISSP programming pinout notation.
Add Reflow Temp. table. Update features (MAC, Oscillator, and voltage range), registers (INT_CLR2/MSK2,
second MAC), and specs. (Rext, IMO, analog output buffer...).
*D
344318
See ECN
HMT
Add new color and logo. Expand analog arch. diagram. Fix IO #. Update Electrical Specifications.
*E
346774
See ECN
HMT
Add USB temperature specifications. Make data sheet Final.
*F
349566
See ECN
HMT
Distribution: External/Public
6.2
Description of Change
Remove USB logo. Add URL to preferred dimensions for mounting MLF packages.
Posting: None
Copyrights and Code Protection
Copyrights
© Cypress Semiconductor Corporation. 2004-2005. All rights reserved. PSoC™, PSoC Designer™, and Programmable System-on-Chip™ are PSoC-related trademarks
of Cypress Semiconductor Corporation. All other trademarks or registered trademarks referenced herein are property of the respective corporations.
The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other than circuitry
embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products
for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of
Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress
Semiconductor against all charges. Cypress Semiconductor products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety
applications, unless pursuant to an express written agreement with Cypress Semiconductor.
Flash Code Protection
Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices.
Cypress Semiconductor products meet the specifications contained in their particular Cypress Semiconductor Data Sheets. Cypress Semiconductor believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor
nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at
Cypress Semiconductor are committed to continuously improving the code protection features of our products.
April 14, 2005
© Cypress Semiconductor Corp. 2004-2005 — Document No. 38-12018 Rev. *F
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