Fairchild FAN5078D3 Complete acpi compliant power solution for ddr3 memory system Datasheet

FAN5078D3 — Complete ACPI Compliant Power Solution for
DDR3 Memory System
Features
Description
ƒ
PWM regulator for VDDQ
ƒ
Linear LDO regulator generates VTT = VDDQ/2,
1.5A peak sink/source capability
The FAN5078D3 DDR memory regulator combines a highefficiency Pulse-Width Modulated (PWM) controller to
generate the memory supply voltage, VDDQ, and a linear
regulator to generate termination voltage (VTT).
ƒ
AMT / M-state support
ƒ
Control to generate 5V USB
ƒ
ACPI drive and control for 5V DUAL generation
ƒ
3.3V internal LDO for 3V-ALW generation
ƒ
300kHz fixed-frequency switching
ƒ
RDS(ON) current sensing or optional current-sense resistor
for precision over-current detect
ƒ
Internal synchronous boot diode
ƒ
Common Power-Good signal for all voltages
ƒ
Input under-voltage lockout (UVLO)
ƒ
Thermal shutdown
ƒ
Latched multi-fault protection
ƒ
Precision reference output for ULDO controllers
ƒ
24-pin 5x5mm MLP package
FAN5078D3 can be configured to provide VDDQ and VTT
power requirements for DDR3 version. For power
requirements of DDR1 and DDR2 memory systems, refer to
FAN5078.
Synchronous rectification provides high efficiency over a
wide range of load currents. Efficiency is further enhanced
by using the low-side MOSFET’s RDS(ON) to sense current.
The VDDQ PWM regulator is a sampled, current-mode
control with external compensation to achieve fast loadtransient response and provide system design optimization.
The VTT regulator derives its reference and takes its
power from the VDDQ PWM regulator output. The VTT
termination regulator is capable of sourcing or sinking up to
1.5A peak currents.
In S5 M1 mode, the VDDQ switcher, VTT regulator, and the
3.3V regulators remain on. S3 mode keeps these regulators
on and turns on an external P-channel to provide 5V USB.
A single soft-start capacitor enables controlled slew rates for
both VDDQ and 3.3V-ALW outputs.
PGOOD becomes true in S0 only after all regulators have
achieved stable outputs.
Applications
ƒ DDR VDDQ and VTT voltage generation with ACPI
support for DDR3
In S5 (EN = 0), the 3.3V internal LDO stays on while the
other regulators are powered down.
Related Resources
ƒ
Memory Power Solutions for Desktop PCs
ƒ
Memory Power Solutions for Servers
Application Note AN-6005: Synchronous Buck MOSFET
Loss Calculations with Excel Model
Application Note AN-6006: FAN5068/FAN5078D3
Components Calculations and Simulation Tools
Ordering Information
Part Number
Temperature Range
Package
Packing
FAN5078D3MPX
-10°C to +85°C
24-Lead, 5x5mm, Molded Leadless Package (MLP)
Tape and Reel
All packages are lead free per JEDEC: J-STD-020B standard.
© 2008 Fairchild Semiconductor Corporation
FAN5078D3 • Rev. 1.0.0
www.fairchildsemi.com
FAN5078D3 — Complete ACPI Compliant Power Solution for DDR3 Memory System
February 2008
+5VSB
R4
+12V
+5MAIN
S3#O
Q4
C13
+5VSB
Q7
+5MAIN
5V USB
SBSW
Q6
SBUSB#
C14
C15
3.3 MAIN
S3#O
EN
Q5
S3#I
3.3 ALW
C12
PGOOD
S3#O
3
1
16
18
4
ACPI
CONTROL
&
LOGIC
2
8
+5VSB
SS
VCC
C4
9
13
11
21
PWM
14
12
P1
R5
ILIM
5V DUAL
S4ST#
23
20
22
7
VTT
LDO
24
5
6
L2
C5
BOOT
C2
Q1
10
C3
5V MAIN
17
15
Q3
CIN
HDRV
SW
L1
R3
ISNS
VDDQ
COUT
Q2
LDRV
R2
GND
R1
FB
C9
COMP
R6
C6
VDDQ IN
R9
REF IN
VTT SNS
VTT OUT
C8
R10
C7
Figure 1. Typical DDR/ACPI System Regulation Schematic
Components are selected for a 15A VDDQ output.
© 2008 Fairchild Semiconductor Corporation
FAN5078D3 • Rev. 1.0.0
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FAN5078D3 — Complete ACPI Compliant Power Solution for DDR3 Memory System
Block Diagrams
Ref.
Q1
Qty Description
NFET, VDS=25V, DPAK
VGS=10V, ID=35A, RDS(ON)=6.5mΩ (Typ)
ID=35A, RDS(ON)=9.1mΩ (Typ)
1
1
NFET, VDS=25V, DPAK
VGS=10V, ID=35A, RDS(ON)=6.5mΩ (Typ)
ID=35A, RDS(ON)=9.1mΩ (Typ)
Q2
Mfg. and Part Number
VGS=4.5V, Fairchild Semiconductor FDD8780
VGS=4.5V, Fairchild Semiconductor FDD8780
1
NFET, VDS=30V, DPAK
VGS=10V, ID=35A, RDS(ON)=7mΩ (Typ)
ID=35A, RDS(ON)=9mΩ (Typ)
Q4, Q6
2
PFET, 20V, 5.5A, 30mΩ, SSOT6
Fairchild Semiconductor FDC602P
Q5
1
NFET, 20V, 6.2A, 20mΩ, SSOT6
Fairchild Semiconductor FDC637AN
Q7
Fairchild Semiconductor FDD6612A
Q3
VGS=4.5V, Fairchild Semiconductor FDD8880
1
NFET, 30V, 30A, 22mΩ, DPAK
C12,C15
2
330µf, 10V, 20%, 110mΩ
C13
1
10nf, 50V, 10%, X7R
C14
1
3.3nf, 50V, 10%, X7R
C2
1
4.7µf, 25V, 20%, X5R
C4, C8
2
1.0µf, 10V, 10%, X5R
C3, C5
2
0.1µf, 16V, 10%, X7R
C6
1
4.7nf, 50V, 10%, X7R
C7
1
820µf, 6.3V, 20%, 36mΩ
C9
1
82pf, 50V, 5%, NPO
CIN
4
1200µf, 6.3V, 20%, 18mΩ
COUT
3
1200µf, 6.3V, 20%, 18mΩ
L1
1
IND, 1.8µH, 16A, 3.2mΩ
Inter-Technical SC5018-1R8M
L2
Inter-Technical SC2511-R47M
1
IND, 470nH, 16A, 2.6mΩ
R1,R2,R3,R9,R10
5
1.21K, 1%
R4
1
3.9K, 5%
R5
1
71.5K, 1%
R6
1
15.0K, 1%
Contact a Fairchild Semiconductor representative for complete reference design and / or evaluation board.
Bypass Capacitor Notes:
1. Input capacitor CIN is typically chosen based on the ripple current requirements. COUT is typically selected based on both
current ripple rating and ESR requirement (see AN-6006 for these calculations).
2. C7, C12, and C15 selection is largely determined by ESR and load transient response requirements. In each case, the
number of capacitors required depends on the capacitor technology chosen. Oscons can meet the requirements with less
space, but higher cost, than low-ESR electrolytics.
© 2008 Fairchild Semiconductor Corporation
FAN5078D3 • Rev. 1.0.0
3
www.fairchildsemi.com
FAN5078D3 — Complete ACPI Compliant Power Solution for DDR3 Memory System
Table 1. BOM for Figure 1
EN
D2
CBOOT
BOOT
VIN
POR/UVLO
Q1
S3#I
S3
HDRV
OVP
FB
Q
RAMP
OSC
CLK
COMP
S
VDDQ
SW
Q2
L OUT
VDD
COUT
LDRV
PWM
PGND
R
PWM
FB
ADAPTIVE
GATE
CONTROL LOGIC
S/H
RAMP
4.41K
ILIM det.
ISNS
RSENSE
ISNS
SS
CURRENT PROCESSING
PGOOD
VDDQ IN
Reference and
Soft Start
VREF
ILIM
RILIM
VDDQ
Figure 2. PWM Modulator Block Diagram
VDDQ IN
S3#I
R9
50K
REF IN
VDDQ IN
R10
50K
+
VTT SNS
EN
VTT OUT
–
110K
PGND
Figure 3. VTT Regulator Block Diagram
© 2008 Fairchild Semiconductor Corporation
FAN5078D3 • Rev. 1.0.0
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FAN5078D3 — Complete ACPI Compliant Power Solution for DDR3 Memory System
5VSB
VCC
24
23
22
21
20
19
EN
SBUSB#
S3#I
S4ST#
S3#O
SBSW
P1 = GND
5V MAIN
3.3 ALW
VTT SNS
VCC
VTT OUT
PGOOD
7
8
9
10
11
12
Figure 4. 5x5mm MLP Package (θJA = 38°C/W)
(Connect P1 pad to GND)
Pin Definitions
Pin #
Name
Description
1
SBUSB#
USB Standby. Pulls LOW with constant current to limit slew rate in S3 if S4ST# is HIGH. Drives a
P-channel MOSFET to connect 5V SB to 5V USB.
2
S4ST#
S4_STATE# Connect to system logic signal that enables 5V USB power in S3.
3
SBSW
Standby Switch. Drives the P-channel MOSFET to power 5V DUAL from 5V SB when in S3. HIGH in
S0 and S5.
4
5V MAIN
5V MAIN. When this pin is below 4.5V, transition from S3 to S0 is inhibited.
5
VTT SNS
VTT remote sense input.
6
VTT OUT
VTT regulator power output.
7
VDDQ IN
VDDQ Input from PWM. Connect to VDDQ output voltage. This is the VTT regulator power input.
8
BOOT
Boot. Positive supply for the upper MOSFET driver. Connect as shown in Figure 1. IC contains a boot
diode to VCC.
9
HDRV
High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side MOSFET.
10
SW
11
ISNS
Current Sense Input. Monitors the voltage drop across the lower MOSFET or external sense resistor
for current feedback and current limiting.
12
LDRV
Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side MOSFET.
13
PGOOD
Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect to
source of high-side MOSFET and low-side MOSFET drain.
Power Good Flag. An open-drain output that pulls LOW when FB is outside of a ±10% range of the
0.9V reference or the VTT output is < 80% or > 110% of its reference. PGOOD goes LOW when the IC
is in the S5 state. The power-good signal from the PWM regulator enables the VTT regulator.
© 2008 Fairchild Semiconductor Corporation
FAN5078D3 • Rev. 1.0.0
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FAN5078D3 — Complete ACPI Compliant Power Solution for DDR3 Memory System
Pin Configuration
Pin #
Name
Description
VCC. Provides IC bias and gate drive power. The IC is held in standby until this pin is above the UVLO
threshold.
14
VCC
15
3.3 ALW
16
S3#O
S3#O Output. Open-drain output that pulls the gate of the N-channel blocking MOSFETs LOW in S5
and S3. This pin goes HIGH (open) in S0.
17
S3#I
S3 Input. When LOW, turns off VTT and turns on the 3.3V regulator. Also causes S3#O to pull LOW to
turn off blocking switch Q3, as shown in Figure 1. PGOOD is LOW when S3#I is LOW.
18
EN
19,
P1
GND
GROUND for the IC is tied to this pin and is also connected to P1.
20
ILIM
Current Limit. A resistor from this pin to GND sets the current limit.
21
SS
Soft Start. A capacitor from this pin to GND programs the slew rate of the PWM and all LDOs during
initialization and transitions between states.
22
COMP
COMP. Output of the PWM error amplifier. Connect the compensation network between this pin and
FB.
23
FB
VDDQ Feedback. The feedback from PWM output. Used for regulation as well as PGOOD, undervoltage, and over-voltage protection and monitoring.
24
REF IN
VTT Reference. Input that provides the reference for the VTT regulator. A precision internal divider
from VDDQ IN (which can be overridden with external resistors) is provided.
3.3V LDO Output. Internal LDO output. Turned OFF in S0; ON in S5 or S3.
ENABLE. Typically tied to the system logic signal S5#. When this pin is LOW, the IC is in a low
quiescent current state, all regulators are OFF, and S3#O is LOW.
© 2008 Fairchild Semiconductor Corporation
FAN5078D3 • Rev. 1.0.0
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FAN5078D3 — Complete ACPI Compliant Power Solution for DDR3 Memory System
Pin Definitions (Continued)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable
above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,
extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute
maximum ratings are stress ratings only.
Parameter
Min.
Max.
Units
VCC
6.5
V
SW, ISNS, HDRV, S3#O
28
V
BOOT to SW
6.5
V
Continuous
-1
20
V
Transient (t < 100ns)
-5
20
V
All Other Pins
-0.3
Vcc+0.3
V
Junction Temperature (TJ)
-20
+150
°C
Storage Temperature
-65
+150
°C
+300
°C
SW, ISNS, HDRV to PGND
Lead Soldering Temperature, 10 Seconds
IVTT Peak (Duration < 2ms)
-1.5
+1.5
A
IVTT RMS
-1.0
+1.0
A
ESD Rating, Human Body Model
1500
V
ESD Rating, Charged Device Model
1600
V
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend
exceeding them or designing to absolute maximum ratings.
Parameter
Conditions
Supply Voltage VCC
Min.
Typ.
Max.
Units
4.5
5.0
5.5
V
1.25
A
+85
°C
I(3.3 ALW)
Ambient Temperature (TA )
© 2008 Fairchild Semiconductor Corporation
FAN5078D3 • Rev. 1.0.0
-10
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FAN5078D3 — Complete ACPI Compliant Power Solution for DDR3 Memory System
Absolute Maximum Ratings
Recommended operating conditions; component values per Figure 1, unless otherwise noted.
Parameter
Conditions
Min.
Typ.
Max.
Units
Power Supplies
S0
LDRV, HDRV Open, FB forced
above regulation point, I(VTT) = 0,
EN=1, S3#I=1
15
24
mA
S3
EN=1, S3#I = LOW, I(3.3) < 10mA
15
24
mA
VCC Current
S5
VCC UVLO Threshold
2
4
mA
Rising VCC
EN=0, I(3.3) = 0
4.0
4.2
4.4
V
Falling
3.9
4,1
4.3
V
Hysteresis
5V MAIN UVLO Threshold
0.15
4.3
4.4
4.6
V
Falling
3.9
4.1
4.2
V
Hysteresis
5V MAIN Input Resistance
V
Rising
to GND
0.30
V
35
62
KΩ
255
300
Oscillator
Frequency
Ramp Amplitude, pk–pk
(1)
Ramp Offset
345
KHz
1.8
V
0.5
V
Reference and Soft Start
Internal Reference Voltage at 25°C
0.891
0.900
0.882
Reference Temperature Coefficient
ILIM Reference Voltage
-2μA > IILIM > -18μA
Average Soft-Start Current (ISS)
SS Discharge Resistance
0.909
V
20
30
PPM/°C
0.900
0.918
V
Initial ramp after power-up
4.2
During PWM / LDO soft start
45
EN = 0
µA
150
Ω
SS Complete Threshold
1.5
V
SS Complete Hysteresis
50
mV
PWM Converter
Load Regulation
IOUT from 0 to 15A
FB Bias Current
Under-Voltage Shutdown
as % of set point, 2μs noise filter
Over-Voltage Threshold
-2
+2
%
-1.8
-1.3
-0.8
µA
65
75
80
%
as % of set point
110
115
120
%
ISNS Over-Current Threshold
RILIM= 56KΩ
-195
-170
-145
µA
VDDQ IN Discharge Resistance
EN = 0
55
Ω
COMP Source Current
VCOMP = 2.5V
650
VCOMP = 2.5V
100
µA
5.5
MHz
82
dB
COMP Sink Current
Error Amp GBW Product
Error Amp DC Gain
20
(1)
(1)
µA
Continued on the following page…
© 2008 Fairchild Semiconductor Corporation
FAN5078D3 • Rev. 1.0.0
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FAN5078D3 — Complete ACPI Compliant Power Solution for DDR3 Memory System
Electrical Specifications
Parameter
Conditions
Min.
Typ.
Max.
Units
Sourcing
1.8
3.0
Ω
Sinking
1.8
3.0
Ω
Sourcing
1.8
3.0
Ω
Sinking
1.2
2.0
Ω
PWM Output Driver
HDRV Output Resistance
LDRV Output Resistance
PGOOD output
Lower Threshold
as % of set point, 2μs noise filter
86
92
%
Upper Threshold
as % of set point, 2μs noise filter
108
115
%
PGOOD Output Low
IPGOOD = 1.5 mA
0.5
V
Leakage Current
VPULLUP = 5V
1
µA
3.3
3.4
V
35
70
mA
3.3V LDO
Regulation
I(3.3) from 0-1.25A, VCC > 4.75V
3.2
VTT Regulator
VDDQ IN Current
S0 mode, IVTT=0
VREF IN to VTT Differential Output
Voltage
IVTT = 0, TA=25°C
-20
20
IVTT = ± 1.25A (pulsed)
-40
40
VTT Current Limit
Pulsed (300ms maximum)
VTT Leakage Current
EN = LOW
VTT SNS Input Resistance
VTT SNS to GND
VTT PGOOD Threshold
Measured at VTT SNS
Drop-out Voltage
IVTT = ±1.5A
(1)
±1.5
±3.0
-20
±4.0
20
110
mV
A
µA
KΩ
80
110
% VTT
REF
-0.7
+0.7
V
V
Control Functions
EN, S4ST# Input Threshold
1.00
1.25
1.55
S3#I Input Threshold
1.3
1.5
1.7
V
S3#I, EN, S4ST# Input Current
-1
1
µA
Over-Temperature Shutdown
150
°C
Over-Temperature Hysteresis
25
°C
S3#O Output Low RDS(ON)
S3#O Output High Leakage
V(S3#O) = 12V
SBSW Pull-down Resistance
5V MAIN OK
SBSW Pull-up Resistance
SBUSB# Pull-down Resistance
5V MAIN OK
SBUSB# Pull-up Resistance
SBSW, SBUSB# Output Current
5V MAIN < UVLO
170
300
Ω
1
5
µA
150
200
Ω
900
1200
Ω
150
200
Ω
550
750
Ω
500
nA
Note:
1. Guaranteed by design and characterization; not tested in production.
© 2008 Fairchild Semiconductor Corporation
FAN5078D3 • Rev. 1.0.0
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FAN5078D3 — Complete ACPI Compliant Power Solution for DDR3 Memory System
Electrical Specifications (Continued)
Overview
The FAN5078D3 provides five functions:
1.
A general purpose PWM regulator, typically used to
generate VDDQ for DDR Memory.
2.
A low-dropout linear VTT regulator capable of sinking
and sourcing 1.5A peak.
3.
Control to generate 5V DUAL using an external Nchannel to supply power from 5V MAIN in S0 and an
external P-channel to provide power from 5V standby (5V
SB) in S3.
4.
Drive to generate 5V USB. This signal drives a PChannel MOSFET to connect 5V USB to +5V SB in S3.
5.
An internal LDO that regulates 3.3V-ALW in S3 mode
from VCC (5V SB). In S3 or S5, this regulator is capable
of 1.25A peak currents with average currents limited by
the thermal design of the PCB.
At initial power-up, or when transitioning from S5, the PWM
regulator is disabled until 5V MAIN is above the UVLO
threshold.
Table 2. ACPI States
STATE
S5
S5 M1
S3
S0
EN
3.3 ALW
(S5#) S3#I S4ST# SBSW SBUSB# S3#O VDDQ VTT
LDO
L
X
X
H
H
L
OFF OFF
ON
H
L
L
L
H
L
ON
ON
ON
H
L
H
L
L
L
ON
ON
ON
H
H
X
H
H
H
ON
ON
OFF
3.3 ALW
LDO
LDO
LDO
3.3V MAIN
5V Dual
OFF
+5VSB
+5VSB
+5 MAIN
5V USB
OFF
OFF
+5VSB
+5 MAIN
Regulator Sequencing
T4 to T5: After VDDQ is stabilized (when CSS is at about
~1.3V), an internal VDDQ OK is generated that allows the
VTT LDO to start. To ensure that the VDDQ output is not
subjected to large transient currents, the VTT slew rate is
limited by the slew rate of the SS cap. In addition, the VTT
regulator is current limited. VTT is in regulation once CSS
reaches about 3.8V.
The VCC pin provides power to all logic and analog control
functions of the regulator, including:
1.
2.
3.
4.
Power for the 3.3V regulator
LDRV gate driver current
HDRV boot diode charging current
The regulator analog control and logic.
This pin must be decoupled with a X5R ceramic capacitor
(1μF or larger recommended) as close as possible to the
VCC pin. After VCC is above UVLO, the start-up sequence
begins (see Figure 9).
S0 to S3 or S5 M1: The system signals this transition by
dropping the S3#I signal. When this occurs, S3#O goes
LOW, and the 3.3V LDO turns on. SBSW pulls low to turn
ON the P-channel 5V DUAL switch. SBUSB# pulls LOW to
turn on Q6 when S4ST# is HIGH.
UVLO on VCC discharges SS and resets the IC.
S3 or S5 M1 to S0: The system signals this transition by
raising the S3#I signal. S0 mode is not entered until 5V
MAIN OK, then the following occurs:
T0 to T3: After initial power-up, the IC ignores logic inputs
for a period (T3-T0) of approximately:
T3 - T0 ≈ 1.7 • CSS
(1)
where T3-T0 is in ms if CSS is in nF. At T2 (about 2/3 of the
way from T1 to T3), the 3.3V-ALW LDO is in regulation. The
3.3V LDO slew rate is limited by the discharge slope of CSS.
If 3.3V MAIN has come up prior to this time, the 3.3V-ALW
node is already pre-charged through the body diode of Q5
(see Figure 1).
S3#O releases.
ƒ
SBSW and SBUSB# both pull HIGH to turn off their
P-channel switches.
ƒ
The 3.3V LDO turns off.
In most systems, the ATX power supply is enabled when
S3#I goes HIGH. At that time, 5V and 3.3V MAIN starts to
rise. When the FAN5078D3’s 5V MAIN pin is above its
UVLO threshold, Q3 and Q5 turn on. This can cause about a
10% “dip” in both 5V DUAL and 3.3V ALW when Q3 and Q5
turn on, since at that point, 5V MAIN and 3.3V MAIN are at
90% of their regulation value.
T3 to T4: The IC starts VDDQ only if 5V MAIN is above the
UVLO threshold (5V MAIN OK). Provided 5V MAIN is up
before T3, the IC waits about 100μs before initiating softstart on VDDQ to allow CSS time to fully discharge. The IC
is in "SLEEP" or S5 state when EN is LOW. In S5, only the
3.3V LDO is ON. If the IC is in S5 at T4, CSS is held to 0V.
© 2008 Fairchild Semiconductor Corporation
FAN5078D3 • Rev. 1.0.0
ƒ
10
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FAN5078D3 — Complete ACPI Compliant Power Solution for DDR3 Memory System
Circuit Description
5V Dual "dip"
4.4V
5V MAIN
S3#O
S3#I
Figure 5. S3 to S0 Transition: 5V DUAL
This dip can also occur in 5V USB and 3.3V-ALW if 5V and
3.3V are not fully charged before the 5V MAIN pin exceeds
its threshold. To eliminate the dip, add delay to the 5V MAIN
pin, as shown below. The 5V MAIN pin does not supply
power to the IC; it is only used to monitor the voltage level of
the 5V MAIN supply. The pin has a pull-down resistor
impedance of about 62K and therefore requires a low value
RDLY resistor (see Figure 6 below).
3.3-ALW
3.3V LDO
I3.3 x ESRC12
ON
OFF
S3#O
(Q5 gate)
4.4V
5V MAIN
RDLY
+5MAIN
FROM
ATX
5V MAIN
4
CDLY
S3#I
Figure 8. 3.3V-ALW Transition to S0
Figure 6. Adding Delay to 5V MAIN
Another method of eliminating the potential for this dip is to
connect the ATX power supply PWR_OK signal to the 5V
MAIN pin. Some systems cannot tolerate the long delay for
PWR_OK (>100ms) to assert, so the solution in Figure 6
may be preferable.
S5 to S5 M1 or S3: During S5 to S3 transition, the IC pulls
SBSW (or SBUSB# if enabled by S4ST#) LOW with a 500nA
current sink to limit inrush in Q4 if 5V MAIN is below its
UVLO threshold. At that time, 5V DUAL and 5V USB are
discharged. The limited gate drives control the inrush current
through Q4 or Q6 as they charge their respective load
capacitances on 5V DUAL and 5V USB, respectively.
Depending on the CGD of Q4 and Q6, the current available
from 5V SB, and the size of CIN and C15, C13, and C14 may
be omitted.
If the PWR_OK signal is used, the voltage at the 5V MAIN
pin must reach the 5V MAIN threshold. Since the internal
pull-down resistance of the 5V MAIN pin is 62K, a low value
pull-up should be used. A lower current solution can also be
used by employing the 12V supply to provide adequate pullup capability. The circuit in Figure 7 requires that PWR_OK,
12V, and +5MAIN from the ATX are all up before allowing
the IC to go to S0.
10K
FROM ATX
+12V
5V MAIN
IQ 4(INRUSH) =
CIN • 5 X10 −7
C13 + C GD(Q 4 )
C15 • 5X10−7
IQ6(INRUSH) =
C14 + CGD(Q6)
4
(2)
If 5V MAIN is above its UVLO threshold, SBSW (or SBUSB# if
enabled by S4ST#) is pulled down with an impedance of
~150Ω. VDDQ and VTT do not start until 5V MAIN OK is true.
5VS B
PWR_OK
Figure 7. Using PWR_OK to Enable 5V MAIN
© 2008 Fairchild Semiconductor Corporation
FAN5078D3 • Rev. 1.0.0
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FAN5078D3 — Complete ACPI Compliant Power Solution for DDR3 Memory System
Care should also be taken to ensure that 3.3V-ALW does not
glitch during the transition to S0. As shown in Figure 8, the
3.3V internal regulator turns off as soon as 5V MAIN crosses
its rising threshold, releasing S3#O. While the gate
capacitances of Q5, Q7, and Q3 charge sufficiently to turn
Q5 ON, the load current on 3.3-ALW is supplied by C12.
There is an initial “ESR step” of I3.3 x ESRC12, where I3.3 is
the 3.3-ALW load current. This is followed by a discharge of
I
C12 whose slope is proportional to 3.3 . To ensure that the
C12
drop in 3.3-ALW during this transition does not cause system
problems, use sufficiently low-ESR capacitors and a
sufficiently low value for R4 to ensure that 3.3-ALW remains
inside the required system tolerance.
5V DUAL
5V SB
4V
3.8V
SS
1V
VDDQ
3.3V LDO
T0
T1
T2
T3 T4 T5
Figure 9. Start-up Sequence into S0
PWM Regulator
A PSPICE model and spreadsheet calculator are available
in Application Note AN-6006 for the VDDQ PWM regulator
to select external components and verify loop stability. The
topics covered below provide the explanation behind the
calculations in the spreadsheet.
Oscillator
Setting the Output Voltage
When the PWM regulator is enabled, the circuit waits until
the VDDQ IN pin is below 100mV to ensure that the softstart cycle does not begin with a large residual voltage on
the PWM regulator output.
The oscillator frequency is 300Khz. The internal PWM
ramp is reset on the rising clock edge.
PWM Soft Start
The output voltage of the PWM regulator can be set in the
range of 0.9V to 80% of its power input by an external
resistor divider.
When the PWM regulator is disabled, 40Ω is connected
from VDDQ IN to PGND to discharge the output. The
circuit waits until the FB pin is below 100mV to ensure that
the soft-start cycle does not begin with a large residual
voltage on the VDDQ regulator output.
The internal reference is 0.9V. The output is divided down
by an external voltage divider to the FB pin (for example,
R1 and R2 in Figure 1). There is also a 1.3μA current
sourced out of FB to ensure that if the pin is open, VDDQ
remains LOW. The output voltage therefore is:
The voltage at the positive input of the error amplifier is
limited to VCSS, which is charged with about 45μA. Once
CSS reaches 0.9V, the output voltage is in regulation.
0.9V VOUT − 0.9V
(3a)
=
+ 1.3 μA
R2
R1
To minimize noise pickup on this node, keep the resistor
to GND (R2) below 2K. In the example below, R2 is 1.82K
and R1 is calculated:
R1 =
R2 • (VOUT − 0.9)
=
0.9 − 1.3 μA
1.815K ≈ 1.82K
The time it takes SS to reach 0.9V and VDDQ to achieve
regulation is:
T0.9 ≈
(3b)
(4)
where T0.9 is in ms if CSS is in nF.
CSS charges another 400mV before the PWM regulator’s
fault latch is enabled. When CSS reaches 1.2V, the VTT
regulator begins its soft-start. After VTT is in regulation,
PGOOD is allowed to go HIGH (open).
The synchronous buck converter is optimized for 5V input
operation. The PWM modulator uses an average current
mode control for simplified feedback loop compensation.
© 2008 Fairchild Semiconductor Corporation
FAN5078D3 • Rev. 1.0.0
0.9 X C SS
45
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V(UVLO)
The following discussion refers to Figure 11.
The ILIM pin (pin 20) may be used as a precision 0.9V
reference for external ULDO controllers, as shown in
Figure 10. The ILIM pin is ON during all ACPI states.
The current through RSENSE resistor (ISNS) is sampled
shortly after Q2 is turned on. That current is held and
summed with the output of the error amplifier. This
effectively creates a current-mode control loop. RSENSE
sets the gain in the current feedback loop. For stable
operation, the voltage induced by the current feedback at
the PWM comparator input should be set to 30% of the
ramp amplitude at maximum load current and line voltage.
5VSB
Q1
R3
U1
C1
ILIM
R5
R1
VOUT
Equation 5 estimates the recommended value of RSENSE
as a function of the maximum load current (ILOAD(MAX)) and
the value of the MOSFET RDS(ON):
COUT
R2
20
Figure 10. Using ILIM as a ULDO Reference
R SENSE =
R5 in Figure 1 is the current limit setting resistor and
comprises the only DC current path from the ILIM pin to
GND. The circuit is configured so that the reference for the
ULDO is presented at the positive terminal of U1 and
draws negligible DC current. R3 and C1 filter noise that
might be induced if there is significant PCB trace length.
C1 should be placed as close as possible to the op-amp’s
input pin. R3 should be placed as close as possible to pin
20 of the FAN5078D3 and should be greater than 10K to
isolate the ILIM pin from noise.
ILOAD(MAX ) • R DS(ON) • 4.41K
30% • 0.125 • VIN(MAX)
− 100
(5)
where RDS(ON) is the maximum RDS(ON) of the low-side
MOSFET at its maximum temperature.
RSENSE must, however, be kept higher than:
ILOAD(MAX ) • R DS(ON)
R SENSE(MIN) =
145 μA
− 100
(6)
Recommended values for the circuit of Figure 10:
R3
R5
C1
50K
See AN-6006
1nF
Per desired VOUT:
R1, R2
R1 ⎞
⎛
VOUT = 0.9 • ⎜ 1 +
⎟
R
2⎠
⎝
S/H
COMP
FB
4.41K
V to I
in +
ISNS
SS/EN
Reference and
Soft Start
TO
PWM
COMP
LDRV
in –
PGND
2.5V
I2 =
ILIM*9.6
RSENSE
ISNS
CSS
ILIM det.
ISNS
0.9V
ILIM
RILIM
ILIM
mirror
Figure 11. Current Limit / Summing Circuits
© 2008 Fairchild Semiconductor Corporation
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FAN5078D3 — Complete ACPI Compliant Power Solution for DDR3 Memory System
Current Processing Section
Reference Output for ULDO Controllers
Gate Drive
ISNS is compared to the current established when a 0.9V
internal reference drives the ILIM pin. RILIM, the RDS(ON) of
Q2, and RSENSE determine the current limit:
The adaptive gate control logic translates the internal
PWM control signal into the MOSFET gate drive signals,
providing necessary amplification, level shifting, and
shoot-through protection. It also has functions to help
optimize the IC performance over a wide range of
operating conditions.
R ILIM =
(100 + R SENSE )
9.6
X
ILIMIT
R DS(ON)
(7)
where ILIMIT is the peak inductor current. Since the
tolerance on the current limit is largely dependent on the
ratio of the external resistors, it is fairly accurate if the
voltage drop on the switching node side of RSENSE is an
accurate representation of the load current. When using
the MOSFET as the sensing element, the variation of
RDS(ON) causes proportional variation in the ISNS. This value
not only varies from device to device, but also has a
typical junction temperature coefficient of about 0.4%/°C
(consult the MOSFET datasheet for actual values), so the
actual current limit set point decreases proportional to
increasing MOSFET die temperature. A factor of 1.6 in the
current limit set point should compensate for MOSFET
RDS(ON) variations, assuming the MOSFET heat sinking
keeps its operating die temperature below 125°C.
Since MOSFET switching time can vary dramatically from
type to type and with the input voltage, the gate control
logic provides adaptive dead time by monitoring the gateto-source voltages of both upper and lower MOSFETs.
The lower MOSFET drive is not turned on until the gate-tosource voltage of the upper MOSFET has decreased to
less than ~1V. Similarly, the upper MOSFET is not turned
on until the gate-to-source voltage of the lower MOSFET
has decreased to less than ~1V. This allows a wide variety
of upper and lower MOSFETs to be used without concern
for simultaneous conduction or shoot-through.
There must be a low-resistance, low-inductance path
between the driver pin and the MOSFET gate for the
adaptive dead-time circuit to work properly. Any delay
along that path subtracts from the delay generated by the
adaptive dead-time circuit and shoot-through may occur.
Current limit (ILIMIT) should be set sufficiently high as to
allow the inductor current to rise in response to an output
load transient. Typically, a factor of 1.3 is sufficient. In
addition, since ILIMIT is a peak current cut-off value, multiply
ILOAD(MAX) by the inductor ripple current (i.e. 20%). To
account all of these variations, set ILIMIT as:
ILIMIT > ILOAD(MAX) x 1.6 x 1.3 x 1.2
Frequency Loop Compensation
The loop is compensated using a feedback network
around the error amplifier.
(8)
COMP
C1
Q2
C2
RSENSE
VDDQ
R1
FB
R1
R4
PGND
R2
ISNS
VREF
R3
LDRV
C3
Figure 13. Compensation Network
Figure 12. Improving Current Sensing Accuracy
Figure 13 shows a complete Type-3 compensation
network. A Type-2 compensation configuration eliminates
R4 and C3 and is shown in Figure 1. Since the
FAN5078D3 architecture employs summing current mode,
Type-2 compensation can be used for most applications.
For critical applications that require wide loop bandwidth
and use very low ESR output capacitors, Type-3
compensation may be required. The PSPICE model and
spreadsheet calculator of AN-6006 can be used to
calculate these component values.
More accurate sensing can be achieved using a resistor
(R1) instead of the RDS(ON) of the FET, shown in Figure 12.
This approach causes higher losses, but greater accuracy.
Transient response during a rapid decrease in ILOAD can
be improved by adding a pull-down resistor (>5K) from the
COMP pin to GND.
© 2008 Fairchild Semiconductor Corporation
FAN5078D3 • Rev. 1.0.0
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FAN5078D3 — Complete ACPI Compliant Power Solution for DDR3 Memory System
Setting the Current Limit
OVP / HS Fault / FB Short to GND Detection
PGOOD monitors the status of the PWM output and VTT.
PGOOD remains LOW unless all these conditions are met:
A HS fault is detected when there is more than 0.5V from
SW to PGND 350ns after LDRV reaches 4V (same as the
current sampling time).
ƒ
SS is above 3.5V
ƒ
Fault latch is cleared
ƒ
FB is between 90% and 110% of VREF
ƒ
VTT is in regulation.
OVP fault detection occurs if FB>115% VREF for 16 clock cycles.
During soft-start, the output voltage could potentially "run
away" if either the FB pin is shorted to GND or R1 is open.
This fault is detected if the following condition persists for
more than 14μs during soft-start:
Protection
ƒ
VDDQ IN (PWM output voltage) > 1V
ƒ
FB < 100mV
The converter output is monitored and protected against
extreme overload, short-circuit, over-voltage, and undervoltage conditions.
Any of these faults sets the fault latch, even during the SS
time (SS < 1.2V).
An internal fault latch is set for any fault intended to shut
down the IC. When the fault latch is set, the IC discharges its
output by driving LDRV HIGH until VDDQ IN < 0.5V. LDRV
goes LOW until VDDQ IN > 0.8V. This discharges VDDQ
without causing undershoot (negative output voltage).
To ensure that FB pin open does not cause a destructive
condition, a 1.3μA current source ensures that the FB pin is
HIGH if open. This causes the regulator to keep the output
LOW and eventually results in an under-voltage fault
shutdown (after PWM SS completes).
To discharge the output capacitors, a 40Ω load resistor is
switched from VDDQ IN to PGND whenever the IC is in fault
condition or when EN is LOW. After a latched fault, operation
can be restored by recycling power or toggling the EN pin.
COMP
1.3μA
–
FB
+ E/A
Under-Voltage Shutdown
RAMP
+
4.41K
ISS
SS
If FB stays below the under-voltage threshold for 2μs, the
fault latch is set. This fault is prevented from setting the fault
latch during PWM soft-start (SS < 1.3V).
VREF
–
+ PWM
+
ISNS
Over-Current Sensing
Figure 15. SS Clamp and FB Open Protection
If the circuit’s current limit signal (ILIM det shown in Figure
11) is high at the beginning of a clock cycle, a pulse-skipping
circuit is activated and HDRV is inhibited. The circuit
continues to pulse skip in this manner for the next 8 clock
th
th
cycles. If, at any time from the 9 to the 16 clock cycle, the
ILIM det is again reached, the fault latch is set. If ILIM det
does not occur between cycle 9 and 16, normal operation is
restored and the over-current circuit resets itself.
Over-Temperature Protection
The chip incorporates an over-temperature protection circuit
that shuts the chip down when a die temperature of ~150°C
is reached. Normal operation is restored when the die
temperature falls below 125°C with internal Power On Reset
asserted, resulting in a full soft-start cycle. To accomplish this,
the over-temperature comparator discharges the SS pin.
This fault is prevented from setting the fault latch during softstart (SS < 1.3V).
VTT Regulator Section (see Figure 3)
The VTT regulator includes an internal resistor divider (50K
for each resistor) from the output of the PWM regulator. If
the REF IN pin is left open, the divider produces a voltage
50% of VDDQ IN. Using a low-impedance external precision
voltage divider produces greater accuracy.
The VTT regulator is enabled when S3#I is HIGH and the
PWM regulator’s internal PGOOD signal is true. The VTT
regulator also includes its own PGOOD signal, which is
HIGH when VTT SNS > 90% of REF IN.
Figure 14. Over-Current Protection Waveforms
© 2008 Fairchild Semiconductor Corporation
FAN5078D3 • Rev. 1.0.0
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FAN5078D3 — Complete ACPI Compliant Power Solution for DDR3 Memory System
PGOOD Signal
AN-6006 provides a PSPICE model and spreadsheet
calculator for the PWM regulator, simplifying external
component selections and verifying loop stability.
Power MOSFET Selection
For a complete analysis of MOSFET selection and efficiency
calculations, see Application Note AN-6005: Synchronous
Buck MOSFET Loss Calculations with Excel Model.
The spreadsheet calculator can be used to calculate external
component values for the FAN5078D3. The spreadsheet
calculates compensation components that can be verified in
the PSPICE model to ensure stability.
3.3V and VTT LDO Output Capacitors
The PSPICE model in AN-6006 simulates both loop stability
(Bode Plot) and transient analysis, and can be customized
for a wide variety of applications and external component
configurations.
For stability, use at least 100μF for 3.3V-ALW bypass
capacitor with a minimum ESR of 20mΩ.
The VTT output is typically bypassed with 820μF with at
least 30mΩ ESR.
As an initial step, define:
ƒ
Output voltage
ƒ
Maximum PWM output load current
ƒ
Maximum load transient current and maximum allowable
output drop during load transient
ƒ
RDS(ON) of the low-side MOSFET (Q2)
ƒ
Maximum allowable output ripple.
© 2008 Fairchild Semiconductor Corporation
FAN5078D3 • Rev. 2.0.0
16
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FAN5078D3 — Complete ACPI Compliant Power Solution for DDR3 Memory System
Design Tools
FAN5078D3 — Complete ACPI Compliant Power Solution for DDR3 Memory System
Physical Dimensions
Figure 15.
24-Lead, 5x5mm, Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most
recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty
therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2008 Fairchild Semiconductor Corporation
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FAN5078D3 — Complete ACPI Compliant Power Solution for DDR3 Memory System
© 2008 Fairchild Semiconductor Corporation
FAN5078D3 • Rev. 2.0.0
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