AKM AK4636EN 16-bit mono codec with alc & mic/spk/video-amp Datasheet

[AK4636]
AK4636
16-Bit Mono CODEC with ALC & MIC/SPK/Video-AMP
GENERAL DESCRIPTION
The AK4636 is a 16-bit mono CODEC with Microphone-Amplifier, Speaker-Amplifier and VideoAmplifier. Input circuits include a Microphone-Amplifier and an ALC (Automatic Level Control) circuit.
Output circuits include a Speaker-Amplifier and Mono Line Output. Video circuits include a LPF and
Video-Amplifier. The AK4636 suits a video recording/playback system of Digital Still Cameras. The
AK4636 is housed in a space-saving 29-pin CSP 2.5mm x 3.0mm package (AK4636ECB) or a 32pin QFN
4.0mm x 4.0mm package (AK4636EN).
1.
2.
3.
4.
5.
6.
7.
FEATURE
16-Bit Delta-Sigma Mono CODEC
Recording Function
• 1ch Mono Input
• MIC Amplifier: (0dB/+3dB/+6dB/+10dB/ +17dB/+20dB/+23dB/+26dB/+29dB/+32dB)
• Digital ALC (Automatic Level Control)
- Output Noise Suppression
- Setting Rate (+36dB ∼ -54dB, 0.375dB Step, Mute)
• ADC Performance (MIC-Amp=+20dB)
- S/(N+D): 83dB
- DR, S/N: 85dB
• Wind-noise Reduction Filter
• 5 band notch Filter
• Digital Microphone Interface
Playback Function
• Digital ALC (Automatic Level Control)
- Output Noise Suppression
- Setting Rate (+36dB ∼ -54dB, 0.375dB Step, Mute)
• Mono Line Output:
- S/(N+D): 84dB
- S/N: 90dB
• Mono Speaker-Amp
- S/(N+D): 60dB (150mW@8Ω)
- BTL Output
- Output Power: 400mW @ 8Ω (SVDD=3.3V)
• Beep Generator
Video Function
• A Composite Video Input
• Gain Control (-1.0dB ∼ +10.5dB, 0.5dB Step)
• Low Pass Filter
• A Video-Amp for Composite Video Signal
• DC Direct Output
Power Management
PLL Mode:
• Frequencies:
11.2896MHz, 12MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin)
1fs (FCK pin)
16fs, 32fs or 64fs (BICK pin)
EXT Mode:
MS1012-E-01
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[AK4636]
• Frequencies: 256fs, 512fs or 1024fs (MCKI pin)
8. Sampling Rate:
• PLL Slave Mode (FCK pin): 7.35kHz ~ 48kHz
• PLL Slave Mode (BICK pin): 7.35kHz ~ 48kHz
• PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• EXT Slave Mode / EXT Master Mode:
7.35kHz ~ 48kHz (256fs), 7.35kHz ~ 26kHz (512fs), 7.35kHz ~ 13kHz (1024fs)
9. Output Master Clock Frequency: 256fs
10. Serial μP Interface: 3-wire, I2C Bus (Ver 1.0, 400kHz High Speed Mode)
11. Master / Slave Mode
12. Audio Interface Format: MSB First, 2’s complement
• ADC: DSP Mode, 16bit MSB justified, I2S
• DAC: DSP Mode, 16bit MSB justified, 16bit LSB justified, I2S
13. Ta = - 30 ∼ 85°C
14. Power Supply
• Analog Supply (AVDD): 2.6 ∼ 3.6V
• Digital Supply (DVDD): 1.6 ∼ 3.6V
• Speaker Supply (SVDD): 2.6 ∼ 3.6V
• Video Supply (VVDD): 2.8 ∼ 3.6V
15. Package: AK4636ECB Æ29pin CSP (2.5mm x 3.0mm, 0.5mm pitch)
AK4636EN Æ32pin QFN (4.0mm x 4.0mm, 0.4mm pitch)
■ Block Diagram
AVDD
VSS1
VCOM
DVDD
VSS2
PMMP
MPI/DMP
PDN
MIC Power
Supply
I2C
Mic
PMADC or PMDM
A/D
MIC/MICP/DMDAT
HPF1
MIC-Amp
0dB / +3dB/+6dB/+10dB/+17dB/+20dB/
+23dB/+26dB / +29dB / +32dB
LIN/MICN/DMCLK
PMPFIL
HPF2
BICK
LPF
Audio
I/F
PMAO
Line Out
4 Band
EQ
AOUT
PMSPK
SDTO
SDTI
VOL
(ALC)
SVDD
FCK
EQ
SPP
Speaker
SPN
SPK-amp
PMDAC
MCKO
D/A
SMUTE D ATT
PMPLL
PMBP
PLL
VSS3
MCKI
VCOC
BEEP
Generator
VVDD
PMV
Composite
Video Out
VOUT
GCA
+6dB
-1dB ~ +10.5dB
Step 0.5dB
CSN/SDA
LPF
Control
Register
CLAMP
CCLK/SCL
CDTIO
BEEP
VIN
Figure 1. AK4636 Block Diagram
MS1012-E-01
2010/08
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[AK4636]
■ Ordering Guide
−30 ∼ +85°C
−30 ∼ +85°C
AK4636ECB
AK4636EN
AKD4636
29pin CSP (2.5mmx3.0mm 0.5mm pitch)
32pin QFN (4.0mmx4.0mm 0.4mm pitch)
AK4636ECB Evaluation Board
■ Pin Layout
AK4636ECB
6
5
4
Top View
3
2
1
A
B
C
D
E
6
PDN
DVDD
VSS2
SPP
SVDD
5
SDTO
MCKO
SDTI
VSS3
SPN
4
BICK
MCKI
FCK
AOUT
BEEP
3
CCLK/SCL
CDTIO
I2C
2
CSN/SDA
VOUT
VVDD
VCOM
MPI/DMP
1
VIN
VSS1
AVDD
VCOC
C
D
E
A
B
MIC/MICP/ LIN/MICN/
DMDAT
DMCLK
Top View
MS1012-E-01
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[AK4636]
SPN
SVDD
SPP
NC
VSS2
DVDD
MCKO
PDN
24
23
22
21
20
19
18
17
AK4636EN
NC
25
16
SDTO
NC
26
15
SDTI
VSS3
27
14
BICK
BEEP
28
AK4636EN
13
MCKI
AOUT
29
Top View
12
FCK
6
7
8
VOUT
VIN
I2C
CSN/ SDA
5
9
VVDD
32
MPI/ DMP
4
CDTIO
VSS1
10
3
31
AVDD
MIC/ MICP/ DMDAT
2
CCLK/ SCL
VCOC
11
1
30
VCOM
LIN/ MICN/ DMCLK
MS1012-E-01
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[AK4636]
PIN/FUNCTION
AK4636ECB
No. Pin Name
I/O
D2
VCOM
O
E1
VCOC
O
D1
C1
C2
B2
A1
C3
AVDD
VSS1
VVDD
VOUT
VIN
I2C
CSN
SDA
O
I
I
I
I/O
CDTIO
I/O
C4
B4
A4
C5
A5
CCLK
SCL
FCK
MCKI
BICK
SDTI
SDTO
I
I
I/O
I
I/O
I
O
A6
PDN
I
B5
B6
C6
D6
E6
E5
E4
D5
D4
MCKO
DVDD
VSS2
SPP
SVDD
SPN
BEEP
VSS3
AOUT
LIN
O
O
O
I
O
I
E3
MICN
I
DMCLK
MIC
I
I
MICP
I
DMDAT
MPI
DMP
O
O
O
A2
B3
A3
D3
E2
Function
Common Voltage Output Pin = 1.15V(typ)
Bias voltage of ADC inputs and DAC outputs.
Output Pin for Loop Filter of PLL Circuit
This pin must be connected to VSS1 with one resistor and capacitor in series.
Analog Power Supply Pin
Ground Pin
Video Amp Power Supply Pin
Composite Video Signal Driver Pin
Composite Video Signal Input Pin
Control Mode Select Pin “H”: I2C Bus, “L”: 3-wire Serial
Chip Select Pin
(I2C pin = “L”)
Control Data Input/Output Pin
(I2C pin = “H”)
Control Data Input/Output Pin
(I2C pin = “L”)
This pin must be connected to the ground. (I2C pin = “H”)
Control Data Clock Pin
(I2C pin = “L”)
Control Data Clock Pin
(I2C pin = “H”)
Frame Clock Pin
External Master Clock Input Pin
Audio Serial Data Clock Pin
Audio Serial Data Input Pin
Audio Serial Data Output Pin
Power-down & Reset
When “L”, the AK4636 is in power-down mode and is held in reset.
The AK4636 must be always reset upon power-up.
Master Clock Output Pin
Digital Power Supply Pin
Ground Pin.
Speaker Amp Positive Output Pin
Speaker Amp Power Supply Pin
Speaker Amp Negative Output Pin
Beep Signal Input Pin
Ground Pin
Mono Line Output Pin
Line Input Pin for Single Ended Input
(MDIF bit = “0”, DMIC bit = “0”)
Microphone Negative Input Pin for Differential Input
(MDIF bit = “1”, DMIC bit = “0”)
Digital Microphon Clock pin
(DMIC bit = “1”)
Microphone Input Pin for Single Ended Input (MDIF bit = “0”,DMIC bit = “0”)
Microphone Positive Input Pin for Differential Input
(MDIF bit = “1” DMIC bit = “0”)
Digital Microphone Data Input pin
(DMIC bit = “1”)
MIC Power Supply Pin for Microphone
(DMPE bit = “0”)
MIC Power Supply pin for Digital Microphone (DMPE bit = “1”)
MS1012-E-01
2010/08
-5-
[AK4636]
AK4636EN
No. Pin Name
I/O
1
VCOM
O
2
VCOC
O
3
4
5
6
7
8
AVDD
VSS1
VVDD
VOUT
VIN
I2C
CSN
SDA
O
I
I
I
I/O
CDTIO
I/O
12
13
14
15
16
CCLK
SCL
FCK
MCKI
BICK
SDTI
SDTO
I
I
I/O
I
I/O
I
O
17
PDN
I
18
19
20
21
22
23
24
25
26
27
28
29
MCKO
DVDD
VSS2
NC
SPP
SVDD
SPN
NC
NC
VSS3
BEEP
AOUT
LIN
O
O
O
I
O
I
30
MICN
I
DMCLK
MIC
O
I
MICP
I
DMDAT
MPI
DMP
I
O
O
9
10
11
31
32
Function
Common Voltage Output Pin = 1.15V(typ)
Bias voltage of ADC inputs and DAC outputs.
Output Pin for Loop Filter of PLL Circuit
This pin must be connected to VSS1 with one resistor and capacitor in series.
Analog Power Supply Pin
Ground Pin
Video Amp Power Supply Pin
Composite Video Signal Driver Pin
Composite Video Signal Input Pin
Control Mode Select Pin “H”: I2C Bus, “L”: 3-wire Serial
Chip Select Pin
(I2C pin = “L”)
Control Data Input/Output Pin
(I2C pin = “H”)
Control Data Input/Output Pin
(I2C pin = “L”)
This pin must be connected to the ground. (I2C pin = “H”)
Control Data Clock Pin
(I2C pin = “L”)
Control Data Clock Pin
(I2C pin = “H”)
Frame Clock Pin
External Master Clock Input Pin
Audio Serial Data Clock Pin
Audio Serial Data Input Pin
Audio Serial Data Output Pin
Power-down & Reset
When “L”, the AK4636EN is in power-down mode and is held in reset.
The AK4636EN must always be reset upon power-up.
Master Clock Output Pin
Digital Power Supply Pin
Ground Pin.
No Connection. No internal bonding. This pin must be connected to the ground.
Speaker Amp Positive Output Pin
Speaker Amp Power Supply Pin
Speaker Amp Negative Output Pin
No Connection. No internal bonding. This pin must be connected to the ground.
No Connection. No internal bonding. This pin must be connected to the ground.
Ground Pin
Beep Signal Input Pin
Mono Line Output Pin
Line Input Pin for Single Ended Input
(MDIF bit = “0”, DMIC bit = “0”)
Microphone Negative Input Pin for Differential Input
(MDIF bit = “1”, DMIC bit = “0”)
Digital Microphone Clock pin
(DMIC bit = “1”)
Microphone Input Pin for Single Ended Input (MDIF bit = “0”,DMIC bit = “0”)
Microphone Positive Input Pin for Differential Input
(MDIF bit = “1” DMIC bit = “0”)
Digital Microphon Data Input pin
(DMIC bit = “1”)
MIC Power Supply Pin for Microphone
(DMPE bit = “0”)
MIC Power Supply pin for Digital Microphone (DMPE bit = “1”)
Note: All input pins except analog input pins (MIC/MICP/DMDAT, LIN/MICN/DMCLK, VIN, BEEP pins) must not be
left floating.
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[AK4636]
■ Handling of Unused Pin
The unused I/O pins must be processed appropriately as below.
Classification
Analog
Digital
Pin Name
MIC/MICP, LIN/MICN, MPI, AOUT,
SPP, SPN, VCOC, VIN, VOUT
MCKI, SDTI
Setting
These pins must be open.
These pins must be connected to VSS2.
When I2C pin = “H”, These pins should be
connected to VSS2.
These pins must be open.
CDTIO
MCKO, SDTO
ABSOLUTE MAXIMUM RATINGS
(VSS=VSS2=VSS3=0V; Note 1)
Parameter
Symbol
min
−0.3
AVDD
Analog
Power Supplies:
−0.3
DVDD
Digital
−0.3
SVDD
Speaker-Amp
−0.3
VVDD
Video-Amp
Input Current, Any Pin Except Supplies
IIN
Analog Input Voltage (Note 2)
VINA
−0.3
Digital Input Voltage (Note 3)
VIND
−0.3
Video-amp Input Voltage (Note 4)
VINV
−0.3
Ambient Temperature (powered applied)
Ta
−30
Storage Temperature
Tstg
−65
Maximum Power Dissipation (Note 5)
Pd
-
max
4.6
4.6
4.6
4.6
±10
AVDD+0.3
DVDD+0.3
VVDD+0.3
85
150
450
Units
V
V
V
V
mA
V
V
V
°C
°C
mW
Note 1. All voltages with respect to ground. VSS21, VSS2 and VSS3 must be connected to the same analog ground plane.
Note 2. LIN/MICN/DMCLK, MIC/MICP/DMDAT, BEEP pins
Note 3. PDN, I2C, CSN/SDA, CCLK/SCL, CDTIO, SDTI, FCK, BICK, MCKI pins
Pull-up resistors at SDA and SCL pins should be connected to (DVDD+0.3)V or less voltage.
Note 4. VIN pin
Note 5. AK4636ECB: When PCB wiring density is more than 200% and superficial layer writing density is more than
50%. AK4636EN: When PCB wiring density is more than 100%.
This power is the AK4636 internal dissipation that does not include power of externally connected speakers.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
MS1012-E-01
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[AK4636]
RECOMMENDED OPERATING CONDITIONS
(VSS=VSS2=VSS3=0V; Note 1)
Parameter
Symbol
min
typ
3.3
2.6
AVDD
Analog
Power Supplies
3.3
1.6
DVDD
Digital
(Note 6)
3.3
2.6
SVDD
Speaker-Amp
3.3
2.8
VVDD
Video-Amp
max
3.6
3.6
3.6
3.6
Units
V
V
V
V
Note 1. All voltages with respect to ground.
Note 6. The power up sequence between AVDD, DVDD, SVDD and VVDD is not critical. The internal circuit is invalid
when power up the AK4636 at the PDN pin = “H”. Set the PDN pin to “L” to reset the internal circuit after
power up. To avoid an internal circuit error, the PDN pin must be “L” upon power up, and changed to “H” after
all power supplies are supplied. The AK4636 can not be partially powered-off, all powers must be ON.
(Power-off state is identified as when the power supplies are floating or short to ground.) When connecting the
AK4636 to the I2C bus, do not turn the AK4636 off unless other external devices are off.
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS1012-E-01
2010/08
-8-
[AK4636]
ANALOG CHRACTERISTICS
(Ta=25°C; AVDD=DVDD=SVDD = 3.3V, VVDD = 3.3V, VSS1=VSS2=VSS3 = 0V; fs = 8kHz; LP bit = “1”
BICK = 64fs; Signal Frequency = 1kHz; 16bit Data; Measurement frequency = 20Hz ∼ 3.4kHz; EXT Slave Mode; unless
otherwise specified)
Parameter
min
typ
max
Units
MIC Amplifier: MIC, LIN pins ; MDIF bit = “0”; (Single-ended input)
Input Resistance
20
30
40
kΩ
Gain
(MGAIN3-0 bits = “0000”)
0
dB
(MGAIN3-0 bits = “0001”)
19
20
21
dB
(MGAIN3-0 bits = “0010”)
25
26
27
dB
(MGAIN3-0 bits = “0011”)
31
32
33
dB
(MGAIN3-0 bits = “0100”)
9
10
11
dB
(MGAIN3-0 bits = “0101”)
16
17
18
dB
(MGAIN3-0 bits = “0110”)
22
23
24
dB
(MGAIN3-0 bits = “0111”)
28
29
30
dB
(MGAIN3-0 bits = “1000”)
2
3
4
dB
(MGAIN3-0 bits = “1001”)
5
6
7
dB
MIC Amplifier: MICP, MICN pins ; MDIF bit = “1”; (Full-differential input)
0.173
Input Voltage
(MGAIN3-0 bits = “0001”)
0.128
0.150
Vpp
(Note 7)
(MGAIN3-0 bits = “0010”)
0.064
0.075
0.086
Vpp
(MGAIN3-0 bits = “0011”)
0.032
0.038
0.044
Vpp
(MGAIN3-0 bits = “0100”)
0.403
0.474
0.545
Vpp
(MGAIN3-0 bits = “0101”)
0.180
0.212
0.244
Vpp
(MGAIN3-0 bits = “0110”)
0.090
0.106
0.122
Vpp
(MGAIN3-0 bits = “0111”)
0.045
0.053
0.061
Vpp
(MGAIN3-0 bits = “1001”)
0.639
0.752
0.864
Vpp
MIC Power Supply: MPI pin
Output Voltage
2.1
2.3
2.5
V
Load Resistance
2
kΩ
Load Capacitance
30
pF
ADC Analog Input Characteristics: MIC/LIN Æ ADC, MIC Gain = +20dB, IVOL = 0dB, ALC1bit = “0”
Resolution
16
Bits
Input Voltage (MIC Gain=20dB)
0.128
0.150
0.173
Vpp
73
83
dB
S/(N+D)
(−1dBFS) (Note 8)
74
85
dB
D-Range
(−60dBFS)
S/N
74
85
dB
ADC Analog Input Characteristics: MIC/LIN Æ ADC, MIC Gain = 0dB, IVOL = 0dB, ALC1bit = “0”
Resolution
16
Bits
Input Voltage (MIC Gain=0dB)
1.28
1.50
1.73
Vpp
73
83
dB
S/(N+D)
(−1dBFS) (Note 8)
78
89
dB
D-Range
(−60dBFS)
S/N
78
89
dB
DAC Characteristics:
Resolution
16
Bits
Mono Line Output Characteristics: AOUT pin, DAC → AOUT, RL = 10kΩ, LOVL bit = “0”
1.28
1.50
1.73
Vpp
Output Voltage
LOVL bit = “0”
2.12
Vpp
LOVL bit = “1”(Note 9)
74
84
dB
S/(N+D)
(0dBFS) (Note 8)
80
90
dB
D-Range
(−60dBFS)
80
90
dB
S/N
10
Load Resistance
kΩ
30
pF
Load Capacitance
MS1012-E-01
2010/08
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[AK4636]
Parameter
min
typ
max
Speaker-Amp Characteristics: DAC Æ SPP/SPN pins, ALC2 bit = “0”, RL=8Ω, BTL, SVDD=3.3V
Output Voltage SPKG1-0 bits = “00” (-4.1dBFS)
2.54
3.17
3.80
(Note 10)
SPKG1-0 bits = “01” (-4.1dBFS)
3.20
4.00
4.80
When output 150mW
40
60
S/(N+D)
When output 400mW
20
-84
SPKG1-0 bits = “00”
Output Noise
-82
-72
SPKG1-0 bits = “01”
Level
-80
SPKG1-0 bits = “10”
Load Resistance
8
30
Load Capacitance
BEEP Input: BEEP pin, Internal Resistance mode (BPM1-0 bits = “01”)
Input Resistance
23
33
43
Maximum Input Voltage
1.50
Output Voltage (Input Voltage=0.5Vpp)
BEEP Æ SPP/SPN (BPLVL 2-0 bits = 0H)
1.35
1.69
2.03
(SPKG1-0 bits = “00”)
BEEP Æ AOUT
(BPLVL 2-0 bits = 0H)
0.40
0.50
0.60
(LOVL bit = “0”)
BEEP Input: BEEP pin, External Resistance mode (BPM1-0 bits = “10”) Input Resistance= 33kΩ
Maximum Input Voltage (Note 11)
1.50
Output Voltage (Input Voltage=0.5Vpp)
BEEP Æ SPP/SPN (BPLVL 2-0 bits = 0H)
1.69
(SPKG1-0 bits = “00”)
BEEP Æ AOUT
(BPLVL 2-0 bits = 0H)
0.50
(LOVL bit = “0”)
Video Signal Input:
Maximum Input Voltage (Note 12), (GCA = 0dB)
1.2
Pull Down Current
1
Video Signal Output:
Output Gain (Note 13)
5.3
6.0
6.7
VIN=100kHz (GCA = 0dB)
Maximum Output Voltage (Note 13)
2.4
Output Clamp Voltage (Note 13)
50
100
S/N (Note 13)
66
100kH ∼ 6MHz (GCA = 0dB)
Secondary harmonic distortion (Note 13, Note 14)
−42
VIN = 3.58MHz, 0.2Vpp (GCA = 0dB, Sin Wave)
Load Resistance
140
150
15
CL1 (Figure 3)
Load Capacitance
400
CL2 (Figure 3)
LPF: (Note 13, Note 14)
Frequency Response
-3.0
Response at 6.75MHz
−0.5
Input=0.2Vpp, Sin Wave
Response at 27MHz
−40
−20
(0dB at 100kHz)
Frequency Responce
Response at 6.75MHz
−0.5
Input=0.2Vpp, Sin Wave
Response at 27MHz
−40
(+6dB at 100kHz)
Group Delay
10
100
|GD3MHz−GD6MHz|
GCA Characteristics:
Step Width
0.1
0.5
0.9
GCA = −1.0dB ∼ +10.5dB
Units
MS1012-E-01
2010/08
- 10 -
Vpp
Vpp
dB
dB
dBV
dBV
dBV
Ω
pF
kΩ
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
μA
dB
Vpp
mV
dB
dB
Ω
pF
pF
dB
dB
dB
dB
ns
dB
[AK4636]
Parameter
min
typ
Power Supplies
Power Up (PDN = “H”)
All Circuit Power-up: (Note 15)
AVDD+DVDD
fs=8kHz (LP bit = “1”)
7
(Note 17)
fs=48kHz(LP bit = “0”)
11
(Note 17)
SVDD: Speaker-Amp Normal Operation (SPPSN bit = “1”, No Output)
4
VVDD (Note 16)
8
Power Down (PDN = “L”) (Note 18)
1
AVDD+DVDD+SVDD+VVDD
max
Units
-
mA
17
mA
12
mA
12
mA
5
μA
Note 7. The voltage difference between MICP and MICN pins. AC coupling capacitor should be inserted in series at each
input pin. Full-differential microphone input is not available at MGAIN3-0 bits = “1000” or “0000”. If the input
signal over those maximum voltages are input, the ADC does not operate properly.
Note 8. When a PLL reference clock is input to the FCK pin in PLL Slave Mode, S/ (N+D) of MICÆADC is 75dB (typ),
S/ (N+D) of DACÆAOUT is75dB (typ).
Note 9. When LOVL bit = “1”, large-amplitude output may have clip noise.
Note 10. When SPGK1-0 bits = “01” or “10”, large-amplitude output may have clip noise if the SVDD is low.
Note 11. The maximum input voltage is inversely proportional to the external input resistance (Rin). Vout = Vin ×
Rin/33kΩ(max). The volume can not be changed by BPLVL 7-0 bits in “BEEP pin External Input Resistance
Mode” (BPM1-0 bits = “10”). BPLVL 7-0 bits should be fixed “00H” to change the gain by the external
resistance (Rin).
Note 12. Input Voltage does not depend on VVDD voltage.
Note 13. Measurement point is A of Figure 2.
Note 14. This is the value when the lowest input signal level is more than -20IRE.
Note 15. When PLL Master Mode (MCKI=12MHz), and PMV = PMMP = PMADC = PMDAC = PMPFIL = PMSPK =
PMVCM = PMPLL = MCKO = PMAO = M/S = “1”. The MPI pin outputs 0mA. In EXT mode, when PMPLL=
MCKO= M/S= “0” and LP= “0”, AVDD+ DVDD= 6mA (fs=8kHz, typ) or 9mA (fs=48kHz, typ), when LP=
“1”, AVDD+DVDD = 5mA (fs=8kHz, typ).
Note 16. When Black signal is input to the VIN pin, and the VOUT pin has no load resistance. If the resistance is 150Ω,
it is 12.5mA(typ).
Note 17. Set LP bit = “1” when sampling frequency ≤ 22.05kHz, set LP bit = “0” when > 22.05kHz.
Note 18. All digital input pins are fixed to DVDD or VSS2.
Measuring point A
VIN
75Ω
CLAMP
LPF
GCA
-1dB ~ +10.5dB
Step 0.5dB
+6dB
VOUT
75Ω
Figure 2. Measurement Point
MS1012-E-01
2010/08
- 11 -
[AK4636]
R1
75Ω
VIN
CLAMP
LPF
GCA
-1dB ~ +10.5dB
Step 0.5dB
+6dB
VOUT
R2
75Ω
CL 1
CL 2
Figure 3. Load Capacitance CL1 and C L2
FILTER CHRACTERISTICS
(Ta = −30 ~ 85°C; AVDD = 2.6 ∼ 3.6V, DVDD = 1.6 ∼ 3.6V, SVDD = 2.6 ∼ 3.6V, VVDD = 2.8 ∼ 3.6V; fs = 8kHz)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
Passband
(Note 19) ±0.16dB
PB
0
3.0
kHz
−0.66dB
3.5
kHz
−1.1dB
3.6
kHz
−6.9dB
4.0
kHz
Stopband
(Note 19)
SB
4.7
kHz
Passband Ripple
PR
±0.1
dB
Stopband Attenuation
SA
73
dB
Group Delay
(Note 20)
GD
16
1/fs
Group Delay Distortion
ΔGD
0
μs
DAC Digital Filter (Decimation LPF):
Passband
(Note 19)
±0.16dB
PB
0
3.0
kHz
−0.54dB
3.5
−1.0dB
3.6
kHz
−6.7dB
4.0
Stopband
(Note 19)
SB
4.7
kHz
Passband Ripple
PR
±0.1
dB
Stopband Attenuation
SA
73
dB
Group Delay
(Note 20)
GD
16
1/fs
Group Delay Distortion
ΔGD
0
μs
DAC Digital Filter + Analog Filter:
Frequency Response: 0 ∼ 3.4kHz
FR
±1.0
dB
Note 19. The passband and stopband frequencies are proportional to fs (system sampling rate).
For example, ADC of PB = 3.6kHz is 0.45*fs (@ −1.0dB). A reference of frequency response is 1kHz.
Note 20. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the
16-bit data of a channel from the input register to the output register of the ADC. For the DAC, this time is from
setting the 16-bit data of a channel from the input register to the output of analog signal. When there is not a
phase change with the IIR filter, group delay of the programmable filter (primary HPF + primary LPF + 4-band
Equalizer + ALC) increases for 3/fs than a value above mentioned.
MS1012-E-01
2010/08
- 12 -
[AK4636]
DC CHRACTERISTICS
(Ta = −30 ~ 85°C; AVDD = 2.6 ∼ 3.6V, DVDD = 1.6 ∼ 3.6V, SVDD = 2.6 ∼ 3.6V, VVDD = 2.8 ∼ 3.6V)
Parameter
Symbol
min
typ
max
Audio Interface & Serial µP Interface
(CDTIO, CSN/SDA, CCLK/SCL, I2C, PDN, BICK, FCK, SDTI, MCKI pins Input )
70%DVDD
VIH
High-Level Input Voltage
(DVDD ≥ 2.2V)
80%DVDD
(DVDD < 2.2V)
30%DVDD
VIL
Low-Level Input Voltage
(DVDD ≥ 2.2V)
20%DVDD
(DVDD < 2.2V)
Audio Interface & Serial µP Interface (CDTIO, SDA MCKO, BICK, FCK, SDTO pins Output)
DVDD−0.2
VOH
High-Level Output Voltage
(Iout = −80μA)
Low-Level Output Voltage
0.2
(Except SDA pin : Iout = 80μA) VOL1
0.4
(SDA pin, 2.0V ≤ DVDD ≤ 3.6V: Iout = 3mA) VOL2
20%DVDD
(SDA pin, 1.6V ≤ DVDD < 2.0V: Iout = 3mA) VOL2
Input Leakage Current
Iin
±10
Digital MIC Interface (DMDAT pin Input ; DMIC bit = “1”)
High-Level Input Voltage
Low-Level Input Voltage
VIH2
VIL2
Units
V
V
V
V
V
V
V
μA
65%AVDD
-
-
35%AVDD
V
V
Digital MIC Interface (DMCLK pin Output ; DMIC bit = “1”)
High-Level Output Voltage
(Iout=−80μA)
VOH3
AVDD-0.4
Low-Level Output Voltage
(Iout= 80μA)
VOL3
Input Leakage Current
Iin
-
-
0.4
±10
V
V
μA
SWITING CHARACTERISTICS
(Ta = −30 ~ 85°C; AVDD =2.6 ∼ 3.6V, DVDD = 1.6 ∼ 3.6V, SVDD = 2.6 ∼ 3.6V, VVDD = 2.8 ∼ 3.6V; CL = 20pF)
Parameter
Symbol
min
typ
max
Units
PLL Master Mode (PLL Reference Clock = MCKI pin) (Figure 4)
MCKI Input: Frequency
Pulse Width Low
Pulse Width High
MCKO Output:
Frequency
Duty Cycle except fs=29.4kHz, 32kHz
fs=29.4kHz, 32kHz (Note 22)
FCK Output: Frequency
Pulse width High
(DIF1-0 bits = “00” and FCKO bit = “1”)
fCLK
tCLKL
tCLKH
11.2896
0.4/fCLK
0.4/fCLK
-
27.0
-
MHz
ns
ns
fMCK
dMCK
dMCK
fFCK
40
8
256 x fFCK
50
33
-
60
48
kHz
%
%
kHz
tFCKH
-
tBCK
-
ns
dFCK
tBCK
tBCK
tBCK
dBCK
-
50
1/16fFCK
1/32fFCK
1/64fFCK
50
-
%
ns
ns
ns
%
Duty Cycle
(DIF1-0 bits = “00” or FCKO bit = “0”)
BICK: Period (BCKO1-0 bit = “00”)
(BCKO1-0 bit = “01”)
(BCKO1-0 bit = “10”)
Duty Cycle
MS1012-E-01
2010/08
- 13 -
[AK4636]
Parameter
Audio Interface Timing
DSP Mode: (Figure 5, Figure 6)
FCK “↑” to BICK “↑” (Note 23)
FCK “↑” to BICK “↓” (Note 24)
BICK “↑” to SDTO (BCKP bit = “0”)
BICK “↓” to SDTO (BCKP bit = “1”)
SDTI Hold Time
SDTI Setup Time
Except DSP Mode: (Figure 7)
BICK “↓” to FCK Edge
FCK to SDTO (MSB)
(Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
Symbol
min
typ
max
Units
tDBF
tDBF
tBSD
tBSD
tSDH
tSDS
0.5 x tBCK −40
0.5 x tBCK −40
−70
−70
50
50
0.5 x tBCK
0.5 x tBCK
-
0.5 x tBCK + 40
0.5 x tBCK +40
70
70
-
ns
ns
ns
ns
ns
ns
tBFCK
tFSD
−40
−70
-
40
70
ns
ns
tBSD
tSDH
tSDS
−70
50
50
-
70
-
ns
ns
ns
8
-
48
1/fFCK−tBCK
55
1/16fFCK
-
kHz
ns
%
ns
ns
ns
8
1/16fFCK
1/32fFCK
1/64fFCK
-
48
1/fFCK−tBCK
55
-
kHz
ns
%
ns
ns
ns
ns
ns
PLL Slave Mode (PLL Reference Clock: FCK pin) (Figure 8, Figure 9)
FCK: Frequency
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
BICK: Period
Pulse Width Low
Pulse Width High
fFCK
tFCKH
duty
tBCK
tBCKL
tBCKH
7.35
tBCK−60
45
1/64fFCK
0.4 x tBCK
0.4 x tBCK
PLL Slave Mode (PLL Reference Clock: BICK pin) (Figure 8, Figure 9)
FCK: Frequency
DSP Mode: Pulse width High
Except DSP Mode: Duty Cycle
BICK: Period (PLL3-0 bit = “0001”)
(PLL3-0 bit = “0010”)
(PLL3-0 bit = “0011”)
Pulse Width Low
Pulse Width High
fFCK
tFCKH
duty
tBCK
tBCK
tBCK
tBCKL
tBCKH
7.35
tBCK−60
45
0.4 x tBCK
0.4 x tBCK
PLL Slave Mode (PLL Reference Clock: MCKI pin) (Figure 10)
MCKI Input: Frequency
Pulse Width Low
Pulse Width High
MCKO Output:
Frequency
Duty Cycle except fs=29.4kHz, 32kHz
fs=29.4kHz, 32kHz (Note 22)
FCK: Frequency
DSP Mode: Pulse width High
Except DSP Mode: Duty Cycle
BICK: Period
Pulse Width Low
Pulse Width High
fCLK
fCLKL
fCLKH
11.2896
0.4/fCLK
0.4/fCLK
-
27.0
-
MHz
ns
ns
fMCK
dMCK
dMCK
fFCK
tFCKH
duty
tBCK
tBCKL
tBCKH
40
8
tBCK−60
45
1/64fFCK
0.4 x tBCK
0.4 x tBCK
256 x fFCK
50
33
-
60
48
1/fFCK−tBCK
55
1/16fFCK
-
kHz
%
%
kHz
ns
%
ns
ns
ns
MS1012-E-01
2010/08
- 14 -
[AK4636]
Parameter
Audio Interface Timing
DSP Mode: (Figure 11, Figure 12)
FCK “↑” to BICK “↑” (Note 23)
FCK “↑” to BICK “↓” (Note 24)
BICK “↑” to FCK “↑” (Note 23)
BICK “↓” to FCK “↑” (Note 24)
BICK “↑” to SDTO (BCKP bit = “0”)
BICK “↓” to SDTO (BCKP bit = “1”)
SDTI Hold Time
SDTI Setup Time
Except DSP Mode: (Figure 14)
FCK Edge to BICK “↑” (Note 21)
BICK “↑” to FCK Edge (Note 21)
FCK to SDTO (MSB) (Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
Symbol
min
typ
max
Units
tFCKB
tFCKB
tBFCK
tBFCK
tBSD
tBSD
tSDH
tSDS
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
50
50
-
80
80
-
ns
ns
ns
ns
ns
ns
ns
ns
tFCKB
tBFCK
tFSD
tBSD
tSDH
tSDS
50
50
50
50
-
80
80
-
ns
ns
ns
ns
ns
ns
MCKI Frequency: 256fs
512fs
1024fs
Pulse Width Low
Pulse Width High
FCK Frequency (MCKI = 256fs)
(MCKI = 512fs)
(MCKI = 1024fs)
Duty Cycle
BICK Period
BICK Pulse Width Low
Pulse Width High
fCLK
fCLK
fCLK
tCLKL
tCLKH
fFCK
fFCK
fFCK
duty
tBCK
tBCKL
tBCKH
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
7.35
7.35
7.35
45
312.5
130
130
2.048
4.096
8.192
8
8
8
-
12.288
13.312
13.312
48
26
13
55
-
MHz
MHz
MHz
ns
ns
Audio Interface Timing (Figure 14)
FCK Edge to BICK “↑” (Note 21)
BICK “↑” to FCK Edge (Note 21)
FCK to SDTO (MSB) (Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
tFCKB
tBFCK
tFSD
tBSD
tSDH
tSDS
50
50
50
50
-
80
80
-
ns
ns
ns
ns
ns
ns
EXT Slave Mode (Figure 13)
MS1012-E-01
kHz
kHz
%
ns
ns
ns
2010/08
- 15 -
[AK4636]
Parameter
EXT Master Mode (Figure 4)
Symbol
min
typ
max
Units
MCKI Frequency: 256fs
512fs
1024fs
Pulse Width Low
Pulse Width High
FCK Frequency (MCKI = 256fs)
(MCKI = 512fs)
(MCKI = 1024fs)
Duty Cycle
BICK: Period (BCKO1-0 bit = “00”)
(BCKO1-0 bit = “01”)
(BCKO1-0 bit = “10”)
Duty Cycle
fCLK
fCLK
fCLK
tCLKL
tCLKH
fFCK
fFCK
fFCK
dFCK
tBCK
tBCK
tBCK
dBCK
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
7.35
7.35
7.35
-
2.048
4.096
8.192
8
8
8
50
1/16fFCK
1/32fFCK
1/64fFCK
50
12.288
13.312
13.312
48
26
13
-
MHz
MHz
MHz
ns
ns
kHz
kHz
kHz
%
ns
ns
ns
%
tDBF
tDBF
tBSD
tBSD
tSDH
tSDS
0.5 x tBCK−40
0.5 x tBCK−40
−70
−70
50
50
0.5 x tBCK
0.5 x tBCK
-
0.5 x tBCK+40
0.5 x tBCK+40
70
70
-
ns
ns
ns
ns
ns
ns
tBFCK
tFSD
−40
−70
-
40
70
ns
ns
tBSD
tSDH
tSDS
−70
50
50
-
70
-
ns
ns
ns
Audio Interface Timing
DSP Mode: (Figure 5, Figure 6)
FCK “↑” to BICK “↑” (Note 23)
FCK “↑” to BICK “↓” (Note 24)
BICK “↑” to SDTO (BCKP bit = “0”)
BICK “↓” to SDTO (BCKP bit = “1”)
SDTI Hold Time
SDTI Setup Time
Except DSP Mode: (Figure 7)
BICK “↓” to FCK Edge
FCK to SDTO (MSB)
(Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
Note 21. BICK rising edge must not occur at the same time as FCK edge.
Note 22. Duty Cycle = (the width of “L”)/(the period of clock)*100
Note 23. MSBS, BCKP bits = “00” or “11”
Note 24. MSBS, BCKP bits = “01” or “10”
MS1012-E-01
2010/08
- 16 -
[AK4636]
Parameter
Control Interface Timing (3-wire Serial mode)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN edge to CCLK “↑” (Note 26)
CCLK “↑” to CSN edge (Note 26)
CCLK “↓” to CDTI (at Read Command)
CSN “↑” to CDTI (Hi-Z) (at Read Command)
(Note 27)
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 28)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Capacitive Load on Bus
Pulse Width of Spike Noise Suppressed by Input Filter
Reset Timing
PDN Pulse Width
(Note 29)
PMADC “↑” to SDTO valid
(Note 30)
ADRST bit = “0”
ADRST bit = “1”
Digital MIC Interface
DMCLK Output Timing ; CL=100pF
Period
Rise Time
Fall Time
Duty Cycle
DMDAT Interface Timing
DMDAT Setup Time
DMDAT Hold Time
Symbol
min
typ
max
Units
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
200
80
80
40
40
150
50
50
-
-
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCCZ
-
-
70
ns
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
tSP
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
400
0.3
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
tPD
150
-
-
ns
tPDV
tPDV
-
1059
291
-
1/fs
1/fs
tSCK
tSRise
tSFall
dSCK
40
1/(64fs)
50
10
10
60
ns
ns
ns
%
tSDS
tSDH
50
0
-
-
ns
ns
Note 25. I2C-bus is a trademark of NXP B.V.
Note 26. CCLK rising edge must not occur at the same time as CSN edge.
Note 27. RL = 1kΩ/10% change ( Pull-up to DVDD)
Note 28. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 29. The AK4636 can be reset by the PDN pin = “L”
Note 30. This is the count of FCK “↑” from the PMADC = “1”.
MS1012-E-01
2010/08
- 17 -
[AK4636]
■ Timing Diagram
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fFCK
50%DVDD
FCK
dFCK
dFCK
1/fMCK
50%DVDD
MCKO
tMCKOH
tMCKOL
dMCK = tMCKOL x fMCK x 100%
Figure 4. Clock Timing (PLL/EXT Master mode) (MCKO isn’t available at EXT Master Mode)
FCK
50%DVDD
tBCK
tDBF
dBCK
BICK
(BCKP = "0")
50%DVDD
BICK
(BCKP = "1")
50%DVDD
tBSD
SDTO
MSB
tSDS
50%DVDD
tSDH
VIH
SDTI
MSB
VIL
Figure 5. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “0”)
MS1012-E-01
2010/08
- 18 -
[AK4636]
FCK
50%DVDD
tBCK
tDBF
dBCK
BICK
(BCKP = "1")
50%DVDD
BICK
(BCKP = "0")
50%DVDD
tBSD
SDTO
50%DVDD
MSB
tSDS
SDTI
tSDH
VIH
MSB
VIL
Figure 6. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “1”)
50%DVDD
FCK
tBFCK
dBCK
BICK
50%DVDD
tFSD
tBSD
SDTO
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 7. Audio Interface Timing (PLL/EXT Master mode & Except DSP mode)
MS1012-E-01
2010/08
- 19 -
[AK4636]
1/fFCK
VIH
FCK
VIL
tFCKH
tBFCK
tBCK
VIH
BICK
(BCKP = "0")
VIL
tBCKH
tBCKL
VIH
BICK
(BCKP = "1")
VIL
Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = FCK or BICK pin & DSP mode; MSBS = 0)
1/fFCK
VIH
FCK
VIL
tFCKH
tBFCK
tBCK
VIH
BICK
(BCKP = "1")
VIL
tBCKH
tBCKL
VIH
BICK
(BCKP = "0")
VIL
Figure 9. Clock Timing (PLL Slave mode; PLL Reference Clock = FCK or BICK pin & DSP mode; MSBS = 1)
MS1012-E-01
2010/08
- 20 -
[AK4636]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fFCK
VIH
FCK
VIL
tFCKH
tFCKL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
1/fMCK
50%DVDD
MCKO
tMCKOH
tMCKOL
dMCK = tMCKOL x fMCK x 100%
Figure 10. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode)
MS1012-E-01
2010/08
- 21 -
[AK4636]
tFCKH
VIH
FCK
VIL
tFCKB
VIH
BICK
VIL
(BCKP = "0")
VIH
BICK
(BCKP = "1")
VIL
tBSD
SDTO
50%DVDD
MSB
tSDS
tSDH
VIH
SDTI
MSB
VIL
Figure 11. Audio Interface Timing (PLL Slave mode & DSP mode; MSBS = 0)
tFCKH
VIH
FCK
VIL
tFCKB
VIH
BICK
VIL
(BCKP = "1")
VIH
BICK
(BCKP = "0")
VIL
tBSD
SDTO
MSB
tSDS
50%DVDD
tSDH
VIH
SDTI
MSB
VIL
Figure 12. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = 1)
MS1012-E-01
2010/08
- 22 -
[AK4636]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fFCK
VIH
FCK
VIL
tFCKH
tFCKL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 13. Clock Timing (EXT Slave mode)
VIH
FCK
VIL
tBFCK
tFCKB
VIH
BICK
VIL
tFSD
tBSD
SDTO
MSB
tSDS
50%DVDD
tSDH
VIH
SDTI
VIL
Figure 14. Audio Interface Timing (PLL, EXT Slave mode & Except DSP mode)
MS1012-E-01
2010/08
- 23 -
[AK4636]
VIH
CSN
VIL
tCSH
tCCKL
tCSS
tCCKH
VIH
CCLK
VIL
tCCK
tCDH
tCDS
VIH
CDTIO
A6
A5
R/W
VIL
Figure 15. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
tCSS
VIH
CCLK
VIL
VIH
CDTIO
D2
D1
D0
VIL
Figure 16. WRITE Data Input Timing
MS1012-E-01
2010/08
- 24 -
[AK4636]
VIH
CSN
VIL
VIH
CCLK
Clock, H or L
tCCZ
tDCD
CDTIO
D3
VIL
D2
D1
50%
DVDD
D0
Hi-Z
Figure 17. Read Data Output Timing
VIH
SDA
VIL
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
Figure 18. I2C Bus Mode Timing
PMADC
bit
tPDV
SDTO
50%DVDD
Figure 19. Power Down & Reset Timing 1
tPD
PDN
VIL
Figure 20. Power Down & Reset Timing 2
MS1012-E-01
2010/08
- 25 -
[AK4636]
tSCK
65%AVDD
DMCLK
50%AVDD
35%AVDD
tSCKL
tSRise
tSFall
dSCK = 100 x tSCKL / tSCK
Figure 21. DMCLK Clock Timing
65%AVDD
DMCLK
35%AVDD
tSDS
tSDH
VIH3
DMDAT
VIL3
Figure 22. Audio Interface Timing (DCLKP bit = “1”)
65%AVDD
DMCLK
35%AVDD
tSDS
tSDH
VIH3
DMDAT
VIL3
Figure 23. Audio Interface Timing (DCLKP bit = “0”)
MS1012-E-01
2010/08
- 26 -
[AK4636]
OPERATION OVERVIEW
■ System Clock
There are the following five clock modes to interface with external devices. (Table 1 and Table 2)
Mode
PMPLL bit M/S bit
PLL3-0 bit
PLL Master Mode
1
1
Table 4
PLL Slave Mode 1
Table 4
1
0
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
Table 4
1
0
(PLL Reference Clock: FCK or BICK pin)
EXT Slave Mode
0
0
x
EXT Master Mode
0
1
x
Table 1. Clock Mode Setting (x: Don’t care)
Mode
PLL Master Mode
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: FCK or BICK pin)
EXT Slave Mode
EXT Master Mode
MCKO bit
MCKO pin
0
“L” Output
1
256fs Output
0
“L” Output
1
0
Figure
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
MCKI pin
BICK pin
FCK pin
Master Clock
Input for PLL
(Note 31)
16fs/32fs/64fs
Output
1fs
Output
256fs Output
Master Clock
Input for PLL
(Note 31)
≥ 16fs
Input
1fs
Input
“L” Output
GND
16fs/32fs/64fs
Input
1fs
Input
≥ 32fs
Input
1fs
Input
32fs/64fs
Output
1fs
Output
256fs/
512fs/
0
“L” Output
1024fs
Input
256fs/
512fs/
0
“L” Output
1024fs
Input
Note 31. 11.2896MHz/12MHz/13.5MHz/24MHz/27MHz
Table 2. Clock pins state in Clock Mode
MS1012-E-01
2010/08
- 27 -
[AK4636]
■ Master Mode/Slave Mode
The M/S bit selects either master or slave modes. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4636 is power-down mode (PDN pin = “L”) and when exits reset state, the AK4636 is in slave mode. After exiting
reset state, the AK4636 changes to master mode by bringing M/S bit = “1”.
When the AK4636 is in master mode, FCK and BICK pins are a floating state until M/S bit becomes “1”. The FCK and
BICK pins of the AK4636 should be pulled-down or pulled-up by about 100kΩ resistor externally to avoid the floating
state.
M/S bit
Mode
0
Slave Mode
(default)
1
Master Mode
Table 3. Select Master/Salve Mod
■ PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4. Ether when the AK4636 is supplied stable clocks after
PLL is powered-up (PMPLL bit = “0” → “1”) or when the sampling frequency changes, the PLL lock time is the same.
1) Setting of PLL Mode
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
PLL Reference
Clock Input Pin
0
1
2
3
4
6
7
12
13
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
1
1
0
0
0
1
0
1
0
0
1
0
1
FCK pin
BICK pin
BICK pin
BICK pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
Input
Frequency
R and C of
VCOC pin
(Note 32)
R[Ω] C[F]
6.8k
220n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
10n
10k
10n
PLL Lock
Time
(max)
1fs
160ms
16fs
2ms
32fs
2ms
64fs
2ms
11.2896MHz
10ms
12MHz
10ms
24MHz
10ms
13.5MHz
10ms
27MHz
10ms
Others
Others
N/A
Note 32. The tolerance of R is ±5%, the tolerance of C is ±30%
Table 4. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)
(default)
2) Setting of sampling frequency in PLL Mode.
When PLL2 bit is “1” (PLL reference clock input is the MCKI pin), the sampling frequency is selected by FS3-0 bits as
defined in Table 5.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
0
0
8kHz
(default)
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
4
0
1
0
0
7.35kHz
5
0
1
0
1
11.025kHz
6
0
1
1
0
14.7kHz
7
0
1
1
1
22.05kHz
10
1
0
1
0
32kHz
11
1
0
1
1
48kHz
14
1
1
1
0
29.4kHz
15
1
1
1
1
44.1kHz
Others
Others
N/A
Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” (N/A: Not available)
MS1012-E-01
2010/08
- 28 -
[AK4636]
When PLL2 bit is “0” (PLL reference clock input is FCK or BICK pin), the sampling frequency is selected by FS3-2
bits. (Table 6)
Mode
0
1
2
Others
FS3 bit
FS2 bit
Sampling Frequency
Range
0
0
x
x
(default)
7.35kHz ≤ fs ≤ 12kHz
0
1
x
x
12kHz < fs ≤ 24kHz
1
0
x
x
24kHz < fs ≤ 48kHz
Others
N/A
(x: Don’t care, N/A: Not available)
Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1”
FS1 bit
FS0 bit
■ PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, after PMPLL bit = “0” Æ “1” until the PLL is locked, the BICK and FCK pins output “L” for a moment, and
invalid frequency clock is output from the MCKO pin at MCKO bit = “1”. If the MCKO bit is “0”, the MCKO pin outputs
“L”. (Table 7)
When sampling frequency is changed, BICK and FCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
MCKO pin
BICK pin
FCK pin
MCKO bit = “0” MCKO bit = “1”
After that PMPLL bit “0” Æ “1”
“L” Output
Invalid
“L” Output
“L” Output
PLL Unlock
“L” Output
Invalid
Invalid
Invalid
PLL Lock
“L” Output
256fs Output
See Table 9
1fs Output
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
PLL State
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from the MCKO pin after PMPLL bit = “0” Æ “1” or sampling frequency is
changed. 256fs is output from the MCKO pin when PLL is locked again. ADC and DAC output invalid data when the
PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACA and DACS bits in Addr=02H.
MCKO pin
MCKO bit = “0” MCKO bit = “1”
After that PMPLL bit “0” Æ “1”
“L” Output
Invalid
PLL Unlock
“L” Output
Invalid
PLL Lock
“L” Output
Output
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
PLL State
MS1012-E-01
2010/08
- 29 -
[AK4636]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 13.5MHz, 24MHz or 27MHz) is input to the MCKI pin, the MCKO,
BICK and FCK clocks are generated by an internal PLL circuit. The MCKO output frequency is fixed to 256fs, the output
is enabled by MCKO bit. The BICK is selected among 16fs, 32fs or 64fs, by BCKO1-0 bits. (Table 9)
In DSP mode, FCK output can select Duty 50% or High-output only during 1 BICK cycle (Table 10). Except DSP mode,
FCKO bit should be set “0”.
When BICK output frequency is 16fs, the audio interface format supports Mode 0 only (DSP Mode).
11.2896MHz,12MHz, 13.5MHz,
24MHz, 27MHz
DSP or μP
AK4636
MCKI
MCKO
BICK
FCK
256fs
16fs, 32fs, 64fs
1fs
MCLK
BCLK
FCK
SDTO
SDTI
SDTI
SDTO
Figure 24. PLL Master Mode
Mode
0
1
2
3
Mode
0
1
BICK Output
Frequency
0
0
16fs
0
1
32fs
1
0
64fs
1
1
N/A
Table 9. BICK Output Frequency at Master Mode
BCKO1
BCKO0
(default)
FCKO
FCK Output
0
Duty = 50%
(default)
1
High Width = 1/fBCK
fBCK is BICK Output Frequency.
Table 10. FCK Output at PLL Master Mode and DSP Mode
MS1012-E-01
2010/08
- 30 -
[AK4636]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to the MCKI, BICK or FCK pin. The required clock to the
AK4636 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits. When BICK input frequency
is 16fs, the audio interface format supports Mode 0 only (DSP Mode).
a) PLL reference clock: MCKI pin
BICK and FCK inputs should be synchronized with MCKO output. The phase between MCKO and FCK is not important.
The MCKO pin outputs the frequency selected by FS3-0 bits (Note 5)
11.2896MHz, 12MHz, 13.5MHz,
24MHz, 27MHz
AK4636
DSP or μP
MCKI
MCKO
BICK
FCK
256fs
16fs, 32fs, 64fs
1fs
MCLK
BCLK
FCK
SDTO
SDTI
SDTI
SDTO
Figure 25. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
MS1012-E-01
2010/08
- 31 -
[AK4636]
b) PLL reference clock: BICK or LRCK pin
The sampling frequency corresponds to a range from 7.35kHz to 48kHz by changing FS3-0 bits. (Table 6)
AK4636
DSP or μP
MCKO
MCKI
BICK
FCK
16fs, 32fs, 64fs
1fs
BCLK
FCK
SDTO
SDTI
SDTI
SDTO
Figure 26 PLL Slave Mode 2 (PLL Reference Clock: BICK pin)
AK4636
DSP or μP
MCKO
MCKI
BICK
FCK
≥16fs
1fs
BCLK
FCK
SDTO
SDTI
SDTI
SDTO
Figure 27. PLL Slave Mode 2 (PLL Reference Clock: FCK pin)
The external clocks (MCKI, BICK and FCK) should always be present whenever the ADC or DAC or Programmable
Filter is in operation (PMADC bit = “1”, PMDM bit = “1”, PMDAC bit = “1” or PMPFIL bit = “1”). If these clocks are not
provided, the AK4636 may draw excess current and it is not possible to operate properly because utilizes dynamic
refreshed logic internally. If the external clocks are not present, the ADC, DAC and Programmable Filter should be in the
power-down mode (PMADC bit = PMDM bit = PMDAC bit = PMPFIL bit = “0”).
MS1012-E-01
2010/08
- 32 -
[AK4636]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4636 becomes EXT Slave mode. Master clock is input from the MCKI pin, the internal
PLL circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate
are MCKI (256fs, 512fs or 1024fs), FCK (fs) and BICK (≥32fs). The master clock (MCKI) should be synchronized with
FCK. The phase between these clocks is not important. The input frequency of MCKI is selected by FS1-0 bits. (Table 11)
Mode
0
1
2
3
FS3-2 bits
FS1 bit
FS0 bit
MCKI Input
Sampling Frequency
Frequency
Range
x
0
256fs
0
7.35kHz ≤ fs ≤ 48kHz (default)
x
1
1024fs
0
7.35kHz ≤ fs ≤ 13kHz
x
0
512fs
1
7.35kHz ≤ fs ≤ 26kHz
x
1
256fs
1
7.35kHz ≤ fs ≤ 48kHz
Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) (x: Don’t care)
External Slave Mode does not support Mode 0 (DSP Mode) of Audio Interface Format.
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be reduced by using higher frequency master clock. (Table 12, Table 13)
MCKI
S/N (fs = 8kHz, 20kHzLPF + A-weighted)
DAC →AOUT
256fs
81dB
512fs
89dB
1024fs
89dB
Table 12. Relationship between MCKI and S/N of AOUT and SPK-Amp
MCKI
Output Noise Level
(SVDD =3.3V,fs = 8kHz, 20kHzLPF + A-weighted)
SDTI → SPK-Amp
256fs
– 61dBV
512fs
– 75dBV
1024fs
– 83dBV
Table 13. Relationship between MCKI and Output Noise Level of SPK-Amp
The external clocks (MCKI, BICK and FCK) should always be present whenever the ADC or DAC or Programmable
Filter is in operation (PMADC bit = “1”, PMDM bit = “1”, PMDAC bit = “1” or PMPFIL bit = “1”). If these clocks are not
provided, the AK4636 may draw excess current and it is not possible to operate properly because utilizes dynamic
refreshed logic internally. If the external clocks are not present, the ADC, DAC, SPK and Programmable Filter should be
in the power-down mode (PMADC bit = PMDM bit= PMDAC bit = PMPFIL bit = “0”).
AK4636
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
BICK
MCLK
≥ 32fs
1fs
FCK
BCLK
FCK
SDTO
SDTI
SDTI
SDTO
Figure 28. EXT Slave Mode
MS1012-E-01
2010/08
- 33 -
[AK4636]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The AK4636 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from the
MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The
input frequency of MCKI is selected by FS1-0 bits (Table 14). The BICK is selected among 32fs or 64fs, by BCKO1-0
bits (Table 15). FCK bit should be set to “0”.
Mode
FS3-2 bits
FS1 bit
FS0 bit
MCKI Input
Sampling Frequency
Frequency
Range
x
0
256fs
0
0
7.35kHz ≤ fs ≤ 48kHz (default)
x
1
1024fs
1
0
7.35kHz ≤ fs ≤ 13kHz
x
0
512fs
2
1
7.35kHz ≤ fs ≤ 26kHz
x
1
256fs
3
1
7.35kHz ≤ fs ≤ 48kHz
Table 14. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) (x: Don’t care)
External Master Mode does not support Mode 0 (DSP Mode) of Audio Interface Format.
MCKI should always be present whenever the ADC, DAC or Programmable Filter is in operation (PMADC bit = “1”,
PMDM bit = “1”, PMDAC bit = “1” or PMPFIL bit = “1”). If MCKI is not provided, the AK4636 may draw excess
current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not
present, the ADC, DAC and Programmable Filter should be in the power-down mode (PMADC bit = PMDM bit =
PMDAC bit = PMPFIL bit = “0”).
AK4636
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
BICK
FCK
MCLK
32fs, 64fs
1fs
BCLK
FCK
SDTO
SDTI
SDTI
SDTO
Figure 29. EXT Master Mode
BICK Output
Frequency
0
0
0
N/A
1
0
1
32fs
(default)
2
1
0
64fs
3
1
1
N/A
Table 15. BICK Output Frequency at Master Mode (N/A: Not available)
Mode
BCKO1
BCKO0
MS1012-E-01
2010/08
- 34 -
[AK4636]
■ Audio Interface Format
Four types of data formats are available and are selected by setting the DIF1-0 bits. (Table 16) In all modes, the serial data
is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. FCK and
BICK pins are outputs in master mode, but must be inputs in slave mode.
In Mode 1-3, the SDTO is clocked out on the falling edge of BICK and the SDTI is latched on the rising edge.
Mode
0
1
2
3
DIF1
0
0
1
1
DIF0
0
1
0
1
SDTO (ADC)
SDTI (DAC)
BICK
DSP Mode
DSP Mode
≥ 16fs
MSB justified
LSB justified
≥ 32fs
MSB justified
MSB justified
≥ 32fs
I2S compatible I2S compatible
≥ 32fs
Table 16. Audio Interface Format
Figure
Table 17
Figure 30
Figure 31
Figure 32
(default)
In Mode0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits.
When BCKP bit is “0”, SDTO data is output on a rising edge of BICK, SDTI data is latched on a falling edge of BICK.
When BCKP bit is “1”, SDTO data is output on a falling edge of BICK, SDTI data is latched on a rising edge of BICK.
MSB data position of SDTO and SDTI can be shifted for a halt period of BICK by MSBS bit.
MSBS bit BCKP bit
Audio Interface Format
0
0
Figure 33
0
1
Figure 34
1
0
Figure 35
1
1
Figure 36
Table 17. Audio Interface Format in Mode 0
(default)
If 16-bit data, the output of ADC, is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data
and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
FCK
0
1
2
8
3
9
10
11
12
13
14
15
0
1
2
3
8
9
10
11
12
13
14
15
0
1
BICK(32fs)
SDTO(o)
15 14 13
SDTI(i)
15 14 13
0
1
2
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
3
14
15
16
17
18
31
15
15
Don’t Care
0
1
2
3
14
15
16
17
18
31
0
1
BICK(64fs)
SDTO(o)
15 14 13
SDTI(i)
Don’t Care
15:MSB, 0:LSB
2
1
0
15
15 14
1
0
Don’t Care
Data
1/fs
Figure 30. Mode 1 Timing
MS1012-E-01
2010/08
- 35 -
[AK4636]
FCK
0
1
2
8
9
10
11
12
13
14
15
0
1
2
8
9
10
11
12
13
14
15
0
1
BICK(32fs)
SDTO(o)
15 14
8
7
6
5
4
3
2
1
0
SDTI(I)
15 14
8
7
6
5
4
3
2
1
0
0
1
2
3
14
15
16
17
18
31
15
15
Don’t Care
0
1
2
3
14
14
15
16
17
18
31
0
1
BICK(64fs)
SDTO(o)
15 14 13
13 2
1
0
SDTI(i)
15 14 13
13 2
1
0
15
Don’t Care
Don’t Care
15
15:MSB, 0:LSB
Data
1/fs
Figure 31. Mode 2 Timing
FCK
0
1
2
3
4
9
10
11
12
13
14
15
0
1
2
3
1
2
3
4
9
10
11
12
13
14
15
16
17
18
14
15
0
1
31
0
1
BICK(32fs)
SDTO(o)
15 14 13
SDTI(i)
15 14 13
0
1
2
3
4
7
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
14
15
16
17
18
31
0
4
BICK(64fs)
SDTO(o)
15 14 13
2
1
0
SDTI(i)
15 14 13
2
1
0
15:MSB, 0:LSB
Don’t Care
Don’t Care
Data
1/fs
Figure 32. Mode 3 Timing
MS1012-E-01
2010/08
- 36 -
[AK4636]
FCK
15
0
1
8
2
8
9
10
11
12
13
14
15
0
1
8
2
8
9
10
11
12
13
14
15
0
BICK(16fs)
SDTO(o)
0
15 14
SDTI(i)
0
15 14
31
0
1
8
8
7
6
5
4
3
2
1
0
15 14
8
7
6
5
4
3
2
1
0
15 14
8
2
14
15
16
17
18
29
30
31
0
1
8
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
2
8
9
10
11
12
13
30
31
0
15
0
BICK(32fs)
SDTO(o)
15 14
SDTI(i)
15 14
8
2
1
0
2
1
0
Don’t Care
15 14
8
2
1
0
15 14
8
2
1
0
Don’t Care
1/fs
1/fs
15:MSB, 0:LSB
Figure 33. Mode 0 Timing (BCKP = “0”, MSBS = “0”)
FCK
15
0
1
8
2
8
9
10
11
12
13
14
15
0
1
8
2
8
9
10
11
12
13
14
BICK(16fs)
SDTO(o)
0
15 14
SDTI(i)
0
15 14
31
0
1
8
8
7
6
5
4
3
2
1
0
15 14
8
7
6
5
4
3
2
1
0
15 14
8
2
14
15
16
17
18
29
30
31
0
1
8
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
2
8
9
10
11
12
13
30
31
0
BICK(32fs)
SDTO(o)
15 14
SDTI(i)
15 14
8
2
1
0
2
1
0
Don’t Care
15 14
8
2
1
0
15 14
8
2
1
0
Don’t Care
1/fs
1/fs
15:MSB, 0:LSB
Figure 34. Mode 0 Timing (BCKP = “1”, MSBS = “0”)
MS1012-E-01
2010/08
- 37 -
[AK4636]
FCK
15
0
1
8
2
8
9
10
11
12
13
14
15
0
1
8
2
8
9
10
11
12
13
14
15
0
BICK(16fs)
SDTO(o)
0
15 14
SDTI(i)
0
15 14
31
0
1
8
8
7
6
5
4
3
2
1
0
15 14
8
7
6
5
4
3
2
1
0
15 14
8
2
14
15
16
17
18
29
30
31
0
1
8
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
2
8
9
10
11
12
13
30
31
0
15
0
BICK(32fs)
SDTO(o)
15 14
SDTI(i)
15 14
8
2
1
0
2
1
0
Don’t Care
15 14
8
2
1
0
15 14
8
2
1
0
Don’t Care
1/fs
1/fs
15:MSB, 0:LSB
Figure 35. Mode 0 Timing (BCKP = “0”, MSBS = “1”)
FCK
15
0
1
8
2
8
9
10
11
12
13
14
15
0
1
8
2
8
9
10
11
12
13
14
BICK(16fs)
SDTO(o)
0
15 14
SDTI(i)
0
15 14
31
0
1
8
8
7
6
5
4
3
2
1
0
15 14
8
7
6
5
4
3
2
1
0
15 14
8
2
14
15
16
17
18
29
30
31
0
1
8
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
2
8
9
10
11
12
13
30
31
0
BICK(32fs)
SDTO(o)
15 14
SDTI(i)
15 14
8
2
1
0
2
1
0
Don’t Care
15 14
8
2
1
0
15 14
8
2
1
0
Don’t Care
1/fs
1/fs
15:MSB, 0:LSB
Figure 36. Mode 0 Timing (BCKP = “1”, MSBS = “1”)
MS1012-E-01
2010/08
- 38 -
[AK4636]
■ System Reset
When power-up, the PDN pin should be “L” and change to “H” after all powers are supplied. “L” time of 150ns or more
is needed to reset the AK4636.
The ADC enters an initialization cycle when the PMADC bit is changed from “0” to “1”. The initialization cycle time is
set by ADRST bit (Table 18). During the initialization cycle, the ADC digital data outputs of both channels are forced to
a 2's compliment, “0”. The ADC output reflects the analog input signal after the initialization cycle is complete. The same
initializing cycle is occurred when using the digital microphone. The DAC does not require an initialization cycle.
(Note) Off-set occurs in the initial data depending on the conditions of a microphone and cut-off frequency of HPF.
When Off-set becomes a problem, lengthen initialization time of ADC by ADRST bit = “0” or do not use initial
output data of ADC.
ADRST bit
0
1
Init Cycle
Cycle
fs = 8kHz
fs = 16kHz
1059/fs
132.4ms
66.2ms
291/fs
36.4ms
18.2ms
Table 18 Initialization cycle of ADC
fs = 48kHz
22.1ms
6.1ms
■ MIC/LINE/Digital MIC Selector
The AK4636 has an input selector. When MDIF bit is “0”, LIN bit selects the MIC pin or LIN pin. When MDIF bit is “1”,
MIC/LIN pins become MICP/MICN pins, and full-differential input is available. When DMIC bit is “1”, MIC/LIN pins
become DMCLC/ DMDAT pins, and they can be connected to digital microphone.
MDIF bit
0
0
1
x
LIN bit
0
1
x
x
DMIC bit
Input circuit
Input pin
0
Single-Ended
MIC pin
0
Single-Ended
LIN pin
0
Differential
MICP/MICN pin
1
Digital MIC
DMDAT/ DMCLK pin
Table 19. Input Select (x: Don’t care)
MS1012-E-01
(default)
2010/08
- 39 -
[AK4636]
■ MIC Gain Amplifier
The AK4636 has a Gain Amplifier for Microphone input. These gains are selected by the MGAIN3-0 bit. The typical
input impedance is 30kΩ.
MGAIN3 bit
0
0
0
0
0
0
0
0
1
1
MGAIN2 bit
MGAIN1 bit
MGAIN0 bit
Input Gain
0
0
0
0dB
0
0
1
+20dB
0
1
0
+26dB
0
1
1
+32dB
1
0
+10dB
0
1
0
+17dB
1
1
1
0
+23dB
1
1
1
+29dB
0
0
0
+3dB
0
0
1
+6dB
Others
N/A
Table 20. Input Gain (N/A: Not available)
(default)
■ MIC Power (DMPE bit = “0”)
The MPI pin supplies power for the Microphone. This output voltage is 2.3V (typ) and the load resistance is minimum
2kΩ. Any capacitor must not be connected to the MPI pin directly.
AK4636
MPI pin
MIC-Power
≥ 2k
Audio
MIC pin
A/D
HPF
I/F
BICK pin
FCK pin
STDO pin
MIC-Amp
Figure 37. MIC Block Circuit
AK4636
MIC-Power
MPI pin
1k
MICP pin
Audio
MICNpin
A/D
MIC-Amp
HPF
I/F
BICK pin
FCK pin
STDO pin
1k
Figure 38. MIC Block Circuit (Differential; MDIF = “1”)
MS1012-E-01
2010/08
- 40 -
[AK4636]
■ Digital MIC
1. Connection to Digital MIC
The AK4636 can be connected to digital microphone by setting DMIC bit = “1”. When DMIC bit is set to “1”, the MPI,
LIN and MIC pins become DMP (digital microphone power supply), DMCLK (digital microphone clock supply) and
DMDAT (digital microphone data input) pins respectively. By setting DMPE bit = “1”, the DMP (digital microphone
power supply) pin and can supply the power to the digital microphone (max. 2mA). When DMPE bit = “0”, the same
power supply as AVDD must be provided to the digital microphone. The Figure 39 and Figure 40 show connection
examples. The DMCLK signal is output from the AK4636, and the digital microphone outputs 1bit data, which is
generated by ΔΣModulator, from DMDAT. PMDML/R bits control power up/down of the digital block (Decimation
Filter and Digital Filter). PMADL/PMADR bits settings do not affect the digital microphone power management. The
DCLKE bit controls ON/OFF of the clock output from the DMCLK pin. When the AK4636 is powered down (PDN pin=
“L”), the DMCLK and DMDAT pin are floating state. Pull-down resistors must be connected to the DMCLK and
DMDAT pin externally to avoid floating state.
AVDD
AK4636
DMP
DMPE = “1”
VDD
DMCLK(64fs)
ΔΣ
AMP
PLL
MCKI
100kΩ
Modulator
DMDAT
Decimation
Filter
HPF1
Programmable
Filter
ALC
SDTO
R
Figure 39. Connection Example of Digital MIC (DMPE bit = “1”)
AVDD
AVDD
AK4636
DMP
DMPE = “0”
VDD
DMCLK(64fs)
AMP
ΔΣ
PLL
MCKI
100kΩ
Modulator
DMDAT
Decimation
Filter
HPF1
Programmable
Filter
ALC
SDTO
R
Figure 40. Connection Example of Digital MIC (DMPE bit = “0”)
MS1012-E-01
2010/08
- 41 -
[AK4636]
2. Interface
The digital microphone outputs data when DMCLK is “H” by setting DCLKP bit = “1”, and it outputs data when
DMCLK is “L” by setting DCLKP bit = “0”. The DMCLK data only supports 64fs. The DMCLK pin outputs is 64fs when
DCLKE bit = “1”. In this case, necessary clocks must be supplied to the AK4636 for ADC operation. The DMCLK
outputs “L” when DCLKE bit = “0”. Figure 41 and Figure 42 show data input/output timings. When DCLKP bit = “1”,
the digital microphone outputs data on the rising edge “↑” of DMCLK and the AK4636 latches data on the falling edge
“↓” of DMCLK. When DCLKP bit = “0”, the digital microphone outputs data on the rising edge “↓” of DMCLK and the
AK4636 latches data on the falling edge “↑” of DMCLK.
The PDM signal is defined as 0dB (full scale) when the 1 bit data density ranges ±50% from 50%.
DMCLK(64fs)
DMDAT
DCLKP bit = “1”
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 41. Data In/Output Timing with Digital MIC (DCLKP bit = “1”)
DMCLK(64fs)
DMDAT
DCLKP bit = “0”
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 42. Data In/Output Timing with Digital MIC (DCLKP bit = “0”)
MS1012-E-01
2010/08
- 42 -
[AK4636]
■ Digital Block
The digital block consists of block diagram as shown in Figure 43. The AK4636 can choose signal process path on a
recording path or on a playback path by setting ADCPF bit, PFDAC bit and PFSDO bit. (Figure 43 ~ Figure 46, Table 21)
PMADC bit
SDTI
ADC
1st Order
HPF1
“1”
“0”
ADCPF bit
PMPFIL bit
HPF bit
1st Order
HPF2
1st Order
LPF bit
LPF
4 Band
EQ2-5 bits
EQ
ALC
(Volume)
EQ
EQ1 bit
“0”
“1”
“1”
PFSDO bit
“0”
PFDAC bit
PMDAC bit
DATT
SDTO
SMUTE
DAC
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
ADC: Include a Digital Filter (LPF) for ADC as shown in “FILTER CHRACTERISTICS”.
DAC: Include a Digital Filter (LPF) for DAC as shown in “FILTER CHRACTERISTICS”.
HPF1/2: High Pass Filter. Applicable to use as Wind-Noise Reduction Filter. (See “Programmable Filter”.)
LPF: Low Pass Filter (See “Digital Programmable Filter”.)
4-Band EQ: Applicable to use as an Equalizer or Notch Filter. (See “Digital Programmable Filter”.)
ALC: Input Digital Volume with ALC function. (See “Input Digital Volume” and “ALC”.)
EQ: Applicable to use as an Equalizer or Notch Filter. (See “Digital Programmable Filter”.)
DATT: 4-step Digital Volume for playback path. (See “Digital Volume 2”)
SMUTE: Soft mute. (See “Soft Mute”.)
Figure 43. Digital Block Path Select
MS1012-E-01
2010/08
- 43 -
[AK4636]
Mode
Recording Mode
Playback Mode
Loop Back Mode
ADCPF bit
PFDAC bit
PFSDO bit
1
0
1
0
1
0
1
1
1
Table 21 Recording Reproduction Mode
ADC
DAC
2nd Order
1st Order
4 Band
HPF
LPF
EQ
SMUTE
ALC
(Volume)
Figure
Figure 44
Figure 45
Figure 46
(default)
EQ
DATT
Figure 44. Path at Recording Mode (default)
1st Order
ADC
DAC
SMUTE
HPF
DATT
ALC
EQ
(Volume)
4 Band
1st Order
1st Order
EQ
LPF
HPF
ALC
EQ
Figure 45. Path at Playback Mode
ADC
DAC
2nd Order
1st Order
4 Band
HPF
LPF
EQ
SMUTE
(Volume)
DATT
Figure 46. Path at Recording & Playback Mode
MS1012-E-01
2010/08
- 44 -
[AK4636]
■ Digital Programmable Filter Circuit
The AK4636 has 2 steps of 1st order HPF, 1st order LPF and 5-band Equalizer built-in on recording/playback paths.
(1)
High Pass Filter (HPF1/2)
Normally, this HPF is used as a Wind-Noise Reduction Filter. This is composed with 2 steps of 1st order HPF. The
coefficient of both HPF is the same and set by F1A13-0 bits and F1B13-0 bits. HPF bit controls ON/OFF of the HPF2.
When the HPF2 is OFF, the audio data passes this block by 0dB gain. The coefficient should be set when PMADC =
PMPFIL bits = “0”.
fs : Sampling frequency
fc : Cut-off frequency
Register setting (Note 33)
HPF: F1A[13:0] bits = A, F1B[13:0] bits = B
(MSB = F1A13, F1B13; LSB = F1A0, F1B0)
1
1− tan (πfc/fs)
A=
,
B=
1 + tan (πfc/fs)
Transfer Function
H(z) = A
1 + tan (πfc/fs)
1 − z −1
1 − Bz −1
The cut-off frequency should be set as below.
fc/fs ≥ 0.0001 (fc min = 1.6Hz at fs=16kHz)
(2) Low Pass Filter(LPF)
This is composed with 1st order LPF. F2A13-0 bits and F2B13-0 bits set the coefficient of LPF. LPF bit controls ON/OFF
of the LPF. When the LPF is OFF, the audio data passes this block by 0dB gain. The coefficient should be set when LPF
bit = “0” or PMPFIL bits = “0”.
fs : Sampling frequency
fc : Cut-off frequency
Register setting (Note 33)
LPF: F2A[13:0] bits =A, F2B[13:0] bits =B
(MSB=F2A13, F1B13; LSB=F2A0, F2B0)
1 − 1 / tan (πfc/fs)
1
A=
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
Transfer Function
1 + z −1
H(z) = A
1 + Bz −1
The cut-off frequency should be set as below.
fc/fs ≥ 0.05 (fc min = 2205Hz at fs=44.1kHz)
MS1012-E-01
2010/08
- 45 -
[AK4636]
(3) 4-band Equalizer and Equalizer after ALC
This block can be used as Equalizer or Notch Filter. ON/OFF 5-band Equalizer (EQ2, EQ3, EQ4 and EQ5) can be
controlled independently by EQ2, EQ3, EQ4 and EQ5 bits. The Equalizer after ALC (EQ1) can be ON/OFF by EQ1 bit.
When Equalizer is OFF, the audio data passes this block by 0dB gain. E1A15-0, E1B15-0 and E1C15-0 bits set the
coefficient of EQ1. E2A15-0, E2B15-0 and E2C15-0 bits set the coefficient of EQ2. E3A15-0, E3B15-0 and E3C15-0
bits set the coefficient of EQ3. E4A15-0, E4B15-0 and E4C15-0 bits set the coefficient of EQ4. E5A15-0, E5B15-0 and
E5C15-0 bits set the coefficient of EQ5. Each EQ coefficient setting should be made when the corresponding EQ bit is
“0” or PMPFIL bit “0”.
fs : The Sampling frequency
fo1 ~ fo5 : The Center frequency
fb1 ~ fb5 : The Band width where the gain is 3dB different from center frequency
K1 ~ K5 : The Gain ( -1 ≤ Kn < 3 )
Register setting (Note 33)
EQ1: E1A[15:0] bits = A1, E1B[15:0] bits = B1, E1C[15:0] bits =C1
EQ2: E2A[15:0] bits = A2, E2B[15:0] bits = B2, E2C[15:0] bits =C2
EQ3: E3A[15:0] bits = A3, E3B[15:0] bits = B3, E3C[15:0] bits =C3
EQ4: E4A[15:0] bits = A4, E4B[15:0] bits = B4, E4C[15:0] bits =C4
EQ5: E5A[15:0] bits = A5, E5B[15:0] bits = B5, E5C[15:0] bits =C5
(MSB=E1A15, E1B15, E1C15, E2A15, E2B15, E2C15, E3A15, E3B15, E3C15, E4A15, E4B15, E4C15,
E5A15, E5B15, E5C15;
LSB= E1A0, E1B0, E1C0, E2A0, E2B0, E2C0, E3A0, E3B0, E3C0, E4A0, E4B0, E4C0, E5A0, E5B0, E5C0)
tan (πfbn/fs)
An = Kn x
2
, Bn = cos(2π fon/fs) x
1 + tan (πfbn/fs)
1 + tan (πfbn/fs)
,
Cn =
1 − tan (πfbn/fs)
1 + tan (πfbn/fs)
(n = 1, 2, 3, 4, 5)
Transfer Function
H(z) = ( 1 + h2(z) + h3(z) + h4(z) + h5(z) ) x {1 + h1(z)}
1 − z −2
hn (z) = An
1− Bnz −1− Cnz −2
(n = 1, 2, 3, 4, 5)
The center frequency should be set as below
fon / fs < 0.497
When gain of K is set to “−1”, the equalizer becomes notch filter. The central frequency of a real notch filter deviates from
the above calculation, if the central frequency of each band is near. The control soft that is attached to the evaluation board
has a function that revises a gap of frequency, and calculates the coefficient. When the central frequency of each band is
near, revise the central frequency and confirm the frequency response.
Note 33.
[Translation the filter coefficient calculated by the equations above from real number to binary code (2’s complement)]
X = (Real number of filter coefficient calculated by the equations above) x 213
X should be rounded to integer, and then should be translated to binary code (2’s complement).
MSB of each filter coefficient setting register is sine bit.
MS1012-E-01
2010/08
- 46 -
[AK4636]
■ Input Digital Volume (Manual Mode)
When ADCPF bit = “1” and ALC1 bit = “0”, the ALC block becomes an input digital volume (manual mode). The digital
volume’s gain is set by IVOL7-0 bits as shown in Table 22. The IVOL value is changed at zero cross or zero cross time
out. The zero crossing timeout period is set by ZTM1-0 bits.
IVOL7-0bits
F1H
F0H
EFH
:
92H
91H
90H
:
2H
1H
0H
GAIN(0dB)
Step
+36.0
+35.625
+35.25
:
0.375dB
+0.375
0.0
-0.375
:
-53.625
-54.0
MUTE
Table 22. Input Digital Volume Setting
(default)
When writing to the IVOL7-0 bits continually, the control register should be written in an interval more than zero
crossing timeout. If not, a zero crossing counter is reset at each time and the volume will not be changed. However, it
could be ignored when writing the same register value as the last time. At this time, zero crossing counter is not reset, so
it can be written in an interval less than zero crossing timeout.
MS1012-E-01
2010/08
- 47 -
[AK4636]
■ Output Digital volume (Manual mode)
When ADCPF bit = “0” and ALC2 bit = “0”, the ALC block becomes an output digital volume (manual mode). The
digital volume’s gain is set by OVOL7-0 bits as shown in Table 23. The OVOL7-0 bits value are reflected to this output
volume at zero cross or zero cross time out. The zero crossing timeout period is set by ZTM1-0 bits.
OVOL7-0bits
F1H
F0H
EFH
:
92H
91H
90H
:
2H
1H
0H
GAIN(0dB)
Step
+36.0
+35.625
+35.25
:
0.375dB
+0.375
0.0
-0.375
:
-53.625
-54.0
MUTE
Table 23 Output Digital Volume Setting
(default)
When writing to the OVOL7-0 bits continually, the control register should be written by an interval more than zero
crossing timeout. If not, a zero crossing counter is reset at each time and the volume will not be changed. However, It
could be ignored when writing a same register value as the last time. At this time, zero crossing counter is not reset, so it
can be written by an interval less than zero crossing timeout.
■ Output Digital Volume2
AK4636 has 4 steps output volume in addition to the volume setting by OVOL7-0 bits. This volume is set by DATT1-0
bits as shown in Table 24.
DATT1-0bits
0H
1H
2H
3H
GAIN(0dB)
Step
0.0
(default)
6.0dB
-6.0
-12.0
-18.1
Table 24. Output Digital Volume2 Setting
MS1012-E-01
2010/08
- 48 -
[AK4636]
■ Output Digital Volume3
The AK4636 has a digital output volume (DVOL) with 256 levels in linear steps (Table 24). The volume can be set by the
DVL7-0 and DVR7-0 bits. The volume is included in front of a DAC block. The input data of DAC is changed from
+0.35 to –47.78dB or MUTE. The volume calculating formula is shown in Table 26.
DVOL7-0 bits
FFH
FEH
:
F5H
:
02H
01H
00H
ATT_DATA
GAIN(0dB)
255
+0.35
254
+0.31
:
:
245
0
(default)
:
:
2
-41.76
1
-47.78
Mute
Table 25. Output Digital Volume3 Setting
DVOL7-0 bits
GAIN (dB)
FFH
0.35 + 20 log10 (ATT_DATA / 255)
:
01H
00H
Mute
Table 26. Output Digital Volume3 Formula
MS1012-E-01
2010/08
- 49 -
[AK4636]
■ ALC Operation
The ALC (Automatic Level Control) is operated by ALC block. When ADCPF bit = “1”, ALC operation is enable at
recording path. When ADCPF bit = “0”, ALC operation is enable at playback path. ON/OFF switching of ALC operation
is controlled by ALC1 bit for recording and ALC2 bit for playback.
1.
ALC Limiter Operation
During the ALC limiter operation, if the output data exceeds the ALC limiter detection level (Table 27), the volume value
is automatically attenuated by the amount defined in LMAT1-0 bits (Table 28).
When ZELMN bit = “0” (zero cross detection valid), the IVL and VOL value is changed by ALC limiter operation at the
individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing timeout
period of both ALC limiter and recovery operation (Table 29). When ALC output level exceeds full-scale at LFST bit =
“1”, VOL value is immediately (Period: 1/fs) changed in 1 step. When ALC output level is less than full-scale, VOL value
is changed at the individual zero crossing point of each channels or at the zero crossing timeout.
When ZELMN bit = “1” (zero cross detection invalid), VOL value is immediately (period: 1/fs) changed by ALC limiter
operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits.
After completing the attenuate operation, unless ALC bit is changed to “0”, the operation repeats when the input signal
level exceeds the ALC limiter detection level.
LMTH1
0
0
1
1
LMTH0 ALC Limiter Detection Level ALC Recovery Waiting Counter Reset Level
0
ALC Output ≥ −2.5dBFS
−2.5dBFS > ALC Output ≥ −4.1dBFS
1
ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
0
ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
1
ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
Table 27. ALC Limiter Detection Level / Recovery Waiting Counter Reset Level
(default)
ALC1 Limiter ATT Step
LMAT1
LMAT0
0
0
1
1
0
1
0
1
ZTM1
ZTM0
0
0
1
1
0
1
0
1
ALC1 Output ALC1 Output
≥ LMTH
≥ FS
ALC1 Output
≥ FS + 6dB
ALC1 Output
≥ FS + 12dB
1
1
1
2
2
2
2
4
4
1
2
4
Table 28. ALC Limiter ATT Step Setting
Zero Crossing Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 29. ALC Zero Crossing Timeout Period Setting
MS1012-E-01
1
2
8
8
(default)
(default)
2010/08
- 50 -
[AK4636]
2.
ALC Recovery Operation
The ALC recovery operation waits for the WTM2-0 bits (Table 30) to be set after completing the ALC limiter operation.
If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 27) during the wait time, the ALC
recovery operation is executed. The VOL value is automatically incremented by RGAIN1-0 bits (Table 31) up to the set
reference level (Table 32, Table 33) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 29).
The ALC recovery operation is executed in a period set by WTM2-0 bits.
For example, when the current VOL value is 30H and RGAIN1-0 bits are set to “01”(2 steps), VOL is changed to 32H by
the auto limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When the VOL value
exceeds the reference level (IREF7-0 or OREF5-0), the VOL values are not increased.
When
“ALC recovery waiting counter reset level (LMTH1-0) ≤ Output Signal < ALC limiter detection level (LMTH1-0)”
during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When
“ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”,
the waiting timer of ALC recovery operation starts.
The ALC operation corresponds to the impulse noise. When the impulse noise is input, the ALC recovery operation
becomes faster than a normal recovery operation. When large noise is input to microphone instantaneously, the quality of
small level in the large noise can be improved by this fast recovery operation. The speed of first recovery operation is set
by RFST1-0 bits (Table 34).
WTM2
WTM1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
ALC Recovery Operation Waiting Period
8kHz
16kHz
44.1kHz
0
128/fs
16ms
8ms
2.9ms
1
256/fs
32ms
16ms
5.8ms
0
512/fs
64ms
32ms
11.6ms
1
1024/fs
128ms
64ms
23.2ms
0
2048/fs
256ms
128ms
46.4ms
1
4096/fs
512ms
256ms
92.9ms
0
8192/fs
1024ms
512ms
185.8ms
1
16384/fs
2048ms
1024ms
371.5ms
Table 30. ALC Recovery Operation Waiting Period
WTM0
RGAIN1
0
0
1
1
RGAIN0
GAIN STEP
0
1
0.375dB
1
2
0.750dB
0
3
1.125dB
1
4
1.500dB
Table 31. ALC Recovery GAIN Step
MS1012-E-01
(default)
(default)
2010/08
- 51 -
[AK4636]
IREF7-0bits
GAIN(0dB)
Step
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
C5H
+19.5
(default)
0.375dB
:
:
92H
+0.375
91H
0.0
90H
-0.375
:
:
2H
-53.625
1H
-54.0
0H
MUTE
Table 32. Reference Level at ALC Recovery operation for recoding
OREF5-0bits
GAIN(0dB)
Step
3CH
+36.0
3BH
+34.5
3AH
+33.0
:
:
28H
+6.0
(default)
1.5dB
:
:
25H
+1.5
24H
0.0
23H
-1.5
:
:
2H
-51.0
1H
-52.5
0H
-54.0
Table 33. Reference Level at ALC Recovery operation for playback
RFST1 bit
RFST0 bit
Recovery Speed
0
0
4 times
(default)
0
1
8 times
1
0
16times
1
1
N/A
Table 34. First Recovery Speed Setting (N/A: Not available)
MS1012-E-01
2010/08
- 52 -
[AK4636]
3.
The Volume at the ALC Operation
The current volume value at the ALC operation is reflected in VOL7-0 bits. It is enable to check the current volume value
by reading the register value of VOL7-0 bits.
VOL7-0bits
GAIN(0dB)
F1H
F0H
EFH
:
C5H
:
92H
91H
90H
:
2H
1H
0H
+36.0
+35.625
+35.25
:
+19.5
:
+0.375
0.0
−0.375
:
−53.625
−54.0
MUTE
Table 35. Value of VOL7-0 bits
4.
Example of the ALC Operation for Recording
Table 36 shows the examples of the ALC setting for a microphone recording.
Register Name
LMTH1-0
ZELM
ZTM1-0
WTM2-0
IREF7-0
IVOL7-0
LMAT1-0
LFST
RGAIN1-0
ALC1
FRSL1-0
fs=8kHz
Operation
−4.1dBFS
Enable
16ms
Comment
Data
Limiter detection Level
01
Limiter zero crossing detection
0
Zero crossing timeout period
00
Recovery waiting period
*WTM1-0 bits should be more than or
000
16ms
equal to ZTM1-0 bits
Maximum gain at recovery operation
C5H
19.5dB
Gain of IVOL
C5H
19.5dB
Limiter ATT step
00
1step
Fast Limiter Operation
1
ON
Recovery GAIN step
00
1 step
ALC enable
1
Enable
Speed of Fast Recovery
00
4 times
Table 36. Example of the ALC Setting (Recording)
MS1012-E-01
Data
01
0
01
fs=16kHz
Operation
−4.1dBFS
Enable
16ms
001
16ms
C5H
C5H
00
1
00
1
00
19.5dB
19.5dB
1step
ON
1 step
Enable
4times
2010/08
- 53 -
[AK4636]
5.
Example of ALC for Playback Operation
Table 37 shows the example of the ALC setting for playback.
fs=8kHz
Operation
−4.1dBFS
Enable
16ms
Register Name
Comment
LMTH1-0
ZELM
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM1-0 bits should be more than or
000
16ms
equal to ZTM1-0 bits
Maximum gain at recovery operation
28
+6dB
Gain of IVOL
91
0dB
Fast Limiter Operation
1
ON
Limiter ATT step
00
1step
Recovery GAIN step
00
1 step
ALC enable
1
Enable
Speed of Fast Recovery
00
4 times
Table 37. Examples of the ALC Setting (Playback)
WTM2-0
OREF5-0
OVOL7-0
LFST
LMAT1-0
RGAIN1-0
ALC2
FRSL1-0
Data
01
0
00
MS1012-E-01
Data
01
0
01
fs=16kHz
Operation
−4.1dBFS
Enable
16ms
001
16ms
28
91
1
00
00
1
00
+6dB
0dB
ON
1step
1 step
Enable
4 times
2010/08
- 54 -
[AK4636]
6.
Noise Suppression
The Noise Suppression is enabled when NSCE bit (Noise suppression enable bit) = “1” during ALC operation (ALC1 bit
= “1”). This function attenuates output signal level automatically when minute amount of the signal is input.
NSCE bit: Noise Suppression Enable
0: Disable (default)
1: Enable
(1)
Noise Level Suppressing Operation
The output signal (Note 34) is suppressed when the input peak level is lower than “Noise Suppression Threshold Low
Level” set by NSTHL3-0 bits (Table 38) during the waiting time set by WTM2-0 bits (Table 30).
VOL value is changed by this noise suppressing operation only at the individual zero crossing points of Lch and Rch or at
the zero crossing timeout. Noise level suppressing operation has common zero cross timeout period to ALC recovery
operation which is set by ZTM1-0 bits. (Table 29)
This operation sets the volume automatically to the reference level (Table 42) with zero cross detection in the period
which is set by ZTM1-0 bits (Table 29). It is executed in the cycle of WTM2-0 bits settings.
Note 34. When the input signal volume is smaller than the value set by NSREF7-0 bits, normal ALC recovery operation
is executed.
NSTHL3
NSTHL2
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
Noise Suppression
Threshold Low Level
0
0
−81dB
0
1
−78dB
1
0
−75dB
1
1
−72dB
0
0
−69dB
0
1
−66dB
1
0
−63dB
1
1
−60dB
0
0
−57dB
0
1
−54dB
1
0
−51dB
Table 38. Noise Suppression Threshold Low Level
NSTHL1
NATT1 bit
0
0
1
1
NSTHL0
Step
(default)
3dB
NATT0 bit
ATT STEP
0
1/4 (Note 35)
1
1/2 (Note 36) (default)
0
1
1
2
Table 39. Noise ATT Settings
Note 35. 1step attenuated in 4 x “WTM cycles”.
Note 36. 1step attenuated in 2 x “WTM cycles”.
MS1012-E-01
2010/08
- 55 -
[AK4636]
ZTM1 bit
ZTM0 bit
0
0
1
1
0
1
0
1
Zero Cross Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 29. ALC Zero Cross Timeout Period Settings
(default)
(2) Noise Level Hold
During the waiting time set by WTM2-0 bits (Table 3), VOL values are kept when the input signal peak level is in
between the set value of NSTHH1-0 (Note 37) and Noise Suppression Threshold Low Level (Noise Suppression High
Level >input signal level ≥ Noise Suppression Threshold Low Level) therefore the output signal level does not change.
NSTHH1 bit NSTHH0 bit Noise Suppression High Level (Note 37)
0
0
NSTHL3-0bits + 3dB
(default)
0
1
NSTHL3-0bits + 6dB
1
0
NSTHL3-0bits + 9dB
1
1
NSTHL3-0bits + 12dB
Note 37. Noise Suppression Threshold Low Level (NSTHL3-0 bits) + Gain (NSTHH1-0 bits) = Noise Suppression High
Level
Table 40. Noise Suppression High Level Settings
(3) Noise Suppression → Normal ALC Operation
During noise suppressing operation, if the input signal level exceeds Noise Suppression High Level, the operation
switches to normal ALC operation from noise suppressing or noise level hold operation. In this case, recovery speed is
faster than the normal recovery. (Table 41)
When the internal volume level is lower than noise suppressing operation reference level (set by NSREF7-0 bits), the
recovery speed to ALC operation from noise suppressing operation is the same as normal ALC recovery speed.
NSGAIN1 bit
NSGAIN0 bit
Recovery Speed
0
0
8 step
0
1
12 step
(default)
1
0
16 step
1
1
28 step
Table 41. Fast Recovery Speed Setting from Noise Suppression to ALC Operation
MS1012-E-01
2010/08
- 56 -
[AK4636]
NSREF7-0 bits
GAIN[dB]
Step
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
C5H
+19.5
0.375dB
:
:
92H
+0.375
91H
0.0
(default)
90H
−0.375
:
:
2H
−53.625
1H
−54.0
0H
MUTE
Table 42. Reference Value Setting when Noise Suppression is ON
MS1012-E-01
2010/08
- 57 -
[AK4636]
7.
Example of ALC Operation
The following registers must not be changed during the ALC operation. These bits should be changed, after the ALC
operation is finished by ALC1 bit = ALC2 bit = “0” or PMPFIL bit = “0”. When ALC is restarted, after ALC1 bit and
ALC2 bit set to “0” or PMPFIL bit sets to “0”, the waiting time of zero crossing timeout is not needed.
LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, IREF7-0/OREF5-0, ZELM,
RFST1-0, LFST, NSCE, NSTHL3-0, NSTHH1-0, NSGAIN1-0, NSREF7-0 bits
Example:
Limiter = Zero crossing Enable
Manual Mode
Recovery Cycle = 16ms@8kHz
Limiter and Recovery Step = 1
WR (ZTM1-0, WTM2-0)
LFST = 1
Maximum Gain = +19.5dB
Limiter Detection Level = −4.1dBFS
WR (IREF7-0/OREF5-0)
ALC1 bit = “1”
WR (IVOL7-0/OVOL7-0)
*1
(1) Addr=06H, Data=00H
WR (RGAIN1, LMTH1,RFST1-0)
(2) Addr=08H, Data=C5H
WR (LFST,LMAT1-0, RGAIN0, ZELMN, LMTH0)
WR (ALC1= “1”)
(3) Addr=09H, Data=C5H
*2
ALC Operation
(4) Addr=0BH, Data=28H
(5) Addr=07H, Data=A1H
Note. WR: Write
*1: The value of volume at starting should be the same or smaller than REF’s.
*2: When setting ALC1 bit or ALC2 bit to “0”, the operation is shifted to manual mode after passing the zero crossing
time set by ZTM1-0 bits.
Figure 47. Registers set-up sequence at the ALC operation
MS1012-E-01
2010/08
- 58 -
[AK4636]
■ SOFTMUTE
Soft mute operation is performed in the digital input domain. When the SMUTE bit changes to “1”, the input signal is
attenuated by −∞ (“0”) in 245/fs cycles (31msec@fs=8kHz, DVOL bits = F5H). When the SMUTE bit is returned to “0”,
the mute is cancelled and the input attenuation gradually changes to 0dB in 245/fs cycles (31msec@fs=8kHz, DVOL bits
= F5H). If the soft mute is cancelled within the 245/fs cycles (31msec@fs=8kHz, DVOL bits = F5H), the attenuation is
discontinued and returned to 0dB. The soft mute for Playback operation is effective for changing the signal source
without stopping the signal transmission.
S M U T E bit
245/fs
0dB
245/fs
(1)
(3)
A ttenuation
-∞
GD
(2)
GD
A nalog O utput
Figure 48. Soft Mute Function
(1) The input signal is attenuated by −∞ (“0”) in 245/fs cycles (31msec@fs=8kHz, DVOL bits = F5H).
(2) Analog output corresponding to digital input has group delay (GD).
(3) If the soft mute is cancelled within the 245/fs cycles (31msec@fs=8kHz, DVOL bits = F5H), the attenuation is
discounted and returned to 0dB within the same cycle.
MS1012-E-01
2010/08
- 59 -
[AK4636]
■ BEEP input and Generating Circuit
The AK4636 has the BEEP pin (external signal input pin) and BEEP generating circuit.
BEEP Mode can be set by BPM1-0 bits.
BPM1 bit
0
BPM0 bit
0
BEEP Mode
Disable
BEEP pin
1
(Internal Resisitance mode)
BEEP pin
0
(External Resisitance mode)
1
BEEP Generator mode
Table 43. BEEP Mode Settings
0
1
1
(default)
1. BEEP input pin (BPM1-0 bits =“01” or “10”)
When BMP1-0 bits = “01” or “10”, the input signal to BEEP pin is output from the speaker amplifier by setting BEEPS
bits to “1”, and it is output from Mono lineout amplifier by setting BEEPA bit to “1”.
BPM1-0 bits = “10”
Ri can control the BEEP signal gain which is in invert proportional to Ri resister value (Figure 49). The gain setting can
not be made by BPLVL2-0 bits.
BPM1-0 bits = “01”
The BEEP signal gain is controlled by BPLVL2-0 bits (Table 46). Ri is not necessary.
33kΩ ± 30%
Ci
Ri
-
BEEP
+
Figure 49. Block Diagram of BEEP pin (BPM1-0 bits =“10”)
SPKG1-0 bits
BEEP → SPP/SPN Gain
00
+10.6dB
01
+12.6dB
10
+14.6dB
11
+16.6dB
Table 44.BEEP → SPK Output Gain
LOVL bit
BEEP → AOUT Gain
0
0dB
1
+3dB
Table 45.BEEP → AOUT Output Gain
MS1012-E-01
2010/08
- 60 -
[AK4636]
AOUT
SPK
(LOVL =“0”) (SPKG1-0 bits = “00”)
0
0
0dB
1.5Vpp
5.08Vpp
(default)
0
1
1.06Vpp
3.60Vpp
−3dB
1
0
0.75Vpp
2.55Vpp
−6dB
1
1
0.38Vpp
1.28Vpp
−12dB
0
0
0.19Vpp
0.64Vpp
−18dB
0
1
0.10Vpp
0.36Vpp
−23dB
1
0
0.05Vpp
0.18Vpp
−29dB
1
1
0.03Vpp
0.10Vpp
−34dB
Table 46. BEEP Output Gain Setting when BPM 1-0 bits = “01” (BEEP input =1.5Vpp)
BPLVL2
0
0
0
0
1
1
1
1
BPLVL1
BPLVL0
BEEP Gain
2. BEEP Signal Generating Circuit
The AK4636 integrates a BEPP signal generating circuit. When BPM 1-0 bits = “11”, the speaker amplifier outputs
BEEP signal by setting BEEPS bit = “1”, and the Mono lineout amplifier outputs BEEP signal by setting BEEPA bit =
“1”.
After outputting the signal during the time set by BPON7-0 bits, the AK4636 stops the output signal during the time set by
BPOFF7-0 bits (Figure 50). The repeat count is set by BPTM6-0 bit, and the output level is set by BPLVL2-0 bits. When
BPCNT bit is “0”, if BPOUT bit is written “1”, the AK4636 outputs the beep for the times of repeat count. When the
output is finished, BPOUT bit is set to “0” automatically. When BPCNT bit is set to “1”, it outputs the beep in succession
regardless of repeat count, on-time and off-time. The output frequency is set by BPFR1-0 bits.
< Setting parameter >
1) Output Frequency ( Table 47 ~ Table 49)
2) ON Time (Table 50)
3) OFF Time (Table 51)
4) Repeat Count (Table 52)
5) Output Level (Table 53)
* BPFR1-0, BPON7-0, BPOFF7-0, BPTM6-0 and BPLVL3-0 bits should be set when BPOUT
=BPCNT = “0”.
* BPCNT bit is given priority in BPOUT bit. When BPOUT bit be set to “1”, if BPCNT bit is set to
“0”, BPOUT bit is set to “0” forcibly.
* When stopping the BEEP outputs by changing BPCNT bit to “0” from “1”, writing to BPOUT bit
and BPCNT bit are inhibited for 10ms.
BEEP Output
ON Time
OFF Time
Repeat Count
Figure 50. BEEP Signal Output
MS1012-E-01
2010/08
- 61 -
[AK4636]
Output frequency of BEEP Generator [Hz]
fs = 44.1kHz system
fs = 48kHz system
(Note 39)
(Note 38)
00
4000
4009
(default)
01
2000
2005
10
1000
1002
11
N/A
Note 38. Sampling frequency is 8kHz, 16kHz, 32kHz or 48kHz.
Note 39. Sampling frequency is 11.025kHz, 22.05kHz or 44.1kHz.
Table 47. Beep signal frequency (PLL Master/Slave Mode: reference clock: MCKI) (N/A: Not available)
BPFR1-0 bit
Output frequency of BEEP Generator [Hz]
BPFR1-0 bit
FS3-2 bits = “00”
FS3-2 bits = “01”
FS3-2 bits = “10”
00
fs/2.75
fs/5.5
fs/11
(default)
01
fs/5.5
fs/11
fs/22
10
fs/11
fs/22
fs/44
11
N/A
Table 48. Beep signal frequency ( PLL Slave Mode: reference clock : FCK/BICK) (N/A: Not available)
BPFR1-0 bit
00
01
10
11
Output frequency of BEEP Generator [Hz]
FS1-0 bits = “01”
FS1-0 bits = “10”
FS1-0 bits = “11”
fs/2.75
fs/55
fs/11
fs/5.5
fs/11
fs/22
fs/11
fs/22
fs/44
N/A
Table 49. Beep signal frequency (EXT Slave/Master Mode) (N/A: Not available)
FS1-0 bits = “00”
fs/11
fs/22
fs/44
(default)
ON Time of BEEP Generator [msec]
Step [msec]
fs = 48kHz
fs = 44.1kHz
fs = 48kHz
fs = 44.1kHz
system
system
system
system
(Note 38)
(Note 39)
(Note 38)
(Note 39)
0H
8.0
7.98
8.0
7.98
(default)
1H
16.0
15.86
2H
24.0
23.95
3H
32.0
31.93
4H
40.0
39.9
:
:
FDH
2032
2027.3
FEH
2040
2035.3
FFH
2048
2043.4
Note 38. Sampling frequency is 8kHz, 16kHz, 32kHz or 48kHz.
Note 39. Sampling frequency is 11.025kHz, 22.05kHz or 44.1kHz.
Table 50. Beep output ON-time (PLL Master/Slave Mode reference clock: MCKI)
BPON7-0 bit
MS1012-E-01
2010/08
- 62 -
[AK4636]
OFF Time of BEEP Generator [msec]
Step [msec]
fs = 48kHz
fs = 44.1kHz
fs = 48kHz
fs = 44.1kHz
system
system
system
system
(Note 38)
(Note 39)
(Note 38)
(Note 39)
0H
8.0
7.98
8.0
7.98
(default)
1H
16.0
15.86
2H
24.0
23.95
3H
32.0
31.93
4H
40.0
39.9
:
:
:
FDH
2032
2027.3
FEH
2040
2035.3
FFH
2048
2043.4
Note 38. Sampling frequency is 8kHz, 16kHz, 32kHz or 48kHz.
Note 39. Sampling frequency is 11.025kHz, 22.05kHz or 44.1kHz.
Table 51. Beep output OFF-time (PLL Master/Slave Mode reference clock: MCKI)
BPOFF7-0 bit
BPTM6-0 bit
Repeat Count
0H
1
(default)
1H
2
2H
3
3H
4
:
:
7DH
126
7EH
127
7FH
128
Table 52. Beep output Repeat Count
BPLVL2-0 bits
Beep Output Level
STEP
0H
0dB
(default)
3dB
1H
−3dB
2H
−6dB
−12dB
3H
6dB
4H
−18dB
5H
5dB
−23dB
6dB
6H
−29dB
5dB
7H
−34dB
Note 40. Beep output amplitude in 0dB setting is 1.5Vpp (LOVL bit = “0”) from AOUT, and 5.08Vpp @8Ω
(SPKG1-0 bits = “00”) from the speaker amplifier.
Table 53. Beep Output Level
MS1012-E-01
2010/08
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[AK4636]
■ MONO LINE OUTPUT (AOUT pin)
A signal of DAC is output from the AOUT pin. When the DACA bit is “0”, this output is OFF. When the LOVL bit is “1”,
this gain changes to +3dB (large amplitude outputs may clip). The load resistance is 10kΩ(min). When PMAO bit is “0”
and AOPS bit is “0”, the mono line output enters power-down state and it is pulled down by 100Ω(typ). If PMAO bit is
controlled when AOPS bit = “1”, POP noise will be reduced at power-up and down. Then, this line should be pulled down
by 20kΩ of resister after C-coupling shown in Figure 51. This rising and falling time is max 300 ms at C = 1.0μF. When
PMAO bit is “1” and AOPS bit is “0”, the mono line output enters power-up state.
DAC
Input Level
AOUT
LOVL bit
Gain
OUT
0
0dB
1.5Vpp
0dBFS
1
+3dB
2.12Vpp
Table 54. Mono Line Output Volume Setting
1μF
AOUT
(default)
220Ω
20kΩ
Figure 51. AOUT External Circuit when Using POP Reduction Function
AOUT Control Sequence in case of using POP Reduction Circuit
(2 )
(5 )
P M A O b it
(1 )
(3 )
(4 )
(6 )
A O P S b it
A O U T p in
N o r m a l O u tp u t
≥ 300 m s
≥ 300 m s
Figure 52. Mono Line Output Control Sequence when using POP Reduction Function
(1) Set AOPS bit = “1”. Mono line output enters the power-save mode.
(2) Set PMAO bit = “1”. Mono line output exits the power-down mode.
AOUT pin rises up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1μF.
(3) Set AOPS bit = “0” after AOUT pin rises up. Mono line output exits the power-save mode.
Mono line output is enabled.
(4) Set AOPS bit = “1”. Mono line output enters power-save mode.
(5) Set PMAO bit = “1”. Mono line output enters power-down mode.
AOUT pin falls down to VSS1. Fall time is 200ms (max 300ms) at C=1μF.
(6) Set AOPS bit = “0” after AOUT pin falls down. Mono line output exits the power-save mode.
MS1012-E-01
2010/08
- 64 -
[AK4636]
■ Speaker Output
AK4636 has a Mono Class-D Speaker-Amp. Power supply for Speaker-Amp can be set from 2.6V up to 3.6V.
The output signal from DAC is input to the Speaker-amp. This Speaker-amp is a mono output controlled by BTL and the
gain of Speaker-Amp is set by SPKG1-0 bits. The output voltage is depend on SPKG1-0 bits.
DAC
SPK-amp
Output Level
SPKG1-0 bits
Gain
OUT (R=8Ω)
00
10.6dB
3.17Vpp
157mW
(default)
01
12.6dB
4.00Vpp
250mW
-4.1dBFS 0.94Vpp
10
14.6dB
5.03Vpp
395mW
11
N/A
N/A
N/A
Note 41. The setting of SPKG1-0 bits = “01” is recommended when 8Ω dynamic speaker is connected.
The SPK-Amp Power is 250mW at 8Ω Load Resistance and 4.0Vpp output level.
Table 55. SPK- Amp Gain
< Speaker-Amp Control Sequence >
Speaker-Amp is powered-up/down by PMSPK bit. When PMSPK bit is “0”, both SPP and SPN pins are in Hi-Z state.
When PMSPK bit is “1” and SPPSN bit is “0”, the Speaker-Amp enters power-save mode. In this mode, the SPP pin is
placed in Hi-Z state and the SPN pin outputs SVDD/2 voltage.
When the PMSPK bit is “1” after the PDN pin is changed from “L” to “H”, the SPP and SPN pins are powered-up in
power-save-mode. In this mode, the SPP pin is placed in a Hi-Z state and the SPN pin goes to SVDD/2 voltage and pop
noise can be reduced. When the AK4646 is powered-down, pop noise can be also reduced by first entering
power-save-mode.
PMSPK bit
SPPSNbit
SPP pin
SPN pin
Hi-Z
Hi-Z
Hi-Z
SVDD/2
SVDD/2
>t1(Note)
Hi-Z
>0
(Note)
SPPSN bit should be set to “1” at more than 1ms after PMSPK bit is set to “1”. When BEEP Input Amp and Speaker Amp
are powered-up at the same time, SPPSN bit should be set to “1” after BEEP Input become stable. When the resistance
and capacitance of BEEP pin are R=33kΩ and C=0.1μF, 16.5ms(=5τ) is required for BEEP Input to become stable.
Figure 53. Power-up/Power-down Timing for Speaker-Amp
MS1012-E-01
2010/08
- 65 -
[AK4636]
■ Video Block
The AK4636 has a Video-Amp with drivability for a load resistance of 150Ω. It has a composite input and output. A Low
Pass Filter (LPF) and Gain Control Amp (GCA) are integrated and DC output is supported as shown in Figure 54. The
output clamp voltage is 50 mV(typ) at DC output. The gain control and the step are shown in Table 56. The gain can be set
by VGCA4-0 bits. PMV bit controls the power up and down of the video block. The VOUT pin outputs 0V at PMV bit =
“0”. When no data is input to the VIN pin, PMV bit must be “0”.
VIN
0.1uF (±50% )
75Ω
CLAMP
LPF
GCA
-1dB ~ +10.5dB
Step 0.5dB
+6dB
VOUT
Figure 54. Video Block
VGCA4-0 bits
GAIN(dB)
STEP
17H
+10.5dB
16H
+10.0dB
15H
+9.5dB
0.5dB
:
:
04H
+1.0dB
03H
+0.5dB
02H
0.0dB
(default)
01H
−0.5dB
00H
−1.0dB
Table 56. Recommended Value of Video Input Resistance
■ Video Input
The video input signals must be C coupled by a 0.1μF (±50%) capacitor. The output impedance of video input signal
source should be 30Ω~390Ω(±5%).
MS1012-E-01
2010/08
- 66 -
[AK4636]
■ Serial Control Interface
(1) 3-wire Serial Control Mode
Internal registers may be written and read by the 3-wire µP interface pins (CSN, CCLK and CDTIO). The data on this
interface consists of Read/Write, Register address (MSB first, 7bits) and Control data (MSB first, 8bits). Address and data
is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. Data writing is valid on the rising
edge of the 16th CCLK after the falling edge of CSN. In reading operation, the CDTIO pin changes to output mode at the
falling edge of 8th CCLK and outputs D7-D0. The output finishes on the rising edge of CSN. However this reading
function is available only at READ bit = “1”. When READ bit = “0”, the CDTIO pin stays as Hi-Z even after the falling
edge of 8th CCLK. The CDTIO pin is placed in a Hi-Z state except outputting data at read operation mode. The clock
speed of CCLK is 5MHz (max). The value of internal registers is initialized at the PDN pin = “L”.
Note 42. A read operation is available at 00H ~ 11H, 1CH ~ 24H and 27H~30H addresses. When reading the address 12H
~ 1BH, 25H ~ 26H and 31H ~ 4FH, the register values are invalid.
CSN
0
CCLK
Clock, “H” or “L”
CDTIO
“H” or “L”
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Clock, “H” or “L”
A6 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
R/W:
A6-A0:
D7-D0:
“H” or “L”
READ/WRITE (“1”: WRITE, “0”: READ)
Register Address
Control data
Figure 55. Serial Control I/F Timing
MS1012-E-01
2010/08
- 67 -
[AK4636]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4636 supports the fast-mode I2C-bus (max: 400kHz). Pull-up resistors at SDA and SCL pins should be connected
to (DVDD+0.3)V or less voltage.
(2)-1. WRITE Operations
Figure 56 shows the data transfer sequence for I2C-bus mode. All commands are preceded by START condition. A HIGH
to LOW transition on the SDA line while SCL is HIGH indicates START condition (Figure 62). After the START
condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W).
The most significant seven bits of the slave address are fixed as “0010010” (Figure 57). If the slave address matches that
of the AK4636, the AK4636 generates an acknowledge and the operation is executed. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 63). A
R/W bit value of “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be
executed.
The second byte consists of the control register address of the AK4636. The format is MSB first, and those most
significant 1-bits are fixed to zeros (Figure 58). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 59). The AK4636 generates an acknowledge after each byte is received. A data transfer is always
terminated by STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH
defines STOP condition (Figure 62).
The AK4636 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4636
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 4FH prior to
generating stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 64) except for the START and STOP
conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 56. Data Transfer Sequence at the I2C-Bus Mode
0
0
1
0
0
1
0
R/W
A2
A1
A0
D2
D1
D0
Figure 57. The First Byte
0
A6
A5
A4
A3
Figure 58. The Second Byte
D7
D6
D5
D4
D3
Figure 59. Byte Structure after the second byte
MS1012-E-01
2010/08
- 68 -
[AK4636]
(2)-2. READ Operations
Set the R/W bit = “1” for READ operation of the AK4636. After a transmission of data, if the master generates an
acknowledge instead of terminating a write cycle, the internal 7-bit address counter of the AK4636 is incremented by one,
and the next data is automatically taken into the next address so that the data can be read from the AK4636. If the address
exceeds 4FH prior to generating a stop condition, the address counter will “roll over” to 00H and the data of 00H will be
read out.
Note 42. A read operation is available at 00H ~ 11H, 1CH ~ 24H and 27H~30H addresses. When reading the address 12H
~ 1BH, 25H ~ 26H and 31H ~ 4FH, the register values are invalid.
The AK4636 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4636 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address “n”, the next CURRENT READ operation would
access data from the address “n+1”. After receipt of the slave address with R/W bit “1”, the AK4636 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge but instead generates a stop condition, the AK4636
ceases transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
Data(n+1)
Data(n+2)
Data(n+x)
MA
AC
SK
T
E
R
MA
AC
SK
T
E
R
MA
AC
SK
T
E
R
A
C
K
P
MN
AA
SC
T
EK
R
MA
AC
SK
T
E
R
Figure 60. CURRENT ADDRESS READ
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave
address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4636 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge but instead generates a stop condition, the AK4636 ceases transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
MA
AC
S K
T
E
R
Data(n+x)
MA
AC
S
T K
E
R
MA
AC
S
T K
E
R
P
MN
A A
S
T C
E K
R
Figure 61. RANDOM ADDRESS READ
MS1012-E-01
2010/08
- 69 -
[AK4636]
SDA
SCL
S
P
start condition
stop condition
Figure 62. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 63. Acknowledge on the I2C-Bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 64. Bit Transfer on the I2C-Bus
MS1012-E-01
2010/08
- 70 -
[AK4636]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Mode Control 1
Mode Control 2
Timer Select
ALC Mode Control 1
ALC Mode Control 2
0BH
ALC Mode Control 3
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
Video Mode Control
ALC LEVEL
Signal Select 3
Digital Volume Control
Signal Select 4
Digital Filter Select 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
HPF Co-efficient 0
HPF Co-efficient 1
HPF Co-efficient 2
HPF Co-efficient 3
BEEP Frequency
BEEP ON Time
BEEP OFF Time
BEEP Repeat Count
BEEP VOL/Control
Reserved
Reserved
Digital MIC
BEEP Mode Select
Noise Suppression 1
Noise Suppression 2
Noise Suppression 3
LPF Co-efficient 0
LPF Co-efficient 1
LPF Co-efficient 2
LPF Co-efficient 3
Input Digital Volume Control
Output Digital Volume Control
D7
PMPFIL
PMV
SPPSN
PFSDO
PLL3
ADRST
0
LFST
IREF7
IVOL7
OVOL7
RGAIN
1
VDC1
VOL7
DATT1
DVOL7
0
0
0
0
0
0
0
0
0
0
0
0
F1A7
0
F1B7
0
BPCNT
BPON7
BPOFF7
0
BPOUT
0
0
0
0
0
0
NSREF7
F2A7
0
F2B7
0
D6
PMVCM
0
BEEPS
AOPS
PLL2
FCKO
WTM2
ALC2
IREF6
IVOL6
OVOL6
D5
PMBP
0
DACS
MGAIN1
PLL1
FS3
ZTM1
ALC1
IREF5
IVOL5
OVOL5
D4
PMSPK
0
DACA
SPKG1
PLL0
MSBS
ZTM0
ZELMN
IREF4
IVOL4
OVOL4
D3
PMAO
M/S
MGAIN3
SPKG0
BCKO1
BCKP
WTM1
LMAT1
IREF3
IVOL3
OVOL3
D2
PMDAC
0
PMMP
BEEPA
BCKO0
FS2
WTM0
LMAT0
IREF2
IVOL2
OVOL2
D1
0
MCKO
MGAIN2
PFDAC
DIF1
FS1
RFST1
RGAIN0
IREF1
IVOL1
OVOL1
D0
PMADC
PMPLL
MGAIN0
ADCPF
DIF0
FS0
RFST0
LMTH0
IREF0
IVOL0
OVOL0
LMTH1
OREF5
OREF4
OREF3
OREF2
OREF1
OREF0
VDC2
VOL6
DATT0
DVOL6
LOVL
0
0
0
0
0
0
0
0
0
0
0
F1A6
0
F1B6
0
0
BPON6
BPOFF6
BPTM6
0
0
0
0
0
NSCE
0
NSREF6
F2A6
0
F2B6
0
0
VOL5
SMUTE
DVOL5
LP
LPF
0
0
0
0
0
0
0
0
0
0
F1A5
F1A13
F1B5
F1B13
0
BPON5
BPOFF5
BPTM5
0
0
0
0
0
NSTHH1
NATT1
NSREF5
F2A5
F2A13
F2B5
F2B13
VGCA4
VOL4
MDIF
DVOL4
0
HPF
0
0
0
0
0
0
0
0
0
0
F1A4
F1A12
F1B4
F1B12
0
BPON4
BPOFF4
BPTM4
0
0
0
PMDM
0
NSTHH0
NATT0
NSREF4
F2A4
F2A12
F2B4
F2B12
VGCA3
VOL3
0
DVOL3
0
0
0
0
0
0
0
0
0
0
0
0
F1A3
F1A11
F1B3
F1B11
0
BPON3
BPOFF3
BPTM3
0
0
0
DCLKE
0
NSTHL3
0
NSREF3
F2A3
F2A11
F2B3
F2B11
VGCA2
VOL2
0
DVOL2
0
0
0
0
0
0
0
0
0
0
0
0
F1A2
F1A10
F1B2
F1B10
0
BPON2
BPOFF2
BPTM2
BPLVL2
0
0
DMPE
0
NSTHL2
0
NSREF2
F2A2
F2A10
F2B2
F2B10
VGCA1
VOL1
0
DVOL1
LIN
0
0
0
0
0
0
0
0
0
0
0
F1A1
F1A9
F1B1
F1B9
BPFR1
BPON1
BPOFF1
BPTM1
BPLVL1
0
0
DCLKP
BPM1
NSTHL1
NSGAIN1
NSREF1
F2A1
F2A9
F2B1
F2B9
VGCA0
VOL0
READ
DVOL0
0
1
0
0
0
0
0
0
0
0
0
0
F1A0
F1A8
F1B0
F1B8
BPFR0
BPON0
BPOFF0
BPTM0
BPLVL0
0
0
DMIC
BPM0
NSTHL0
NSGAIN0
NSREF 0
F2A0
F2A8
F2B0
F2B8
MS1012-E-01
2010/08
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[AK4636]
Addr
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
Register Name
Digital Filter Select 2
Reserved
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
D7
0
0
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
D6
0
0
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
E4A6
E4A14
E4B6
E4B14
E4C6
E4C14
E5A6
E5A14
E5B6
E5B14
E5C6
E5C14
D5
0
0
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
E4A5
E4A13
E4B5
E4B13
E4C5
E4C13
E5A5
E5A13
E5B5
E5B13
E5C5
E5C13
D4
EQ5
0
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
E4A4
E4A12
E4B4
E4B12
E4C4
E4C12
E5A4
E5A12
E5B4
E5B12
E5C4
E5C12
D3
EQ4
0
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
E4A3
E4A11
E4B3
E4B11
E4C3
E4C11
E5A3
E5A11
E5B3
E5B11
E5C3
E5C11
D2
EQ3
0
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
D1
EQ2
0
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
D0
EQ1
0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
The PDN pin = “L” resets the registers to their default values.
Note 43. The bits defined as 0 must contain a “0” value.
Note 44. The bits defined as 1 must contain a “1” value.
Note 45. Reading of address 12H ~ 1BH, 25H ~ 26H and 31H ~ 4FH are not possible.
Note 46. 0FH and 0DH are for address read only. Writing access to 0DH and 0FH does not effect the operation.
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■ Register Definitions
Addr
00H
Register Name
Power Management 1
R/W
Default
D7
PMPFIL
R/W
0
D6
PMVCM
R/W
0
D5
PMBP
R/W
0
D4
PMSPK
R/W
0
D3
PMAO
R/W
0
D2
PMDAC
R/W
0
D1
0
R
0
D0
PMADC
R/W
0
PMADC: ADC Block Power Control
0: Power down (default)
1: Power up
When the PMADC bit changes from “0” to “1”, the initialization cycle (1059/fs=133ms@8kHz) starts. After
initializing, digital data of the ADC is output.
PMDAC: DAC Block Power Control
0: Power down (default)
1: Power up
PMAO: Mono Line Out Power Control
0: Power down (default)
1: Power up
PMSPK: Speaker Amplifier Power Control
0: Power down (default)
1: Power up
PMBP: BEEP Input Power Management
0: Power down (default)
1: Power up
When PMBP bit = “0”, the path from BEEP to speaker is still connected. Set BEEPS bit = “0” to disconnect
this path. The path from BEEP to mono lineout is the same. It can be disconnected by setting BEEPA bit = “0”.
PMVCM: VCOM Block Power Control
0: Power down (default)
1: Power up
PMPFIL: Programmable Filter Block (HPF/ LPF/ 5-Band EQ/ ALC) Power Control
0: Power down (default)
1: Power up
All blocks can be powered-down by writing “0” to the address “00H”, PMPLL, PMV, PMMP, PMDM, DMPE and
MCKO bits. In this case, register values are maintained.
PMVCM bit must be “1” when one of bocks is powered-up. PMVCM bit can only be “0” when the address “00H”
and all power management bits (PMPLL, PMV, PMMP, PMDM, DMPE and MCKO) are “0”.
When using either ADC, DAC, digital microphone or Programmable Filter (PMADL bit = “1”, PMDM bit =”1”,
PMDAC bit = “1” or PMPFIL bit = “1”), clock must be supplied.
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Addr
01H
Register Name
Power Management 2
R/W
Default
D7
PMV
R/W
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
M/S
R/W
0
D2
0
R
0
D1
MCKO
R/W
0
D0
PMPLL
R/W
0
D4
DACA
R/W
0
D3
MGAIN3
R/W
0
D2
PMMP
R/W
0
D1
MGAIN2
R/W
0
D0
MGAIN0
R/W
1
PMPLL: PLL Block Power Control Select
0: PLL is Power down and External is selected. (default)
1: PLL is Power up and PLL Mode is selected.
MCKO: Master Clock Output Enable
0: “L” Output (default)
1: 256fs Output
M/S: Select Master/ Slave Mode
0: Slave Mode (default)
1: Master Mode
PMV: Video Block Power Control
0: Power down (default)
1: Power up
Addr
02H
Register Name
Signal Select 1
R/W
Default
D7
SPPSN
R/W
0
D6
BEEPS
R/W
0
D5
DACS
R/W
0
MGAIN3-2, MGAIN0: MIC-amp Gain control (Table 20)
MGAIN1 bit is located at D5 bit of 03H. Default: “0001” (+20.0dB)
PMMP: MPI pin Power Control
0: OFF (default)
1: ON
DACA: Switch Control from DAC to mono line amp
0: OFF (default)
1: ON
When PMAO bit is “1”, DACA bit is enabled. When PMAO bit is “0”, the AOUT pin goes VSS1.
DACS: Switch Control from DAC to Speaker-Amp
0: OFF (default)
1: ON
When DACS bit is “1”, DAC output signal is input to Speaker-Amp.
BEEPS: Switch Control from MIN pin to Speaker-Amp
0: OFF (default)
1: ON
When BEEPS bit is “1”, mono signal is input to Speaker-Amp.
SPPSN: Speaker-Amp Power-Save Mode
0: Power-Save Mode (default)
1: Normal Operation
When SPPSN bit is “0”, Speaker-Amp is on power-save mode. In this mode, the SPP pin goes to Hi-Z and
outputs SVDD/2 voltage. When PMSPK bit = “1”, SPPSN bit is enabled. After the PDN pin is set to “L”,
Speaker-Amp is in power-down mode since PMSPK bit is “0”.
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Addr
03H
Register Name
Signal Select 2
R/W
Default
D7
PFSDO
R/W
1
D6
AOPS
R/W
0
D5
MGAIN1
R/W
0
D4
SPKG1
R/W
0
D3
SPKG0
R/W
0
D2
BEEPA
R/W
0
D1
PFDAC
R/W
0
D0
ADCPF
R/W
0
ADCPF: Select input signal to Programmable Filter/ALC.
0: SDTI
1: Output of ADC (default)
PFDAC: Select input signal to DAC.
0: SDTI (default)
1: Output of Programmable Filter/ALC
BEEPA: Switch Control of BEEP signal to Mono-Amp
0: OFF (default)
1: ON
When PMAO bit=“1”, this bit is enabled. When PMAO bit=“0”, AOUT pin goes to VSS1.
SPKG1-0: Select Speaker-Amp Output Gain (Table 55)
Default: “00”
DACS
DAC
SPK
BEEPS
BEEP
DACA
BEEPA
AOUT
Figure 65. Speaker and Mono Lineout-Amps switch control
MGAIN1: Mic-Amplifier Gain Control (Table 20)
MGAIN3-2 and MGAIN0 bits are D3, D1 and D0 of 02H. Default: “0001” (+20.0dB)
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AOPS: Mono Line Output Power-Save Mode
0: Normal Operation (default)
1: Power-Save Mode
Power-save mode is enable at AOPS bit = “1”. POP noise at power-up/down can be reduced by changing at
PMAO bit = “1”. (Figure 52)
PFSDO: Select of signal from SDTO
0: Output of ADC (1st - HPF)
1: Output of Programmable Filter/ALC (default)
Addr
04H
Register Name
Mode Control 1
R/W
Default
D7
PLL3
R/W
0
D6
PLL2
R/W
0
D5
PLL1
R/W
0
D4
PLL0
R/W
0
D3
BCKO1
R/W
0
D2
BCKO0
R/W
1
D1
DIF1
R/W
1
D0
DIF0
R/W
0
D3
BCKP
R/W
0
D2
FS2
R/W
0
D1
FS1
R/W
0
D0
FS0
R/W
0
DIF1-0: Audio Interface Format (Table 16)
Default: “10” (MSB First)
BCKO1-0: Select BICK output frequency at Master Mode (Table 9)
Default: “01” (32fs)
PLL3-0: Select input frequency at PLL mode (Table 4)
Default: “0000” (FCK pin)
Addr
05H
Register Name
Mode Control 2
R/W
Default
D7
ADRST
R/W
0
D6
FCKO
R/W
0
D5
FS3
R/W
0
D4
MSBS
R/W
0
FS3-0: Setting of Sampling Frequency (Table 5 and Table 6) and MCKI Frequency (Table 11)
These bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
Default: “0000”
BCKP, MSBS: “00” (default) (Table 17)
FCKO: Select FCK output frequency at Master Mode (Table 10)
Default: “0”
ADRST: Initialization cycle setting of ADC
0: 1059/fs (default)
1: 291/fs
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Addr
06H
Register Name
Timer Select
R/W
Default
D7
0
R
0
D6
WTM2
R/W
0
D5
ZTM1
R/W
0
D4
ZTM0
R/W
0
D3
WTM1
R/W
0
D2
WTM0
R/W
0
D1
RFST1
R/W
0
D0
RFST0
R/W
0
WTM2-0: ALC1 Recovery Waiting Period (Table 30)
A period of recovery operation when any limiter operation does not occur during the ALC1 operation.
Default is “000”.
ZTM1-0: ALC1, ALC2, IVOL and OVOL Zero crossing timeout Period (Table 29)
The gain is changed by the manual volume controlling (ALC off) or the recovery operation (ALC on) only at
Zero crossing or timeout. The default value is “00”.
RFST1-0 : ALC First recovery Speed (Table 34)
Default: “00” (4times)
Addr
07H
Register Name
ALC Mode Control 1
R/W
Default
D7
LFST
R/W
0
D6
ALC2
R/W
0
D5
ALC1
R/W
0
D4
ZELMN
R/W
0
D3
LMAT1
R/W
0
D2
LMAT0
R/W
0
D1
RGAIN0
R/W
0
D0
LMTH0
R/W
1
LMTH1-0: ALC Limiter Detection Level / Recovery Waiting Counter Reset Level (Table 27)
LMTH1 bit is located at D6 bit of 0BH. Default: “01”
RGAIN1-0: ALC Recovery GAIN Step (Table 31)
RGAIN1 bit is located at D7 bit of 0BH. Default: “00”
LMAT1-0: ALC Limiter ATT Step (Table 28)
Default: “00”
ZELMN: Zero crossing detection enable at ALC Limiter operation
0: Enable (default)
1: Disable
ALC1: ALC of recoding path Enable
0: Disable (default)
1: Enable
ALC2: ALC2 of playback path Enable
0: Disable (default)
1: Enable
LFST: Limiter function of ALC when the output is bigger than Fs.
0: The volume value is changed at zero crossing or timeout. (default)
1: When output of ALC is bigger than FS, VOL value is changed instantly.
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Addr
08H
Register Name
ALC Mode Control 2
R/W
Default
D7
IREF7
R/W
1
D6
IREF6
R/W
1
D5
IREF5
R/W
0
D4
IREF4
R/W
0
D3
IREF3
R/W
0
D2
IREF2
R/W
1
D1
IREF1
R/W
0
D0
IREF0
R/W
1
IREF7-0: Reference value at ALC Recovery operation for recoding. (0.375dB step, 242 Level) (Table 32)
Default: “C5H” (+19.5dB)
Addr
09H
Register Name
Input Digital Volume Control
R/W
Default
D7
IVOL7
R/W
1
D6
IVOL6
R/W
0
D5
IVOL5
R/W
0
D4
IVOL4
R/W
1
D3
IVOL3
R/W
0
D2
IVOL2
R/W
0
D1
IVOL1
R/W
0
D0
IVOL0
R/W
1
D3
OVOL3
R/W
0
D2
OVOL2
R/W
0
D1
OVOL1
R/W
0
D0
OVOL0
R/W
1
D3
OREF3
R/W
1
D2
OREF2
R/W
0
D1
OREF1
R/W
0
D0
OREF0
R/W
0
IVOL7-0: Input Digital Volume; 0.375dB step, 242 Level (Table 22)
Default: “91H” (0.0dB)
Addr
0AH
Register Name
Digital Volume Control
R/W
Default
D7
OVOL7
R/W
1
D6
OVOL6
R/W
0
D5
OVOL5
R/W
0
D4
OVOL4
R/W
1
OVOL7-0: Output Digital Volume; 0.375dB step, 242 Level (Table 23)
Default: “91H” (0.0dB)
Addr
0BH
Register Name
ALC Mode Control 3
R/W
Default
D7
RGAIN1
R/W
0
D6
LMTH1
R/W
0
D5
OREF5
R/W
1
D4
OREF4
R/W
0
OREF5-0: Reference value at ALC Recovery operation for playback. 1.5dB step, 60 Level (Table 33)
Default: “28H” (+6.0dB)
LMTH1-0: ALC Limiter Detection Level / Recovery Waiting Counter Reset Level (Table 27)
LMTH0 bit is located at D0 bit of 07H. Default: “01”
RGAIN1-0: ALC Recovery GAIN Step (Table 31)
RGAIN0 bit is located at D1 bit of 07H. Default: “00”
Addr
0CH
Register Name
Video Mode Control
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
VGCA4
R/W
0
D3
VGCA3
R/W
0
D2
VGCA2
R/W
0
D1
VGCA1
R/W
1
D0
VGCA0
R/W
0
VGCA4-0: Gain Control of Video output (Table 56)
Default: “00010”
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Addr
0DH
Register Name
Input Digital Volume Control
R/W
Default
D7
VOL7
R
-
D6
VOL6
R
-
D5
VOL5
R
-
D4
VOL4
R
-
D3
VOL3
R
-
D2
VOL2
R
-
D1
VOL1
R
-
D0
VOL0
R
-
VOL7-0: The current volume of ALC; 0.375dB step, 242 Level, Read only (Table 35)
Addr
0EH
Register Name
Mode Control 3
R/W
Default
D7
DATT1
R/W
0
D6
DATT0
R/W
0
D5
SMUTE
R/W
0
D4
MDIF
R/W
0
D3
0
R
0
D2
0
R
0
D1
0
R
0
D0
READ
R/W
0
D4
DVOL4
R/W
1
D3
DVOL3
R/W
0
D2
DVOL2
R/W
1
D1
DVOL1
R/W
0
D0
DVOL0
R/W
1
READ: Read function Enable
0: Disable (default)
1: Enable
MDIF: Single-ended / Full-differential Input Select
0: Single-ended input (MIC pin or LIN pin: Default)
1: Full-differential input (MIC/MICP and LIN/MICN pins)
SMUTE: Soft Mute Control
0: Normal Operation (default)
1: DAC outputs soft-muted
DATT1-0: Output Digital Volume2; 6dB step, 4 Level (Table 24)
Default: “00H” (0.0dB)
Addr
0FH
Register Name
Thermal Shutdown
R/W
Default
D7
DVOL7
R/W
1
D6
DVOL6
R/W
1
D5
DVOL5
R/W
1
DVOL7-0: Output Digital Volume3; Linear step (Table 25, Table 26)
Default: “F5H” (0dB)
Addr
10H
Register Name
Signal Select 4
R/W
Default
D7
0
R
0
D6
LOVL
R/W
0
D5
LP
R/W
0
D4
0
R
0
D3
0
R
0
D2
0
R
0
D1
LIN
R/W
0
D0
0
R
0
LIN: Select Input data of ADC
0: MIC pin (default)
1: LIN pin
LP: Low Power Mode
0: Normal Mode (default)
1: Low Power Mode: It can be operated by fs=22.05kHz or less.
LOVL: Lineout Gain Setting
0: 0dB(default)
1: +3dB
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Addr
11H
Register Name
Digital Filter Select 1
R/W
Default
D7
0
R
0
D6
0
R
0
D5
LPF
R/W
0
D4
HPF
R/W
1
D3
0
R
0
D2
0
R
0
D1
0
R
0
D0
1
R
1
D1
F1A1
F1A9
F1B1
F1B9
W
D0
F1A0
F1A8
F1B0
F1B8
W
D1
BPFR1
R/W
0
D0
BPFR0
R/W
0
HPF: HPF2 Enable
0: Disable
1: Enable (default)
When HPF bit is “0”, HPF2 block is bypassed (0dB).
When HPF bit is “1”, F1A13-0, F1B13-0 bits are enabled.
LPF: LPF Coefficient Setting Enable
0: Disable (default)
1: Enable
When LPF bit is “0”, LPF block is bypassed (0dB).
When LPF bit is “1”, F2A13-0, F2B13-0 bits are enabled.
Addr
1CH
1DH
1EH
1FH
Register Name
HPF Co-efficient 0
HPF Co-efficient 1
HPF Co-efficient 2
HPF Co-efficient 3
R/W
Default
D7
F1A7
0
F1B7
0
W
D6
F1A6
0
F1B6
0
W
D5
D4
D3
D2
F1A5
F1A4
F1A3
F1A2
F1A13
F1A12
F1A11
F1A10
F1B5
F1B4
F1B3
F1B2
F1B13
F1B12
F1B11
F1B10
W
W
W
W
F1A13-0 bits = 0x1F16, F1B13-0 bits = 0x1E2B
F1A13-0, F1B13-0: FIL1 (Wind-noise Reduction Filter) Coefficient (14bit x 2)
Default: F1A13-0 bits = 0x1F16, F1B13-0 bits = 0x1E2B
fc = 75Hz@fs = 8kHz, 150Hz@fs = 16kHz
Addr
20H
Register Name
BEEP Frequency
R/W
Default
D7
BPCNT
R/W
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
0
R
0
BPFR1-0: BEEP Signal Output Frequency Setting (Table 47, Table 48, Table 49)
Default: “00H”
BPCNT: BEEP Signal Output Mode Setting
0: Once Output Mode. (default)
1: Continuous Mode
In continuous mode, the BEEP signal is output while BPCNT bit is “1”.
In once output mode, the BEEP signal is output by only the frequency set with BPTM6-0 bits.
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Addr
21H
Register Name
BEEP ON Time
R/W
Default
D7
BPON7
R/W
0
D6
BPON6
R/W
0
D5
BPON5
R/W
0
D4
BPON4
R/W
0
D3
BPON3
R/W
0
D2
BPON2
R/W
0
D1
BPON1
R/W
0
D0
BPON0
R/W
0
D4
BPOFF4
R/W
0
D3
BPOFF3
R/W
0
D2
BPOFF2
R/W
0
D1
BPOFF1
R/W
0
D0
BPOFF0
R/W
0
D4
BPTM4
R/W
0
D3
BPTM3
R/W
0
D2
BPTM2
R/W
0
D1
BPTM1
R/W
0
D0
BPTM0
R/W
0
BPON7-0: Setting ON-time of BEEP signal output (Table 50)
Default: “00H”
Addr
22H
Register Name
BEEP OFF Time
R/W
Default
D7
BPOFF7
R/W
0
D6
BPOFF6
R/W
0
D5
BPOFF5
R/W
0
BPOFF7-0: Setting OFF-time of BEEP signal output (Table 51)
Default: “00H”
Addr
23H
Register Name
BEEP Repeat Count
D7
0
R
0
R/W
Default
D6
BPTM6
R/W
0
D5
BPTM5
R/W
0
BPTM6-0: Setting the number of times that BEEP signal repeats (Table 52)
Default: “00H”
Addr
24H
Register Name
BEEP VOL/Control
R/W
Default
D7
BPOUT
R/W
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
BPLVL2
R/W
0
D1
BPLVL1
R/W
0
D0
BPLVL0
R/W
0
BPLVL2-0: Setting Output Level of BEEP signal (Table 53)
Default: “0H” (0dB)
BPOUT: BEEP Signal Control
0: OFF (default)
1: ON
At the time of BPCNT = “0”, when BPOUT bit is “1”, the beep signal starts outputting. The Beep signal stops
after the number of times that is set by BPTM6-0 bit, and BPOUT bit is set to “0” automatically.
Addr
27H
Register Name
Digital MIC
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
PMDM
R/W
0
D3
DCLKE
R/W
0
D2
DMPE
R/W
0
D1
DCLKP
R/W
1
D0
DMIC
R/W
0
DMIC: Digital Microphone Connection Select
0: Analog MIC (set to MIC/LIN pin or MICP/MICN pin: Default)
1: Digital MIC (set to DMDAT pin/ DMCLK pin)
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DCLKP: Data Latching Edge Select
0: Data is latched on the DMCLK rising edge (“↑”). (default)
1: Data is latched on the DMCLK falling edge (“↓”).
DMPE: Digital Microphone Power Supply
0: Externally (the same supply as AVDD) (default)
1: DMP pin
DCLKE: DMCLK pin Output Clock Control
0: “L” Output (default)
1: 64fs Output
PMDM: Digital Microphone Power Management
0: OFF (default)
1: ON
Addr
28H
Register Name
BEEP Mode Select
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D6
NSCE
R/W
0
D5
NSTHH1
R/W
0
D4
0
R
0
D3
0
R
0
D2
0
R
0
D1
BPM1
R/W
0
D0
BPM0
R/W
0
BPM1-0: BEEP Mode Setting (Table 43)
Default: “00”: Disable
Addr
29H
Register Name
Noise Suppression 1
R/W
Default
D7
0
R
0
D4
NSTHH0
R/W
1
D3
NSTHL3
R/W
0
D2
NSTHL2
R/W
0
D1
NSTHL1
R/W
0
D0
NSTHL0
R/W
0
NSTHL3-0: Noise Suppression Threshold Low Level Setting (Table 38)
Default: “0000” (-81dBFS)
NSTHH1-0: Noise Suppression Threshold High Level Setting(Table 40)
Default: “01” (NSTHL3-0 bits + 6dB)
NSCE: Noise Suppression Enable
0: Disable (default)
1: Enable
Addr
2AH
Register Name
Noise Suppression 2
R/W
Default
D7
0
R
0
D6
0
R
0
D5
NATT1
R/W
0
D4
NATT0
R/W
1
D3
0
R
0
D2
0
R
0
D1
NSGAIN1
R/W
0
D0
NSGAIN0
R/W
1
NSGAIN1-0: ALC First Recovery Speed Setting after Noise Suppression (Table 41)
Default: “01” (12 times)
NATT1-0: Noise Attenuate Step Setting (Table 39)
Default: “01” (1/2 step)
MS1012-E-01
2010/08
- 82 -
[AK4636]
Addr
2BH
Register Name
Noise Suppression 3
R/W
Default
D7
NSREF7
R/W
1
D6
NSREF6
R/W
0
D5
NSREF5
R/W
0
D4
NSREF4
R/W
1
D3
NSREF3
R/W
0
D2
NSREF2
R/W
0
D1
NSREF1
R/W
0
D0
NSREF0
R/W
1
D5
F2A5
F2A13
F2B5
F2B13
W
0
D4
F2A4
F2A12
F2B4
F2B12
W
0
D3
F2A3
F2A11
F2B3
F2B11
W
0
D2
F2A2
F2A10
F2B2
F2B10
W
0
D1
F2A1
F2A9
F2B1
F2B9
W
0
D0
F2A0
F2A8
F2B0
F2B8
W
0
D5
0
R
0
D4
EQ5
R/W
0
D3
EQ4
R/W
0
D2
EQ3
R/W
0
D1
EQ2
R/W
0
D0
EQ1
R/W
0
NSREF7-0: Reference Level Setting at Noise Suppression
0.375dB step, 242 Level (Table 42)
Default: “91H” (0dB)
Addr
2CH
2DH
2EH
2FH
Register Name
LPF Co-efficient 0
LPF Co-efficient 1
LPF Co-efficient 2
LPF Co-efficient 3
R/W
Default
D7
F2A7
0
F2B7
0
W
0
D6
F2A6
0
F2B6
0
W
0
F2A13-0, F2B13-0: LPF Coefficient (14bit x 2)
Default: “0000”
Addr
30H
Register Name
Digital Filter Select 2
R/W
Default
D7
0
R
0
D6
0
R
0
EQ1: Equalizer 1 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ1 bit is “1”, E1A15-0, E1B15-0, E1C15-0 bits are enabled. When EQ1 bit is “0”, EQ1 block is through
(0dB).
EQ2: Equalizer 2 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ2 bit is “1”, E2A15-0, E2B15-0, E2C15-0 bits are enabled. When EQ2 bit is “0”, EQ2 block is through
(0dB).
EQ3: Equalizer 3 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ3 bit is “1”, E3A15-0, E3B15-0, E3C15-0 bits are enabled. When EQ3bit is “0”, EQ3 block is through (0dB).
EQ4: Equalizer 4 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ4 bit is “1”, E4A15-0, E4B15-0, E4C15-0 bits are enabled. When EQ4 bit is “0”, EQ4 block is through
(0dB).
EQ5: Equalizer 5 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ5 bit is “1”, E5A15-0, E5B15-0, E5C15-0 bits are enabled. When EQ5 bit is “0”, EQ5 block is through
(0dB).
MS1012-E-01
2010/08
- 83 -
[AK4636]
Addr
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
Register Name
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
R/W
Default
D7
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
W
0
D6
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
E4A6
E4A14
E4B6
E4B14
E4C6
E4C14
E5A6
E5A14
E5B6
E5B14
E5C6
E5C14
W
0
D5
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
E4A5
E4A13
E4B5
E4B13
E4C5
E4C13
E5A5
E5A13
E5B5
E5B13
E5C5
E5C13
W
0
D4
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
E4A4
E4A12
E4B4
E4B12
E4C4
E4C12
E5A4
E5A12
E5B4
E5B12
E5C4
E5C12
W
0
D3
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
E4A3
E4A11
E4B3
E4B11
E4C3
E4C11
E5A3
E5A11
E5B3
E5B11
E5C3
E5C11
W
0
D2
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
W
0
D1
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
W
0
D0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
W
0
E1A15-0, E1B15-0, E1C15-0: Equalizer 1 Coefficient (16bit x3)
Default: “0000H”
E2A15-0, E2B15-0, E2C15-0: Equalizer 2 Coefficient (16bit x3)
Default: “0000H”
E3A15-0, E3B15-0, E3C15-0: Equalizer 3 Coefficient (16bit x3)
Default: “0000H”
E4A15-0, E4B15-0, E4C15-0: Equalizer 4 Coefficient (16bit x3)
Default: “0000H”
E5A15-0, E5B15-0, E5C15-0: Equalizer 5 Coefficient (16bit x3)
Default: “0000H”
MS1012-E-01
2010/08
- 84 -
[AK4636]
SYSTEM DESIGN
Figure 66 ~ Figure 69 show the system connection diagram. The evaluation board [AKD4636] demonstrates the optimum
layout, power supply arrangements and measurement results.
< MIC Single-end Input >
AK4636ECB
0.1µ
10
Digital
Ground
Analog
Ground
DSP
Speaker
0.1µ
PDN
DVDD
VSS2
SPP
SVDD
SDTO
MCKO
SDTI
VSS3
SPN
BICK
MCKI
FCK
AOUT
1µ
220
Ri
Ci
&
µP
20 k
BEEP
C
Top View
CCLK
CDTIO
I2C
MIC
LIN
CSN
VOUT
VVDD
VCOM
MPI
C
2.2k
0.1µ
0.1µ
VIN
VSS1
0.1µ
AVDD
VCOC
Rp
+
2.2µ
Cp
0.1µ
75
Analog Supply
2.8∼3.6V
10µ
+
Figure 66. Typical Connection Diagram (3-wire Mode, I2C pin = “L”, BPM1-0 bits = “10”)
Notes:
- VSS1, VSS2 and VSS3 of the AK4636 should be distributed separately from the ground of external controllers.
- All digital input pins except pull-down pin should not be left floating.
- In EXT mode (PMPLL bit = “0”), Rp and Cp of the VCOC pin can be open.
- In PLL mode (PMPLL bit = “1”), Rp and Cp of the VCOC pin should be connected as shown in Table 4.
- When the AK4636 is used at master mode, FCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, a pull-up resistor with around 100Ω should be connected to FCK and BICK pins of the AK4636.
-When AVDD, DVDD, SVDD and VVDD were distributed, AVDD = 2.6 ~ 3.6V, DVDD = 1.6 ~ 3.6V, SVDD
= 2.6 ~ 3.6V, VVDD = 2.8 ~ 3.6V.
-1st-oder HPF consists of the input impedance of the LIN pin and MIN pin (R = typ 30 kΩ) and the LIN, MIN pin
capacitors “C” before MIC-Amp. The cut-off frequency of the HPF(fs) is calculated by the following formula.
fc = 1 / (2πR C)
MS1012-E-01
2010/08
- 85 -
[AK4636]
AK4636EN
Speaker
10u
10
Power Supply
2.8 ∼ 3.6V
0.1u
24
23
22
21
20
19
18
17
SVDD
SPP
NC
VSS2
DVDD
MCKO
PDN
BICK
14
MCKI
13
FCK
12
AK4636EN
28 BEEP
Top View
29 AOUT
30 LIN
CCLK/ SCL
31 MIC
AVDD
VSS1
VVDD
VOUT
VIN
3
4
5
6
7
75
0.1u
1
9
0.1u
VCOM
CSN/ SDA
Rp
0.1u
2.2u
11
CDTIO 10
32 MPI
2.2k
DSP
&
μP
I2C
20k
C
15
27 VSS3
8
C
16
SDTI
Cp
0.1u
1u
SDTO
26 NC
VCOC
220
Ri
25 NC
2
Ci
SPN
0.1u
Analog Ground
Digital Ground
Figure 67. Typical Connection Diagram (3-wire Mode, I2C pin = “L”, BPM1-0 bits = “10”)
Notes:
- VSS1, VSS2 and VSS3 of the AK4636 should be distributed separately from the ground of external controllers.
- All digital input pins except pull-down pin should not be left floating.
- In EXT mode (PMPLL bit = “0”), Rp and Cp of the VCOC pin can be open.
- In PLL mode (PMPLL bit = “1”), Rp and Cp of the VCOC pin should be connected as shown in Table 4.
- When the AK4636 is used at master mode, FCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, a pull-up resistor with around 100Ω should be connected to FCK and BICK pins of the AK4636.
-When AVDD, DVDD, SVDD and VVDD were distributed, AVDD = 2.6 ~ 3.6V, DVDD = 1.6 ~ 3.6V, SVDD
= 2.6 ~ 3.6V, VVDD = 2.8 ~ 3.6V.
-1st-oder HPF consists of the input impedance of the LIN pin and MIN pin (R = typ 30 kΩ) and the LIN, MIN pin
capacitors “C” before MIC-Amp. The cut-off frequency of the HPF(fs) is calculated by the following formula.
fc = 1 / (2πR C)
MS1012-E-01
2010/08
- 86 -
[AK4636]
< MIC differential Input >
AK4636ECB
0.1µ
10
Digital
Ground
Analog
Ground
DSP
Speaker
0.1µ
PDN
DVDD
VSS2
SPP
SVDD
SDTO
MCKO
SDTI
VSS3
SPN
BICK
MCKI
FCK
AOUT
1µ
220
Ri
Ci
&
µP
C
Top View
CCLK
CDTIO
I2C
CSN
VOUT
VVDD
20k
BEEP
MICP
VCOM
MICN
MPI
C
1k
1k
0.1µ
0.1µ
VIN
VSS1
0.1µ
AVDD
VCOC
Rp
+
2.2µ
Cp
0.1µ
75
Analog Supply
2.8∼3.6V
10µ
+
Figure 68. Typical Connection Diagram (3-wire Mode, I2C pin = “L”, BPM1-0 bits = “10”)
Notes:
- VSS1, VSS2 and VSS3 of the AK4636 should be distributed separately from the ground of external controllers.
- All digital input pins except pull-down pin should not be left floating.
- In EXT mode (PMPLL bit = “0”), Rp and Cp of the VCOC pin can be open.
- In PLL mode (PMPLL bit = “1”), Rp and Cp of the VCOC pin should be connected as shown in Table 4.
- When the AK4636 is used at master mode, FCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, a pull-up resistor with around 100Ω should be connected to FCK and BICK pins of the AK4636.
-When AVDD, DVDD, SVDD and VVDD were distributed, AVDD = 2.6 ~ 3.6V, DVDD = 1.6 ~ 3.6V, SVDD
= 2.6 ~ 3.6V, VVDD = 2.8 ~ 3.6V.
-1st-oder HPF consists of the input impedance of the MICP pin and MICN pin (R = typ 30 kΩ) and the MICP,
MICN pin capacitors “C” before MIC-Amp. The cut-off frequency of the HPF(fs) is calculated by the
following formula.
fc = 1 / (2πR C)
MS1012-E-01
2010/08
- 87 -
[AK4636]
AK4636EN
Speaker
10u
0.1u
10
Power Supply
2.8 ∼ 3.6V
1k
24
23
22
21
20
19
18
17
SVDD
SPP
NC
VSS2
DVDD
MCKO
PDN
BICK
14
MCKI
13
FCK
12
AK4636EN
28 BEEP
Top View
29 AOUT
30 MICN
CCLK/ SCL
31 MICP
32 MPI
CSN/ SDA
VSS1
VVDD
VOUT
VIN
4
5
6
7
75
Rp
0.1u
2.2u
11
Cp
9
0.1u
AVDD
3
0.1u
1
VCOM
1k
DSP
&
μP
CDTIO 10
VCOC
20k
C
15
27 VSS3
I2C
C
16
SDTI
8
1u
SDTO
26 NC
2
220
Ri
25 NC
0.1u
Ci
SPN
0.1u
Analog Ground
Digital Ground
Figure 69. Typical Connection Diagram (3-wire Mode, I2C pin = “L”, BPM1-0 bits = “10”)
Notes:
- VSS1, VSS2 and VSS3 of the AK4636 should be distributed separately from the ground of external controllers.
- All digital input pins except pull-down pin should not be left floating.
- In EXT mode (PMPLL bit = “0”), Rp and Cp of the VCOC pin can be open.
- In PLL mode (PMPLL bit = “1”), Rp and Cp of the VCOC pin should be connected as shown in Table 4.
- When the AK4636 is used at master mode, FCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, a pull-up resistor with around 100Ω should be connected to FCK and BICK pins of the AK4636.
-When AVDD, DVDD, SVDD and VVDD were distributed, AVDD = 2.6 ~ 3.6V, DVDD = 1.6 ~ 3.6V, SVDD
= 2.6 ~ 3.6V, VVDD = 2.8 ~ 3.6V.
-1st-oder HPF consists of the input impedance of the MICP pin and MICN pin (R = typ 30 kΩ) and the MICP,
MICN pin capacitors “C” before MIC-Amp. The cut-off frequency of the HPF(fs) is calculated by the
following formula.
fc = 1 / (2πR C)
MS1012-E-01
2010/08
- 88 -
[AK4636]
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
PLL Reference
Clock Input Pin
0
1
2
3
4
6
7
12
13
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
1
1
0
0
0
1
0
1
0
0
1
0
1
FCK pin
BICK pin
BICK pin
BICK pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
Input
Frequency
R and C of
VCOC pin
(Note 32)
R[Ω] C[F]
6.8k
220n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
10n
10k
10n
PLL Lock
Time
(max)
1fs
160ms
16fs
2ms
32fs
2ms
64fs
2ms
11.2896MHz
10ms
12MHz
10ms
24MHz
10ms
13.5MHz
10ms
27MHz
10ms
Others
Others
N/A
Note 32. The tolerance of R is ±5%, the tolerance of C is ±30%
Table 4. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)
(default)
1. Grounding and Power Supply Decoupling
The AK4636 requires careful attention to power supply and grounding arrangements. AVDD, DVDD, SVDD and VVDD
are usually supplied from the system’s analog supply. If AVDD, DVDD, SVDD and VVDD are supplied separately, the
power up sequence is not critical but the PDN pin must be put “L” after all powers are supplied. VSS1, VSS2 and VSS3
of the AK4636 should be connected to the analog ground plane. System analog ground and digital ground should be
connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be
as near to the AK4636 as possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference
VCOM is a signal ground of this chip. A 2.2μF electrolytic capacitor in parallel with a 0.1μF ceramic capacitor attached
to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All
signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the
AK4636.
3. Analog Inputs
The Microphone input supports both single-ended and differential inputs. The input signal range is 1.5Vpp
(typ)@MGAIN = 0dB or 0.15Vpp (typ)@MGAIN = +20dB entered around the internal common voltage 1.15V (typ).
Usually the input signal is AC coupled with a capacitor. The cut-off frequency is fc =1/ (2πRC). The AK4636 can accept
input voltages from VSS to AVDD.
4. Analog Outputs
The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and
a negative full scale for 8000H(@16bit). The ideal output is VCOM voltage for 0000H (@16bit). Mono Line Output from
the AOUT pin is 1.5Vpp (typ)@LOVL bit = “0” centered around common voltage 1.15V (typ).
5. Video Inputs
Video inputs are AC coupled with a 0.1uF capacitor. This AC coupling capacitor must be 0.1uF (in ±30% tolerance).
Attention should be given to avoid coupling with other analog and digital signals.
6. Video Outputs
The AK4636 integrates 2ch video amp for driving 150Ω resistance. The gain of each amp is +6dB@GCA=0dB (typ)
MS1012-E-01
2010/08
- 89 -
[AK4636]
CONTROL SEQUENCE
■ Clock Set up
When ADC, DAC, Digital microphone and Programmable Filter are used, the clocks must be supplied.
1. PLL Master Mode
Example:
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 12MHz
MCKO : Enable
Sampling Frequency:48kHz
Power Supply
(1)
PDN pin
(2)
(3)
PMVCM bit
(1) Power Supply & PDN pin = “L” Æ “H”
(Addr:00H, D6)
(4)
MCKO bit
(Addr:01H, D1)
(2)Addr:01H, Data:01H
Addr:04H, Data:6AH
Addr:05H, Data:23H
PMPLL bit
(Addr:01H, D0)
(5)
MCKI pin
Input
(3)Addr:00H, Data:40H
M/S bit
(Addr:01H, D3)
20msec(max)
(6)
BICK pin
FCK pin
(4)Addr:01H, Data:0BH
Output
(7)
1msec (max)
MCKO, BICK and FCK output
20msec(max)
(9)
MCKO pin
(8)
Output
Figure 70. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin = “L” → “H”
“L” time (1) of 150ns or more is needed to reset the AK4636.
(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP and M/S bits must be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” → “1”
VCOM should first be powered-up before the other block operates.
(4) In case of using MCKO output: MCKO bit = “1”
In case of not using MCKO output: MCKO bit = “0”
(5) PLL lock time is 20ms(max) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external
source.
(6) The AK4636 starts to output the FCK and BICK clocks after the PLL becomes stable and the normal operation
starts.
(7) The invalid frequencies are output from FCK and BICK pins during this period.
(8) The invalid frequency is output from the MCKO pin during this period.
(9) The normal clock is output from the MCKO pin after the PLL is locked.
MS1012-E-01
2010/08
- 90 -
[AK4636]
2. When the external clock (FCK or BICK pin) is used in PLL Slave mode.
Example:
Audio I/F Format: DSP Mode BCKP = MSBS = “0”
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 48kHz
Power Supply
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(3)
PMVCM bit
(2) Addr:04H, Data:38H
Addr:05H, Data:20H
(Addr:00H, D6)
PMPLL bit
(Addr:01H, D0)
FCK pin
BICK pin
(3) Addr:00H, Data:40H
Input
(4)
(4) Addr:01H, Data:01H
Internal Clock
(5)
BICK and FCK input
Figure 71. Clock Set Up Sequence (2)
<Example>
(1) After Power Up: PDN pin “L” → “H”
“L” time (1) of 150ns or more is needed to reset the AK4636.
(2) DIF1-0, FS3-0, PLL3-0, MSBS and BCKP bits must be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” → “1”
VCOM should first be powered up before the other block operates.
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clocks (FCK or BICK pin) are
supplied. PLL lock time is 160ms(max) when PLL reference clock is FCK, and PLL lock time is 2ms(max) when
PLL reference clock is BICK.
(5) Normal operation starts after the PLL is locked.
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[AK4636]
3. When the external clock (MCKI pin) is used in PLL Slave mode.
Example:
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 12MHz
MCKO :
Enable
Sampling Frequency:48kHz
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(3)
(2)Addr:04H, Data:68H
Addr:05H, Data:23H
PMVCM bit
(Addr:00H, D6)
(4)
PMPLL bit
(Addr:01H, D0)
(3)Addr:00H, Data:40H
(5)
MCKI pin
Input
20msec(max)
(4)Addr:01H, Data:03H
(6)
MCKO pin
Output
(7)
MCKO output start
(8)
BICK pin
FCK pin
Input
BICK and FCK input start
Figure 72. Clock Set Up Sequence (3)
<Example>
(1) After Power Up: PDN pin “L” → “H”
“L” time (1) of 150ns or more is needed to reset the AK4636.
(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP and M/S bits must be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” → “1”
VCOM should first be powered up before the other block operates.
(4) PLL Power Up: PMPLL bit “0” → “1”
(5) PLL lock time is 20ms(max) after the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin)
is supplied.
(6) Normal clock is output from the MCKO pin after PLL is locked.
(7) The invalid frequency is output from the MCKO pin during this period.
(8) BICK and FCK clocks should be synchronized with MCKO clock.
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[AK4636]
4. EXT Slave Mode
Example
Audio I/F Format:MSB justified (ADC and DAC)
Input MCKI frequency: 256fs
Sampling Frequency:48kHz
MCKO: Disable
Power Supply
(1)
PDN pin
(1) Power Supply & PDN pin = “L” Æ “H”
(2)
(3)
PMVCM bit
(Addr:00H, D6)
(2) Addr:04H, Data:02H
Addr:05H, Data:00H
(4)
PMPLL bit
(Addr:01H, D0)
"L"
(5)
MCKI pin
Input
(3) Addr:00H, Data:40H
(5)
FCK pin
BICK pin
Input
MCKI, BICK and FCK input
Figure 73. Clock Set Up Sequence (4)
<Example>
(1) After Power Up: PDN pin “L” → “H”
“L” time (1) of 150ns or more is needed to reset the AK4636.
(2) DIF1-0 and FS1-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” → “1”
VCOM should first be powered up before the other block operates.
(4) Power down PLL: PMPLL bit = “0”
(5) Normal operation starts after the MCKI, FCK and BICK are supplied.
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[AK4636]
■ Digital MIC Inputs
Example:
FS3-0 bits
(Addr:05H, D5,D2-0)
X,XXX
PLL Master Mode
Audio I/F Format: MSB justified
Sampling Frequency: 16kHz
Digital MIC setting:
D ata is latched on the DMCLK failing edge
Digital MIC Power Supply “Extenally”
ALC1 setting:Refer to Table 36
HPF : ON (fc=150Hz)
4+1 band EQ : OFF
0,010
(1)
ADRST bit
(Addr:05H, D7)
Digital MIC
Control
X
X
(1) Addr:05H, Data:02H
XXH
XXH
(Addr:08H)
(3) Addr:06H, Data:14H
14H
(Addr:06H)
ALC1 Control 2
(2) Addr:27H, Data:0BH
(2)
(Addr:27H, D3-0)
ALC1 Control 1
0BH
(3)
(4) Addr:08H, Data:C5H
XXH
C5H
(4)
IVOL7-0 bits
(Addr:09H)
(5) Addr:09H, Data:C5H
C5H
XXH
(6) Addr:07H, Data:A1H
(5)
ALC1 Control 3
(Addr:07H)
Signal Select
(Addr:03H)
XXH
A1H
(7) Addr:03H, Data:81H
(6)
XXH
(8-1) Addr:1CH, Data:A9H
81H
(7)
Filter Co-ef
(Addr:10H-1F)
Filter Select
(Addr:11H D5-4, D0)
(8-2) Addr:1DH, Data:1FH
XX....X
XX....X
(8)
(8-3) Addr:1EH, Data:53H
XX1
011
(8-4) Addr:1FH, Data:1FH
(9)
ALC1 State
ALC1 Disable
ALC1 Enable
ALC1 Disable
(9) Addr:11H, Data:11H
(10) Addr:00H, Data:80H
PMPFIL bit
(Addr:00H, D7)
(13)
(10)
(11) Addr:27H, Data:1BH
PMDM bit
Recording
(Addr:27H, D4)
(11)
291/fs or 1059/fs
(12)
(12) Addr:27H, Data:0BH
SDTO pin
State
O data output
Initialize
Normal
data ouput
O data output
(13) Addr:00H, Data:00H
Figure 74. Digital MIC Input Recording Sequence
<Example>
This sequence is an example of ALC1 setting at fs=16kHz. If the parameter of the ALC1 is changed, please refer to
the Figure 47.
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bit) and the initializing cycle of programmable filter (ADRST bit). When
the AK4636 is in PLL mode, MIC and Programmable filter should be powered-up in consideration of PLL lock
time after the sampling frequency is changed.
(2) Set up Digital MIC(address 27H)
(3) Set up Timer Select for ALC1 (Addr: 06H)
(4) Set up REF value for ALC1 (Addr: 08H)
(5) Set up IVOL value for ALC1 (Addr: 09H)
(6) Set up LMTH0, RGAIN0, LMAT1-0, ZELM and ALC1 bits (Addr: 07H)
(7) Set up Programmable Filter Path: PFSDO bit = ADCPF bit = “1”
(8) Set up Coefficient of the Programmable Filter (HPF/EQ) Addr: 1CH ~ 1FH, 2CH ~ 2FH, 32H ~ 4FH
(9) Switch ON/OFF of the Programmable Filter (HPF/EQ)
(10) Power-up Programmable Filter: PMPFIL bit = “0” Æ “1”
(11) Power-up Digital MIC: PMDM bit = “0” Æ “1”
The initializing cycle of the digital filter is 1059/fs= 24ms@fs=44.1kHz when ADRST bit = “0”, and
291/fs=18ms@16kHz when ADRST bit = “1”. ALC starts operating at the value set by IVOL (5).
(12) Power-down Digital MIC: PMDM bit = “1” Æ “0”
(13) Power-down Programmable Filter: PMPFIL bit = “1” Æ “0”
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[AK4636]
■ MIC Input Recording
Example:
FS3-0 bits X,XXX
(Addr:05H,
D5,D2-0)
ADRST bit
(Addr:05H, D7)
MIC Control
(Addr:02H, D2-0
Addr :03H, D5)
ALC1 Control 1
(Addr:06H)
PLL Master Mode
Audio I/F Format: MSB justified
Sampling Frequency: 16kHz
Pre MIC AMP:+20dB
MIC Power On
ADC Initialize time: 291/fs
ALC1 setting:Refer to Table 36
HPF : ON (fc=150Hz)
4+1 band EQ : OFF
0,010
(1)
X
(1) Addr:05H, Data:02H
X
XXXX
(2) Addr:02H, Data:05H
0,001
(2)
(3) Addr:06H, Data:14H
XXH
14H
(3)
(4) Addr:08H, Data:C5H
ALC1 Control 2
(Addr:08H)
XXH
C5H
(4)
IVOL7-0 bits
(Addr:09H)
(5) Addr:09H, Data:C5H
C5H
XXH
(6) Addr:07H, Data:A1H
(5)
ALC1 Control 3
(Addr:07H)
Signal Select
(Addr:03H)
Filter Co-ef
(Addr:10H-1F)
Filter Select
(Addr:11H D5-4, D0)
XXH
A1H
(7) Addr:03H, Data:81H
(6)
XXH
81H
(8-1) Addr:1CH, Data:A9H
XX....X
(8-2) Addr:1DH, Data:1FH
(7)
XX....X
(8)
XX1
(8-3) Addr:1EH, Data:53H
011
(9)
(8-4) Addr:1FH, Data:1FH
ALC1 State
ALC1 Disable
ALC1 Enable
ALC1 Disable
(9) Addr:11H, Data:11H
PMADC bit
(Addr:00H, D0)
(10)
PMPFIL bit
291/fs or 1059/fs
(Addr:00H, D7)
ADC Internal
State
(11)
Power Down
Initialize Normal State Power Down
(10) Addr:00H, Data:C1H
Recording
(11) Addr:00H, Data:40H
Figure 75. MIC Input Recording Sequence
<Example>
This sequence is an example of ALC1 setting at fs=16kHz. If the parameter of the ALC1 is changed, please refer to
the Figure 47.
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bit). When the AK4636 is in PLL mode, programmable filter and ADC
should be powered-up in consideration of PLL lock time after the sampling frequency is changed.
(2) Set up MIC input (Addr: 02H)
(3) Set up Timer Select for ALC1 (Addr: 06H)
(4) Set up REF value for ALC1 (Addr: 08H)
(5) Set up IVOL value for ALC1 (Addr: 09H)
(6) Set up LMTH0, RGAIN0, LMAT1-0, ZELM and ALC1 bits (Addr: 07H)
(7) Set up Programmable Filter Path: PFSDO bit = ADCPF bit = “1”
(8) Set up Coefficient of the Programmable Filter (HPF/EQ) Addr: 1CH ~ 1FH, 2CH ~ 2FH, 32H ~ 4FH
(9) Switch ON/OFF of the Programmable Filter
(10) Power-up of the ADC and Programmable Filter: PMPFIL bit = PMADC bit = “0” Æ “1”
The initialization cycle of the ADC is 1059/fs=24ms@fs=44.1kHz when ADRST bit = “0”,
291/fs=18ms@fs=16kHz when ADRST bit= “1”. ALC starts operating at the value set by IVOL (5).
(11) Power-down of the ADC and Programmable Filter: PMPFIL bit = PMADC bit = “1” Æ “0”
MS1012-E-01
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[AK4636]
■ Mono Lineout
Example:
FS3-0 bits
(Addr:05H,
D5, D2-0)
X,XXX
PLL Master Mode
Audio I/F Format: MSB justified
Sampling Frequency: 16kHz
LOVL bit = “0”
ALC2 : OFF, OVOL = “91H “
ALC 2 setting:Refer to Table 33
HPF : ON (fc=150Hz)
4+1 band EQ : OFF
0,010
(1)
(11)
DACA bit
(2)
(1) Addr:05H, Data:02H
(Addr:02H, D4)
(3)
ADCPF bit
0 or 1
0
0 or 1
1
(2) Addr:02H, Data:10H
(Addr:03H, D0)
PFDAC bit
(Addr:03H, D1)
(3) Addr:03H, Data:02H
(4) Addr:07H, Data:00H
(4)
ALC2 Control
0 or 1
0
(5) Addr:0AH, Data:91H
(Addr:07H)
(5)
OVOL7-0 bits
(Addr:0AH, D7-0)
XXH
(6) Addr:03H, Data:42H
91H
(7) Addr:00H, Data:CCH
AOPS bit
(Addr:03H, D6)
(6)
(9)
(8)
(12)
(8) Addr:03H, Data:02H
PMDAC bit
(Addr:00H, D2)
Playback
(7)
(10)
PMPFIL bit
(9) Addr:03H, Data:42H
(Addr:00H, D7)
PMAO bit
(Addr:00H, D3)
(10) Addr:00H, Data:40H
>300 ms
>300 ms
AOUT pin
Normal Output
(11) Addr:02H, Data:00H
(12) Addr:03H, Data:02H
Figure 76. Mono Lineout Sequence
<Example>
In case of using digital volume in manual mode
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up the sampling frequency (FS3-0 bits). When the AK4636 is PLL mode, DAC should be powered-up in
consideration of PLL lock time after the sampling frequency is changed.
(2) Set up the path of “DAC → Mono Line Amp”
DACA bit: “0” → “1”
(3) Set up the path: ADCPF bit = “0”, PFDAC bit = “1”
(4) ALC2 Disable: ALC2 bit = “0”
(5) Set up the digital volume (Addr: 0AH)
(6) AOUT power save mode: AOPS bit: “0” → “1”
(7) Power-up of DAC, Programmable Filter and Mono Line Amp:
PMDAC bit = PMPFIL bit = PMAO bit = “0” → “1”
AOUT pin goes to “H”. It takes 300ms (max) when C = 1µF
(8) Exit power save mode of AOUT: AOPS bit = “1” → “0”
Set up AOPS bit after AOUT became “H”, then the AOUT pin starts outputting data.
(9) Enter power save mode of AOUT: AOPS bit= “0” → “1”
(10) Power –down the DAC, Programmable Filter and Mono Line Amp:
PMDAC bit = PMPFIL bit = PMAO bit = “1” Æ “0”
The AOUT pin starts going to “L”. It takes 300ms(max) when C = 1μF.
(11) Disable the path of “DAC → Mono Line Amp”: DACA bit= “1” → “0”
(12) Exit power save mode of AOUT: AOPS bit=“1” → “0”
Set up AOPS bit after AOUT became “L”.
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[AK4636]
■ Speaker-amp Output
FS3-0 bits
(Addr:05H,
D5,D2-0)
X,XXX
0,010
Example:
(1)
PLL Master Mode
Audio I/F Format: MSB justified
Sampling Frequency: 16kHz
SPKG bit = “1”
ALC2 : ON
ALC2 setting:Refer to Table 33
HPF : ON (fc=150Hz)
5 band EQ : OFF
(13)
DACS bit
(Addr:02H, D3)
(2)
ALC2 Control 1
(Addr:06H)
ALC2 Control 2
(Addr:08H)
XXH
14H
(1) Addr:05H, Data:A2H
(3)
XXH
(2) Addr:02H, Data:20H
28H
(4)
OVOL7-0 bits
(Addr:0AH)
(3) Addr:06H, Data:14H
91H
XXH
(4) Addr:08H, Data:28H
(5)
ALC2 Control 3
(Addr:07H)
Signal Select
(Addr:03H)
Filter Co-ef
(Addr:1CH-1FH)
Filter Select
(Addr:11H, D5-4, D0 )
XXH
C1H
(5) Addr:0AH, Data:91H
(6)
XXH
(6) Addr:07H, Data:C1H
0A
(7)
(7) Addr:03H, Data:0AH
XX....X
XX....X
(8)
(8-1) Addr:1CH, Data:16H
XX, X
X1, 1
(8-2) Addr:1DH, Data:1FH
(9)
ALC2 State
ALC2 Disable
ALC2 Disable
ALC2 Enable
(8-3) Addr:1EH, Data:2BH
(8-4) Addr:1FH, Data:1EH
PMPFIL bit
(Addr:00H, D7)
(9) Addr:11H, Data:11H
(14)
PMDAC bit
(Addr:00H, D2)
(10) Addr:00H, Data:D4H
(10)
PMSPK bit
(11) Addr:02H, Data:A0H
(Addr:00H, D4)
(11)
Playback
SPPSN bit
(Addr:02H, D7)
(12) Addr:02H, Data:20H
(12)
SPP pin
SPN pin
Hi-z
Hi-z
Normal Output
Hi-z
Normal Output
Hi-z
Hi-z
(13) Addr:02H, Data:00H
Hi-z
(14) Addr:00H, Data:40H
Figure 77. Speaker-Amp Output Sequence
<Example>
In case of fs=16kHz. Refer to the Table 37 for changing ALC2 parameter.
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4636 is PLL mode, DAC and Speaker-Amp should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of “DAC → SPK-Amp”: DACS bit = “0” → “1”
(3) Set up Timer Select for ALC2 (Addr: 06H)
(4) Set up REF value for ALC2 (Addr: 08H)
(5) Set up OVOL value, RGAIN1 and LMTH1 for ALC2 (Addr: 10H)
(6) Set up LMTH0, RGAIN0, LMAT1-0, ZELM and ALC2 bit (Addr: 07H)
(7) Set up the Programmable Filter Path and SPK-Amp Gain:
PFDAC bit = “1”, ADCPF bit = “0”, SPKG bit = “X”
(8) Set up Coefficient of the Programmable Filter (HPF/EQ) Addr: 1C ~ 1FH, 2CH ~ 2FH, 32H ~ 4FH
(9) Switch ON/OFF of the Programmable Filter
(10) Power-up of the DAC, SPK-Amp and Programmable Filter:
PMDAC bit = PMSPK bit = PMPFIL bit = “0” → “1”
(11) Enable Speaker Output: SPPSN bit = “0” → “1”
1ms or more time is needed before setting SPPSN bit = “1”after setting PMSPK bit = “1”.
(12) Disable Speaker Output: SPPSN bit = “1” → “0”
(13) Disable the path of “DAC → SPK-Amp”: DACS bit = “1” → “0”.
(14) Power down of the DAC, SPK-Amp and Programmable Filter:
PMDAC bit = PMSPK bit = PMPFIL bit = “1”Æ “0”
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[AK4636]
■ BEEP Signal Output from Speaker-Amp
Example:default
(1) Addr:00H, Data:50H
(1)
(6)
(2) Addr:20-24H, Data:00H
PMSPK bit
(Addr:00H, D4)
(3) Addr:02H, Data:80H
(2)
BEEP Gen bits
(Addr:20-24H)
XXH
00H
(4) Addr:24H, Data:80H
(3)
(5)
SPPSN bit
BEEP Signal Output
(Addr:00H, D4)
(4)
(4)
BPOUT bit
Addr:24H, Data:00H (Auto)
(Addr:24H, D7)
(5) Addr:02H, Data:00H
(6) Addr:00H, Data:40H
Figure 78. “BEPP Generator Æ Speaker-Amp” Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Power Up BEEP-Generator and Speaker-Amp: PMSPK bit = “0” → “1”
(2) Set up BEEP Generator (Addr: 20H ~ 24H)(When repeat output time BPCNT bit = “0”)
(3) Enable SPK-Amp Output: SPPSN bit = “0” → “1”
(4) BEEP Output: BPOUT bit= “0” → “1” (after outputting data particular set times, BPOUT bit automatically
goes to “0”)
(5) Disable Speaker Output: SPPSN bit = “1” → “0”
(6) Power down of the SPK-Amp: PMSPK bit = “1” → “0”
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[AK4636]
■ Video Signal Input and Output
Example:
Clocks
PMVCM bit
(Addr:00H, D6)
Audio Function :No use
PLL Master Mode
VGCA : 0dB
Clocks can be stopped, if only video output is enabled.
(1) Addr:00H, Data:45H
1
X
(1)
VGCA4-0 bits
(Addr:0CH, D4-0)
X,XXXX
(2) Addr:0CH, Data:02H
0,0010
(2)
(4)
(3)
(3) Addr:01H, Data:8BH
PMV bit
(Addr:01H, D7)
Video Output
VOUT pin
VSS1
Normal Output
VSS1
(4) Addr:01H, Data:0BH
Figure 79. Video Output Sequence
<Example>
When only the video block is operated, the clocks are not needed to be supplied.
(1) Power up VCOM: PMVCM bit = “X” → “1”
(2) Set up the GCA gain (VGCA4-0 bits)
(3) Power up the Video Amp: PMV bit = “0” → “1”
The signal input to the VIN pin is output from the VOUT pin.
(4) Power down of the Video Amp: PMV bit = “1” → “0”
The output from the VOUT pin will stop and goes to 0V. Then VCOM can be powered-down when not using
any audio functions.
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[AK4636]
■ Stop of Clock
Master clock can be stopped when ADC, DAC and Programmable Filter are not in operation.
1. PLL Master Mode
Example:
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 12MHz
MCKO : Enable
Sampling Frequency:48kHz
(1)
PMPLL bit
(Addr:01H, D0)
(1) (2) Addr:01H, Data:08H
(2)
MCKO bit
"H" or "L"
Stop an external MCKI
(Addr:01H, D1)
(3)
External MCKI
Input
Figure 80. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO clock: MCKO bit = “1” → “0”
(3) Stop an external master clock
2. PLL Slave Mode (FCK, BICK pin)
Example
Audio I/F Format: DSP Mode BCKP = MSBS = “0”
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 48kH z
(1)
PMPLL bit
(Addr:01H,D0)
(2)
External BICK
Input
(1) Addr:01H, Data:00H
(2)
External FCK
Input
(2) Stop the external clocks
Figure 81. Clock Stopping Sequence (2)
<Example>
(1) Power down of the PLL: PMPLL bit = “1” → “0”
(2) Stop an external master clock
MS1012-E-01
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[AK4636]
3. PLL Slave Mode (MCKI pin)
Example
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 12MHz
MCKO :
Enable
Sampling Frequency:48kHz
(1)
PMPLL bit
(Addr:01H, D0)
(1)
MCKO bit
(1) Addr:01H, Data:00H
(Addr:01H, D1)
(2)
External MCKI
Input
(2) Stop the external clocks
Figure 82. Clock Stopping Sequence (3)
<Example>
(1) Power down of the PLL: PMPLL bit = “1” → “0”
Stop the MCKO output: MCKO bit = “1” → “0”
(2) Stop an external master clock.
4. EXT Slave Mode
Example
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 12MHz
MCKO :
Enable
Sampling Frequency:48kHz
(1)
External MCKI
Input
External BICK
Input
(1)
(1) Addr:01H, Data:00H
(1)
External FCK
Input
(2) Stop the external clocks
Figure 83. Clock Stopping Sequence (4)
<Example>
(1) Stop an external master clock.
■ Power Down
VCOM should be powered-down after the master clock is stopped if clocks are supplied when all blocks except for
VCOM are powered-down. The AK4636 is also powered-down by the PDN pin = “L”. In this case, the registers are
initialized.
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[AK4636]
PACKAGE (AK4636ECB)
29pin CSP: 2.5mm x 3.0mm
Top View
Bottom View
A
2.46 ± 0.05
6
6
5
5
4
4636
3
XXXX
B
2.96 ± 0.05
4
3
2
2
1
1
B
C
D
E
E
0.625 ± 0.05
D
C
B
φ 0.3 ± 0.05
0.25 ± 0.05
A
0.5
A
φ 0.05
M S AB
S
0.08 S
■ Material & Lead finish
Package material: Epoxy resin, Halogen (bromine and chlorine) free
Solder ball material: SnAgCu
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[AK4636]
PACKAGE (AK4636EN)
32pin QFN (Unit: mm)
4.0 ± 0.1
2.4 ± 0.1
17
24
0.40 ± 0.10
25
2.4 ± 0.1
4.0 ± 0.1
16
A
Exposed
Pad
32
9
0.45 ± 0.10
8
1
0.22 ± 0.05
B
0.18 ± 0.05
0.05 M
C0.3
PIN #1 ID
0.00 MIN
0.05 MAX
0.4
0.65 MAX
0.08
Note: The exposed pad on the bottom surface of the package must be open or connected to the ground.
■ Material & Lead finish
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
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[AK4636]
MARKING (AK4636ECB)
4636
XXXX
1
A
“4636”: Market Number
XXXX: Date code (4 digit)
●: Pin #1 indication
MARKING (AK4636EN)
4636
XXXX
1
XXXX: Date code identifier (4 digit)
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[AK4636]
REVISION HISTORY
Date (YY/MM/DD)
09/02/27
10/08/19
Revision
00
01
Reason
First Edition
Error
Correction
Page
Contents
46
Transfer function was changed.
“H(z) = {1 + h2(z) + h3(z) + h4(z) + h5(z) } x h1(z)” →
“H(z) = {1 + h2(z) + h3(z) + h4(z) + h5(z) } x {1+h1(z)}”
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
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