DRV8832-Q1 www.ti.com SLVSBW9B – APRIL 2013 – REVISED JANUARY 2014 LOW-VOLTAGE MOTOR DRIVER IC Check for Samples: DRV8832-Q1 FEATURES 1 • • 2 • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: -40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C4B H-Bridge Voltage-Controlled Motor Driver – Drives DC Motor, One Winding of a Stepper Motor, or Other Actuators/Loads – Efficient PWM Voltage Control for Constant Motor Speed With Varying Supply Voltages – Low MOSFET On-Resistance: HS + LS 450 mΩ 1-A Maximum DC/RMS or Peak Drive Current 2.75-V to 6.8-V Operating Supply Voltage Range • • • • • 300-nA (Typical) Sleep Mode Current Reference Voltage Output Current Limit Circuit Fault Output Thermally Enhanced Surface Mount Packages APPLICATIONS • • Battery-Powered: – Printers – Toys – Robotics – Cameras – Phones Small Actuators, Pumps, etc. DESCRIPTION The DRV8832-Q1 provides an integrated motor driver solution for battery-powered toys, printers, and other lowvoltage or battery-powered motion control applications. The device has one H-bridge driver, and can drive one DC motor or one winding of a stepper motor, as well as other loads like solenoids. The output driver block consists of N-channel and P-channel power MOSFET’s configured as an H-bridge to drive the motor winding. Provided with sufficient PCB heatsinking, the DRV8832-Q1 can supply up to 1-A of DC/RMS or peak output current. It operates on power supply voltages from 2.75 V to 6.8 V. To maintain constant motor speed over varying battery voltages while maintaining long battery life, a PWM voltage regulation method is provided. An input pin allows programming of the regulated voltage. A built-in voltage reference output is also provided. Internal protection functions are provided for over current protection, short circuit protection, under voltage lockout and overtemperature protection. The DRV8832-Q1 also provides a current limit function to regulate the motor current during conditions like motor startup or stall, as well as a fault output pin to signal a host processor of a fault condition. The DRV8832-Q1 is available in tiny 3-mm x 3-mm 10-pin MSOP package with PowerPAD™ (Eco-friendly: RoHS & no Sb/Br). 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013–2014, Texas Instruments Incorporated DRV8832-Q1 SLVSBW9B – APRIL 2013 – REVISED JANUARY 2014 www.ti.com ORDERING INFORMATION (1) -40°C to 125°C (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING Reel of 250 DRV8832QDGQRQ1 8832Q Tube of 80 DRV8832QDGQQ1 8832Q PACKAGE (2) TA PowerPAD™ (MSOP) - DGQ For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DEVICE INFORMATION Functional Block Diagram Battery VCC VCC VCC OCP Integ. Comp VREF Ref Gate Drive + OUT1 VSET DCM VCC Logic IN1 OCP IN2 Gate Drive OverTemp FAULTn OUT2 Osc Current Sense ISENSE GND 2 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: DRV8832-Q1 DRV8832-Q1 www.ti.com SLVSBW9B – APRIL 2013 – REVISED JANUARY 2014 Table 1. TERMINAL FUNCTIONS EXTERNAL COMPONENTS OR CONNECTIONS NAME PIN I/O (1) GND 5 - Device ground VCC 4 - Device and motor supply Bypass to GND with a 0.1-μF (minimum) ceramic capacitor. IN1 9 I Bridge A input 1 Logic high sets OUT1 high DESCRIPTION IN2 10 I Bridge A input 2 Logic high sets OUT2 high VREF 8 O Reference voltage output Reference voltage output VSET 7 I Voltage set input Input voltage sets output regulation voltage FAULTn 6 OD Fault output Open-drain output driven low if fault condition present OUT1 3 O Bridge output 1 Connect to motor winding OUT2 1 O Bridge output 2 Connect to motor winding ISENSE 2 IO Current sense resistor Connect current sense resistor to GND. Resistor value sets current limit level. (1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output DGQ PACKAGE (TOP VIEW) OUT2 ISENSE OUT1 VCC GND 1 10 2 9 3 4 5 GND (PPAD) 8 7 6 IN2 IN1 VREF VSET FAULTn ABSOLUTE MAXIMUM RATINGS (1) (2) VCC VALUE UNIT Power supply voltage range –0.3 to 7 V Input pin voltage range –0.5 to 7 V Internally limited A 1 A Peak motor drive output current (3) Continuous motor drive output current (3) Continuous total power dissipation See Dissipation Ratings table TJ Operating virtual junction temperature range –40 to 150 °C Tstg Storage temperature range –60 to 150 °C (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Power dissipation and thermal limits must be observed. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: DRV8832-Q1 3 DRV8832-Q1 SLVSBW9B – APRIL 2013 – REVISED JANUARY 2014 www.ti.com THERMAL INFORMATION DRV8832-Q1 THERMAL METRIC (1) DGQ UNITS 10 PINS Junction-to-ambient thermal resistance (2) θJA 69.3 (3) θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (4) 51.6 ψJT Junction-to-top characterization parameter (5) 1.5 ψJB Junction-to-board characterization parameter (6) 23.2 θJCbot Junction-to-case (bottom) thermal resistance (7) 9.5 (1) (2) (3) (4) (5) (6) (7) 63.5 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VCC IOUT (1) 4 Motor power supply voltage range Continuous or peak H-bridge output current (1) NOM MAX UNIT 2.75 6.8 V 0 1 A Power dissipation and thermal limits must be observed. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: DRV8832-Q1 DRV8832-Q1 www.ti.com SLVSBW9B – APRIL 2013 – REVISED JANUARY 2014 ELECTRICAL CHARACTERISTICS VCC = 2.75 V to 6.8 V, TA = -40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES IVCC VCC operating supply current VCC = 5 V 1.4 2 mA IVCCQ VCC sleep mode supply current VCC = 5 V, TA = 25°C 0.3 1 μA VCC undervoltage lockout voltage VCC rising 2.575 2.75 VCC falling 2.47 VUVLO V LOGIC-LEVEL INPUTS VIL Input low voltage VIH Input high voltage IIL Input low current VIN = 0 IIH Input high current VIN = 3.3 V 0.25 x VCC V 10 μA 50 μA 0.5 x VCC V -10 LOGIC-LEVEL OUTPUTS (FAULTn) VOL Output low voltage VCC = 5 V, IOL = 4 mA (1) 0.5 VCC = 5 V, I O = 0.8 A, TJ = 125°C 340 VCC = 5 V, I O = 0.8 A, TJ = 25°C 250 VCC = 5 V, I O = 0.8 A, TJ = 125°C 270 VCC = 5 V, I O = 0.8 A, TJ = 25°C V H-BRIDGE FETS RDS(ON) HS FET on resistance RDS(ON) LS FET on resistance IOFF Off-state leakage current 450 360 200 mΩ mΩ –20 20 μA 300 ns MOTOR DRIVER tR Rise time VCC = 3 V, load = 4 Ω 50 tF Fall time VCC = 3 V, load = 4 Ω 50 fSW Internal PWM frequency 300 44.5 ns kHz PROTECTION CIRCUITS IOCP Overcurrent protection trip level tOCP OCP deglitch time TTSD Thermal shutdown temperature 1.3 3 A μs 2 Die temperature (1) 150 160 180 °C 1.235 1.285 1.335 V VOLTAGE CONTROL VREF Reference output voltage ΔVLINE Line regulation VCC = 3.3 V to 6 V, VOUT = 3 V (1) IOUT = 500 mA ΔVLOAD Load regulation VCC = 5 V, VOUT = 3 V IOUT = 200 mA to 800 mA (1) ±1 % ±1 % CURRENT LIMIT VILIM Current limit sense voltage tILIM Current limit fault deglitch time RISEN Current limit set resistance (external resistor value) (1) 160 200 240 275 0 mV ms 1 Ω Not production tested. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: DRV8832-Q1 5 DRV8832-Q1 SLVSBW9B – APRIL 2013 – REVISED JANUARY 2014 www.ti.com TYPICAL PERFORMANCE GRAPHS EFFICIENCY EFFICIENCY vs LOAD CURRENT (VIN = 5 V, VOUT = 3 V) 100% 95% 90% 85% 80% 75% 70% 65% 60% 55% 50% 0.2 0.4 0.6 0.8 LOAD - A Figure 1. EFFICIENCY vs OUTPUT VOLTAGE (VIN = 5 V, IOUT = 500 mA) 100% 90% 80% EFFICENCY 70% 60% 50% 40% 30% Linear Regulator 20% DRV8832-Q1 10% 0% 0.5 1.5 2.5 3.5 4.5 5.5 VOUT - V Figure 2. FUNCTIONAL DESCRIPTION Power Supervisor The DRV8832 is capable of entering a low-power sleep mode by bringing both of the INx control inputs logic low. The outputs will be disabled Hi-Z. In order to exit the sleep mode, bring either or both of the INx inputs logic high. This will enable the H-bridges. When exiting the sleep mode, the FAULTn pin will pulse low. PWM Motor Driver The DRV8832-Q1 contains an H-bridge motor driver with PWM voltage-control circuitry with current limit circuitry. A block diagram of the motor control circuitry is shown below. 6 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: DRV8832-Q1 DRV8832-Q1 www.ti.com SLVSBW9B – APRIL 2013 – REVISED JANUARY 2014 VCC VCC OCP IN1 OUT 1 IN2 Predrive PWM DCM OUT2 VSET + COMP OCP /4 Integrator DIFF + - ITRIP ISEN COMP REF Figure 3. Motor Control Circuitry Bridge Control The IN1 and IN2 control pins enable the H-bridge outputs. The following table shows the logic: Table 2. H-Bridge Logic IN1 IN2 OUT1 OUT2 Function 0 0 Z Z Sleep/coast 0 1 L H Reverse 1 0 H L Forward 1 1 H H Brake When both bits are zero, the output drivers are disabled and the device is placed into a low-power sleep state. The current limit fault condition (if present) is also cleared. Note that when transitioning from either brake or sleep mode to forward or reverse, the voltage control PWM starts at zero duty cycle. The duty cycle slowly ramps up to the commanded voltage. This can take up to 12 ms to go from sleep to 100% duty cycle. Because of this, highspeed PWM signals cannot be applied to the IN1 and IN2 pins. To control motor speed, use the VSET pin as described below. Because of the sleep mode functionality described previously, when applying an external PWM to the DRV8832Q1, hold one input logic high while applying a PWM signal to the other. If the logic input is held low instead, then the device will cycle in and out of sleep mode, causing the FAULTn pin to pulse low on every sleep mode exit. Voltage Regulation The DRV8832-Q1 provides the ability to regulate the voltage applied to the motor winding. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8832-Q1 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: DRV8832-Q1 7 DRV8832-Q1 SLVSBW9B – APRIL 2013 – REVISED JANUARY 2014 www.ti.com The circuit monitors the voltage difference between the output pins and integrates it, to get an average DC voltage value. This voltage is divided by 4 and compared to the VSET pin voltage. If the averaged output voltage (divided by 4) is lower than VSET, the duty cycle of the PWM output is increased; if the averaged output voltage (divided by 4) is higher than VSET, the duty cycle is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. This is shown in the diagram below as case 1. The current flow direction shown indicates the state when IN1 is high and IN2 is low. Note that if the programmed output voltage is greater than the supply voltage, the device will operate at 100% duty cycle and the voltage regulation feature will be disabled. In this mode the device behaves as a conventional H-bridge driver. During the PWM off time, winding current is re-circulated by enabling both of the high-side FETs in the bridge. This is shown as case 2 below. VCC 2 1 OUT1 Shown with OUT2 IN1=1, IN2=0 1 PWM on 2 PWM off Figure 4. Voltage Regulation Reference Output The DRV8832-Q1 includes a reference voltage output that can be used to set the motor voltage. Typically for a constant-speed application, VSET is driven from VREF through a resistor divider to provide a voltage equal to 1/4 the desired motor drive voltage. For example, if VREF is connected directly to VSET, the voltage will be regulated at 5.14 V. If the desired motor voltage is 3 V, VREF should be 0.75 V. This can be obtained with a voltage divider using 53 kΩ from VREF to VSET, and 75 kΩ from VSET to GND. 8 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: DRV8832-Q1 DRV8832-Q1 www.ti.com SLVSBW9B – APRIL 2013 – REVISED JANUARY 2014 Current Limit A current limit circuit is provided to protect the system in the event of an overcurrent condition, such as what would be encountered if driving a DC motor at start-up or with an abnormal mechanical load (stall condition). The motor current is sensed by monitoring the voltage across an external sense resistor. When the voltage exceeds a reference voltage of 200 mV for more than approximately 3 µs, the PWM duty cycle is reduced to limit the current through the motor to this value. This current limit allows for starting the motor while controlling the current. If the current limit condition persists for some time, it is likely that a fault condition has been encountered, such as the motor being run into a stop or a stalled condition. An overcurrent event must persist for approximately 275 ms before the fault is registered. After approximately 275 ms, a fault signaled to the host by driving the FAULTn signal low. Operation of the motor driver will continue. The current limit fault condition is self-clearing and will be released when the abnormal load (stall condition) is removed. The resistor used to set the current limit must be less than 1 Ω. Its value may be calculated as follows: 200 mV RISENSE = ¾ ILIMIT (1) Where: RISENSE is the current sense resistor value. ILIMIT is the desired current limit (in mA). If the current limit feature is not needed, the ISENSE pin may be directly connected to ground. Protection Circuits The DRV8832-Q1 is fully protected against undervoltage, overcurrent and overtemperature events. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled, and the FAULTn signal will be driven low. The device will remain disabled until VCC is removed and re-applied. Overcurrent conditions are sensed independently on both high and low side devices. A short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Note that OCP is independent of the current limit function, which is typically set to engage at a lower current level; the OCP function is intended to prevent damage to the device under abnormal (e.g., short-circuit) conditions. Thermal Shutdown (TSD) If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the FAULTn signal will be driven low. Once the die temperature has fallen to a safe level operation will automatically resume. Undervoltage Lockout (UVLO) If at any time the voltage on the VCC pins falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled, the FAULTn signal will be driven low, and internal logic will be reset. Operation will resume when VCC rises above the UVLO threshold. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: DRV8832-Q1 9 DRV8832-Q1 SLVSBW9B – APRIL 2013 – REVISED JANUARY 2014 www.ti.com THERMAL INFORMATION Thermal Protection The DRV8832-Q1 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately 160°C, the device will be disabled until the temperature drops to a safe level. Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. Power Dissipation Power dissipation in the DRV8832-Q1 is dominated by the power dissipated in the output FET resistance, or RDS(ON). Average power dissipation when running a stepper motor can be roughly estimated by Equation 2. PTOT = 2 · RDS(ON) · (IOUT(RMS)) 2 (2) where PTOT is the total power dissipation, RDS(ON) is the resistance of each FET, and IOUT(RMS) is the RMS output current being applied to each winding. IOUT(RMS) is equal to the approximately 0.7x the full-scale output current setting. The factor of 2 comes from the fact that at any instant two FETs are conducting winding current for each winding (one high-side and one low-side). The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and heatsinking. Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must be taken into consideration when sizing the heatsink. Heatsinking The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers. For details about how to design the PCB, refer to TI application report SLMA002, " PowerPAD™ Thermally Enhanced Package" and TI application brief SLMA004, " PowerPAD™ Made Easy", available at www.ti.com. In general, the more copper area that can be provided, the more power can be dissipated. 10 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: DRV8832-Q1 DRV8832-Q1 www.ti.com SLVSBW9B – APRIL 2013 – REVISED JANUARY 2014 REVISION HISTORY Changes from Revision A (August 2013) to Revision B Page • Added Power Supervisor section .......................................................................................................................................... 6 • Changed Bridge Control section ........................................................................................................................................... 7 • Changed Current Limit section ............................................................................................................................................. 9 • Changed Thermal Shutdown (TSD) section ......................................................................................................................... 9 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: DRV8832-Q1 11 PACKAGE OPTION ADDENDUM www.ti.com 31-Dec-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DRV8832QDGQQ1 ACTIVE MSOPPowerPAD DGQ 10 80 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 8832Q DRV8832QDGQRQ1 ACTIVE MSOPPowerPAD DGQ 10 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 8832Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF DRV8832-Q1 : • Catalog: DRV8832 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 31-Dec-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DRV8832QDGQRQ1 Package Package Pins Type Drawing MSOPPower PAD DGQ 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 31-Dec-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8832QDGQRQ1 MSOP-PowerPAD DGQ 10 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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