Cypress CY7C60323-LTXCT Encoreâ ¢ iii low voltage Datasheet

CY7C603xx
enCoRe™ III Low Voltage
Features
Applications
■
Powerful Harvard Architecture Processor
❐ M8C Processor speeds to 12 MHz
❐ Low power at high speed
❐ 2.4V to 3.6V Operating Voltage
❐ Operating Voltages down to 1.0V using On-Chip Switch
Mode Pump (SMP)
❐ Commercial Temperature Range: 0°C to +70°C
■
Wireless mice
■
Wireless gamepads
■
Wireless Presenter tools
■
Wireless keypads
■
PlayStation® 2 wired gamepads
Configurable Peripherals
❐ 8-Bit Timers/Counters/PWM
❐ Full Duplex Master or Slave SPI
❐ 10-bit ADC
❐ 8-bit Successive Approximation ADC
❐ Comparator
■
PlayStation 2 bridges for wireless gamepads
❐ Applications requiring a cost effective low voltage 8-bit
microcontroller.
■
Block Diagram
Port 3
■
■
■
Flexible On-Chip Memory
❐ 8K Flash Program Storage 50,000 Erase/Write Cycles
❐ 512 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
Global Digital
Interconnect
Versatile Analog Mux
❐ Common Internal Analog Bus
❐ Simultaneous connection of IO combinations
•
198 Champion Court
Flash 8K
CPU Core
(M8C)
Interrupt
Controller
Sleep and
Watchdog
Clock Sources (Includes IMO and ILO)
enCoRe II LV Core
Digital
PSoC
Block
Array
Digital
Clocks
POR and LVD
I2C
System Resets
ANALOG SYSTEM
Analog
PSoC
Block
Array
Switch
Mode
Pump
Analog
Ref.
Internal
Voltage
Ref.
Analog
Mux
SYSTEM RESOURCES
Additional System Resources
2
❐ I C Master, Slave and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
Cypress Semiconductor Corporation
Document #: 38-16018 Rev. *E
SROM
DIGITAL SYSTEM
■
Port 0
Global Analog Interconnect
SRAM
512 Bytes
Precision, Programmable Clocking
❐ Internal ±2.5% 24-/48-MHz Oscillator
❐ Internal Oscillator for Watchdog and Sleep
Programmable Pin Configurations
❐ 10 mA Drive on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐ Up to 8 Analog Inputs on GPIO
❐ Configurable Interrupt on all GPIO
Port 1
System Bus
Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full-Featured, In-Circuit Emulator and Programmer
❐ Complex Breakpoint Structure
❐ 128K Trace Memory
■
■
Port 2
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 29, 2008
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CY7C603xx
enCoRe III Low Voltage Functional Overview
Figure 1. Digital System Block Diagram
Port 3
The enCoRe III Low Voltage (enCoRe III LV) CY7C603xx device
is based on the flexible PSoC® architecture. This supports a
simple set of peripherals that can be configured to match the
needs of each application. Additionally, a fast CPU, Flash
program memory, SRAM data memory, and configurable IO are
included in a range of convenient pinouts.
Port 1
Port 2
Digital Clocks
From Core
This architecture enables the user to create customized
peripheral configurations that match the requirements of each
individual application. A fast CPU, Flash program memory,
SRAM data memory, and configurable IO are included in both
28-pin SSOP and 32-pin QFN packages.
Port 0
To System Bus
To Analog
System
DIGITAL SYSTEM
The enCoRe III LV architecture, as shown in Figure 1, consists
of four main areas: the enCoRe III LV Core, the System
Resources, Digital System, and Analog System. Configurable
global bus resources allow combining all the device resources
into a complete custom system. Each enCoRe III LV device
supports a limited set of digital and analog peripherals.
Depending on the package, up to 28 general purpose IOs
(GPIOs) are also included. The GPIOs provide access to the
global digital and analog interconnects.
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
Row Output
Configuration
Row Input
Configuration
Digital enCoRe II LV Block Array
8
8
8
8
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
enCoRe III LV Core
The enCoRe III LV core is a powerful engine that supports a rich
feature set. It encompasses SRAM for data storage, an interrupt
controller, sleep and watchdog timers, and IMO (internal main
oscillator) and ILO (internal low-speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 12 MHz. The M8C is a four MIPS 8-bit Harvard
architecture microprocessor. The core includes a CPU, memory,
clocks, and configurable GPIO (General Purpose IO).
The digital blocks may be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
The Analog System
System Resources provide additional capability, such as digital
clocks to increase flexibility, I2C functionality for implementing an
I2C master, slave, MultiMaster, an internal voltage reference that
provides an absolute value of 1.3V to a number of subsystems,
a switch mode pump (SMP) that generates normal operating
voltages off a single battery cell, and various system resets
supported by the M8C.
The Analog System consists of two configurable blocks. Analog
peripherals are very flexible and may be customized to support
specific application requirements. Some of the common analog
functions for this device (available as user modules) are:
The Digital System
The Digital System consists of 4 digital enCoRe III LV blocks.
Each block is an 8-bit resource. Digital peripheral configurations
include the following:
■
PWM usable as Timer/Counter
■
SPI master and slave
■
I2C slave and multi-master
■
CMP
■
ADC10
■
SARADC
Document #: 38-16018 Rev. *E
■
Analog-to-digital converters (single with 8-bit resolution)
■
Pin-to-pin comparators
■
Single-ended comparators with absolute (1.3V) reference
■
1.3V reference (as a System Resource)
Analog blocks are provided in columns of two, which includes
one CT (Continuous Time - ACE00 or ACE01) and one SC
(Switched Capacitor - ASE10 or ASE11) blocks.
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CY7C603xx
Figure 2. Analog System Block Diagram
Array Input
■
Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■
An internal 1.3 voltage reference provides an absolute
reference for the analog system.
■
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low-cost boost converter.
■
Versatile analog multiplexer system.
Configuration
ACI0[1:0]
ACI1[1:0]
enCoRe III LV Device Characteristics
AllIO
X
The enCoRe III LV devices have four digital blocks and four
analog blocks. Table 1 lists the resources available for specific
enCoRe III LV devices.
X
X
ACOL1MUX
X
Analog Mux Bus
ACE01
ASE10
ASE11
Part
Number
Flash
Size
ACE00
SRAM
Size
Array
Digital
IO
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
Table 1. enCoRe III LV Device Characteristics
X
CY7C60323 24
-PVXC
1
4
24
0
2
4
512 8K
Bytes
CY7C60323 28
-LFXC
1
4
28
0
2
4
512 8K
Bytes
CY7C60333 28
-LFXC
1
4
26
0
2
4
512 8K
Bytes
The Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with
comparators and analog-to-digital converters. An additional 8:1
analog input multiplexer provides a second path to bring Port 0
pins to the analog array.
Additional System Resources
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a switch mode pump, low
voltage detection, and power on reset. Brief statements
describing the merits of each system resource follow.
■
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks may
be generated using digital blocks as clock dividers.
The I2C module provides 100 kHz and 400 kHz communication
over two wires. Slave, master, and multi-master modes are all
supported.
Document #: 38-16018 Rev. *E
Getting Started
The quickest path to understanding the enCoRe III LV silicon is
by reading this data sheet and using the PSoC Designer
Integrated Development Environment (IDE). This data sheet is
an overview of the enCoRe III LV and presents specific pin,
register, and electrical specifications. enCoRe III LV is based on
the architecture of the CY8C21x34. For in-depth information,
along with detailed programming information, refer to the PSoC
Mixed-Signal Array Technical Reference Manual, which is
available at http://www.cypress.com/psoc.
For up-to-date Ordering, Packaging, and Electrical Specification
information, refer to the latest device data sheets on the web at
http://www.cypress.com.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
enCoRe III LV development. Go to the Cypress Online Store web
site at http://www.cypress.com, click the Online Store shopping
cart icon at the bottom of the web page, and click USB (Universal
Serial Bus) to view a current list of available items.
Page 3 of 31
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CY7C603xx
Development Tools
PSoC Designer is a Microsoft® Windows®-based, integrated
development environment for the enCoRe III LV. The PSoC
Designer IDE and application runs on Windows NT 4.0, Windows
2000, Windows Millennium (Me), or Windows XP. (Refer
Figure 3)
PSoC Designer helps the customer to select an operating
configuration, write application code that uses the enCoRe III LV,
and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Figure 3. PSoC Designer Subsystems
Context
Sensitive
Help
Graphical Designer
Interface
Results
Commands
PSoCTM
Designer
selected components and, if the project uses more than one
operating configuration, contains routines to switch between
different sets of block configurations at run time. PSoC Designer
can print out a configuration sheet for a given project
configuration for use during application programming in
conjunction with the Device Data Sheet. After the framework is
generated, the user can add application-specific code to flesh
out the framework. It is also possible to change the selected
components and regenerate the framework.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.
Assembler. The macro assembler allows the assembly code to
be merged seamlessly with C code. The link libraries
automatically use absolute addressing or can be compiled in
relative mode and linked with other software modules to get
absolute addressing.
C Language Compiler. A C language compiler that supports the
enCoRe III LV family of devices is available. Even if you have
never worked in the C language before, the product quickly
allows you to create complete C programs.
The embedded, optimizing C compiler provides all the features
of C tailored to the enCoRe III LV architecture. It comes complete
with embedded libraries providing port and bus operations,
standard keypad and display support, and extended math
functionality.
Importable
Design
Database
Debugger
Device
Database
Application
Database
PSoC
Configuration
Sheet
PSoCTM
Designer
Core
Engine
Manufacturing
Information
File
Project
Database
User
Modules
Library
Emulation
Pod
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, enabling designers to test the program in a
physical system while providing an internal view of the device.
Debugger commands allow the designer to read the program
and read and write data memory, read and write IO registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
Online Help System
In-Circuit
Emulator
Device
Programmer
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
PSoC Designer Software Subsystems
Device Editor
The device editor subsystem enables the user to select different
on-board analog and digital components called user modules
using the blocks. Examples of user modules are ADCs, PWMs,
and SPI.
PSoC Designer sets up power on initialization tables for selected
block configurations and creates source code for an application
framework. The framework contains software to operate the
Document #: 38-16018 Rev. *E
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
enCoRe III LV, enCoRe III, and all PSoC devices. Emulation
pods for each device family are available separately. The
emulation pod takes the place of the enCoRe III LV device in the
target board and performs full speed (12 MHz) operation.
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CY7C603xx
Designing with User Modules
The development process for the enCoRe III LV device differs
from that of a traditional fixed-function microprocessor. The
configurable analog and digital hardware blocks provide a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources have the ability to implement a
wide variety of user-selectable functions. Each block has several
registers that determine its function and connectivity to other
blocks, multiplexers, buses and to the IO pins. Iterative
development cycles permit you to adapt the hardware and
software. This substantially lowers the risk of having to select a
different part to meet the final design requirements.
To speed the development process, the PSoC Designer
Integrated Development Environment (IDE) provides a library of
prebuilt, pretested hardware peripheral functions, called “User
Modules.” User Modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library
contains seven common peripherals such as ADCs, SPI, I2C
and PWMs to configure the enCoRe III LV peripherals.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures a digital enCoRe III LV block for 8 bits of resolution.
The user module parameters permit you to establish the pulse
width and duty cycle. User modules also provide tested software
to cut your development time. The user module application
programming interface (API) provides high-level functions to
control and respond to hardware events at run time. The API also
provides optional interrupt service routines that you can adapt as
needed.
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the enCoRe III LV
blocks with point-and-click simplicity. Next, you build signal
chains by interconnecting user modules to each other and the IO
pins. At this stage, you also configure the clock source
connections and enter parameter values directly or by selecting
values from drop-down menus. When you are ready to test the
hardware configuration or move on to developing code for the
project, perform the “Generate Application” step. This causes
PSoC Designer to generate source code that automatically
configures the device to your specification and provides the
high-level user module API functions.
Document #: 38-16018 Rev. *E
Figure 4. User Module and Source Code Development Flows
Device Editor
User
Module
Selection
Placement
and
Parameter
-ization
Source
Code
Generator
Generate
Application
Application Editor
Project
Manager
Source
Code
Editor
Build
Manager
Build
All
Debugger
Interface
to ICE
Storage
Inspector
Event &
Breakpoint
Manager
The next step is to write your main program, and any subroutines
using PSoC Designer’s Application Editor subsystem.
The
Application Editor includes a Project Manager that allows you to
open the project source code files (including all generated code
files) from a hierarchal view. The source code editor provides
syntax coloring and advanced edit features for both C and
assembly language. File search capabilities include simple string
searches and recursive “grep-style” patterns. A single mouse
click invokes the Build Manager. It employs a
professional-strength “makefile” system to automatically analyze
all file dependencies and run the compiler and assembler as
necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in a
console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
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CY7C603xx
Document Conventions
Table 2. Acronyms Used
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CT
continuous time
ECO
external crystal oscillator
Units of Measure
A units of measure table is located in the Electrical Specifications
section. Table 8 on page 15 lists all the abbreviations used to
measure the enCoRe III LV devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.
EEPROM electrically erasable programmable read-only
memory
FSR
full scale range
GPIO
general purpose IO
GUI
graphical user interface
HBM
human body model
ICE
in-circuit emulator
ILO
internal low speed oscillator
IMO
internal main oscillator
IO
input/output
IPOR
imprecise power on reset
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
PC
program counter
PLL
phase-locked loop
POR
power on reset
PPOR
precision power on reset
PSoC
Programmable System-on-Chip™
PWM
pulse width modulator
SC
switched capacitor
SRAM
static random access memory
Document #: 38-16018 Rev. *E
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CY7C603xx
Pin Information
The enCoRe III LV device is available in 28-pin SSOP and 32-pin QFN packages, which are listed and shown in the following tables.
Every port pin (labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, SMP, and
XRES are not capable of Digital IO.
28-Pin Part Pinout
Figure 5. CY7C60323-PVXC 28-Pin Device
A, I, M, P0[7]
A, I, M, P0[5]
A, I, M, P0[3]
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
Vss
M, I2C SCL, P1[7]
M, I2C SDA, P1[5]
M, P1[3]
M, I2C SCL, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
XRES
P1[6], M
P1[4], EXTCLK, M
P1[2], M
P1[0], I2C SDA, M
Table 3. Pin Definitions - CY7C60323-PVXC 28-Pin Device
Type
Pin No.
Digital
Analog
Name
Description
1
IO
I, M
P0[7]
Analog Column Mux Input.
2
IO
I, M
P0[5]
Analog Column Mux Input and Column Output.
3
IO
I, M
P0[3]
Analog Column Mux Input and Column Output, Integrating Input.
4
IO
I, M
P0[1]
Analog Column Mux Input, Integrating Input.
5
IO
M
P2[7]
6
IO
M
P2[5]
7
IO
I, M
P2[3]
8
IO
I, M
P2[1]
Direct Switched Capacitor Block Input.
9
Power
Vss
Ground Connection.
10
IO
M
P1[7]
I2C Serial Clock (SCL).
11
IO
M
P1[5]
I2C Serial Data (SDA).
12
IO
M
P1[3]
13
IO
M
P1[1]
14
Power
15
IO
16
Direct Switched Capacitor Block Input.
I2C Serial Clock (SCL), ISSP-SCLK.
Vss
Ground Connection.
M
P1[0]
I2C Serial Data (SDA), ISSP-SDATA.
IO
M
P1[2]
17
IO
M
P1[4]
18
IO
M
P1[6]
19
Input
XRES
Active HIGH External Reset with Internal Pull Down.
20
IO
I, M
P2[0]
Direct Switched Capacitor Block Input.
21
IO
I, M
P2[2]
Direct Switched Capacitor Block Input.
22
IO
M
P2[4]
23
IO
M
P2[6]
24
IO
I, M
P0[0]
Document #: 38-16018 Rev. *E
Optional External Clock Input (EXTCLK).
Analog Column Mux Input.
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CY7C603xx
Table 3. Pin Definitions - CY7C60323-PVXC 28-Pin Device (continued)
Type
Pin No.
Digital
Analog
Name
Description
25
IO
I, M
P0[2]
Analog Column Mux Input.
26
IO
I, M
P0[4]
Analog Column Mux Input.
27
IO
I, M
P0[6]
Analog Column Mux Input.
28
Power
Vdd
Supply Voltage.
LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input.
Document #: 38-16018 Rev. *E
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CY7C603xx
32-Pin Part Pinout
Vss
P0[3], A, I, M
P0[5], A, I, M
P0[7], A, I, M
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
32
31
30
29
28
27
1
2
3
4
5
6
7
8
QFN
24
23
22
21
20
19
18
17
M, 12C SDA, P1[5]
M, P1[3]
M, 12C SCL, P1[1]
Vss
M, 12C SDA, P1[0]
M, P1[2]
M, EXTCLK, P1[4]
M, P1[6]
9
10
11
12
13
14
15
16
M, P3[1]
M, 12C SCL, P1[7]
Document #: 38-16018 Rev. *E
26
25
15
M, EXTCLK,
M, P1[4]
P1[6]
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P3[0], M
XRES
16
13
14
P0[0], A, I, M
P2[6], M
Vss
P0[3], A, I, M
P0[5], A, I, M
P0[7], A, I, M
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
Figure 9. CY7C60333-LTXC 32-Pin Device
P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P3[0], M
XRES
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
SMP
Vss
M, 12C SCL, P1[7]
32
31
30
29
28
27
26
25
32
31
30
29
28
27
26
25
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
M, P3[3]
M, I2C SCL, P1[1]
Vss
M, I2C SDA, P1[0]
M, P1[2]
(Top View)
24
23
22
21
20
19
18
17
9
10
11
12
M, I2C SCL, P1[1]
Vss
M, I2C SDA, P1[0]
M, P1[2]
M, EXTCLK, P1[4]
M, P1[6]
M, I2C SDA, P1[5]
M, P1[3]
QFN
Vss
P0[3], A, I, M
P0[5], A, I, M
P0[7], A, I, M
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
Figure 8. CY7C60323-LTXC 32-Pin Device
1
2
3
4
5
6
7
8
M, I2C SDA, P1[5]
M, P1[3]
(Top View)
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P3[0], M
XRES
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
SMP
Vss
M, I2C SCL, P1[7]
1
2
3
4
5
6
7
8
QFN
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
QFN
P0[0], A, I, M
P2[6], M
24
23
22
21
20
19
18
17
Figure 7. CY7C60333-LFXC 32-Pin Device
P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P3[0], M
XRES
M, 12C SDA, P1[5]
M, P1[3]
M, 12C SCL, P1[1]
Vss
M, 12C SDA, P1[0]
M, P1[2]
M, EXTCLK, P1[4]
M, P1[6]
P0[4], A, I, M
P0[2], A, I, M
26
25
A, I, M
Vss
P0[3],
P0[5],
P0[7],
Vdd
P0[6],
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
M, P3[3]
M, P3[1]
M, I2C SCL, P1[7]
32
31
30
29
28
27
A, I, M
A, I, M
A, I, M
Figure 6. CY7C60323-LFXC 32-Pin Device
Page 9 of 31
[+] Feedback
CY7C603xx
Table 4. 32-Pin Part Pinout (QFN*)
Pin
No.
Type
Digital
Analog
Name
Description
1
IO
I, M
P0[1]
2
IO
M
P2[7]
3
IO
M
P2[5]
4
IO
M
P2[3]
5
IO
M
P2[1]
6
IO
M
P3[3]
In CY7C60323 Part.
6
Power
SMP
Switch Mode Pump (SMP) Connection to required external components in CY7C60333
Part.
7
IO
P3[1]
In CY7C60323 Part.
7
Power
Vss
Ground Connection in CY7C60333 Part.
8
IO
M
P1[7]
I2C Serial Clock (SCL).
9
IO
M
P1[5]
I2C Serial Data (SDA).
10
IO
M
P1[3]
11
IO
M
P1[1]
I2C Serial Clock (SCL), ISSP-SCLK.
12
Power
Vss
Ground Connection.
13
IO
M
P1[0]
I2C Serial Data (SDA), ISSP-SDATA.
14
IO
M
P1[2]
15
IO
M
P1[4]
16
IO
M
P1[6]
17
Input
18
IO
M
P3[0]
19
IO
M
P3[2]
20
IO
M
P2[0]
21
IO
M
P2[2]
22
IO
M
P2[4]
23
IO
M
P2[6]
24
IO
I, M
P0[0]
Analog Column Mux Input.
25
IO
I, M
P0[2]
Analog Column Mux Input.
26
IO
I, M
P0[4]
Analog Column Mux Input.
27
IO
I, M
P0[6]
Analog Column Mux Input.
28
Power
Vdd
Supply Voltage.
29
IO
I, M
P0[7]
Analog Column Mux Input.
30
IO
I, M
P0[5]
Analog Column Mux Input.
31
IO
I, M
P0[3]
Analog Column Mux Input, Integrating Input.
32
Power
Vss
Ground Connection.
M
XRES
Analog Column Mux Input, Integrating Input.
Optional External Clock Input (EXTCLK).
Active HIGH External Reset with Internal Pull Down.
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* The QFN package has a center pad that must be connected to ground (Vss).
Document #: 38-16018 Rev. *E
Page 10 of 31
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CY7C603xx
Register Reference
Register Mapping Tables
This section lists the registers of the enCoRe III LV device. For
detailed register information, refer the PSoC Mixed-Signal Array
Technical Reference Manual.
The enCoRe III LV device has a total register address space of
512 bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.
Register Conventions
The register conventions specific to this section are listed in
Table 5.
Table 5. Register Conventions
Convention
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Table 6. Register Map 0 Table: User Space
Name
Addr
(0,Hex) Access
Name
Addr
(0,Hex)
Access
Name
Name
Access
00
RW
40
01
RW
41
81
C1
PRT0GS
02
RW
42
82
C2
PRT0DM2
03
RW
43
83
C3
PRT1DR
04
RW
44
PRT1IE
05
RW
45
85
C5
PRT1GS
06
RW
46
86
C6
PRT1DM2
07
RW
47
87
C7
PRT2DR
08
RW
48
88
C8
PRT2IE
09
RW
49
89
C9
PRT2GS
0A
RW
4A
8A
CA
PRT2DM2
0B
RW
4B
8B
CB
PRT3DR
0C
RW
4C
8C
CC
PRT3IE
0D
RW
4D
8D
CD
PRT3GS
0E
RW
4E
8E
CE
PRT3DM2
0F
RW
4F
8F
CF
10
50
90
CUR_PP
D0
RW
11
51
91
STK_PP
D1
RW
12
52
92
13
53
93
IDX_PP
D3
RW
14
54
94
MVR_PP
D4
RW
15
55
95
MVW_PP
D5
RW
16
56
96
I2C_CFG
D6
RW
17
57
97
I2C_SCR
D7
#
18
58
98
I2C_DR
D8
RW
19
59
99
I2C_MSCR
D9
#
1A
5A
9A
INT_CLR0
DA
RW
1B
5B
9B
INT_CLR1
DB
RW
1C
5C
Document #: 38-16018 Rev. *E
84
9C
RW
Addr
(0,Hex)
PRT0IE
ASE11CR0
80
Access
PRT0DR
Blank fields are Reserved and must not be accessed.
ASE10CR0
Addr
(0,Hex)
C0
RW
C4
D2
DC
# Access is bit specific.
Page 11 of 31
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CY7C603xx
Table 6. Register Map 0 Table: User Space (continued)
Name
Addr
(0,Hex) Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
1D
5D
9D
INT_CLR3
DD
RW
1E
5E
9E
INT_MSK3
DE
RW
1F
5F
9F
DF
DBB00DR0
20
#
AMX_IN
60
RW
A0
INT_MSK0
E0
RW
DBB00DR1
21
W
AMUXCFG
61
RW
A1
INT_MSK1
E1
RW
DBB00DR2
22
RW
PWM_CR
62
RW
A2
INT_VC
E2
RC
DBB00CR0
23
#
A3
RES_WDT
E3
W
DBB01DR0
24
#
DBB01DR1
25
W
DBB01DR2
26
RW
DBB01CR0
27
#
DCB02DR0
28
#
ADC0_CR
68
#
A8
E8
DCB02DR1
29
W
ADC1_CR
69
#
A9
E9
DCB02DR2
2A
RW
6A
AA
EA
DCB02CR0
2B
#
6B
AB
EB
DCB03DR0
2C
#
TMP_DR0
6C
RW
AC
EC
DCB03DR1
2D
W
TMP_DR1
6D
RW
AD
ED
DCB03DR2
2E
RW
TMP_DR2
6E
RW
AE
EE
DCB03CR0
2F
#
TMP_DR3
6F
RW
AF
63
CMP_CR0
64
#
65
CMP_CR1
66
RW
67
A4
E4
A5
E5
A6
DEC_CR0
E6
RW
A7
DEC_CR1
E7
RW
EF
30
70
RDI0RI
B0
RW
F0
31
71
RDI0SYN
B1
RW
F1
32
ACE00CR1
72
RW
RDI0IS
B2
RW
F2
33
ACE00CR2
73
RW
RDI0LT0
B3
RW
F3
34
74
RDI0LT1
B4
RW
F4
35
75
RDI0RO0
B5
RW
F5
RDI0RO1
B6
RW
36
ACE01CR1
76
RW
37
ACE01CR2
77
RW
B7
F6
CPU_F
F7
RL
38
78
B8
F8
39
79
B9
F9
3A
7A
BA
FA
3B
7B
BB
FB
3C
7C
BC
3D
7D
BD
DAC_D
FD
RW
3E
7E
BE
CPU_SCR1
FE
#
3F
7F
BF
CPU_SCR0
FF
#
Blank fields are Reserved and must not be accessed.
Document #: 38-16018 Rev. *E
FC
# Access is bit specific.
Page 12 of 31
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CY7C603xx
Table 7. Register Map 1 Table: Configuration Space
Name
Addr
(1,Hex) Access
Name
Addr
(1,Hex)
Access
Name
ASE10CR0
Addr
(1,Hex)
80
Access
Name
RW
Addr
(1,Hex)
PRT0DM0
00
RW
40
PRT0DM1
01
RW
41
81
C1
PRT0IC0
02
RW
42
82
C2
PRT0IC1
03
RW
43
PRT1DM0
04
RW
44
83
PRT1DM1
05
RW
45
85
C5
PRT1IC0
06
RW
46
86
C6
ASE11CR0
84
C3
RW
C4
PRT1IC1
07
RW
47
87
C7
PRT2DM0
08
RW
48
88
C8
PRT2DM1
09
RW
49
89
C9
PRT2IC0
0A
RW
4A
8A
CA
PRT2IC1
0B
RW
4B
8B
CB
PRT3DM0
0C
RW
4C
8C
CC
PRT3DM1
0D
RW
4D
8D
CD
PRT3IC0
0E
RW
4E
8E
CE
0F
RW
PRT3IC1
Access
C0
4F
8F
10
50
90
GDI_O_IN
D0
RW
11
51
91
GDI_E_IN
D1
RW
12
52
92
GDI_O_OU
D2
RW
13
53
93
GDI_E_OU
D3
RW
14
54
94
D4
15
55
95
D5
16
56
96
D6
17
57
97
18
58
98
MUX_CR0
D8
RW
19
59
99
MUX_CR1
D9
RW
1A
5A
9A
MUX_CR2
DA
RW
1B
5B
9B
MUX_CR3
DB
RW
1C
5C
9C
DC
1D
5D
9D
OSC_GO_EN DD
RW
1E
5E
9E
OSC_CR4
DE
RW
1F
5F
CF
D7
9F
OSC_CR3
DF
RW
DBB00FN
20
RW
CLK_CR0
60
RW
A0
OSC_CR0
E0
RW
DBB00IN
21
RW
CLK_CR1
61
RW
A1
OSC_CR1
E1
RW
DBB00OU
22
RW
ABF_CR0
62
RW
A2
OSC_CR2
E2
RW
AMD_CR0
63
RW
A3
VLT_CR
E3
RW
DBB01FN
24
RW
CMP_GO_EN 64
RW
A4
VLT_CMP
E4
R
DBB01IN
25
RW
65
A5
ADC0_TR
E5
RW
DBB01OU
26
RW
ADC1_TR
E6
RW
DCB02FN
28
RW
68
A8
IMO_TR
E8
W
DCB02IN
29
RW
69
A9
ILO_TR
E9
W
DCB02OU
2A
RW
6A
AA
BDG_TR
EA
RW
AB
ECO_TR
EB
W
23
27
2B
AMD_CR1
66
RW
A6
ALT_CR0
67
RW
A7
CLK_CR3
6B
Blank fields are Reserved and must not be accessed.
Document #: 38-16018 Rev. *E
RW
E7
# Access is bit specific.
Page 13 of 31
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CY7C603xx
Table 7. Register Map 1 Table: Configuration Space (continued)
Name
DCB03FN
Addr
(1,Hex) Access
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
2C
RW
TMP_DR0
6C
RW
AC
EC
DCB03IN
2D
RW
TMP_DR1
6D
RW
AD
ED
DCB03OU
2E
RW
TMP_DR2
6E
RW
AE
EE
TMP_DR3
6F
RW
AF
2F
30
70
31
71
EF
RDI0RI
B0
RW
F0
RDI0SYN
B1
RW
F1
32
ACE00CR1
72
RW
RDI0IS
B2
RW
F2
33
ACE00CR2
73
RW
RDI0LT0
B3
RW
F3
RDI0LT1
B4
RW
F4
RDI0RO0
B5
RW
F5
RDI0RO1
B6
RW
34
74
35
75
36
ACE01CR1
76
RW
37
ACE01CR2
77
RW
B7
Access
F6
CPU_F
F7
RL
38
78
B8
39
79
B9
3A
7A
BA
3B
7B
BB
FB
3C
7C
BC
FC
3D
7D
BD
DAC_CR
FD
3E
7E
BE
CPU_SCR1
FE
#
3F
7F
BF
CPU_SCR0
FF
#
Blank fields are Reserved and must not be accessed.
Document #: 38-16018 Rev. *E
F8
F9
FLS_PR1
FA
RW
RW
# Access is bit specific.
Page 14 of 31
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CY7C603xx
Electrical Specifications
This section presents the DC and AC electrical specifications of the enCoRe III LV device. For the most up to date electrical
specifications, check the latest data sheet by visiting the web at http://www.cypress.com.
Specifications are valid for 0°C ≤ TA ≤ 70°C and TJ ≤ 85°C as specified, except where noted.
Refer to Table 20 on page 22 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
Figure 10. Voltage versus CPU Frequency
Figure 11. IMO Frequency Trim Options
3.60 V
Valid
Operating
Region
3.00
V
Vdd Voltage
Vdd Voltage
3.60
V
2.70
V
2.40
V
SLIMO
Mode=1
3.00 V
SLIMO
Mode=0
SLIMO SLIMO
Mode=1 Mode=1
2.40 V
93 kHz
3 MHz
93 kHz
12 MHz
6 MHz
12 MHz
24 MHz
IMO Frequency
CPU Frequency
The allowable CPU operating region for 12 MHz has been extended down to 2.7V from the original 3.0V design target. The customer's
application is responsible for monitoring voltage and throttling back CPU speed in accordance with Figure 10 when voltage
approaches 2.7V. Refer to Table 18 for LVD specifications. Note that the device does not support a preset trip at 2.7V. To detect Vdd
drop at 2.7V, an external circuit or device such as the WirelessUSB LP - CYRF6936 must be employed; or if the design permits, the
nearest LVD trip value at 2.9V can be used.
Table 8 lists the units of measure that are used in this section.
Table 8. Units of Measure
Symbol
°C
dB
fF
Hz
KB
Kbit
kHz
kΩ
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
Unit of Measure
degree Celsius
decibels
femtofarad
hertz
1024 bytes
1024 bits
kilohertz
kilohm
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
microvolts root-mean-square
Document #: 38-16018 Rev. *E
Symbol
μW
mA
ms
mV
nA
ns
nV
W
pA
pF
pp
ppm
ps
sps
s
V
Unit of Measure
microwatts
milliampere
millisecond
millivolts
nanoampere
nanosecond
nanovolts
ohm
picoampere
picofarad
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
Page 15 of 31
[+] Feedback
CY7C603xx
Absolute Maximum Ratings
Table 9. Absolute Maximum Ratings
Parameter
Description
TSTG
Storage Temperature
TA
Ambient Temperature with Power Applied
Vdd
Supply Voltage on Vdd Relative to Vss
VIO
DC Input Voltage
VIOZ
DC Voltage Applied to Tri-state
IMIO
Maximum Current into any Port Pin
ESD
Electro Static Discharge Voltage
LU
Latch-up Current
Min
Typ
Max
Unit
–40
–
+90
°C
0
–
+70
°C
–0.5
–
5
V
Vss – 0.5
–
Vdd + 0.5
V
Vss – 0.5
–
Vdd + 0.5
V
–25
–
+25
mA
2000
–
–
V
–
–
200
mA
Notes
Higher storage temperatures
reduce data retention time.
Human Body Model ESD.
Operating Temperature
Table 10. Operating Temperature
Parameter
Min
Typ
Max
Unit
TA
Ambient Temperature
Description
0
–
+70
°C
TJ
Junction Temperature
0
–
+85
°C
Notes
The temperature rise from ambient
to junction is package specific. See
Table 33 on page 30. The user must
limit the power consumption to
comply with this requirement.
DC Electrical Characteristics
DC Chip-Level Specifications
Table 11 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0°C < TA <
70°C, or 2.4V to 3.0V and 0°C < TA < 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and are for design guidance
only.
Table 11. DC Chip-Level Specifications
Parameter
Description
Min
Typ
Max
Unit
2.40
–
3.6
V
Supply Current, IMO = 6 MHz using SLIMO
mode.
–
1.2
2
mA
Conditions are Vdd = 3.3V,
TA = 25°C, CPU = 3 MHz, clock
doubler disabled. VC1 = 375 kHz,
VC2 = 23.4 kHz, VC3 = 0.091 kHz.
IDD27
Supply Current, IMO = 6 MHz using SLIMO
mode.
–
1.1
1.5
mA
Conditions are Vdd = 2.55V,
TA = 25°C, CPU = 3 MHz, clock
doubler disabled. VC1 = 375 kHz,
VC2 = 23.4 kHz, VC3 = 0.091 kHz.
ISB27
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and internal slow oscillator
active. Mid temperature range.
–
2.6
4.
μA
Vdd = 2.55V, 0°C < TA < 40°C.
ISB
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and internal slow oscillator
active.
–
2.8
5
μA
Vdd = 3.3V, 0°C < TA < 70°C.
VREF
Reference Voltage (Bandgap)
1.28
1.30
1.32
V
Trimmed for appropriate Vdd.
Vdd = 3.0V to 3.6V.
VREF27
Reference Voltage (Bandgap)
1.16
1.30
1.33
V
Trimmed for appropriate Vdd.
Vdd = 2.4V to 3.0V.
AGND
Analog Ground
VREF –
0.003
VREF
VREF +
0.003
V
Vdd
Supply Voltage
IDD3
Document #: 38-16018 Rev. *E
Notes
See Table 18 on page 20.
Page 16 of 31
[+] Feedback
CY7C603xx
DC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and
0°C < TA < 70°C, or 2.4V to 3.0V and 0°C < TA < 70°C, respectively. Typical parameters apply to 3.3V, and 2.7V at 25°C and are for
design guidance only.
Table 12. 3.3V DC GPIO Specifications
Parameter
Description
Min
Typ
Max
Unit
Notes
RPU
Pull up Resistor
4
5.6
8
kΩ
RPD
Pull down Resistor
4
5.6
8
kΩ
VOH
High Output Level
Vdd –
1.0
–
–
V
IOH = 3 mA, VDD > 3.0V
VOL
Low Output Level
–
–
0.75
V
IOL = 10 mA, VDD > 3.0V
VIL
Input Low Level
–
–
0.8
V
Vdd = 3.0 to 3.6.
V
Vdd = 3.0 to 3.6.
–
mV
VIH
Input High Level
2.1
–
VH
Input Hysteresis
–
60
IIL
Input Leakage (Absolute Value)
–
1
–
nA
Gross tested to 1 μA.
CIN
Capacitive Load on Pins as Input
–
3.5
10
pF
Package and pin dependent.
Temp = 25°C.
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent.
Temp = 25°C.
Min
Typ
Max
Unit
4
5.6
8
kΩ
Table 13. 2.7V DC GPIO Specifications
Parameter
Description
Notes
RPU
Pull up Resistor
RPD
Pull down Resistor
4
5.6
8
kΩ
VOH
High Output Level
Vdd –
0.4
–
–
V
IOH = 2.5 mA (6.25 Typ), VDD = 2.4
to 3.0V (16 mA maximum, 50 mA
Typ combined IOH budget).
VOL
Low Output Level
–
–
0.75
V
IOL = 10 mA, VDD = 2.4 to 3.0V (90
mA maximum combined IOL
budget).
VIL
Input Low Level
–
–
0.75
V
Vdd = 2.4 to 3.0.
VIH
Input High Level
2.0
–
–
V
Vdd = 2.4 to 3.0.
VH
Input Hysteresis
–
90
–
mV
IIL
Input Leakage (Absolute Value)
–
1
–
nA
Gross tested to 1 μA.
CIN
Capacitive Load on Pins as Input
–
3.5
10
pF
Package and pin dependent.
Temp = 25°C.
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent.
Temp = 25°C.
Document #: 38-16018 Rev. *E
Page 17 of 31
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CY7C603xx
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and
0°C < TA < 70°C, or 2.4V to 3.0V and 0°C < TA < 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and are for
design guidance only.
Table 14. 3.3V DC Operational Amplifier Specifications
Parameter
Description
Min
Typ
Max
Unit
Notes
VOSOA
Input Offset Voltage (absolute value)
–
2.5
15
mV
TCVOSOA
Average Input Offset Voltage Drift
–
10
–
μV/°C
IEBOA[1]
Input Leakage Current (Port 0 Analog Pins)
–
200
–
pA
Gross tested to 1 μA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25°C.
VCMOA
Common Mode Voltage Range
0
–
Vdd – 1
V
GOLOA
Open Loop Gain
–
80
–
dB
ISOA
Amplifier Supply Current
–
10
30
μA
Min
Typ
Max
Unit
Table 15. 2.7V DC Operational Amplifier Specifications
Parameter
Description
Notes
VOSOA
Input Offset Voltage (absolute value)
–
2.5
15
mV
TCVOSOA
Average Input Offset Voltage Drift
–
10
–
μV/°C
IEBOA[1]
Input Leakage Current (Port 0 Analog Pins)
–
200
–
pA
Gross tested to 1 μA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25°C.
VCMOA
Common Mode Voltage Range
0
–
Vdd – 1
V
GOLOA
Open Loop Gain
–
80
–
dB
ISOA
Amplifier Supply Current
–
10
30
μA
Note
1. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25°C; 50 nA over temperature. Use Port 0 Pins 1–7 for the lowest leakage of 200 nA.
Document #: 38-16018 Rev. *E
Page 18 of 31
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CY7C603xx
DC Switch Mode Pump Specifications
Table 16 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0°C < TA
< 70°C, or 2.4V to 3.0V and 0°C < TA < 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and are for design
guidance only.
Table 16. DC Switch Mode Pump (SMP) Specifications
Parameter
Description
Min
Typ
Max
Unit
Notes
VPUMP3V
3.3V Output Voltage from Pump
3.00
3.25
3.60
V
Configuration of footnote.[2]
Average, neglecting ripple.
SMP trip voltage is set to 3.25V.
VPUMP2V
2.6V Output Voltage from Pump
2.45
2.55
2.80
V
Configuration of footnote.[2]
Average, neglecting ripple.
SMP trip voltage is set to 2.55V.
IPUMP
Available Output Current
VBAT = 1.5V, VPUMP = 3.25V
VBAT = 1.3V, VPUMP = 2.55V
8
8
–
–
–
–
mA
mA
VBAT3V
Input Voltage Range from Battery
1.0
–
3.3
V
Configuration of footnote.[2]
SMP trip voltage is set to 3.25V.
VBAT2V
Input Voltage Range from Battery
1.0
–
2.8
V
Configuration of footnote.[2]
SMP trip voltage is set to 2.55V.
1.2
–
–
V
Configuration of footnote.[2]
0°C < TA < 100. 1.25V at TA = –40°C.
–
5
–
%VO
Configuration of footnote.[2] VO is the
“Vdd Value for PUMP Trip” specified
by the VM[2:0] setting in the DC POR
and LVD Specification, Table 18 on
page 20.
–
5
–
%VO
Configuration of footnote.[2] VO is the
“Vdd Value for PUMP Trip” specified
by the VM[2:0] setting in the DC POR
and LVD Specification, Table 18 on
page 20.
ΔVPUMP_Ri Output Voltage Ripple (depends on
cap/load)
pple
–
100
–
mVpp Configuration of footnote.[2] Load is
5 mA.
E3
Efficiency
35
50
–
%
Configuration of footnote.[2] Load is
5 mA.
SMP trip voltage is set to 3.25V.
E2
Efficiency
35
80
–
%
For I load = 1 mA, VPUMP = 2.55V,
VBAT = 1.3V, 10 μH inductor, 1 μF
capacitor, and Schottky diode.
FPUMP
Switching Frequency
–
1.3
–
MHz
DCPUMP
Switching Duty Cycle
–
50
–
%
VBATSTART Minimum Input Voltage from Battery to Start
Pump
ΔVPUMP_Li Line Regulation (over Vi range)
ne
ΔVPUMP_Lo Load Regulation
ad
Configuration of footnote.[2]
SMP trip voltage is set to 3.25V.
SMP trip voltage is set to 2.55V.
Note
2. L1 = 2 μH inductor, C1 = 10 μF capacitor, D1 = Schottky diode. See Figure 12 on page 20.
Document #: 38-16018 Rev. *E
Page 19 of 31
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CY7C603xx
Figure 12. Basic Switch Mode Pump Circuit
D
1
Vdd
enCoRe III LV
L1
VBAT
+
VPUMP
SMP
C
1
Battery
Vss
DC Analog Mux Bus Specifications
Table 17 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0°C < TA
< 70°C, or 2.4V to 3.0V and 0°C < TA < 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and are for design
guidance only.
Table 17. DC Analog Mux Bus Specifications
Description
Min
Typ
Max
Unit
RSW
Parameter
Switch Resistance to Common Analog Bus
–
–
400
800
Ω
Ω
RVDD
Resistance of Initialization Switch to Vdd
–
–
800
Ω
Notes
Vdd > 2.7V
2.4V < Vdd < 2.7V
DC POR and LVD Specifications
Table 18 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0°C < TA
< 70°C, or 2.4V to 3.0V and 00°C < TA < 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and are for design
guidance only.
Table 18. DC POR and LVD Specifications
Parameter
Description
VPPOR0
VPPOR1
Vdd Value for PPOR Trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
VLVD0
VM[2:0] = 000b
Min
Typ
Max
Unit
Notes
Vdd must be greater than or equal to
2.5V during startup, reset from the
XRES pin, or reset from Watchdog.
–
2.36
2.82
2.40
2.95
V
V
2.40
2.45
2.51[3]
V
V
Vdd Value for LVD Trip
VLVD1
VM[2:0] = 001b
2.85
2.92
2.99[4]
VLVD2
VM[2:0] = 010b
2.95
3.02
3.09
V
VLVD37
VM[2:0] = 011b
3.06
3.13
3.20
V
Vdd Value for PUMP Trip
VPUMP0
VM[2:0] = 000b
2.45
2.55
2.62[5]
V
VPUMP1
VM[2:0] = 001b
2.96
3.02
3.09
V
VPUMP2
VM[2:0] = 010b
3.03
3.10
3.16
V
VPUMP3
VM[2:0] = 011b
3.18
3.25
3.32[6]
V
Notes
3. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply.
4. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply.
5. Always greater than 50 mV above VLVD0.
6. Always greater than 50 mV above VLVD3.
Document #: 38-16018 Rev. *E
Page 20 of 31
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CY7C603xx
DC Programming Specifications
Table 19 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0°C < TA
< 70°C, or 2.4V to 3.0V and 0°C < TA < 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and are for design
guidance only.
Table 19. DC Programming Specifications
Parameter
Description
VddIWRITE Supply Voltage for Flash Write Operations
Min
Typ
Max
Unit
Notes
2.70
–
–
V
IDDP
Supply Current During Programming or
Verify
–
5
25
mA
VILP
Input Low Voltage During Programming or
Verify
–
–
0.8
V
VIHP
Input High Voltage During Programming or
Verify
2.1
–
–
V
IILP
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
–
–
0.2
mA
Driving internal pull down resistor.
IIHP
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
–
–
1.5
mA
Driving internal pull down resistor.
VOLV
Output Low Voltage During Programming or
Verify
–
–
Vss +
0.75
V
VOHV
Output High Voltage During Programming or
Verify
Vdd –
1.0
–
Vdd
V
50,000
–
–
–
Erase/write cycles per block.
1,800,00
0
–
–
–
Erase/write cycles.
10
–
–
Years
FlashENPB Flash Endurance (per block)
(total)[7]
FlashENT
Flash Endurance
FlashDR
Flash Data Retention
Note
7. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block
ever sees more than 50,000 cycles).
Document #: 38-16018 Rev. *E
Page 21 of 31
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CY7C603xx
AC Electrical Characteristics
AC Chip-Level Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and
0°C < TA < 70°C, or 2.4V to 3.0V and 0°C < TA < 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and are for
design guidance only.
Table 20. 3.3V AC Chip-Level Specifications
Min
Typ
Max
Unit
Notes
FIMO24
Parameter
Internal Main Oscillator Frequency for
24 MHz
Description
23.4
24
24.6[8, 9]
MHz
Trimmed for 3.3V operation using
factory trim values. See Figure 11 on
page 15. SLIMO mode = 0.
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
6
6.35[8, 9]
MHz
Trimmed for 3.3V operation using
factory trim values. See Figure 11 on
page 15. SLIMO mode = 1.
FCPU2
CPU Frequency (3.3V Nominal)
0.93
12
12.3[8, 9]
MHz
MHz
FBLK33
Digital Block Frequency (3.3V Nominal)
0
24
24.6[8, 10]
F32K1
Internal Low Speed Oscillator Frequency
15
32
64
kHz
Jitter32k
32 kHz RMS Period Jitter
–
100
200
ns
Jitter32k
32 kHz Peak-to-Peak Period Jitter
–
1400
–
TXRST
External Reset Pulse Width
10
–
–
μs
DC24M
24 MHz Duty Cycle
40
50
60
%
Step24M
24 MHz Trim Step Size
Fout48M
48 MHz Output Frequency
–
50
–
kHz
46.8
48.0
49.2[9]
MHz
Jitter24M1 24 MHz Peak-to-Peak Period Jitter (IMO)
–
600
FMAX
Maximum frequency of signal on row input or
row output.
–
–
12.3
MHz
TRAMP
Supply Ramp Time
0
–
–
μs
Min
Typ
Max
Unit
Notes
12.7[8, 11]
MHz
Trimmed for 2.7V operation using
factory trim values. See Figure 11 on
page 15. SLIMO mode = 1.
Trimmed. Using factory trim values.
ps
Table 21. 2.7V AC Chip-Level Specifications
Parameter
Description
FIMO12
Internal Main Oscillator Frequency for 12
MHz
11.5
120
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
6
6.35[8, 11]
MHz
Trimmed for 2.7V operation using
factory trim values. See Figure 11 on
page 15. SLIMO mode = 1.
FCPU1
CPU Frequency (2.7V Nominal)
0.093
3
3.15[8, 11]
MHz
24 MHz only for SLIMO mode = 0.
FBLK27
Digital Block Frequency (2.7V Nominal)
0
12
12.5[8, 11]
MHz
Refer to the AC Digital Block
Specifications.
F32K1
Internal Low Speed Oscillator Frequency
8
32
96
kHz
Jitter32k
32 kHz RMS Period Jitter
–
150
200
ns
Jitter32k
32 kHz Peak-to-Peak Period Jitter
–
1400
–
TXRST
External Reset Pulse Width
10
–
–
μs
FMAX
Maximum frequency of signal on row input or
row output.
–
–
12.3
MHz
TRAMP
Supply Ramp Time
0
–
–
μs
Notes
8. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
9. 3.0V < Vdd < 3.6V.
10. See the individual user module data sheets for information on maximum frequencies for user modules.
11. 2.4V < Vdd < 3.0V.
Document #: 38-16018 Rev. *E
Page 22 of 31
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CY7C603xx
Figure 13. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F24M
Figure 14. 32 kHz Period Jitter (ILO) Timing Diagram
Jitter32k
F32K1
AC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and
0°C < TA < 70°C, or 2.4V to 3.0V and 0°C < TA < 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and are for
design guidance only.
Table 22. 3.3V AC GPIO Specifications
Parameter
Description
Min
Typ
Max
Unit
Notes
Normal Strong Mode
FGPIO
GPIO Operating Frequency
0
–
12
MHz
TRiseS
Rise Time, Slow Strong Mode, Cload = 50 pF
7
27
–
ns
Vdd = 3 to 3.6V, 10%–90%
TFallS
Fall Time, Slow Strong Mode, Cload = 50 pF
7
22
–
ns
Vdd = 3 to 3.6V, 10%–90%
Table 23. 2.7V AC GPIO Specifications
Min
Typ
Max
Unit
Notes
FGPIO
Parameter
GPIO Operating Frequency
Description
0
–
3
MHz
Normal Strong Mode
TRiseF
Rise Time, Normal Strong Mode, Cload = 50
pF
6
–
50
ns
Vdd = 2.4 to 3.0V, 10%–90%
TFallF
Fall Time, Normal Strong Mode, Cload = 50
pF
6
–
50
ns
Vdd = 2.4 to 3.0V, 10%–90%
TRiseS
Rise Time, Slow Strong Mode, Cload = 50 pF
18
40
120
ns
Vdd = 2.4 to 3.0V, 10%–90%
TFallS
Fall Time, Slow Strong Mode, Cload = 50 pF
18
40
120
ns
Vdd = 2.4 to 3.0V, 10%–90%
Figure 15. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
Document #: 38-16018 Rev. *E
TFallF
TFallS
Page 23 of 31
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CY7C603xx
AC Operational Amplifier Specifications
Table 24 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0°C < TA
< 70°C, or 2.4V to 3.0V and 0°C < TA < 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and are for design
guidance only.
Table 24. AC Operational Amplifier Specifications
Parameter
TCOMP
Description
Min
Typ
Comparator Mode Response Time, 50 mV
Overdrive
Max
Unit
100
200
ns
ns
Notes
Vdd > 3.0V.
2.4V < Vcc < 3.0V.
AC Analog Mux Bus Specifications
Table 25 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0°C < TA
< 70°C, or 2.4V to 3.0V and 0°C < TA < 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and are for design
guidance only.
Table 25. AC Analog Mux Bus Specifications
Parameter
FSW
Description
Switch Rate
Min
Typ
Max
Unit
–
–
3.17
MHz
Notes
AC Digital Block Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and
0°C < TA < 70°C, or 2.4V to 3.0V and 0°C < TA < 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and are for
design guidance only.
Table 26. 3.3V AC Digital Block Specifications
Function
Description
All
Functions
Maximum Block Clocking Frequency (<
3.6V)
Timer/
Counter/
PWM
Enable Pulse Width
Min
Typ
Max
Unit
24.6
MHz
50[12]
–
–
ns
–
–
24.6
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50
–
–
ns
Disable Mode
Maximum Frequency
Notes
3.0V < Vdd < 3.6V.
Dead Band Kill Pulse Width:
50
–
–
ns
Maximum Frequency
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
Maximum data rate at 4.1 MHz due
to 2 x over clocking.
SPIS
Maximum Input Clock Frequency
–
–
4.1
MHz
Width of SS_ Negated Between Transmissions
50
–
–
ns
Transmitter Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due
to 8 x over clocking.
Receiver
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due
to 8 x over clocking.
Maximum Input Clock Frequency
Note
12. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
Document #: 38-16018 Rev. *E
Page 24 of 31
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CY7C603xx
AC External Clock Specifications
Table 27. 2.7V AC Digital Block Specifications
Function
Description
All
Functions
Maximum Block Clocking Frequency
Timer/
Counter/
PWM
Enable Pulse Width
Min
Typ
Max
Unit
12.7
MHz
100
–
–
ns
–
–
12.7
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
100
–
–
ns
Disable Mode
100
–
–
ns
Maximum Frequency
Notes
2.4V < Vdd < 3.0V.
Dead Band Kill Pulse Width:
Maximum Frequency
–
–
12.7
MHz
SPIM
Maximum Input Clock Frequency
–
–
6.35
MHz
SPIS
Maximum Input Clock Frequency
–
–
4.1
MHz
100
–
–
ns
Transmitter Maximum Input Clock Frequency
–
–
12.7
MHz
Maximum data rate at 1.59 MHz due
to 8 x over clocking.
Receiver
–
–
12.7
MHz
Maximum data rate at 1.59 MHz due
to 8 x over clocking.
Width of SS_ Negated Between Transmissions
Maximum Input Clock Frequency
Maximum data rate at 3.17 MHz due
to 2 x over clocking.
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and
0°C < TA < 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 28. 3.3V AC External Clock Specifications
Min
Typ
Max
Unit
Notes
FOSCEXT
Parameter
Frequency with CPU Clock divide by 1
Description
0.093
–
12.3
MHz
Maximum CPU frequency is 12 MHz
at 3.3V. With the CPU clock divider
set to 1, the external clock must
adhere to the maximum frequency
and duty cycle requirements.
FOSCEXT
Frequency with CPU Clock divide by 2 or
greater
0.186
–
24.6
MHz
If the frequency of the external clock
is greater than 12 MHz, the CPU
clock divider must be set to 2 or
greater. In this case, the CPU clock
divider ensures that the fifty percent
duty cycle requirement is met.
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Document #: 38-16018 Rev. *E
Page 25 of 31
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CY7C603xx
Table 29. 2.7V AC External Clock Specifications
Parameter
Description
Min
Typ
Max
Unit
Notes
0
FOSCEXT
Frequency with CPU Clock divide by 1
0.093
–
3.08
MHz
Maximum CPU frequency is 3 MHz
at 2.7V. With the CPU clock divider
set to 1, the external clock must
adhere to the maximum frequency
and duty cycle requirements.
FOSCEXT
Frequency with CPU Clock divide by 2 or
greater
0.186
–
6.35
MHz
If the frequency of the external clock
is greater than 3 MHz, the CPU clock
divider must be set to 2 or greater. In
this case, the CPU clock divider
ensures that the fifty percent duty
cycle requirement is met.
–
High Period with CPU Clock divide by 1
160
–
5300
ns
–
Low Period with CPU Clock divide by 1
160
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
AC Programming Specifications
Table 30 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0°C < TA
< 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 30. AC Programming Specifications
Parameter
Description
Min
Typ
Max
Unit
1
–
20
ns
Fall Time of SCLK
1
–
20
ns
Data Set up Time to Falling Edge of SCLK
40
–
–
ns
THSCLK
Data Hold Time from Falling Edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
TERASEB
Flash Erase Time (Block)
–
15
–
ms
TWRITE
Flash Block Write Time
–
30
–
ms
TDSCLK3
Data Out Delay from Falling Edge of SCLK
–
–
50
ns
3.0 ≤ Vdd ≤ 3.6
TDSCLK2
Data Out Delay from Falling Edge of SCLK
–
–
70
ns
2.4 ≤ Vdd ≤ 3.0
TRSCLK
Rise Time of SCLK
TFSCLK
TSSCLK
Document #: 38-16018 Rev. *E
Notes
Page 26 of 31
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CY7C603xx
AC I2C Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and
0°C < TA < 70°C, or 2.4V to 3.0V and 0°C < TA < 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and are for
design guidance only.
Table 31. AC Characteristics of the I2C SDA and SCL Pins for Vdd > 3.0V
Parameter
Description
Standard Mode
Fast Mode
Unit
Min
Max
Min
Max
0
100
0
400
kHz
THDSTAI2C Hold Time (repeated) START Condition.
After this period, the first clock pulse is
generated.
4.0
–
0.6
–
μs
TLOWI2C
LOW Period of the SCL Clock
4.7
–
1.3
–
μs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
0.6
–
μs
TSUSTAI2C
Set up Time for a Repeated START
Condition
4.7
–
0.6
–
μs
0
–
0
–
μs
FSCLI2C
SCL Clock Frequency
THDDATI2C Data Hold Time
TSUDATI2C Data Set up Time
250
–
100[13]
–
ns
TSUSTOI2C Set up Time for STOP Condition
4.0
–
0.6
–
μs
TBUFI2C
Bus Free Time Between a STOP and START
Condition
4.7
–
1.3
–
μs
TSPI2C
Pulse Width of spikes are suppressed by the
input filter.
–
–
0
50
ns
Table 32. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported)
Parameter
Description
Standard Mode
Fast Mode
Unit
Min
Max
Min
Max
0
100
–
–
kHz
THDSTAI2C Hold Time (repeated) START Condition.
After this period, the first clock pulse is
generated.
4.0
–
–
–
μs
TLOWI2C
LOW Period of the SCL Clock
4.7
–
–
–
μs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
–
–
μs
TSUSTAI2C
Set up Time for a Repeated START
Condition
4.7
–
–
–
μs
0
–
–
–
μs
TSUDATI2C Data Set up Time
250
–
–
–
ns
TSUSTOI2C Set up Time for STOP Condition
4.0
–
–
–
μs
TBUFI2C
Bus Free Time Between a STOP and START
Condition
4.7
–
–
–
μs
TSPI2C
Pulse Width of spikes are suppressed by the
input filter.
–
–
–
–
ns
FSCLI2C
SCL Clock Frequency
THDDATI2C Data Hold Time
Note
13. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT > 250 ns must then be met. This is automatically
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document #: 38-16018 Rev. *E
Page 27 of 31
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CY7C603xx
Figure 16. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Packaging Information
This section illustrates the packaging specifications for the CY7C603xx device, along with the thermal impedances for each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/support.
Packaging Dimensions
Figure 17. 28-Pin (210-Mil) SSOP
51-85079-*C
Document #: 38-16018 Rev. *E
Page 28 of 31
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CY7C603xx
Figure 18. 32-Pin QFN (5 x 5 mm)
SIDE VIEW
TOP VIEW
BOTTOM VIEW
3.50
PIN1 ID
0.20 R.
Ø
N
N
1
2
1
2
0.45
SOLDERABLE
EXPOSED
3.50
3.50
PAD
-0.20
0°-12°
0.50
C
SEATING
PLANE
0.42±0.18
[4X]
3.50
NOTES:
1.
51-85188 *B
HATCH AREA IS SOLDERABLE EXPOSED PAD.
2. REFERENCE JEDEC#: MO-220
Figure 19. 32-Pin QFN (5 x 5 mm) (Sawn)
SIDE VIEW
TOP VIEW
4.90
5.10
BOTTOM VIEW
3.50
(0.93 MAX)
PIN #1 CORNER
0.23±0.05
0.20 REF
N
0.50
PIN #1 I.D.
R0.20
N
1
1
2
2
0.20 DIA TYP.
0.45
SOLDERABLE
EXPOSED
4.90
5.10
3.50
2X
3.50
PAD
-0.20
2X
NOTES:
1.
HATCH AREA IS SOLDERABLE EXPOSED PAD
SEATING PLANE
(0.05 MAX)
3.50
001-30999 **
2. BASED ON REF JEDEC # MO-248
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Document #: 38-16018 Rev. *E
Page 29 of 31
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CY7C603xx
Thermal Impedances
Solder Reflow Peak Temperature
Table 33. Thermal Impedances per Package
Following is the minimum solder reflow peak temperature to
achieve good solderability.
Package
Typical θJA *
Typical θJC
28 SSOP
96 °C/W
39 °C/W
32 QFN
22 °C/W
12 °C/W
Table 34. Solder Reflow Peak Temperature
* TJ = TA + Power x θJA
Package
Minimum Peak
Temperature*
Maximum Peak
Temperature
28 SSOP
240°C
260°C
32 QFN
240°C
260°C
*Higher temperatures may be required based on the solder
melting point. Typical temperatures for solder are 220±5°C
with Sn-Pb or 245±5°C with Sn-Ag-Cu paste. Refer to the
solder manufacturer specifications.
Ordering Information
The following table lists the CY7C603xx device’s key package features and ordering codes.
Table 35. CY7C603xx Device Key Features and Ordering Information
Flash Size
RAM Size
SMP
IO
Package Type
CY7C60323-PVXC
Ordering Part Number
8K
512
No
24
28-SSOP
CY7C60323-PVXCT
8K
512
No
24
28-SSOP Tape and Reel
CY7C60323-LFXC
8K
512
No
28
32-QFN
CY7C60323-LFXCT
8K
512
No
28
32-QFN Tape and Reel
CY7C60323-LTXC
8K
512
No
28
32-QFN Sawn
CY7C60323-LTXCT
8K
512
No
28
32-QFN Sawn Tape and Reel
CY7C60333-LFXC
8K
512
Yes
26
32-QFN
CY7C60333-LFXCT
8K
512
Yes
26
32-QFN Tape and Reel
CY7C60333-LTXC
8K
512
Yes
26
32-QFN Sawn
CY7C60333-LTXCT
8K
512
Yes
26
32-QFN Sawn Tape and Reel
Document #: 38-16018 Rev. *E
Page 30 of 31
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CY7C603xx
Document History Page
Description Title: CY7C603xx, enCoRe™ III Low Voltage
Document Number: 38-16018
REV.
ECN NO.
Issue Date
Orig. of
Change
**
339394
See ECN
BON
New Advance Data Sheet
*A
399556
See ECN
BHA
Changed from Advance Information to Preliminary.
Changed data sheet format.
Removed CY7C604xx.
*B
461240
See ECN
TYJ
Modified Figure 10 to include 2.7V Vdd at 12 MHz operation
*C
470485
See ECN
TYJ
Corrected part numbers in section 4 to match with part numbers in Ordering
Information. From CY7C60323-28PVXC, CY7C60323-56LFXC and
CY7C60333-56LFXC to CY7C60323-PVXC, CY7C60323-LFXC and
CY7C60333-LFXC respectively
Changed from Preliminary to final data sheet
*D
513713
See ECN
*E
2197567
See ECN
Description of Change
KKVTMP Change title from Wireless enCoRe II to enCoRe III Low Voltage
Applied new template formatting
UVS/AESA Added 32-Pin Sawn QFN Pin Diagram, package diagram, and ordering
information.
© Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-16018 Rev. *E
Revised February 29, 2008
Page 31 of 31
PlayStation is a registered trademark of Sony. Microsoft and Windows are registered trademarks of Microsoft Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated
Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
PSoC is a registered trademark and enCoRe and Programmable System-on-Chip are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document
may be the trademarks of their respective holders.
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