SHARC Processor ADSP-21477/ADSP-21478/ADSP-21479 SUMMARY The ADSP-2147x processors are available with unique audio-centric peripherals, such as the digital applications interface, serial ports, precision clock generators, S/PDIF transceiver, asynchronous sample rate converters, input data port, and more. Factory programmed ROM versions containing latest audio decoders from Dolby and DTS, available to IP licenses For complete ordering information, see Ordering Guide on Page 75. High performance 32-bit/40-bit floating-point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory—up to 5M bits of on-chip RAM, 4M bits of on-chip ROM Up to 300 MHz operating frequency Qualified for automotive applications. See Automotive Products on Page 74 Code compatible with all other members of the SHARC family Internal Memory SIMD Core Block 0 RAM/ROM Instruction Cache 5 Stage Sequencer DAG1/2 Core Timer PEx FLAGx/IRQx/ TMREXP DMD 64-BIT PEy JTAG PMD 64-BIT THERMAL DIODE S B0D 64-BIT Block 1 RAM/ROM B1D 64-BIT Block 2 RAM B2D 64-BIT Block 3 RAM B3D 64-BIT DMD 64-BIT Core Bus Cross Bar Internal Memory I/F PMD 64-BIT EPD BUS 64-BIT IOD0 32-BIT IOD1 32-BIT PERIPHERAL BUS 32-BIT IOD0 BUS FFT FIR IIR PERIPHERAL BUS DTCP/ MTM EP SPEP BUS CORE FLAGS/ PWM3-1 PCG C-D TIMER 1-0 TWI SPI/B UART SHIFT S/PDIF REG Tx/Rx PCG A-D ASRC PDAP/ SPORT IDP 7-0 3-0 7-0 DAI Routing/Pins DPI Routing/Pins DAI Peripherals DPI Peripherals RTC WDT MLB CORE PWM FLAGS 3-0 AMI SDRAM CTL External Port Pin MUX Peripherals External Port Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.3113 ©2012 Analog Devices, Inc. All rights reserved. ADSP-21477/ADSP-21478/ADSP-21479 TABLE OF CONTENTS Summary ............................................................... 1 ESD Sensitivity ................................................... 23 Product Application Restriction .................................. 2 Absolute Maximum Ratings ................................... 23 General Description ................................................. 3 Timing Specifications ........................................... 24 Family Core Architecture ........................................ 4 Output Drive Currents ......................................... 64 Family Peripheral Architecture ................................ 8 Test Conditions .................................................. 64 I/O Processor Features ......................................... 12 Capacitive Loading .............................................. 64 System Design .................................................... 13 Thermal Characteristics ........................................ 65 Development Tools ............................................. 13 88-LFCSP_VQ Lead Assignment ................................ 67 Additional Information ........................................ 14 100-LQFP_EP Lead Assignment ................................ 69 Related Signal Chains .......................................... 14 196-BGA Ball Assignment ........................................ 71 Pin Function Descriptions ....................................... 15 Outline Dimensions ................................................ 72 Specifications ........................................................ 20 Surface-Mount Design .......................................... 74 Operating Conditions .......................................... 20 Automotive Products .............................................. 74 Electrical Characteristics ....................................... 21 Ordering Guide ..................................................... 75 Maximum Power Dissipation ................................ 23 Package Information ........................................... 23 REVISION HISTORY 3/12—Rev. A to Rev. B S/PDIF Transmitter Input Data Timing ....................... 53 Revised Real Time Clock, SR_LDO and EMU Pin Descriptions in Pin Function Descriptions .................................... 15 SPI Interface—Master ............................................. 55 Corrected tPLLRST, tCLKRST timing in Table 19, Power-Up Sequencing Timing Requirements (Processor Startup) .... 26 JTAG Test Access Port and Emulation ......................... 63 Revised note in Figure 8, 266 MHz Operation (Fundamental Mode Crystal) ....................................................... 28 88-LFCSP_VQ Lead Assignment ................................ 67 Added additional models to: Automotive Products .............................................. 74 Ordering Guide ..................................................... 75 Added the 88-lead LFCSP_VQ package and the ADSP-21477 model. General information, specifications, and ordering information for this package and model can be found in the following sections: ADSP-2147x Family Features ...................................... 3 ADSP-21477 Internal Memory Space, 2M bits ................ 6 Operating Conditions ............................................. 20 Core Timer .......................................................... 30 Timer PWM_OUT Cycle Timing .............................. 30 SPI Interface—Slave ................................................ 56 Thermal Characteristics for 88-Lead LFCSP_VQ ........... 65 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] (CP-88-5) Dimensions Shown in Millimeters ................ 72 Automotive Products .............................................. 74 Ordering Guide ..................................................... 75 PRODUCT APPLICATION RESTRICTION Not for use in in-vivo applications for body fluid constituent monitoring, including monitoring one or more of the components that form, or may be a part of, or contaminate human blood or other body fluids, such as, but not limited to, carboxyhemoglobin, methemoglobin total hemoglobin, oxygen saturation, oxygen content, fractional arterial oxygen saturation, bilirubin, glucose, drugs, lipids, water, protein, and pH. Precision Clock Generator (Direct Pin Routing) ............ 33 Serial Ports ........................................................... 40 Input Data Port (IDP) ............................................. 46 Parallel Data Acquisition Port (PDAP) ........................ 47 Sample Rate Converter—Serial Output Port ................. 49 Pulse-Width Modulation Generators (PWM) ............... 50 Rev. B | Page 2 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 GENERAL DESCRIPTION No Yes No Yes Shift Register IDP/PDAP Yes UART 1 DAI (SRU)/DPI (SRU2) Speed (at 300 MHz) 30.59 μs Speed (at 200 MHz) 45.885 μs 1.66 ns 6.65 ns 2.49 ns 9.975 ns 14.99 ns 26.66 ns 11.61 ns 18.08 ns 22.485 ns 39.99 ns 17.41 ns 27.12 ns 20/14 Pins S/PDIF Transceiver 1 SPI 2 TWI 1 SRC SNR Performance Thermal Diode Package1 ADSP-21479 ADSP-21478 ADSP-21477 200 MHz Yes Yes 100-Lead LQFP 88-Lead LFCSP_VQ 196-Ball CSP_BGA 100-Lead LQFP 88-lead LFCSP_VQ 1 Table 2. ADSP-2147x Family Features Feature –128 dB 4 VISA Support Assumes two files in multichannel SIMD mode. Frequency Yes 2 Table 1. Processor Benchmarks 1 No 2, 3 Real-Time Clock Table 1 shows performance benchmarks for the ADSP-2147x processors. Table 2 shows the features of the individual product offerings. Benchmark Algorithm 1024 Point Complex FFT (Radix 4, with Reversal) FIR Filter (per Tap)1 IIR Filter (per Biquad)1 Matrix Multiply (Pipelined) [3 × 3] × [3 × 1] [4 × 4] × [4 × 1] Divide (y/×) Inverse Square Root Watch Dog Timer2 Up to 300 MHz The diagram on Page 1 shows the two clock domains (core and I/O processor) that make up the ADSP-2147x processors. The core clock domain contains the following features. • Two processing elements (PEx, PEy), each of which comprises an ALU, multiplier, shifter, and data register file 2M bits ROM N/A 4M bits • Two data address generators (DAG1, DAG2) 4 units (3 in 100-lead package) • A program sequencer with instruction cache 3 No Yes, 16-Bit External Port Interface (SDRAM, AMI)1 Serial Ports Direct DMA from SPORTs to External Memory 5M bits • PM and DM buses capable of supporting 2 × 64-bit data transfers between memory and the core at every core processor cycle • One periodic interval timer with pinout 8 • On-chip SRAM (up to 5M bit) No FIR, IIR, FFT Accelerator MediaLB Interface 3M bits The 100-lead and 88-lead packages of the processors do not contain an external port. The SDRAM controller pins must be disabled when using this package. For more information, see Pin Function Descriptions on Page 16. 2 Available on the 196-ball CSP_BGA package only. 3 Real Time Clock (RTC) is supported only for products with a temperature range of 0°C to +70°C and not supported for all other temperature grades. 4 Available on the 88-lead and 100-lead packages only. RAM Pulse-Width Modulation ADSP-21479 Feature ADSP-21478 Table 2. ADSP-2147x Family Features (Continued) ADSP-21477 The ADSP-2147x SHARC® processors are members of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. The processors are source code compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-2146x, and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (singleinstruction, single-data) mode. These processors are 32-bit/ 40-bit floating-point processors optimized for high performance audio applications with a large on-chip SRAM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital applications interface (DAI). Yes • A JTAG test access port for emulation and boundary scan. The JTAG provides software debug through user breakpoints, which allows flexible exception handling. Yes No Automotive models only Rev. B | Page 3 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 The block diagram of the ADSP-2147x on Page 1 also shows the peripheral clock domain (also known as the I/O processor), which contains the following features: elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each memory or register file access. • IOD0 (peripheral DMA) and IOD1 (external port DMA) buses for 32-bit data transfers SIMD mode is supported from external SDRAM but is not supported in the AMI. • Peripheral and external port buses for core connection Independent, Parallel Computation Units • External port with an asynchronous memory interface (AMI) and SDRAM controller Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit singleprecision floating-point, 40-bit extended precision floatingpoint, and 32-bit fixed-point data formats. • 4 units for pulse width modulation (PWM) control • 1 memory-to-memory (MTM) unit for internal-to-internal memory transfers • Digital applications interface that includes four precision clock generators (PCG), an input data port (IDP/PDAP) for serial and parallel interconnect, an S/PDIF receiver/transmitter, four asynchronous sample rate converters, eight serial ports, a shift register, and a flexible signal routing unit (DAI SRU). • Digital peripheral interface that includes two timers, a 2wire interface, one UART, two serial peripheral interfaces (SPI), two precision clock generators (PCG), three pulse width modulation (PWM) units, and a flexible signal routing unit (DPI SRU). As shown in the SHARC core block diagram on Page 5, the processors use two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms. With its SIMD computational hardware, the processors can perform 1.8 GFLOPS running at 300 MHz. FAMILY CORE ARCHITECTURE The processors are code compatible at the assembly level with the ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-2147x share architectural features with the ADSP-2126x, ADSP-2136x, ADSP2137x, ADSP-2146x, and ADSP-2116x SIMD SHARC processors, as shown in Figure 2 and detailed in the following sections. SIMD Computational Engine Timer The processor contains a core timer that can generate periodic software interrupts. The core timer can be configured to use FLAG3 as a timer expired signal. Data Register File Each processing element contains a general-purpose data register file. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the processor’s enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15. Context Switch Many of the processor’s registers have secondary registers that can be activated during interrupt servicing for a fast context switch. The data registers in the register file, the DAG registers, and the multiplier result registers all have secondary registers. The primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register. The processors contain two computational processing elements that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. SIMD mode allows the processor to execute the same instruction in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms. Universal Registers SIMD mode also affects the way data is transferred between memory and the processing elements because twice the data bandwidth is required to sustain computational operation in the processing elements. Therefore, entering SIMD mode also doubles the bandwidth between memory and the processing Single-Cycle Fetch of Instruction and Four Operands Rev. B | Universal registers can be used for general-purpose tasks. The USTAT (4) registers allow easy bit manipulations (Set, Clear, Toggle, Test, XOR) for all peripheral control and status registers. The data bus exchange register (PX) permits data to be passed between the 64-bit PM data bus and the 64-bit DM data bus, or between the 40-bit register file and the PM/DM data bus. These registers contain hardware to handle the data width difference. The processors feature an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 2). With its separate program and data memory Page 4 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. S JTAG FLAG TIMER INTERRUPT CACHE SIMD Core PM ADDRESS 24 DMD/PMD 64 5 STAGE PROGRAM SEQUENCER PM DATA 48 DAG1 16×32 DAG2 16×32 PM ADDRESS 32 SYSTEM I/F DM ADDRESS 32 USTAT 4×32-BIT PM DATA 64 PX 64-BIT DM DATA 64 MULTIPLIER MRF 80-BIT MRB 80-BIT SHIFTER ALU RF Rx/Fx PEx 16×40-BIT DATA SWAP RF Sx/SFx PEy 16×40-BIT ASTATx ASTATy STYKx STYKy ALU SHIFTER MULTIPLIER MSB 80-BIT MSF 80-BIT Figure 2. SHARC Core Block Diagram Instruction Cache The processor includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full speed execution of core looped operations such as digital filter multiply-accumulates, and FFT butterfly processing. Data Address Generators with Zero-Overhead Hardware Circular Buffer Support The processor’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the processors contain sufficient registers to allow the creation of up to 32 circular buffers (16 Rev. B | primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location. Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the processors can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction. Variable Instruction Set Architecture (VISA) In addition to supporting the standard 48-bit instructions from previous SHARC processors, the processors support new instructions of 16 and 32 bits. This feature, called Variable Instruction Set Architecture (VISA), drops redundant/unused Page 5 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 bits within the 48-bit instruction to create more efficient and compact code. The program sequencer supports fetching these 16-bit and 32-bit instructions from both internal and external SDRAM memory. This support is not extended to the asynchronous memory interface (AMI). Source modules need to be built using the VISA option, in order to allow code generation tools to create these more efficient opcodes. On-Chip Memory The processors contain varying amounts of internal RAM and internal ROM which is shown in Table 3 through Table 5. Each block can be configured for different combinations of code and data storage. Each memory block supports single-cycle, independent accesses by the core processor and I/O processor. The processor’s SRAM can be configured as a maximum of 160k words of 32-bit data, 320k words of 16-bit data, 106.7k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 5M bits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one bus dedicated to a memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. The memory maps in Table 3 through Table 5 display the internal memory address space of the processors. The 48-bit space section describes what this address range looks like to an instruction that retrieves 48-bit memory. The 32-bit section describes what this address range looks like to an instruction that retrieves 32-bit memory. Table 3. ADSP-21477 Internal Memory Space, 2M bits IOP Registers 0x0000 0000–0x0003 FFFF Extended Precision Normal or Long Word (64 Bits) Instruction Word (48 Bits) Block 0 ROM (Reserved) Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF 0x0008 0000–0x0008 AAA9 Reserved Reserved 0x0004 8000–0x0004 8FFF 0x0008 AAAA–0x0008 BFFF Block 0 SRAM Block 0 SRAM 0x0004 9000–0x0004 BFFF 0x0008 C000–0x0008 FFFF Reserved Reserved 0x0004 C000–0x0004 FFFF 0x0009 000–0x0009 5554 Block 1 ROM (Reserved) Block 1 ROM (Reserved) 0x0005 0000–0x0005 7FFF 0x000A 0000–0x000A AAA9 Reserved Reserved 0x0005 8000–0x0005 8FFF 0x000A AAAA–0x000A BFFF Block 1 SRAM Block 1 SRAM 0x0005 9000–0x0005 BFFF 0x000A C000–0x000A FFFF Reserved Reserved 0x0005 C000–0x0005 FFFF 0x000B 0000–0x000B 5554 Block 2 SRAM Block 2 SRAM 0x0006 0000–0x0006 0FFF 0x000C 0000–0x000C 1554 Reserved Reserved 0x0006 1000– 0x0006 FFFF 0x000C 1555–0x000D 5554 Block 3 SRAM Block 3 SRAM 0x0007 0000–0x0007 0FFF 0x000E 0000–0x000E 1554 Reserved Reserved 0x0007 1000–0x0007 FFFF 0x000E 1555–0x000F 5554 Rev. B | Normal Word (32 Bits) Block 0 ROM (Reserved) 0x0008 0000–0x0008 FFFF Reserved 0x0009 0000–0x0009 1FFF Block 0 SRAM 0x0009 2000–0x0009 7FFF Reserved 0x0009 8000–0x0009 FFFF Block 1 ROM (Reserved) 0x000A 0000–0x000AFFFF Reserved 0x000B 0000–0x000B 1FFF Block 1 SRAM 0x000B 2000–0x000B 7FFF Reserved 0x000B 8000–0x000B FFFF Block 2 SRAM 0x000C 0000–0x000C 1FFF Reserved 0x000C 2000–0x000D FFFF Block 3 SRAM 0x000E 0000–0x000E 1FFF Reserved 0x000E 2000–0x000F FFFF Page 6 of 76 | March 2012 Short Word (16 Bits) Block 0 ROM (Reserved) 0x0010 0000–0x0011 FFFF Reserved 0x0012 0000–0x0012 FFFF Block 0 SRAM 0x0012 4000–0x0012 FFFF Reserved 0x0013 0000–0x0013 FFFF Block 1 ROM (Reserved) 0x0014 0000–0x0015 FFFF Reserved 0x0016 0000–0x0016 3FFF Block 1 SRAM 0x0016 4000–0x0016 FFFF Reserved 0x0017 0000–0x0017 FFFF Block 2 SRAM 0x0018 0000–0x0018 3FFF Reserved 0x0018 4000–0x001B FFFF Block 3 SRAM 0x001C 0000–0x001C 3FFF Reserved 0x001C 4000–0x001F FFFF ADSP-21477/ADSP-21478/ADSP-21479 Table 4. ADSP-21478 Internal Memory Space (3M bits)1 Long Word (64 Bits) Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF Reserved 0x0004 8000–0x0004 8FFF Block 0 SRAM 0x0004 9000–0x0004 CFFF Reserved 0x0004 D000–0x0004 FFFF Block 1 ROM (Reserved) 0x0005 0000–0x0005 7FFF Reserved 0x0005 8000–0x0005 8FFF Block 1 SRAM 0x0005 9000–0x0005 CFFF Reserved 0x0005 D000–0x0005 FFFF Block 2 SRAM 0x0006 0000–0x0006 1FFF Reserved 0x0006 2000– 0x0006 FFFF Block 3 SRAM 0x0007 0000–0x0007 1FFF Reserved 0x0007 2000–0x0007 FFFF 1 IOP Registers 0x0000 0000–0x0003 FFFF Extended Precision Normal or Instruction Word (48 Bits) Normal Word (32 Bits) Block 0 ROM (Reserved) Block 0 ROM (Reserved) 0x0008 0000–0x0008 AAA9 0x0008 0000–0x0008 FFFF Reserved Reserved 0x0008 AAAA–0x0008 BFFF 0x0009 0000–0x0009 1FFF Block 0 SRAM Block 0 SRAM 0x0008 C000–0x0009 1554 0x0009 2000–0x0009 9FFF Reserved Reserved 0x0009 1555–0x0009 FFFF 0x0009 A000–0x0009 FFFF Block 1 ROM (Reserved) Block 1 ROM (Reserved) 0x000A 0000–0x000A AAA9 0x000A 0000–0x000A FFFF Reserved Reserved 0x000A AAAA–0x000A BFFF 0x000B 0000–0x000B 1FFF Block 1 SRAM Block 1 SRAM 0x000A C000–0x000B 1554 0x000B 2000–0x000B 9FFF Reserved Reserved 0x000B 1555–0x000B FFFF 0x000B A000–0x000B FFFF Block 2 SRAM Block 2 SRAM 0x000C 0000–0x000C 2AA9 0x000C 0000–0x000C 3FFF Reserved Reserved 0x000C 2AAA–0x000D FFFF 0x000C 4000–0x000D FFFF Block 3 SRAM Block 3 SRAM 0x000E 0000–0x000E 2AA9 0x000E 0000–0x000E 3FFF Reserved Reserved 0x000E 2AAA–0x000F FFFF 0x000E 4000–0x000F FFFF Short Word (16 Bits) Block 0 ROM (Reserved) 0x0010 0000–0x0011 FFFF Reserved 0x0012 0000–0x0012 3FFF Block 0 SRAM 0x0012 4000–0x0013 3FFF Reserved 0x0013 4000–0x0013 FFFF Block 1 ROM (Reserved) 0x0014 0000–0x0015 FFFF Reserved 0x0016 0000–0x0016 3FFF Block 1 SRAM 0x0016 4000–0x0017 3FFF Reserved 0x0017 4000–0x0017 FFFF Block 2 SRAM 0x0018 0000–0x0018 7FFF Reserved 0x0018 8000–0x001B FFFF Block 3 SRAM 0x001C 0000–0x001C 7FFF Reserved 0x001C 8000–0x001F FFFF Some processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog Devices sales representative for additional details. Rev. B | Page 7 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 Table 5. ADSP-21479 Internal Memory Space (5M bits)1 IOP Registers 0x0000 0000–0x0003 FFFF 1 Long Word (64 Bits) Extended Precision Normal or Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits) Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF Block 0 ROM (Reserved) 0x0008 0000–0x0008 AAA9 Block 0 ROM (Reserved) 0x0008 0000–0x0008 FFFF Block 0 ROM (Reserved) 0x0010 0000–0x0011 FFFF Reserved 0x0004 8000–0x0004 8FFF Reserved 0x0008 AAAA–0x0008 BFFF Reserved 0x0009 0000–0x0009 1FFF Reserved 0x0012 0000–0x0012 3FFF Block 0 SRAM 0x0004 9000–0x0004 EFFF Block 0 SRAM 0x0008 C000–0x0009 3FFF Block 0 SRAM 0x0009 2000–0x0009 DFFF Block 0 SRAM 0x0012 4000–0x0013 BFFF Reserved 0x0004 F000–0x0004 FFFF Reserved 0x0009 4000–0x0009 FFFF Reserved 0x0009 E000–0x0009 FFFF Reserved 0x0013 C000–0x0013 FFFF Block 1 ROM (Reserved) 0x0005 0000–0x0005 7FFF Block 1 ROM (Reserved) 0x000A 0000–0x000A AAA9 Block 1 ROM (Reserved) 0x000A 0000–0x000AFFFF Block 1 ROM (Reserved) 0x0014 0000–0x0015 FFFF Reserved 0x0005 8000–0x0005 8FFF Reserved 0x000A AAAA–0x000A BFFF Reserved 0x000B 0000–0x000B 1FFF Reserved 0x0016 0000–0x0016 3FFF Block 1 SRAM 0x0005 9000–0x0005 EFFF Block 1 SRAM 0x000A C000–0x000B 3FFF Block 1 SRAM 0x000B 2000–0x000B DFFF Block 1 SRAM 0x0016 4000–0x0017 BFFF Reserved 0x0005 F000–0x0005 FFFF Reserved 0x000B 4000–0x000B FFFF Reserved 0x000B E000–0x000B FFFF Reserved 0x0017 C000–0x0017 FFFF Block 2 SRAM 0x0006 0000–0x0006 3FFF Block 2 SRAM 0x000C 0000–0x000C 5554 Block 2 SRAM 0x000C 0000–0x000C 7FFF Block 2 SRAM 0x0018 0000–0x0018 FFFF Reserved 0x0006 4000– 0x0006 FFFF Reserved 0x000C 5555–0x0000D FFFF Reserved 0x000C 8000–0x000D FFFF Reserved 0x0019 0000–0x001B FFFF Block 3 SRAM 0x0007 0000–0x0007 3FFF Block 3 SRAM 0x000E 0000–0x000E 5554 Block 3 SRAM 0x000E 0000–0x000E 7FFF Block 3 SRAM 0x001C 0000–0x001C FFFF Reserved 0x0007 4000–0x0007 FFFF Reserved 0x000E 5555–0x0000F FFFF Reserved 0x000E 8000–0x000F FFFF Reserved 0x001D 0000–0x001F FFFF Some processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog Devices sales representative for additional details. On-Chip Memory Bandwidth Digital Transmission Content Protection The internal memory architecture allows programs to have four accesses at the same time to any of the four blocks (assuming there are no block conflicts). The total bandwidth is realized using the DMD and PMD buses (2 × 64-bit at CCLK speed) and the IOD0/1 buses (2 × 32-bit at PCLK speed). The DTCP specification defines a cryptographic protocol for protecting audio entertainment content from illegal copying, intercepting, and tampering as it traverses high performance digital buses, such as the IEEE 1394 standard. Only legitimate entertainment content delivered to a source device via another approved copy protection system (such as the DVD content scrambling system) is protected by this copy protection system. For more information on this feature, contact your local ADI sales office. ROM Based Security The processors have a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code. When using this feature, the processors do not boot-load any external code, executing exclusively from internal ROM. Additionally, the processor is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG or Test Access Port, is assigned to each customer. The device ignores an incorrect key. Emulation features are available after the correct key is scanned. Rev. B | FAMILY PERIPHERAL ARCHITECTURE The ADSP-2147x family contains a rich set of peripherals that support a wide variety of applications including high quality audio, medical imaging, communications, military, test equipment, 3D graphics, speech recognition, motor control, imaging, and other applications. Page 8 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 External Memory The external memory interface supports access to the external memory through core and DMA accesses. The external memory address space is divided into four banks. Any bank can be programmed as either asynchronous or synchronous memory. The external ports are comprised of the following modules. Note that code execution is only supported from Bank 0 regardless of VISA/ISA. Table 7 shows the address ranges for instruction fetch in each mode. Table 7. External Bank 0 Instruction Fetch • An AMI which communicates with SRAM, FLASH, and other devices that meet the standard asynchronous SRAM access protocol. The AMI supports 6M words of external memory in Bank 0 and 8M words of external memory in Bank 1, Bank 2, and Bank 3. • An SDRAM controller that supports a glueless interface with any of the standard SDRAMs. The SDC supports 62M words of external memory in Bank 0, and 64M words of external memory in Bank 1, Bank 2, and Bank 3. • Arbitration logic to coordinate core and DMA transfers between internal and external memory over the external port. External Port The external port provides a high performance, glueless interface to a wide variety of industry-standard memory devices. The external port, available on the 196-ball CSP_BGA, may be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory controllers. The first is an SDRAM controller for connection of industry-standard synchronous DRAM devices while the second is an asynchronous memory controller intended to interface to a variety of memory devices. Four memory select pins enable up to four separate devices to coexist, supporting any desired combination of synchronous and asynchronous device types. Non-SDRAM external memory address space is shown in Table 6. Size in Words 6M 8M 8M 8M Address Range 0x0020 0000–0x007F FFFF 0x0400 0000–0x047F FFFF 0x0800 0000–0x087F FFFF 0x0C00 0000–0x0C7F FFFF Address Range ISA (NW) 4M 0x0020 0000–0x005F FFFF VISA (SW) 10M 0x0060 0000–0x00FF FFFF SDRAM Controller The SDRAM controller, available on the ADSP-2147x in the 196-ball CSP_BGA package, provides an interface of up to four separate banks of industry-standard SDRAM devices or DIMMs, at speeds up to fSDCLK. Fully compliant with the SDRAM standard, each bank has its own memory select line (MS0–MS3), and can be configured to contain between 4 Mbytes and 256 Mbytes of memory. SDRAM external memory address space is shown in Table 8. Table 8. External Memory for SDRAM Addresses Bank Size in Words Address Range Bank 0 62M 0x0020 0000–0x03FF FFFF Bank 1 64M 0x0400 0000–0x07FF FFFF Bank 2 64M 0x0800 0000–0x0BFF FFFF Bank 3 64M 0x0C00 0000–0x0FFF FFFF The SDRAM controller address, data, clock, and control pins can drive loads up to distributed 30 pF. For larger memory systems, the SDRAM controller external buffer timing should be selected and external buffering should be provided so that the load on the SDRAM controller pins does not exceed 30 pF. SIMD Access to External Memory The SDRAM controller supports SIMD access on the 64-bit external port data bus (EPD) which allows access to the complementary registers on the PEy unit in the normal word space (NW). This improves performance since there is no need to explicitly load the complementary registers (as in SISD mode). VISA and ISA Access to External Memory The SDRAM controller supports VISA code operation which reduces the memory load since the VISA instructions are compressed. Moreover, bus fetching is reduced because, in the best case, one 48-bit fetch contains three valid instructions. Code execution from the traditional ISA operation is also supported. Rev. B | Size in Words A set of programmable timing parameters is available to configure the SDRAM banks to support slower memory devices. The SDRAM and the AMI interface do not support 32-bit wide devices. Table 6. External Memory for Non-SDRAM Addresses Bank Bank 0 Bank 1 Bank 2 Bank 3 Access Type Note that the external memory bank addresses shown are for normal-word (32-bit) accesses. If 48-bit instructions as well as 32-bit data are both placed in the same external memory bank, care must be taken while mapping them to avoid overlap. Asynchronous Memory Controller The asynchronous memory controller, available on the ADSP-2147x in the 196-ball CSP_BGA package, provides a configurable interface for up to four separate banks of memory or I/O devices. Each bank can be independently programmed with different timing parameters, enabling connection to a wide variety of memory devices including SRAM, flash, and EPROM, as well as I/O devices that interface with standard memory control lines. Bank 0 occupies a 6M word window and Banks 1, 2, and 3 Page 9 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 occupy a 8M word window in the processor’s address space but, if not fully populated, these windows are not made contiguous by the memory controller logic. Serial ports operate in five modes: • Standard serial mode • Multichannel (TDM) mode External Port Throughput • I2S mode The throughput for the external port, based on 133 MHz clock and 16-bit data bus, is 88 Mbytes/sec for the AMI and 266 Mbytes/sec for SDRAM. • Packed I2S mode • Left-justified mode MediaLB S/PDIF-Compatible Digital Audio Receiver/Transmitter The automotive models of the processors have an MLB interface which allows the processor to function as a media local bus device. It includes support for both 3-pin and 5-pin MLB protocols. It supports speeds up to 1024 FS (49.25M bits/sec, FS = 48.1 kHz) and up to 31 logical channels, with up to 124 bytes of data per media local bus frame. For a list of automotive products, see Automotive Products on Page 74. The S/PDIF receiver/transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a bi phase encoded signal. The serial data input to the receiver/transmitter can be formatted as left justified, I2S or right-justified with word widths of 16, 18, 20, or 24 bits. Digital Applications Interface (DAI) The digital applications interface (DAI) provides the ability to connect various peripherals to any of the DAI pins (DAI_P20–1). Programs make these connections using the signal routing unit (SRU), shown in Figure 1. The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with non configurable signal paths. The associated peripherals include eight serial ports, four precision clock generators (PCG), a S/PDIF transceiver, four ASRCs, and an input data port (IDP). The IDP provides an additional input path to the SHARC core, configurable as either eight channels of serial data, or a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the processor’s serial ports. Serial Ports (SPORTs) The processors feature eight synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel. Serial ports can support up to 16 transmit or 16 receive DMA channels of audio data when all eight SPORTs are enabled, or four full duplex TDM streams of 128 channels per frame. Serial port data can be automatically transferred to and from on-chip memory/external memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Rev. B | The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources, such as the SPORTs, external pins, the precision clock generators (PCGs), and are controlled by the SRU control registers. Asynchronous Sample Rate Converter (SRC) The sample rate converter contains four blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter. The SRC block provides up to 128 dB SNR and is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches. Finally, the SRC can be used to clean up audio data from jittery clock sources such as the S/PDIF receiver. Input Data Port The IDP provides up to eight serial input channels—each with its own clock, frame sync, and data inputs. The eight channels are automatically multiplexed into a single 32-bit by eight-deep FIFO. Data is always formatted as a 64-bit frame and divided into two 32-bit words. The serial protocol is designed to receive audio channels in I2S, left-justified sample pair, or right-justified mode. The IDP also provides a parallel data acquisition port (PDAP) which can be used for receiving parallel data. The PDAP port has a clock input and a hold input. The data for the PDAP can be received from DAI pins or from the external port pins. The PDAP supports a maximum of 20-bit data and four different packing modes to receive the incoming data. Precision Clock Generators The precision clock generators (PCG) consist of four units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. The units, A B, C, and D are identical in functionality and operate independently of each other. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair. The outputs of PCG A and B can be routed through the DAI pins and the outputs of PCG C and D can be driven on to the DAI as well as the DPI pins. Page 10 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 Digital Peripheral Interface (DPI) Pulse-Width Modulation The digital peripheral interface provides connections to two serial peripheral interface ports (SPI), one universal asynchronous receiver-transmitter (UART), 12 flags, a 2-wire interface (TWI), three PWM modules (PWM3–1), and two generalpurpose timers. The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM waveforms). Serial Peripheral (Compatible) Interface (SPI) The SPI is an industry-standard synchronous serial link, enabling the SPI-compatible port to communicate with other SPI compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multi-master environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The SPI-compatible peripheral implementation also features programmable baud rate and clock phase and polarities. The SPI-compatible port uses open drain drivers to support a multi-master configuration and to avoid data contention. UART Port The processors provide a full-duplex Universal Asynchronous Receiver/Transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART also has multiprocessor communication capability using 9-bit address detection. This allows it to be used in multidrop networks through the RS-485 data interface standard. The UART port also includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation: The entire PWM module has four groups of four PWM outputs generating 16 PWM outputs in total. Each PWM group produces two pairs of PWM signals on the four PWM outputs. The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single update mode or double update mode. In single update mode the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the midpoint of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters. PWM signals can be mapped to the external port address lines or to the DPI pins. Timers The processors have a total of three timers: a core timer that can generate periodic software interrupts and two general-purpose timers that can generate periodic interrupts and be independently set to operate in one of three modes: • Pulse waveform generation mode • PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive. • DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. The UART port's baud rate, serial data format, error code generation and status, and interrupts are programmable: • Support for bit rates ranging from (fPCLK/1,048,576) to (fPCLK/16) bits per second. • Pulse width count/capture mode • External event watch dog mode The core timer can be configured to use FLAG3 as a timer expired signal, and the general-purpose timers have one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables the generalpurpose timer. 2-Wire Interface Port (TWI) The TWI is a bidirectional 2-wire serial bus used to move 8-bit data while maintaining compliance with the I2C bus protocol. The TWI master incorporates the following features: • Support for data formats from 7 to 12 bits per frame. • 7-bit addressing • Both transmit and receive operations can be configured to generate maskable interrupts to the processor. • Simultaneous master and slave operation on multiple device systems with support for multi-master data arbitration In conjunction with the general-purpose timer functions, autobaud detection is supported. • Digital filtering and timed event processing • 100 kbps and 400 kbps data rates • Low interrupt rate Rev. B | Page 11 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 Shift Register Table 9. DMA Channels (Continued) The shift register can be used as a serial to parallel data converter. The shift register module consists of an 18-stage serial shift register, 18-bit latch, and three-state output buffers. The shift register and latch have separate clocks. Data is shifted into the serial shift register on the positive-going transitions of the shift register serial clock (SR_SCLK) input. The data in each flip-flop is transferred to the respective latch on a positive-going transition of the shift register latch clock (SR_LAT) input. The shift register’s signals can be configured as follows. • The SR_LAT can come from any of SPORT0–7 frame sync outputs, PCGA/B frame sync, any of the DAI pins (1–8), and one dedicated pin (SR_LAT). • The SR_SDI input can from any of SPORT0–7 serial data outputs, any of the DAI pins (1–8), and one dedicated pin (SR_SDI). Note that the SR_SCLK, SR_LAT, and SR_SDI inputs must come from same source except in the case of where SR_SCLK comes from PCGA/B or SR_SCLK and SR_LAT come from PCGA/B. If SR_SCLK comes from PCGA/B, then SPORT0–7 generates the SR_LAT and SR_SDI signals. If SR_SCLK and SR_LAT come from PCGA/B, then SPORT0–7 generates the SR_SDI signal. I/O PROCESSOR FEATURES The I/O processor provides up to 65 channels of DMA as well as an extensive set of peripherals. DMA Controller The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the processor’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP) or the UART. Up to 65 channels of DMA are available on the processors as shown in Table 9. Programs can be downloaded using DMA transfers. Other DMA features include interrupt generation upon completion of DMA transfers, and DMA chaining for automatic linked DMA transfers. Peripheral SPORTs PDAP SPI UART DMA Channels 16 8 2 2 Rev. B | 1 DMA Channels 2 2 2 31 Automotive models only. Delay Line DMA • The SR_SCLK can come from any of the SPORT0–7 SCLK outputs, PCGA/B clock, any of the DAI pins (1–8), and one dedicated pin (SR_SCLK). Table 9. DMA Channels Peripheral External Port Accelerators Memory-to-Memory MediaLB1 The processor provides delay line DMA functionality. This allows processor reads and writes to external delay line buffers (and therefore to external memory) with limited core interaction. Scatter/Gather DMA The processor provides scatter/gather DMA functionality. This allows processor DMA reads/writes to/from noncontiguous memory blocks. FFT Accelerator The FFT accelerator implements radix-2 complex/real input, complex output FFTs with no core intervention. The FFT accelerator runs at the peripheral clock frequency. FIR Accelerator The FIR (finite impulse response) accelerator consists of a 1024 word coefficient memory, a 1024 word deep delay line for the data, and four MAC units. A controller manages the accelerator. The FIR accelerator runs at the peripheral clock frequency. IIR Accelerator The IIR (infinite impulse response) accelerator consists of a 1440 word coefficient memory for storage of biquad coefficients, a data memory for storing the intermediate data and one MAC unit. A controller manages the accelerator. The IIR accelerator runs at the peripheral clock frequency. Watchdog Timer (WDT) The processors include a 32-bit watchdog timer that can be used to implement a software watchdog function. A software watchdog can improve system reliability by forcing the processor to a known state through generation of a system reset if the timer expires before being reloaded by software. Software initializes the count value of the timer, and then enables the timer. The WDT is used to supervise the stability of the system software. When used in this way, software reloads the WDT in a regular manner so that the downward counting timer never expires. An expiring timer then indicates that system software might be out of control. The WDT resets both the core and the internal peripherals. Software must be able to determine if the watch dog was the source of the hardware reset by interrogating a status bit in the watch dog timer control register. Page 12 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 The watch dog timer also has an internal RC oscillator that can be used as the clock source. The internal RC oscillator can be used as an optional alternative to using an external clock applied to the WDT_CLIN pin. Table 10. Boot Mode Selection BOOT_CFG2–01 000 001 010 011 Real-Time Clock The real-time clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the SHARC processor. Connect RTC pins RTXI and RTXO with external components as shown in Figure 3. The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time. An RTCLKOUT signal that operates at 1 Hz is also provided for calibration. 100 1xx 1 Booting Mode SPI Slave Boot SPI Master Boot (from Flash and Other Slaves) AMI User Boot (for 8-bit Flash Boot) No Boot (Processor Executes from Internal ROM After Reset) Reserved Reserved The BOOT_CFG2 pin is not available on the 100-lead or 88-lead packages. A running reset feature is used to reset the processor core and peripherals without resetting the PLL and SDRAM controller, or performing a boot. The functionality of the RESETOUT /RUNRSTIN pin has now been extended to also act as the input for initiating a running reset. For more information, see the ADSP-214xx SHARC Processor Hardware Reference. Power Supplies RTXI The processors have separate power supply connections for the internal (VDD_INT) and external (VDD_EXT) power supplies. The internal and analog supplies must meet the VDD_INT specifications. The external supply must meet the VDD_EXT specification. All external supply pins must be connected to the same power supply. RTXO R1 X1 C1 C2 To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for VDD_INT and GND. NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF. Target Board JTAG Emulator Connector Figure 3. External Components for RTC The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and a 32,768-day counter. When the alarm interrupt is enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is for a time of day. The second alarm is for a day and time of that day. The stopwatch function counts down from a programmed value, with one-second resolution. When the stopwatch interrupt is enabled and the counter underflows, an interrupt is generated. SYSTEM DESIGN The following sections provide an introduction to system design options and power supply issues. Program Booting The internal memory boots at system power-up from an 8-bit EPROM via the external port, an SPI master, or an SPI slave. Booting is determined by the boot configuration (BOOT_CFG2–0) pins in Table 10. Rev. B | Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the processors to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor's JTAG interface ensures that the emulator will not affect target system loading or timing. For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appropriate emulator hardware user’s guide. DEVELOPMENT TOOLS The processors are supported with a complete set of CROSSCORE® software and hardware development tools, including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that supports other SHARC processors also fully emulates the processors. EZ-KIT Lite Evaluation Board For evaluation of the processors, use the EZ-KIT Lite® board being developed by Analog Devices. The board comes with onchip emulation capabilities and is equipped to enable software development. Multiple daughter cards are available. Page 13 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 Designing an Emulator-Compatible DSP Board (Target) ADDITIONAL INFORMATION The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG DSP. Nonintrusive incircuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. This data sheet provides a general overview of the ADSP-2147x architecture and functionality. For detailed information on the family core architecture and instruction set, refer to the SHARC Processor Programming Reference. To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. RELATED SIGNAL CHAINS A signal chain is a series of signal conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the “signal chain” entry in the Glossary of EE Terms on the Analog Devices website. Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website. The Circuits from the LabTM site (www.analog.com/signal chains) provides: Evaluation Kit Analog Devices offers a range of EZ-KIT Lite evaluation platforms to use as a cost effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product. • Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications • Drill down links for components in each chain to selection guides and application information • Reference designs applying best practice design techniques The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board Flash device to store user-specific boot code, enabling the board to run as a standalone unit without being connected to the PC. With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation. Rev. B | Page 14 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 PIN FUNCTION DESCRIPTIONS Table 11. Pin Descriptions State During/ After Reset Name Type Description ADDR23–0 I/O/T (ipu) High-Z/driven low (boot) External Address. The processor outputs addresses for external memory and peripherals on these pins. The ADDR pins can be multiplexed to support the external memory interface address, FLAGS15–8 (I/O) and PWM (O). After reset, all ADDR pins are in EMIF mode, and FLAG(0–3) pins are in FLAGS mode (default). When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the ADDR23–4 pins for parallel input data. DATA15–0 I/O/T (ipu) High-Z External Data. The data pins can be multiplexed to support the external memory interface data (I/O) and FLAGS7–0 (I/O). AMI_ACK I (ipu) MS0–1 O/T (ipu) High-Z Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corresponding banks of external memory. The MS1-0 lines are decoded memory address lines that change at the same time as the other address lines. When no external memory access is occurring the MS1-0 lines are inactive; they are active however when a conditional memory access instruction is executed, whether or not the condition is true. The MS1 pin can be used in EPORT/FLASH boot mode. For more information on processor booting, see the ADSP-214xx SHARC Processor Hardware Reference. AMI_RD O/T (ipu) High-Z AMI Port Read Enable. AMI_RD is asserted whenever the processor reads a word from external memory. AMI_WR O/T (ipu) High-Z AMI Port Write Enable. AMI_WR is asserted when the processor writes a word to external memory. FLAG0/IRQ0 I/O (ipu) FLAG[0] INPUT FLAG0/Interrupt Request0. FLAG1/IRQ1 I/O (ipu) FLAG[1] INPUT FLAG1/Interrupt Request1. FLAG2/IRQ2/MS2 I/O (ipu) FLAG[2] INPUT FLAG2/Interrupt Request2/Memory Select2. This pin is multiplexed with MS2 in the 196-ball BGA package only. FLAG3/TMREXP/MS3 I/O (ipu) FLAG[3] INPUT FLAG3/Timer Expired/Memory Select3. This pin is multiplexed with MS3 in the 196-ball BGA package only. Memory Acknowledge. External devices can deassert AMI_ACK (low) to add wait states to an external memory access. AMI_ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. The following symbols appear in the Type column of Table 11: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive, O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 kΩ to 63 kΩ. The range of an ipd resistor can be 31 kΩ to 85 kΩ. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical conditions the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins. Not all pins are available in the 88-lead LFCSP_VQ and 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 62 on Page 69. Rev. B | Page 15 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 Table 11. Pin Descriptions (Continued) State During/ After Reset Description O/T (ipu) High-Z/ driven high SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other SDRAM command pins, defines the operation for the SDRAM to perform. SDCAS O/T (ipu) High-Z/ driven high SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with other SDRAM command pins, defines the operation for the SDRAM to perform. SDWE O/T (ipu) High-Z/ driven high SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin. SDCKE O/T (ipu) High-Z/ driven high SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK signal. For details, see the data sheet supplied with the SDRAM device. SDA10 O/T (ipu) High-Z/ driven high SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with nonSDRAM accesses. This pin replaces the DSP’s ADDR10 pin only during SDRAM accesses. SDDQM O/T (ipu) High-Z/ driven high DQM Data Mask. SDRAM input mask signal for write accesses and output enable signal for read accesses. Input data is masked when DQM is sampled high during a write cycle. The SDRAM output buffers are placed in a High-Z state when DQM is sampled high during a read cycle. SDDQM is driven high from reset de-assertion until SDRAM initialization completes. Afterwards, it is driven low irrespective of whether any SDRAM accesses occur or not. SDCLK O/T (ipd) High-Z/ driving SDRAM Clock Output. Clock driver for this pin differs from all other clock drivers. See Figure 47 on Page 64. For models in the 100-lead package, the SDRAM interface should be disabled to avoid unnecessary power switching by setting the DSDCTL bit in SDCTL register. For more information, see the ADSP-214xx SHARC Processor Hardware Reference. DAI _P20–1 I/O/T (ipu) High-Z Digital Applications Interface. These pins provide the physical interface to the DAI SRU. The DAI SRU configuration registers define the combination of on-chip audio-centric peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determines the exact behavior of the pin. Any input or output signal present in the DAI SRU may be routed to any of these pins. DPI _P14–1 I/O/T (ipu) High-Z Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU. The DPI SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin's output enable. The configuration registers of these peripherals then determine the exact behavior of the pin. Any input or output signal present in the DPI SRU may be routed to any of these pins. Name Type SDRAS WDT_CLKIN I Watch Dog Timer Clock Input. This pin should be pulled low when not used. WDT_CLKO O Watch Dog Resonator Pad Output. WDTRSTO O (ipu) Watch Dog Timer Reset Out. The following symbols appear in the Type column of Table 11: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive, O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 kΩ to 63 kΩ. The range of an ipd resistor can be 31 kΩ to 85 kΩ. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical conditions the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins. Not all pins are available in the 88-lead LFCSP_VQ and 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 62 on Page 69. Rev. B | Page 16 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 Table 11. Pin Descriptions (Continued) Name Type THD_P I State During/ After Reset Description Thermal Diode Anode. When not used, this pin can be left floating. THD_M O Thermal Diode Cathode. When not used, this pin can be left floating. MLBCLK I Media Local Bus Clock. This clock is generated by the MLB controller that is synchronized to the MOST network and provides the timing for the entire MLB interface at 49.152 MHz at FS = 48 kHz. When the MLB controller is not used, this pin should be grounded. MLBDAT I/O/T in 3 pin mode. I in 5 pin mode. High-Z Media Local Bus Data. The MLBDAT line is driven by the transmitting MLB device and is received by all other MLB devices including the MLB controller. The MLBDAT line carries the actual data. In 5-pin MLB mode, this pin is an input only. When the MLB controller is not used, this pin should be grounded. MLBSIG I/O/T in 3 pin mode. I in 5 pin mode High-Z Media Local Bus Signal. This is a multiplexed signal which carries the Channel/Address generated by the MLB Controller, as well as the Command and RxStatus bytes from MLB devices. In 5-pin mode, this pin is input only. When the MLB controller is not used, this pin should be grounded. MLBDO O/T High-Z Media Local Bus Data Output (in 5 Pin Mode). This pin is used only in 5-pin MLB mode and serves as the output data pin. When the MLB controller is not used, this pin should be grounded. MLBSO O/T High-Z Media Local Bus Signal Output (in 5 Pin Mode). This pin is used only in 5-pin MLB mode and serves as the output signal pin. When the MLB controller is not used, this pin should be grounded. SR_SCLK I (ipu) Shift Register Serial Clock. (Active high, rising edge sensitive) SR_CLR I (ipu) Shift Register Reset. (Active low) SR_SDI I (ipu) Shift Register Serial Data Input. SR_SDO O (ipu) SR_LAT I (ipu) SR_LDO17–0 O/T (ipu) RTXI I RTC Crystal Input. If RTC is not used, then this pin needs to be NC (no connect) and the RTC_PDN and RTC_BUSDIS bits of RTC_INIT register must be set to 1. RTXO O RTC Crystal Output. If RTC is not used, then this pin needs to be NC (No Connect). RTCLKOUT O (ipd) RTC Clock Output. For calibration purposes. The clock runs at 1 Hz. If RTC is not used, then this pin needs to be NC (No Connect). Driven Low Shift Register Serial Data Output. Shift Register Latch Clock Input. (Active high, rising edge sensitive) High-Z Shift Register Parallel Data Output. The following symbols appear in the Type column of Table 11: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive, O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 kΩ to 63 kΩ. The range of an ipd resistor can be 31 kΩ to 85 kΩ. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical conditions the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins. Not all pins are available in the 88-lead LFCSP_VQ and 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 62 on Page 69. Rev. B | Page 17 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 Table 11. Pin Descriptions (Continued) Name Type TDI I (ipu) State During/ After Reset Description Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDO O/T TMS I (ipu) High-Z Test Mode Select (JTAG). Used to control the test state machine. TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up or held low for proper operation of the device. TRST I (ipu) Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the processor. EMU O (O/D, ipu) CLK_CFG1–0 I Core to CLKIN Ratio Control. These pins set the startup clock frequency. Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset. The allowed values are: 00 = 8:1 01 = 32:1 10 = 16:1 11 = reserved CLKIN I Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It configures the processors to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the processors to use the external clock source such as an external clock oscillator. CLKIN may not be halted, changed, or operated below the specified frequency. XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal. RESET I Processor Reset. Resets the processor to a known state. Upon deassertion, there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up. High-Z Test Data Output (JTAG). Serial scan output of the boundary scan path. Emulation Status. Must be connected to the Analog Devices DSP Tools product line of JTAG emulators target board connector only. RESETOUT/RUNRSTIN I/O (ipu) Reset Out/Running Reset In. The default setting on this pin is reset out. This pin also has a second function as RUNRSTIN which is enabled by setting bit 0 of the RUNRSTCTL register. For more information, see the ADSP-214xx SHARC Processor Hardware Reference. BOOT_CFG2–0 Boot Configuration Select. These pins select the boot mode for the processor. The BOOT_CFG pins must be valid before RESET (hardware and software) is deasserted. The BOOT_CFG2 pin is only available on the 196-lead package. I The following symbols appear in the Type column of Table 11: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive, O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 kΩ to 63 kΩ. The range of an ipd resistor can be 31 kΩ to 85 kΩ. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical conditions the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins. Not all pins are available in the 88-lead LFCSP_VQ and 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 62 on Page 69. Rev. B | Page 18 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 Table 12. Pin List, Power and Ground 1 Name Type Description VDD_INT P Internal Power Supply. VDD_EXT P I/O Power Supply. VDD_RTC P Real-Time Clock Power Supply. GND1 G Ground. VDD_THD P Thermal Diode Power Supply. When not used, this pin can be left floating. The exposed pad is required to be electrically and thermally connected to GND. Implement this by soldering the exposed pad to a GND PCB land that is the same size as the exposed pad. The GND PCB land should be robustly connected to the GND plane in the PCB for best electrical and thermal performance. See also 88-LFCSP_VQ Lead Assignment on Page 67 and 100-LQFP_EP Lead Assignment on Page 69. Rev. B | Page 19 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 SPECIFICATIONS OPERATING CONDITIONS 200 MHz 1 266 MHz 300 MHz Parameter Description Min Nom Max Min Nom Max Min Nom Max Unit VDD_INT VDD_EXT VDD_THD VDD_RTC VIH2 VIL3 VIH_CLKIN3 VIL_CLKIN TJ Internal (Core) Supply Voltage External (I/O) Supply Voltage Thermal Diode Supply Voltage Real-Time Clock Power Supply Voltage High Level Input Voltage @ VDD_EXT = Max Low Level Input Voltage @ VDD_EXT = Min High Level Input Voltage @ VDD_EXT = Max Low Level Input Voltage @ VDD_EXT = Max Junction Temperature 88-Lead LFCSP_VQ @ TAMBIENT 0°C to +70°C Junction Temperature 88-Lead LFCSP_VQ @ TAMBIENT –40°C to +85°C Junction Temperature 88-Lead LFCSP_VQ @ TAMBIENT –40°C to +105°C Junction Temperature 100-Lead LQFP_EP @ TAMBIENT 0°C to +70°C Junction Temperature 100-Lead LQFP_EP @ TAMBIENT –40°C to +85°C Junction Temperature 100-Lead LQFP_EP @ TAMBIENT –40°C to +105°C Junction Temperature 196-Ball CSP_BGA @ TAMBIENT 0°C to +70°C Junction Temperature 196-Ball CSP_BGA @ TAMBIENT –40°C to +85°C 1.14 3.13 3.13 2.0 2.0 1.2 3.3 3.3 3.0 1.26 3.47 3.47 3.6 1.14 3.13 3.13 2.0 2.0 1.2 3.3 3.3 3.0 1.26 3.47 3.47 3.6 1.25 3.13 3.13 2.0 2.0 1.3 3.3 3.3 3.0 TJ TJ4 TJ TJ4 TJ4 TJ5 TJ5 2.2 –0.3 0 0.8 VDD_EXT 0.8 105 2.2 –0.3 N/A 0.8 VDD_EXT 2.2 0.8 –0.3 N/A N/A 0.8 VDD_EXT 0.8 N/A V V V V V V V V °C –40 +115 N/A N/A N/A N/A °C –40 +125 N/A N/A N/A N/A °C 0 105 0 105 N/A N/A °C N/A N/A –40 +125 N/A N/A °C –40 +125 –40 +125 N/A N/A °C N/A N/A 0 105 0 100 °C N/A N/A –40 +125 N/A N/A °C 1 1.35 3.47 3.47 3.6 Specifications subject to change without notice. Applies to input and bidirectional pins: ADDR23–0, DATA15–0, FLAG3–0, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RUNRSTIN, RESET, TCK, TMS, TDI, TRST, SDA10, AMI_ACK, MLBCLK, MLBDAT, MLBSIG. 3 Applies to input pin CLKIN, WDT_CLKIN. 4 Applies to automotive models only. See Automotive Products on Page 74. 5 Real Time Clock (RTC) is supported only for products with a temperature range of 0°C to +70°C and not supported for all other temperature grades. For the status of unused RTC pins please see Table 11 on Page 15. 2 Rev. B | Page 20 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 ELECTRICAL CHARACTERISTICS 200 MHz 1 Parameter Description VOH2 IDD-INTYP9 High Level Output Voltage @ VDD_EXT = Min, IOH = –1.0 mA3 Low Level Output Voltage @ VDD_EXT = Min, IOL = 1.0 mA3 High Level Input Current @ VDD_EXT = Max, VIN = VDD_EXT Max Low Level Input Current @ VDD_EXT = Max, VIN = 0 V Low Level Input Current @ VDD_EXT = Max, VIN = 0 V Pull-up Three-State Leakage @ VDD_EXT = Max, Current VIN = VDD_EXT Max Three-State Leakage @ VDD_EXT = Max, VIN = 0 V Current Three-State Leakage @ VDD_EXT = Max, VIN = 0 V Current Pull-up Three-State Leakage @ VDD_EXT = Max, Current Pull-down VIN = VDD_EXT Max VDD_RTC Current @ VDD_RTC = 3.0, TJ = 25°C Supply Current (Internal) fCCLK > 0 MHz CIN10, 11 Input Capacitance VOL2 IIH4, 5 IIL4 IILPU5 IOZH6, 7 IOZL6 IOZLPU7 IOZHPD8 IDD_RTC Test Conditions Min Max 2.4 TCASE = 25°C 266 MHz Min Max 2.4 300 MHz Min Max 2.4 Unit V 0.4 0.4 0.4 V 10 10 10 μA –10 200 –10 200 –10 200 μA μA 10 10 10 μA –10 –10 –10 μA 200 200 200 μA 200 200 200 μA 0.76 0.76 0.76 μA Table 14 + Table 15 × ASF 5 Table 14 + Table 15 × ASF 5 Table 14 + Table 15 × ASF 5 mA 1 pF Specifications subject to change without notice. Applies to output and bidirectional pins: ADDR23-0, DATA15-0, AMI_RD, AMI_WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, RESETOUT,MLBSIG, MLBDAT, MLBDO, MLBSO, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, MS0-1. 3 See Output Drive Currents on Page 64 for typical drive current capabilities. 4 Applies to input pins: BOOT_CFGx, CLK_CFGx, TCK, RESET, CLKIN. 5 Applies to input pins with internal pull-ups: TRST, TMS, TDI. 6 Applies to three-statable pins: TDO, MLBDAT, MLBSIG, MLBDO, and MLBSO. 7 Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU. 8 Applies to three-statable pin with pull-down: SDCLK. 9 See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2147x SHARC Processors” for further information. 10 Applies to all signal pins. 11 Guaranteed, but not tested. 2 Rev. B | Page 21 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 Total Power Dissipation Total power dissipation has two components: 1. Internal power consumption External power consumption is due to the switching activity of the external pins. 2. External power consumption Table 13. Activity Scaling Factors (ASF)1 Internal power consumption also comprises two components: Activity Idle Low Medium Low Medium High Peak-Typical (50:50)2 Peak-Typical (60:40)2 Peak-Typical (70:30)2 High Typical High Peak 1. Static, due to leakage current. Table 14 shows the static current consumption (IDD-STATIC) as a function of junction temperature (TJ) and core voltage (VDD_INT). 2. Dynamic (IDD-DYNAMC), due to transistor switching characteristics and activity level of the processor. The activity level is reflected by the Activity Scaling Factor (ASF), which represents application code running on the processor core and having various levels of peripheral and external port activity (Table 13). Dynamic current consumption is calculated by scaling the specific application by the ASF and using baseline dynamic current consumption as a reference. The ASF is combined with the CCLK frequency and VDD_INT dependent data in Table 15 to calculate this part. Scaling Factor (ASF) 0.31 0.53 0.62 0.78 0.85 0.93 1.00 1.18 1.28 1.34 1 See Estimating Power for ADSP-214xx SHARC Processors (EE-348) for more information on the explanation of the power vectors specific to the ASF table. 2 Ratio of continuous instruction loop (core) to SDRAM control code reads and writes. Table 14. Static Current—IDD-STATIC (mA)1 TJ (°C) –45 –35 –25 –15 –5 +5 +15 +25 +35 +45 +55 +65 +75 +85 +95 +100 +105 +115 +125 1 1.05 V < 0.1 < 0.1 < 0.1 < 0.1 0.2 0.5 0.8 1.3 2.0 3.0 4.3 6.0 8.3 11.2 15.2 17.4 20.0 26.3 34.4 1.10 V < 0.1 < 0.1 0.2 0.4 0.6 0.9 1.4 1.9 2.8 3.9 5.4 7.3 9.9 13.2 17.6 20.2 23.0 30.0 38.9 1.15 V 0.4 0.4 0.4 0.6 0.9 1.3 1.8 2.5 3.4 4.7 6.3 8.6 11.5 15.3 20.1 22.9 26.1 33.9 43.6 VDD_INT (V) 1.20 V 0.8 0.7 0.8 1.0 1.3 1.8 2.3 3.1 4.2 5.7 7.6 10.1 13.3 17.5 22.9 25.9 29.5 38.2 48.8 Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 20. Rev. B | Page 22 of 76 | March 2012 1.25 V 1.3 1.1 1.2 1.4 1.8 2.3 3.0 3.9 5.1 6.7 8.8 11.7 15.3 19.9 26.1 29.4 33.4 42.9 54.8 1.30 V 2.1 1.7 1.7 1.9 2.3 3.0 3.7 4.7 6.0 7.8 10.3 13.5 17.4 22.6 29.4 33.0 N/A N/A N/A 1.35 V 3.3 2.9 2.9 3.2 3.7 4.4 5.1 6.2 8.0 10.1 12.9 16.4 21.2 27.1 34.6 39.2 N/A N/A N/A ADSP-21477/ADSP-21478/ADSP-21479 Table 15. Baseline Dynamic Current in CCLK Domain (mA, with ASF = 1.0)1, 2 fCCLK (MHz) 100 150 200 266 300 1 2 1.05 V 75 111 N/A N/A N/A 1.10 V 78 117 N/A N/A N/A Voltage (VDD_INT) 1.20 V 1.25 V 86 90 128 134 170 178 225 234 N/A 264 1.15 V 82 122 162 215 N/A 1.35 V 98 146 194 256 291 The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 21. Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 20. MAXIMUM POWER DISSIPATION ESD SENSITIVITY See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2147x SHARC Processors” for detailed thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see Thermal Characteristics on Page 65. ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. PACKAGE INFORMATION The information presented in Figure 4 provides details about the package branding. For a complete listing of product availability, see Ordering Guide on Page 75. a ADSP-2147x tppZ-cc vvvvvv.x n.n S Stresses greater than those listed in Table 17 may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in Operating Conditions on Page 20 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter Internal (Core) Supply Voltage (VDD_INT) External (I/O) Supply Voltage (VDD_EXT) Real Time Clock Voltage (VDD_RTC) Thermal Diode Supply Voltage (VDD_THD) Input Voltage Output Voltage Swing Storage Temperature Range Junction Temperature While Biased Figure 4. Typical Package Brand Table 16. Package Brand Information1 Brand Key t pp Z cc vvvvvv.x n.n # yyww ABSOLUTE MAXIMUM RATINGS Table 17. Absolute Maximum Ratings #yyww country_of_origin 1 1.30 V 95 141 186 246 279 Field Description Temperature Range Package Type RoHS Compliant Option See Ordering Guide Assembly Lot Code Silicon Revision RoHS Compliant Designation Date Code Nonautomotive only. For branding information specific to automotive products, contact Analog Devices Inc. Rev. B | Page 23 of 76 | March 2012 Rating –0.3 V to +1.35 V –0.3 V to +4.6 V –0.3 V to +4.6 V –0.3 V to +4.6 V –0.5 V to +3.8 V –0.5 V to VDD_EXT +0.5 V –65°C to +150°C 125°C ADSP-21477/ADSP-21478/ADSP-21479 TIMING SPECIFICATIONS fINPUT is the input frequency to the PLL. Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. See Figure 49 on Page 64 under Test Conditions for voltage reference levels. fINPUT = CLKIN when the input divider is disabled, or CLKIN ÷ 2 when the input divider is enabled. Switching Characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. Core Clock Requirements The processor’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, and serial ports. During reset, program the ratio between the processor’s internal clock frequency and external (CLKIN) clock frequency with the CLK_CFG1–0 pins. Note the definitions of the clock periods that are a function of CLKIN and the appropriate ratio control shown in Table 20. All of the timing specifications for the peripherals are defined in relation to tPCLK. See the peripheral specific section for each peripheral’s timing information. Table 18. Clock Periods Timing Requirements tCK tCCLK tPCLK tSDCLK Figure 5 shows core to CLKIN relationships with an external oscillator or crystal. The shaded divider/multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register (PMCTL). For more information, see the ADSP-214xx SHARC Processor Hardware Reference. The processor’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the processor uses an internal phase-locked loop (PLL, see Figure 5). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the processor’s internal clock. Voltage Controlled Oscillator (VCO) In application designs, the PLL multiplier value should be selected in such a way that the VCO frequency never exceeds fVCO specified in Table 20. • The product of CLKIN and PLLM must never exceed 1/2 of fVCO (max) in Table 20 if the input divider is not enabled (INDIV = 0). • The product of CLKIN and PLLM must never exceed fVCO (max) in Table 20 if the input divider is enabled (INDIV = 1). The VCO frequency is calculated as follows: fVCO = 2 × PLLM × fINPUT fCCLK = (2 × PLLM × fINPUT) ÷ PLLD where: fVCO = VCO output PLLM = Multiplier value programmed in the PMCTL register. During reset, the PLLM value is derived from the ratio selected using the CLK_CFG pins in hardware. PLLD = 2, 4, 8, or 16 based on the divider value programmed on the PMCTL register. During reset this value is 2. Rev. B | Description CLKIN Clock Period Processor Core Clock Period Peripheral Clock Period = 2 × tCCLK SDRAM Clock Period = (tCCLK) × SDCKR Page 24 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 PMCTL (SDCKR) PMCTL (PLLBP) CLKIN DIVIDER fINPUT LOOP FILTER VCO fVCO PLL DIVIDER fCCLK CCLK SDRAM DIVIDER BYPASS MUX CLKIN BYPASS MUX PLL XTAL BUF CLK_CFGx/ PMCTL (2 × PLLM) PMCTL (INDIV) PMCTL (PLLD) DIVIDE BY 2 PMCTL (PLLBP) PCLK fVCO ÷ (2 × PLLM) PCLK CCLK RESET DELAY OF 4096 CLKIN CYCLES PIN MUX CLKOUT (TEST ONLY)* RESETOUT Figure 5. Core Clock and System Clock Relationship to CLKIN Page 25 of 76 | RESETOUT CORESRST *CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS fINPUT. THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN. Rev. B | BUF March 2012 SDCLK ADSP-21477/ADSP-21478/ADSP-21479 • If the VDD_INT power supply comes up after VDD_EXT, any pin, such as RESETOUT and RESET, may actually drive momentarily until the VDD_INT rail has powered up. Systems sharing these signals on the board must determine if there are any issues that need to be addressed based on this behavior. Power-Up Sequencing The timing requirements for processor startup are given in Table 19. While no specific power-up sequencing is required between VDD_EXT and VDD_INT, there are some considerations that the system designs should take into account. • No power supply should be powered up for an extended period of time (>200 ms) before another supply starts to ramp up. Note that during power-up, when the VDD_INT power supply comes up after VDD_EXT, a leakage current of the order of threestate leakage current pull-up, pull-down, may be observed on any pin, even if that is an input only (for example, the RESET pin), until the VDD_INT rail has powered up. Table 19. Power-Up Sequencing Timing Requirements (Processor Startup) Parameter Timing Requirements tRSTVDD RESET Low Before VDD_EXT or VDD_INT On tIVDDEVDD VDD_INT On Before VDD_EXT tCLKVDD1 CLKIN Valid After VDD_INT and VDD_EXT Valid tCLKRST CLKIN Valid Before RESET Deasserted PLL Control Setup Before RESET Deasserted tPLLRST Switching Characteristic tCORERST Core Reset Deasserted After RESET Deasserted Min 0 –200 0 102 203 4096 × tCK + 2 × tCCLK 4, 5 1 Max +200 200 Unit ms ms ms μs μs ns Valid VDD_INT and VDD_EXT assumes that the supplies are fully ramped to their nominal values (it does not matter which supply comes up first). Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem. 2 Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time. Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal. 3 Based on CLKIN cycles. 4 Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and propagate default states at all I/O pins. 5 The 4096 cycle count depends on tSRST specification in Table 21. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles maximum. RESET VDDINT tRSTVDD tIVDDEVDD VDDEXT tCLKVDD CLKIN tCLKRST CLK_CFG1–0 tPLLRST tCORERST RESETOUT Figure 6. Power-Up Sequencing Rev. B | Page 26 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 Clock Input Table 20. Clock Input Min Parameter Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V) tCCLK2 CCLK Period VCO Frequency fVCO3 tCKJ4, 5 CLKIN Jitter Tolerance 40 20 20 5 200 –250 200 MHz Max 100 45 45 3 10 600 +250 Min 266 MHz Max 301 15 15 100 45 45 3 10 600 +250 3.75 200 –250 1 Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL. Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tcclk. 3 See Figure 5 on Page 25 for VCO diagram. 4 Actual input jitter should be combined with ac specifications for accurate timing analysis. 5 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter. 2 tCKJ tCK CLKIN tCKH tCKL Figure 7. Clock Input Rev. B | Page 27 of 76 | March 2012 Min 26.661 13.33 13.33 3.33 200 –250 300 MHz Max Unit 100 45 45 3 10 600 +250 ns ns ns ns ns MHz ps ADSP-21477/ADSP-21478/ADSP-21479 mental mode. Note that the clock rate is achieved using a 16.67 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve the full core clock rate, programs need to configure the multiplier bits in the PMCTL register. Clock Signals The processors can use an external clock or a crystal. See the CLKIN pin description in Table 11. Programs can configure the processor to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 8 shows the component connections used for a crystal operating in funda- ADSP-2147x R1 1MΩ * CLKIN XTAL R2 47Ω * C1 22pF C2 22pF Y1 CHOOSE C1 AND C2 BASED ON THE CRYSTAL Y1. CHOOSE R2 TO LIMIT CRYSTAL DRIVE POWER. REFER TO CRYSTAL MANUFACTURER'S SPECIFICATIONS 16.67 *TYPICAL VALUES Figure 8. 266 MHz Operation (Fundamental Mode Crystal) Reset Table 21. Reset Parameter Timing Requirements tWRST1 RESET Pulse Width Low tSRST RESET Setup Before CLKIN Low 1 Min Max 4 × tCK 8 Unit ns ns Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable Vdd and CLKIN (not including start-up time of external clock oscillator). CLKIN tWRST tSRST RESET Figure 9. Reset Rev. B | Page 28 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 Running Reset The following timing specification applies to RESETOUT/ RUNRSTIN pin when it is configured as RUNRSTIN. Table 22. Running Reset Parameter Timing Requirements tWRUNRST Running RESET Pulse Width Low tSRUNRST Running RESET Setup Before CLKIN High Min Max Unit 4 × tCK 8 ns ns CLKIN tWRUNRST tSRUNRST RUNRSTIN Figure 10. Running Reset Interrupts The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts, as well as the DAI_P20–1 and DPI_P14–1 pins when they are configured as interrupts. Table 23. Interrupts Parameter Timing Requirement tIPW IRQx Pulse Width Min 2 × tPCLK + 2 INTERRUPT INPUTS tIPW Figure 11. Interrupts Rev. B | Page 29 of 76 | March 2012 Max Unit ns ADSP-21477/ADSP-21478/ADSP-21479 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP). Table 24. Core Timer Parameter Switching Characteristic tWCTIM TMREXP Pulse Width Min 88-Lead LFCSP Package Max 4 × tPCLK - 1.55 Min All Other Packages Max 4 × tPCLK – 1.2 Unit ns tWCTIM FLAG3 (TMREXP) Figure 12. Core Timer Timer PWM_OUT Cycle Timing The following timing specification applies to timer0 and timer1 in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the timing specifications provided below are valid at the DPI_P14–1 pins. Table 25. Timer PWM_OUT Timing Parameter Switching Characteristic tPWMO Timer Pulse Width Output Min 88-Lead LFCSP Package Max 2 × tPCLK – 1.65 2 × (231 – 1) × tPCLK tPWMO PWM OUTPUTS Figure 13. Timer PWM_OUT Timing Rev. B | Page 30 of 76 | March 2012 Min All Other Packages Max 2 × tPCLK – 1.2 2 × (231 – 1) × tPCLK Unit ns ADSP-21477/ADSP-21478/ADSP-21479 Timer WDTH_CAP Timing The following timing specification applies to timer0 and timer1, and in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DPI_P14–1 pins through the SRU. Therefore, the timing specification provided below is valid at the DPI_P14–1 pins. Table 26. Timer Width Capture Timing Parameter Timing Requirement tPWI Timer Pulse Width Min Max Unit 2 × tPCLK 2 × (231 – 1) × tPCLK ns Min Max Unit 100 1000 ns 3 7.6 ns tPWI TIMER CAPTURE INPUTS Figure 14. Timer Width Capture Timing Watchdog Timer Timing Table 27. Watchdog Timer Timing Parameter Timing Requirement tWDTCLKPER Switching Characteristics tRST WDT Clock Rising Edge to Watchdog Timer RESET Falling Edge tRSTPW Reset Pulse Width 1 64 × tWDTCLKPER1 When the internal oscillator is used, the 1/tWDTCLKPER varies from 1.5 MHz to 2.5 MHz and the WDT_CLKIN pin should be pulled low. tWDTCLKPER WDT_CLKIN tRST tRSTPW WDTRSTO Figure 15. Watchdog Timer Timing Rev. B | Page 31 of 76 | March 2012 ns ADSP-21477/ADSP-21478/ADSP-21479 Pin to Pin Direct Routing (DAI and DPI) For direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O). Table 28. DAI/DPI Pin to Pin Routing Parameter Timing Requirement tDPIO Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid Min Max Unit 1.5 10 ns DAI_Pn DPI_Pn tDPIO DAI_Pm DPI_Pm Figure 16. DAI Pin to Pin Direct Routing Rev. B | Page 32 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins (DAI_P01 – DAI_P20). Table 29. Precision Clock Generator (Direct Pin Routing) 88-Lead LFCSP Package All Other Packages Unit Parameter Min Max Min Max Timing Requirements tPCGIP Input Clock Period tPCLK × 4 tPCLK × 4 ns PCG Trigger Setup Before 4.5 4.5 ns tSTRIG Falling Edge of PCG Input Clock tHTRIG PCG Trigger Hold After Falling 3 3 ns Edge of PCG Input Clock Switching Characteristics tDPCGIO 12.5 PCG Output Clock and Frame 2 × tPCLK 2.5 ns Sync Active Edge Delay After 2.5 PCG Input Clock tDTRIGCLK PCG Output Clock Delay After 2.5 + (2.5 × tPCGIP) 2 × tPCLK + (2.5 × tPCGIP) 2.5 + (2.5 × tPCGIP) 12.5 + (2.5 × tPCGIP) ns PCG Trigger tDTRIGFS PCG Frame Sync Delay After 2.5 + ((2.5 + D – PH) × 2 × tPCLK + ((2.5 + D – 2.5 + ((2.5 + D – PH) × 12.5 + ((2.5 + D – PH) ns tPCGIP) × tPCGIP) PCG Trigger tPCGIP) PH) × tPCGIP) tPCGOW1 Output Clock Period 2 × tPCGIP – 1 2 × tPCGIP – 1 ns D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-214xx SHARC Processor Hardware Reference, “Precision Clock Generators” chapter. 1 Normal mode of operation. tSTRIG tHTRIG DAI_Pn DPI_Pn PCG_TRIGx_I DAI_Pm DPI_Pm PCG_EXTx_I (CLKIN) tPCGIP tDPCGIO DAI_Py DPI_Py PCK_CLKx_O tDTRIGCLK tDPCGIO DAI_Pz DPI_Pz PCG_FSx_O tDTRIGFS Figure 17. Precision Clock Generator (Direct Pin Routing) Rev. B | Page 33 of 76 | March 2012 tPCGOW ADSP-21477/ADSP-21478/ADSP-21479 Flags The timing specifications provided below apply to ADDR23–0 and DATA7–0 when configured as FLAGS. See Table 11 on Page 15 for more information on flag use. Table 30. Flags Parameter Timing Requirement FLAGs IN Pulse Width1 tFIPW Switching Characteristic tFOPW FLAGs OUT Pulse Width1 1 Min This is applicable when the Flags are connected to DPI_P14–1, ADDR23–0, DATA7–0 and FLAG3–0 pins. FLAG INPUTS tFIPW FLAG OUTPUTS tFOPW Figure 18. Flags Rev. B | Page 34 of 76 | March 2012 Max Unit 2 × tPCLK + 3 ns 2 × tPCLK – 3.5 ns ADSP-21477/ADSP-21478/ADSP-21479 SDRAM Interface Timing Table 31. SDRAM Interface Timing Parameter Timing Requirements tSSDAT DATA Setup Before SDCLK tHSDAT DATA Hold After SDCLK Switching Characteristics tSDCLK1 SDCLK Period tSDCLKH SDCLK Width High SDCLK Width Low tSDCLKL tDCAD2 Command, ADDR, Data Delay After SDCLK 2 tHCAD Command, ADDR, Data Hold After SDCLK tDSDAT Data Disable After SDCLK tENSDAT Data Enable After SDCLK 133 MHz Max Min Min 150 MHz Max Unit 0.7 1.66 0.7 1.5 ns ns 7.5 2.5 2.5 6.66 2.2 2.2 ns ns ns ns ns ns ns 5 4.75 1 1 6.2 5.3 0.3 0.3 1 Systems should use the SDRAM model with a speed grade higher than the desired SDRAM controller speed. For example, to run the SDRAM controller at 133 MHz the SDRAM model with a speed grade of 143 MHz or above should be used. See Engineer-to-Engineer Note “Interfacing SDRAM memory to SHARC processors (EE-286)” for more information on hardware design guidelines for the SDRAM interface. 2 Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDQM, SDCKE. tSDCLKH tSDCLK SDCLK tSSDAT tHSDAT tSDCLKL DATA (IN) tDCAD tENSDAT tHCAD DATA (OUT) tDCAD tHCAD COMMAND/ADDR (OUT) Figure 19. SDRAM Interface Timing Rev. B | Page 35 of 76 | March 2012 tDSDAT ADSP-21477/ADSP-21478/ADSP-21479 AMI Read Use these specifications for asynchronous interfacing to memories. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode. Table 32. AMI Read Parameter Min Timing Requirements tDAD1, 2, 3 Address Selects Delay to Data Valid tDRLD1, 3 AMI_RD Low to Data Valid tSDS4, 5 Data Setup to AMI_RD High 2.6 tHDRH Data Hold from AMI_RD High 0.4 tDAAK2, 6 AMI_ACK Delay from Address Selects tDSAK4 AMI_ACK Delay from AMI_RD Low Switching Characteristics tDRHA Address Selects Hold After AMI_RD High RHC + 0.38 2 tDARL Address Selects to AMI_RD Low tSDCLK – 5 tRW AMI_RD Pulse Width W – 1.4 tRWR AMI_RD High to AMI_RD Low HI + tSDCLK – 1.2 W = (number of wait states specified in AMICTLx register) × tSDCLK. RHC = (number of Read Hold Cycles specified in AMICTLx register) × tSDCLK Where PREDIS = 0 HI = RHC: Read to Read from same bank HI = RHC + IC: Read to Read from different bank HI = RHC + Max (IC, (4 × tSDCLK)) : Read to Write from same or different bank Where PREDIS = 1 HI = RHC + Max (IC, (4 × tSDCLK)) : Read to Write from same or different bank HI = RHC + (3 × tSDCLK): Read to Read from same bank HI = RHC + Max (IC, (3 × tSDCLK)) : Read to Read from different bank IC = (number of idle cycles specified in AMICTLx register) × tSDCLK H = (number of hold cycles specified in AMICTLx register) × tSDCLK. 1 Max Unit W + tSDCLK – 6.32 W–3 ns ns ns ns ns ns tSDCLK – 10 + W W – 7.0 Data delay/setup: System must meet tDAD, tDRLD, or tSDS. The falling edge of AMI_MSx, is referenced. 3 The maximum limit of timing requirement values for tDAD and tDRLD parameters are applicable for the case where AMI_ACK is always high. 4 Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode. 5 Data hold: User must meet tHDRH in asynchronous access mode. See Test Conditions on Page 64 for the calculation of hold times given capacitive and dc loads. 6 AMI_ACK delay/setup: User must meet tdaak, or tdsak, for deassertion of AMI_ACK (low). 2 Rev. B | Page 36 of 76 | March 2012 ns ns ns ns ADSP-21477/ADSP-21478/ADSP-21479 AMI_ADDR AMI_MSx tDARL tRW tDRHA AMI_RD tDRLD tSDS tDAD tHDRH AMI_DATA tRWR tDSAK tDAAK AMI_ACK AMI_WR Figure 20. AMI Read Rev. B | Page 37 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 AMI Write Use these specifications for asynchronous interfacing to memories. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode. Table 33. AMI Write Parameter Timing Requirements tDAAK AMI_ACK Delay from Address Selects1, 2 tDSAK AMI_ACK Delay from AMI_WR Low1, 3 Switching Characteristics tDAWH Address Selects to AMI_WR Deasserted2 tDAWL Address Selects to AMI_WR Low2 tWW AMI_WR Pulse Width tDDWH Data Setup Before AMI_WR High tDWHA Address Hold After AMI_WR Deasserted Data Hold After AMI_WR Deasserted tDWHD tDATRWH Data Disable After AMI_WR Deasserted4 tWWR AMI_WR High to AMI_WR Low5 tDDWR Data Disable Before AMI_RD Low tWDE AMI_WR Low to Data Enabled W = (number of wait states specified in AMICTLx register) × tSDCLK H = (number of hold cycles specified in AMICTLx register) × tSDCLK Min tSDCLK – 4.4 + W tSDCLK – 4.5 W – 1.3 tSDCLK – 4.3 + W H H tSDCLK – 1.37 + H tSDCLK – 1.5+ H 2 × tSDCLK – 7.1 tSDCLK – 4.5 1 Max Unit tSDCLK – 10.1 + W W – 7.1 ns ns tSDCLK + 6.75+ H AMI_ACK delay/setup: System must meet tDAAK, or tDSAK, for deassertion of AMI_ACK (low). The falling edge of AMI_MSx is referenced. 3 Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode. 4 See Test Conditions on Page 64 for calculation of hold times given capacitive and dc loads. 5 For Write to Write: tSDCLK + H, for both same bank and different bank. For Write to Read: 3 × tSDCLK + H, for the same bank and different banks. 2 Rev. B | Page 38 of 76 | March 2012 ns ns ns ns ns ns ns ns ns ns ADSP-21477/ADSP-21478/ADSP-21479 AMI_ADDR AMI_MSx tDWHA tDAWH tDAWL tWW AMI_WR tWWR tWDE tDATRWH tDDWH AMI_DATA tDSAK tDWHD tDAAK AMI_ACK AMI_RD Figure 21. AMI Write Rev. B | Page 39 of 76 | March 2012 tDDWR ADSP-21477/ADSP-21478/ADSP-21479 Serial Ports In slave transmitter mode and master receiver mode, the maximum serial port frequency is fPCLK/8. In master transmitter mode and slave receiver mode, the maximum serial port clock frequency is fPCLK/4. Serial port signals (SCLK, FS, Data Channel A, Data Channel B) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. To determine whether communication is possible between two devices at clock speed, n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Table 34. Serial Ports—External Clock Parameter Timing Requirements tSFSE1 Frame Sync Setup Before SCLK (Externally Generated Frame Sync in Either Transmit or Receive Mode) 1 tHFSE Frame Sync Hold After SCLK (Externally Generated Frame Sync in Either Transmit or Receive Mode) tSDRE1 Receive Data Setup Before Receive SCLK tHDRE1 Receive Data Hold After SCLK tSCLKW SCLK Width tSCLK SCLK Period Switching Characteristics tDFSE2 Frame Sync Delay After SCLK (Internally Generated Frame Sync in Either Transmit or Receive Mode) 2 tHOFSE Frame Sync Hold After SCLK (Internally Generated Frame Sync in Either Transmit or Receive Mode) 2 tDDTE Transmit Data Delay After Transmit SCLK tHDTE2 Transmit Data Hold After Transmit SCLK 1 2 88-Lead LFCSP Package Min Max Min 4 2.5 ns 4 2.5 ns 4 4 (tPCLK × 4) ÷ 2 – 1.5 tPCLK × 4 2.5 2.5 (tPCLK × 4) ÷ 2 – 1.5 tPCLK × 4 ns ns ns ns 15 2 15 2 15 2 Page 40 of 76 | March 2012 Unit ns ns 15 2 Referenced to sample edge. Referenced to drive edge. Rev. B | All Other Packages Max ns ns ADSP-21477/ADSP-21478/ADSP-21479 Table 35. Serial Ports—Internal Clock Parameter Timing Requirements tSFSI1 Frame Sync Setup Before SCLK (Externally Generated Frame Sync in Either Transmit or Receive Mode) tHFSI1 Frame Sync Hold After SCLK (Externally Generated Frame Sync in Either Transmit or Receive Mode) 1 tSDRI Receive Data Setup Before SCLK tHDRI1 Receive Data Hold After SCLK Switching Characteristics tDFSI2 Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode) 2 tHOFSI Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) tDFSIR2 Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode) tHOFSIR2 Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode) tDDTI2 Transmit Data Delay After SCLK tHDTI2 Transmit Data Hold After SCLK tSCKLIW Transmit or Receive SCLK Width Min 88-Lead LFCSP Package Max All Other Packages Max Unit 13 10.5 ns 2.5 2.5 ns 13 2.5 10.5 2.5 ns ns 5 –1.0 5 –1.0 10.7 –1.0 10.7 4 –1.0 2 × tPCLK – 1.5 2 × tPCLK + 1.5 Referenced to the sample edge. 2 Referenced to drive edge. Page 41 of 76 | March 2012 ns ns 4 –1.0 2 × tPCLK – 1.5 ns ns –1.0 1 Rev. B | Min 2 × tPCLK + 1.5 ns ns ns ADSP-21477/ADSP-21478/ADSP-21479 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE tSCLKIW DATA RECEIVE—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE DAI_P20–1 (SCLK) SAMPLE EDGE tSCLKW DAI_P20–1 (SCLK) tDFSIR tDFSE tSFSI tHOFSIR tHFSI DAI_P20–1 (FS) tSFSE tHFSE tSDRE tHDRE tHOFSE DAI_P20–1 (FS) tSDRI tHDRI DAI_P20–1 (DATA CHANNEL A/B) DAI_P20–1 (DATA CHANNEL A/B) DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE tSCLKIW DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE DAI_P20–1 (SCLK) tSCLKW SAMPLE EDGE DAI_P20–1 (SCLK) tDFSI tDFSE tHOFSI tSFSI tHFSI DAI_P20–1 (FS) tSFSE tHOFSE DAI_P20–1 (FS) tHDTI tDDTI tHDTE DAI_P20–1 (DATA CHANNEL A/B) DAI_P20–1 (DATA CHANNEL A/B) Figure 22. Serial Ports Rev. B | Page 42 of 76 | March 2012 tDDTE tHFSE ADSP-21477/ADSP-21478/ADSP-21479 Table 36. Serial Ports—External Late Frame Sync 88-Lead LFCSP Package All Other Packages Min Max Min Max Parameter Switching Characteristics tDDTLFSE1 Data Delay from Late External Transmit Frame Sync or External Receive Frame Sync with MCE = 1, MFD = 0 tDDTENFS1 Data Enable for MCE = 1, MFD = 0 1 2 × tPCLK 0.5 13.5 0.5 The tDDTLFSE and tDDTENFS parameters apply to left-justified as well as DSP serial mode, and MCE = 1, MFD = 0. EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE DAI_P20–1 (SCLK) tSFSE/I tHFSE/I DAI_P20–1 (FS) tDDTE/I tDDTENFS tHDTE/I DAI_P20–1 (DATA CHANNEL A/B) 2ND BIT 1ST BIT tDDTLFSE LATE EXTERNAL TRANSMIT FS DRIVE SAMPLE DRIVE DAI_P20–1 (SCLK) tSFSE/I tHFSE/I DAI_P20–1 (FS) tDDTE/I tDDTENFS DAI_P20–1 (DATA CHANNEL A/B) tHDTE/I 2ND BIT 1ST BIT tDDTLFSE Figure 23. External Late Frame Sync1 1 This figure reflects changes made to support left-justified mode. Rev. B | Page 43 of 76 | March 2012 Unit ns ns ADSP-21477/ADSP-21478/ADSP-21479 Table 37. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDDTEN1 Data Enable from External Transmit SCLK tDDTTE1 Data Disable from External Transmit SCLK 1 tDDTIN Data Enable from Internal Transmit SCLK 1 88-Lead LFCSP Package Min Max Min 2 2 All Other Packages Max 23 –1 20 –1 Referenced to drive edge. DRIVE EDGE DRIVE EDGE DAI_P20–1 (SCLK, EXT) tDDTEN tDDTTE DAI_P20–1 (DATA CHANNEL A/B) DRIVE EDGE DAI_P20–1 (SCLK, INT) tDDTIN DAI_P20–1 (DATA CHANNEL A/B) Figure 24. Enable and Three-State Rev. B | Page 44 of 76 | March 2012 Unit ns ns ns ADSP-21477/ADSP-21478/ADSP-21479 The SPORTx_TDV_O output signal (routing unit) becomes active in SPORT multichannel/packed mode. During transmit slots (enabled with active channel selection registers), the SPORTx_TDV_O is asserted for communication with external devices. Table 38. Serial Ports—TDV (Transmit Data Valid) Parameter Switching Characteristics1 tDRDVEN TDV Assertion Delay from Drive Edge of External Clock tDFDVEN TDV Deassertion Delay from Drive Edge of External Clock tDRDVIN TDV Assertion Delay from Drive Edge of Internal Clock tDFDVIN TDV Deassertion Delay from Drive Edge of Internal Clock 1 88-Lead LFCSP Package All Other Packages Min Max Min Max 3 3 2 × tPCLK –0.1 3.5 3.5 Referenced to drive edge. DRIVE EDGE DRIVE EDGE DAI_P20–1 (SCLK, EXT) TDVx DAI_P20-1 tDFDVEN tDRDVEN DRIVE EDGE DRIVE EDGE DAI_P20–1 (SCLK, INT) TDVx DAI_P20-1 tDFDVIN tDRDVIN Figure 25. Serial Ports—TDM Internal and External Clock Rev. B | Page 45 of 76 | March 2012 13.25 –0.1 Unit ns ns ns ns ADSP-21477/ADSP-21478/ADSP-21479 Input Data Port (IDP) The timing requirements for the IDP are given in Table 39. IDP signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 39. Input Data Port (IDP) Parameter Timing Requirements tSISFS1 Frame Sync Setup Before Serial Clock Rising Edge Frame Sync Hold After Serial Clock Rising Edge tSIHFS1 tSISD1 Data Setup Before Serial Clock Rising Edge 1 tSIHD Data Hold After Serial Clock Rising Edge tIDPCLKW Clock Width tIDPCLK Clock Period 1 88-Lead LFCSP Package Min Max Min All Other Packages Max 4.5 3 4 3 (tPCLK × 4) ÷ 2 – 1 tPCLK × 4 3.8 2.5 2.5 2.5 (tPCLK × 4) ÷ 2 – 1 tPCLK × 4 Unit ns ns ns ns ns ns The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The PCG’s input can be either CLKIN or any of the DAI pins. tIPDCLK SAMPLE EDGE DAI_P20–1 (SCLK) tIPDCLKW tSISFS tSIHFS DAI_P20–1 (FS) tSISD tSIHD DAI_P20–1 (SDATA) Figure 26. IDP Master Timing Rev. B | Page 46 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 PDAP chapter of the ADSP-214xx SHARC Processor Hardware Reference. Note that the 20 bits of external PDAP data can be provided through the ADDR23–0 pins or over the DAI pins. Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 40. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the PDAP, see the Table 40. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements tSPHOLD1 PDAP_HOLD Setup Before PDAP_CLK Sample Edge tHPHOLD1 PDAP_HOLD Hold After PDAP_CLK Sample Edge 1 tPDSD PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge tPDHD1 PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge tPDCLKW Clock Width Clock Period tPDCLK Switching Characteristics tPDHLDD Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word tPDSTRB PDAP Strobe Pulse Width 1 88-Lead LFCSP Package All Other Packages Min Max Min Max Unit 4 4 5 4 (tPCLK × 4) ÷ 2 – 3 tPCLK × 4 2.5 2.5 3.85 2.5 (tPCLK × 4) ÷ 2 – 3 tPCLK × 4 ns ns ns ns ns ns 2 × tPCLK + 3 2 × tPCLK + 3 ns 2 × tPCLK – 1.5 2 × tPCLK – 1.5 ns Source pins of DATA and control are ADDR23–0 or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG. SAMPLE EDGE tPDCLK tPDCLKW DAI_P20–1 (PDAP_CLK) tHPHOLD tSPHOLD DAI_P20–1 (PDAP_HOLD) tPDHD tPDSD DAI_P20–1/ ADDR23–4 (PDAP_DATA) tPDHLDD DAI_P20–1 (PDAP_STROBE) Figure 27. PDAP Timing Rev. B | Page 47 of 76 | March 2012 tPDSTRB ADSP-21477/ADSP-21478/ADSP-21479 Sample Rate Converter—Serial Input Port The ASRC input signals are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table 41 are valid at the DAI_P20–1 pins. Table 41. ASRC, Serial Input Port Parameter Timing Requirements Frame Sync Setup Before Serial Clock Rising Edge tSRCSFS1 tSRCHFS1 Frame Sync Hold After Serial Clock Rising Edge tSRCSD1 Data Setup Before Serial Clock Rising Edge 1 tSRCHD Data Hold After Serial Clock Rising Edge tSRCCLKW Clock Width tSRCCLK Clock Period 1 Min 4 5.5 4 5.5 (tPCLK × 4) ÷ 2 – 1 tPCLK × 4 Max Unit ns ns ns ns ns ns The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE DAI_P20–1 (SCLK) tSRCCLK tSRCCLKW tSRCSFS tSRCHFS DAI_P20–1 (FS) tSRCSD tSRCHD DAI_P20–1 (SDATA) Figure 28. ASRC Serial Input Port Timing Rev. B | Page 48 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 delay specification with regard to serial clock. Note that serial clock rising edge is the sampling edge and the falling edge is the drive edge. Sample Rate Converter—Serial Output Port For the serial output port, the frame sync is an input, and it should meet setup and hold times with regard to the serial clock on the output port. The serial data output has a hold time and Table 42. ASRC, Serial Output Port Parameter Timing Requirements tSRCSFS1 Frame Sync Setup Before Serial Clock Rising Edge tSRCHFS1 Frame Sync Hold After Serial Clock Rising Edge tSRCCLKW Clock Width tSRCCLK Clock Period Switching Characteristics Transmit Data Delay After Serial Clock Falling Edge tSRCTDD1 tSRCTDH1 Transmit Data Hold After Serial Clock Falling Edge 1 88-Lead LFCSP Package Min Max Min 4 5.5 (tPCLK × 4) ÷ 2 – 1 tPCLK × 4 4 5.5 (tPCLK × 4) ÷ 2 – 1 tPCLK × 4 2 × tPCLK 1 All Other Packages Max ns ns ns ns 13 1 Unit ns ns The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSRCCLK tSRCCLKW DAI_P20–1 (SCLK) tSRCSFS tSRCHFS DAI_P20–1 (FS) tSRCTDD tSRCTDH DAI_P20–1 (SDATA) Figure 29. ASRC Serial Output Port Timing Rev. B | Page 49 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 Pulse-Width Modulation Generators (PWM) The following timing specifications apply when the ADDR23–8/DPI_14–1 pins are configured as PWM. Table 43. Pulse-Width Modulation (PWM) Timing Parameter Switching Characteristics tPWMW PWM Output Pulse Width tPWMP PWM Output Period Min 88-Lead LFCSP Package Max tPCLK – 2 2 × tPCLK – 2 (216 – 2) × tPCLK – 2 tPCLK – 2 16 (2 – 1) × tPCLK – 1.5 2 × tPCLK – 1.5 tPWMW PWM OUTPUTS tPWMP Figure 30. PWM Timing Rev. B | Min All Other Packages Max Page 50 of 76 | March 2012 Unit (216 – 2) × tPCLK – 2 ns 16 (2 – 1) × tPCLK – 1.5 ns ADSP-21477/ADSP-21478/ADSP-21479 S/PDIF Transmitter Serial data input to the S/PDIF transmitter can be formatted as left-justified, I2S, or right-justified with word widths of 16, 18, 20, or 24 bits. The following sections provide timing for the transmitter. S/PDIF Transmitter-Serial Input Waveforms Figure 31 shows the right-justified mode. Frame sync is high for the left channel and low for the right channel. Data is valid on the rising edge of serial clock. The MSB is delayed the minimum in 24-bit output mode or the maximum in 16-bit output mode from a frame sync transition, so that when there are 64 serial clock periods per frame sync period, the LSB of the data is rightjustified to the next frame sync transition. Figure 32 shows the default I2S-justified mode. The frame sync is low for the left channel and high for the right channel. Data is valid on the rising edge of serial clock. The MSB is left-justified to the frame sync transition but with a delay. Table 44. S/PDIF Transmitter Right-Justified Mode Parameter Timing Requirement tRJD FS to MSB Delay in Right-Justified Mode 16-Bit Word Mode 18-Bit Word Mode 20-Bit Word Mode 24-Bit Word Mode Nominal Unit 16 14 12 8 SCLK SCLK SCLK SCLK LEFT/RIGHT CHANNEL DAI_P20–1 FS DAI_P20–1 SCLK tRJD DAI_P20–1 SDATA LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB Figure 31. Right-Justified Mode Table 45. S/PDIF Transmitter I2S Mode Parameter Timing Requirement tI2SD FS to MSB Delay in I2S Mode LEFT/RIGHT CHANNEL DAI_P20–1 FS DAI_P20–1 SCLK DAI_P20–1 SDATA tI2SD MSB MSB–1 MSB–2 LSB+2 LSB+1 Figure 32. I 2 S-Justified Mode Rev. B | Page 51 of 76 | March 2012 LSB Nominal Unit 1 SCLK ADSP-21477/ADSP-21478/ADSP-21479 Figure 33 shows the left-justified mode. The frame sync is high for the left channel and low for the right channel. Data is valid on the rising edge of serial clock. The MSB is left-justified to the frame sync transition with no delay. Table 46. S/PDIF Transmitter Left-Justified Mode Parameter Timing Requirement tLJD FS to MSB Delay in Left-Justified Mode DAI_P20–1 FS LEFT/RIGHT CHANNEL DAI_P20–1 SCLK tLJD DAI_P20–1 SDATA MSB MSB–1 MSB–2 LSB+2 LSB+1 Figure 33. Left-Justified Mode Rev. B | Page 52 of 76 | March 2012 LSB Nominal Unit 0 SCLK ADSP-21477/ADSP-21478/ADSP-21479 S/PDIF Transmitter Input Data Timing The timing requirements for the S/PDIF transmitter are given in Table 47. Input signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 47. S/PDIF Transmitter Input Data Timing Parameter Timing Requirements tSISFS1 Frame Sync Setup Before Serial Clock Rising Edge tSIHFS1 Frame Sync Hold After Serial Clock Rising Edge tSISD1 Data Setup Before Serial Clock Rising Edge Data Hold After Serial Clock Rising Edge tSIHD1 tSITXCLKW Transmit Clock Width tSITXCLK Transmit Clock Period tSISCLKW Clock Width tSISCLK Clock Period 1 88-Lead LFCSP Package All Other Packages Min Max Min Max Unit 4.5 3 4.5 3 9 20 36 80 ns ns ns ns ns ns ns ns 3 3 3 3 9 20 36 80 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. tSITXCLKW SAMPLE EDGE tSITXCLK DAI_P20–1 (TxCLK) tSISCLK tSISCLKW DAI_P20–1 (SCLK) tSISFS tSIHFS DAI_P20–1 (FS) tSISD tSIHD DAI_P20–1 (SDATA) Figure 34. S/PDIF Transmitter Input Timing Oversampling Clock (TxCLK) Switching Characteristics The S/PDIF transmitter requires an oversampling clock input. This high frequency clock (TxCLK) input is divided down to generate the internal biphase clock. Table 48. Oversampling Clock (TxCLK) Switching Characteristics Parameter Frequency for TxCLK = 384 × Frame Sync Frequency for TxCLK = 256 × Frame Sync Frame Rate (FS) Max Oversampling Ratio × Frame Sync ≤ 1/tSITXCLK 49.2 192.0 Rev. B | Page 53 of 76 | March 2012 Unit MHz MHz kHz ADSP-21477/ADSP-21478/ADSP-21479 S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 49. S/PDIF Receiver Internal Digital PLL Mode Timing Parameter Switching Characteristics tDFSI tHOFSI tDDTI tHDTI tSCLKIW1 1 Min FS Delay After Serial Clock FS Hold After Serial Clock Transmit Data Delay After Serial Clock Transmit Data Hold After Serial Clock Transmit Serial Clock Width Unit 5 ns ns ns ns ns –2 5 –2 38.5 The serial clock frequency is 64 × frame sync (FS) where FS = the frequency of LRCLK. SAMPLE EDGE DRIVE EDGE tSCLKIW DAI_P20–1 (SCLK) tDFSI tHOFSI DAI_P20–1 (FS) tDDTI tHDTI DAI_P20–1 (DATA CHANNEL A/B) Figure 35. S/PDIF Receiver Internal Digital PLL Mode Timing Rev. B | Max Page 54 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 SPI Interface—Master Both the primary and secondary SPIs are available through DPI only. The timing provided in Table 50 and Table 51 applies to both. Table 50. SPI Interface Protocol—Master Switching and Timing Specifications Parameter Timing Requirements tSSPIDM Data Input Valid to SPICLK Edge (Data Input Setup Time) tHSPIDM SPICLK Last Sampling Edge to Data Input Not Valid Switching Characteristics tSPICLKM Serial Clock Cycle tSPICHM Serial Clock High Period Serial Clock Low Period tSPICLM tDDSPIDM SPICLK Edge to Data Out Valid (Data Out Delay time) tHDSPIDM SPICLK Edge to Data Out Not Valid (Data Out Hold time) tSDSCIM DPI Pin (SPI Device Select) Low to First SPICLK Edge tHDSM Last SPICLK Edge to DPI Pin (SPI Device Select) High tSPITDM Sequential Transfer Delay 88-Lead LFCSP Package All Other Packages Min Max Min Max Unit 10 2 8.6 2 ns ns 8 × tPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 2 8 × tPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 2 ns ns ns 2.5 2.5 4 × tPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 1.4 DPI (OUTPUT) tSDSCIM tSPICHM tSPICLM tSPICLKM SPICLK (CP = 0, CP = 1) (OUTPUT) tHDSM tHDSPIDM tDDSPIDM MOSI (OUTPUT) tSSPIDM tSSPIDM tHSPIDM CPHASE = 1 tHSPIDM MISO (INPUT) tHDSPIDM tDDSPIDM MOSI (OUTPUT) CPHASE = 0 tSSPIDM tHSPIDM MISO (INPUT) Figure 36. SPI Master Timing Rev. B | Page 55 of 76 | March 2012 tSPITDM ns ns ns ns ADSP-21477/ADSP-21478/ADSP-21479 SPI Interface—Slave Table 51. SPI Interface Protocol—Slave Switching and Timing Specifications Parameter Timing Requirements tSPICLKS Serial Clock Cycle tSPICHS Serial Clock High Period tSPICLS Serial Clock Low Period tSDSCO SPIDS Assertion to First SPICLK Edge, CPHASE = 0 or CPHASE = 1 tHDS Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 Data Input Valid to SPICLK Edge (Data Input Setup Time) tSSPIDS tHSPIDS SPICLK Last Sampling Edge to Data Input Not Valid tSDPPW SPIDS Deassertion Pulse Width (CPHASE = 0) Switching Characteristics tDSOE SPIDS Assertion to Data Out Active 1 tDSOE SPIDS Assertion to Data Out Active (SPI2) SPIDS Deassertion to Data High Impedance tDSDHI tDSDHI1 SPIDS Deassertion to Data High Impedance (SPI2) tDDSPIDS SPICLK Edge to Data Out Valid (Data Out Delay Time) tHDSPIDS SPICLK Edge to Data Out Not Valid (Data Out Hold Time) tDSOV SPIDS Assertion to Data Out Valid (CPHASE = 0) 1 88-Lead LFCSP Package All Other Packages Min Max Min Max Unit 4 × tPCLK – 2 2 × tPCLK – 2 2 × tPCLK – 2 2 × tPCLK 2 × tPCLK 2 2 2 × tPCLK ns ns ns ns ns ns ns ns 0 0 0 0 4 × tPCLK – 2 2 × tPCLK – 2 2 × tPCLK – 2 2 × tPCLK 2 × tPCLK 2 2 2 × tPCLK 13 13 2 × tPCLK 2 × tPCLK 13 2 × tPCLK 0 0 0 0 10.25 10.25 13.25 13.25 11.5 2 × tPCLK 5 × tPCLK 5 × tPCLK ns ns ns ns ns ns ns The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the processor hardware reference, “Serial Peripheral Interface Port (SPI)” chapter. SPIDS (INPUT) SPICLK (CP = 0, CP = 1) (INPUT) tSPICHS tSPICLS tSPICLKS tHDS tSDSCO tDSOE tSDPPW tDSDHI tDDSPIDS tDDSPIDS tHDSPIDS MISO (OUTPUT) tSSPIDS tHSPIDS CPHASE = 1 MOSI (INPUT) tHDSPIDS MISO (OUTPUT) tDSOV CPHASE = 0 tSSPIDS MOSI (INPUT) Figure 37. SPI Slave Timing Rev. B | Page 56 of 76 | March 2012 tHSPIDS tDSDHI ADSP-21477/ADSP-21478/ADSP-21479 Media Local Bus All the numbers given are applicable for all speed modes (1024 FS, 512 FS, and 256 FS for 3-pin; 512 FS and 256 FS for 5-pin) unless otherwise specified. Please refer to MediaLB specification document rev 3.0 for more details. Table 52. MLB Interface, 3-Pin Specifications Parameter 3-Pin Characteristics tMLBCLK MLB Clock Period 1024 FS 512 FS 256 FS tMCKL MLBCLK Low Time 1024 FS 512 FS 256 FS tMCKH MLBCLK High Time 1024 FS 512 FS 256 FS tMCKR MLBCLK Rise Time (VIL to VIH) 1024 FS 512 FS/256 FS MLBCLK Fall Time (VIH to VIL) tMCKF 1024 FS 512 FS/256 FS 1 MLBCLK Pulse Width Variation tMPWV 1024 FS 512 FS/256 DAT/SIG Input Setup Time tDSMCF tDHMCF DAT/SIG Input Hold Time tMCFDZ DAT/SIG Output Time to Three-State DAT/SIG Output Data Delay From MLBCLK Rising Edge tMCDRV tMDZH2 Bus Hold Time 1024 FS 512 FS/256 DAT/SIG Pin Load CMLB 1024 FS 512 FS/256 1 2 Min Typ Max 20.3 40 81 Unit ns ns ns 6.1 14 30 ns ns ns 9.3 14 30 ns ns ns 1 1.2 0 1 3 ns ns 1 3 ns ns 0.7 2.0 ns p-p ns p-p 15 8 ns ns ns ns 2 4 ns ns 40 60 pf pf Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (p-p). The board must be designed to ensure that the high impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed. Rev. B | Page 57 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 MLBSIG/ MLBDAT (Rx, Input) VALID tDHMCF tDSMCF tMCKH MLBCLK tMCKR tMCKL tMCKF tMLBCLK tMCFDZ tMCDRV tMDZH MLBSIG/ MLBDAT (Tx, Output) VALID Figure 38. MLB Timing (3-Pin Interface) Table 53. MLB Interface, 5-Pin Specifications Parameter 5-Pin Characteristics tMLBCLK MLB Clock Period 512 FS 256 FS tMCKL MLBCLK Low Time 512 FS 256 FS tMCKH MLBCLK High Time 512 FS 256 FS tMCKR MLBCLK Rise Time (VIL to VIH) tMCKF MLBCLK Fall Time (VIH to VIL) 1 MLBCLK Pulse Width Variation tMPWV tDSMCF2 DAT/SIG Input Setup Time tDHMCF DAT/SIG Input Hold Time tMCDRV DS/DO Output Data Delay From MLBCLK Rising Edge tMCRDL3 DO/SO Low From MLBCLK High 512 FS 256 FS DS/DO Pin Load Cmlb Min Typ Max 40 81 Unit ns ns 15 30 ns ns 15 30 ns ns 6 6 2 8 ns ns ns p-p ns ns ns 10 20 ns ns 40 pf 3 5 1 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (p-p). 2 Gate delays due to OR’ing logic on the pins must be accounted for. 3 When a node is not driving valid data onto the bus, the MLBSO and MLBDO output lines shall remain low. If the output lines can float at anytime, including while in reset, external pull-down resistors are required to keep the outputs from corrupting the MediaLB signal lines when not being driven. Rev. B | Page 58 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 MLBSIG/ MLBDAT (Rx, Input) VALID tDHMCF tDSMCF tMCKH MLBCLK tMCKR tMCKL tMCKF tMLBCLK tMCRDL tMCDRV VALID MLBSO/ MLBDO (Tx, Output) Figure 39. MLB Timing (5-Pin Interface) MLBCLK tMPWV tMPWV Figure 40. MLB 3-Pin and 5-Pin MLBCLK Pulse Width Variation Timing Rev. B | Page 59 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 Shift Register Table 54. Shift Register Parameter Timing Requirements tSSDI SR_SDI Setup Before SR_SCLK Rising Edge tHSDI SR_SDI Hold After SR_SCLK Rising Edge tSSDIDAI1 DAI_P08–01 (SR_SDI) Setup Before DAI_P08–01 (SR_SCLK) Rising Edge tHSDIDAI1 DAI_P08–01 (SR_SDI) Hold After DAI_P08–01 (SR_SCLK) Rising Edge 2 tSSCK2LCK SR_SCLK to SR_LAT Setup tSSCK2LCKDAI1, 2 DAI_P08–01 (SR_SCLK) to DAI_P08–01 (SR_LAT) Setup Removal Time SR_CLR to SR_SCLK tCLRREM2SCK tCLRREM2LCK Removal Time SR_CLR to SR_LAT tCLRW SR_CLR Pulse Width tSCKW SR_SCLK Clock Pulse Width tLCKW SR_LAT Clock Pulse Width fMAX Maximum Clock Frequency SR_SCLK or SR_LAT Switching Characteristics tDSDO13 SR_SDO Hold After SR_SCLK Rising Edge 3 tDSDO2 SR_SDO Max. Delay After SR_SCLK Rising Edge tDSDODAI11, 3 SR_SDO Hold After DAI_P08–01 (SR_SCLK) Rising Edge tDSDODAI21, 3 SR_SDO Max. Delay After DAI_P08–01 (SR_SCLK) Rising Edge 3, 4 tDSDOSP1 SR_SDO Hold After DAI_P20–01 (SR_SCLK) Rising Edge SR_SDO Max. Delay After DAI_P20–01 (SR_SCLK) Rising Edge tDSDOSP23, 4 tDSDOPCG13, 5, 6 SR_SDO Hold After DAI_P20–01 (SR_SCLK) Rising Edge 3, 5, 6 tDSDOPCG2 SR_SDO Max. Delay After DAI_P20–01 (SR_SCLK) Rising Edge tDSDOCLR13 SR_CLR to SR_SDO Min. Delay tDSDOCLR23 SR_CLR to SR_SDO Max. Delay 3 tDLDO1 SR_LDO Hold After SR_LAT Rising Edge tDLDO23 SR_LDO Max. Delay After SR_LAT Rising Edge SR_LDO Hold After DAI_P08–01 (SR_LAT) Rising Edge tDLDODAI13 tDLDODAI23 SR_LDO Max. Delay After DAI_P08–01 (SR_LAT) Rising Edge 3, 4 tDLDOSP1 SR_LDO Hold After DAI_P20–01 (SR_LAT) Rising Edge tDLDOSP23, 4 SR_LDO Max. Delay After DAI_P20–01 (SR_LAT) Rising Edge tDLDOPCG13, 5, 6 SR_LDO Hold After DAI_P20–01 (SR_LAT) Rising Edge 3, 5, 6 tDLDOPCG2 SR_LDO Max. Delay After DAI_P20–01 (SR_LAT) Rising Edge SR_CLR to SR_LDO Min. Delay tDLDOCLR13 tDLDOCLR23 SR_CLR to SR_LDO Max. Delay 1 Min Max 7 2 7 2 2 2 3 × tPCLK – 5 2 × tPCLK – 5 4 × tPCLK – 5 2 × tPCLK – 2 2 × tPCLK – 5 fPCLK ÷ 4 3 13 3 13 –2 5 –2 5 4 13 3 13 3 13 –2 5 –2 5 4 14 Unit ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Any of the DAI_P08–01 pins can be routed to the shift register clock, latch clock and serial data input via the SRU. Both clocks can be connected to the same clock source. If both clocks are connected to same clock source, then data in the 18-stage shift register is always one cycle ahead of latch register data. 3 For setup/hold timing requirements of off-chip shift register interfacing devices. 4 SPORTx serial clock out, frame sync out, and serial data outputs are routed to shift register block internally and are also routed onto DAI_P20–01. 5 PCG serial clock output is routed to SPORT and shift register block internally and are also routed onto DAI_P20–01. The SPORTs generate SR_LAT and SDI internally. 6 PCG Serial clock and frame sync outputs are routed to SPORT and shift register block internally and are also routed onto DAI_P20–01. The SPORTs generate SDI internally. 2 Rev. B | Page 60 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 tSSDI,tSSDIDAI DAI_P08-01 OR SR_SCLK tHSDI,tHSDIDAI DAI_P08-01 OR SR_SDI SR_SDO Figure 41. SR_SDI Setup, Hold SR_SCLK OR DAI_P08-01 OR DAI_P20-01(SPx_CLK_O) OR DAI_P20-01(PCG_CLKx_O) tDSDO2 tDSDO1 SR_SDO THE TIMING PARAMETERS SHOWN FOR tDSDO1 AND tDSDO2 ARE VALID FOR tDSDODAI1, tDSDOSP1, tDSDOPCG1, tDSDODAI2, tDSDOSP2, AND tDSDOPCG2 Figure 42. SR_ SDO Delay SR_LAT OR DAI_P08-01 OR DAI_P20-01 (SPx_FS_O) OR DAI_P20-01 (PCG_FSx_O) tDLDO1 tDLDO2 SR_LDO THE TIMING PARAMETERS SHOWN FOR tDLDO1 AND tDLDO2 ARE ALSO VALID FOR tDLDODAI1, tDLDODAI2, tDLDOSP1, tDLDOSP2, tDLDOPCG1, AND tDLDOPCG2. Figure 43. SR_LDO Delay Rev. B | Page 61 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 SR_SCLK OR DAI_P08-01 tSSCK2LCK tSSCK2LCKDAI SR_LAT OR DAI_P08-01 SR_SDI OR DAI_P08-01 SR_LDO Figure 44. SR_SCLK to SR_LAT Setup, Clocks Pulse Width and Maximum Frequency tCLRW SR_CLR tCLRREM2SCK SR_SDCLK OR DAI_P08-01 tCLRREM2LCK SR_LAT OR DAI_P08-01 tDSDOCLR2 tDSDOCLR1 SR_SDO tDLDOCLR2 tDLDOCLR1 SR_LDO Figure 45. Shift Register Reset Timing Rev. B | Page 62 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing For information on the UART port receive and transmit operations, see the ADSP-214xx SHARC Hardware Reference Manual. 2-Wire Interface (TWI)—Receive and Transmit Timing For information on the TWI receive and transmit operations, see the ADSP-214xx SHARC Hardware Reference Manual. JTAG Test Access Port and Emulation Table 55. JTAG Test Access Port and Emulation Parameter Timing Requirements tTCK TCK Period tSTAP TDI, TMS Setup Before TCK High tHTAP TDI, TMS Hold After TCK High tSSYS1 System Inputs Setup Before TCK High tHSYS1 System Inputs Hold After TCK High TRST Pulse Width tTRSTW Switching Characteristics tDTDO TDO Delay from TCK Low 2 tDSYS System Outputs Delay After TCK Low 88-Lead LFCSP Package Min Max All Other Packages Min Max Unit 20 5 6 7 18 4 × tCK 20 5 6 7 18 4 × tCK ns ns ns ns ns ns 11.5 tCK ÷ 2 + 7 1 10.5 tCK ÷ 2 + 7 ns ns System Inputs = DATA15–0, CLK_CFG1–0, RESET, BOOT_CFG1–0, DAI_Px, DPI_Px, FLAG3–0, MLBCLK, MLBDAT, MLBSIG, SR_SCLK, SR_CLR, SR_SDI, and SR_LAT. 2 System Outputs = DAI_Px, DPI_Px, ADDR23–0, AMI_RD, AMI_WR, FLAG3–0, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, SDCLK, MLBDAT, MLBSIG, MLBDO, MLBSO, SR_SDO, SR_LDO, and EMU. tTCK TCK tSTAP tHTAP TMS TDI tDTDO TDO tSSYS tHSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS Figure 46. IEEE 1149.1 JTAG Test Access Port Rev. B | Page 63 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 OUTPUT DRIVE CURRENTS TESTER PIN ELECTRONICS Table 56 shows the driver types and the pins associated with each driver. Figure 47 shows typical I-V characteristics for each driver. The curves represent the current drive capability of the output drivers as a function of output voltage. 50: VLOAD T1 70: Table 56. Driver Types B Associated Pins FLAG[0–3], AMI_ADDR[23–0], DATA[15–0], AMI_RD, AMI_WR, AMI_ACK, MS[1-0], SDRAS, SDCAS, SDWE, SDDQM, SDCKE, SDA10, EMU, TDO, RESETOUT, DPI[1–14], DAI[1–20], WDTRSTO, MLBDAT, MLBSIG, MLBSO, MLBDO, MLBCLK, SR_CLR, SR_LAT, SR_LDO[17–0], SR_SCLK, SR_SDI SDCLK, RTCLKOUT 0.5pF 2pF 400: NOTES: THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES. Figure 48. Equivalent Device Loading for AC Measurements (Includes All Fixtures) 200 SOURCE/SINK (VDDEXT) CURRENT (mA) ZO = 50:(impedance) TD = 4.04 r 1.18 ns 50: 4pF Driver Type A DUT OUTPUT 45: 150 VOH 3.13 V, 125 °C TYPE B 100 INPUT 1.5V OR OUTPUT TYPE A 50 0 1.5V Figure 49. Voltage Reference Levels for AC Measurements TYPE A -50 CAPACITIVE LOADING -100 TYPE B Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 48). Figure 52 shows graphically how output delays and holds vary with load capacitance. The graphs of Figure 50, Figure 51, and Figure 52 may not be linear outside the ranges shown for Typical Output Delay vs. Load Capacitance and Typical Output Rise Time (20% to 80%, V = Min) vs. Load Capacitance. -150 VOL 3.13 V, 125 °C -200 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 SWEEP (VDDEXT) VOLTAGE (V) Figure 47. Typical Drive at Junction Temperature TEST CONDITIONS 7 Timing is measured on signals when they cross the 1.5 V level as described in Figure 49. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and the point that the second signal reaches 1.5 V. 6 RISE AND FALL TIMES (ns) The ac signal specifications (timing parameters) appear in Table 21 on Page 28 through Table 55 on Page 63. These include output disable time, output enable time, and capacitive loading. The timing specifications for the SHARC apply for the voltage reference levels in Figure 48. TYPE A DRIVE FALL y = 0.0421x + 0.2418 TYPE A DRIVE RISE y = 0.0331x + 0.2662 5 TYPE B DRIVE FALL y = 0.0206x + 0.2271 4 3 TYPE B DRIVE RISE y = 0.0184x + 0.3065 2 1 0 0 25 50 75 100 125 150 175 LOAD CAPACITANCE (pF) Figure 50. Typical Output Rise/Fall Time (20% to 80%, VDD_EXT = Max) Rev. B | Page 64 of 76 | March 2012 200 ADSP-21477/ADSP-21478/ADSP-21479 where: 14 TJ = junction temperature (°C) TYPE A DRIVE FALL y = 0.0748x + 0.4601 RISE AND FALL TIMES (ns) 12 TCASE = case temperature (°C) measured at the top center of the package TYPE A DRIVE RISE y = 0.0567x + 0.482 10 TYPE B DRIVE FALL y = 0.0367x + 0.4502 8 PD = power dissipation Values of θJA are provided for package comparison and PCB design considerations. θJA can be used for a first order approximation of TJ by the equation: 6 TYPE B DRIVE RISE y = 0.0314x + 0.5729 4 ΨJT = junction-to-top (of package) characterization parameter is the typical value from Table 58 T J = T A + ( θ JA × P D ) 2 0 0 25 50 75 100 125 150 175 200 TA = ambient temperature °C LOAD CAPACITANCE (pF) Values of θJC are provided for package comparison and PCB design considerations when an external heatsink is required. Figure 51. Typical Output Rise/Fall Time (20% to 80%, VDD_EXT = Min) Note that the thermal characteristics values provided in Table 58 are modeled values. 4.5 RISE AND FALL DELAY (ns) Table 57. Thermal Characteristics for 88-Lead LFCSP_VQ TYPE A DRIVE FALL y = 0.0199x + 1.1083 4 Parameter θJA θJMA θJMA θJC ΨJT ΨJMT ΨJMT TYPE A DRIVE RISE y = 0.015x + 1.4889 3.5 TYPE B DRIVE RISE y = 0.0088x + 1.6008 3 2.5 TYPE B DRIVE FALL y = 0.0102x + 1.2726 2 1.5 1 Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 22.6 18.2 17.3 7.9 0.22 0.36 0.44 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W Table 58. Thermal Characteristics for 100-Lead LQFP_EP 0.5 0 where: 0 25 50 75 100 125 150 175 200 LOAD CAPACITANCE (pF) Figure 52. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) THERMAL CHARACTERISTICS The processor is rated for performance over the temperature range specified in Operating Conditions on Page 20. Table 58 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to-board measurement complies with JESD51-8. Test board design complies with JEDEC standards JESD51-7 (PBGA). The junction-to-case measurement complies with MIL- STD-883. All measurements use a 2S2P JEDEC test board. To determine the junction temperature of the device while on the application PCB, use: T J = T CASE + ( Ψ JT × P D ) Rev. B | Parameter θJA θJMA θJMA θJC ΨJT ΨJMT ΨJMT Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 18.1 15.5 14.6 2.4 0.22 0.36 0.50 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W Table 59. Thermal Characteristics for 196-Ball CSP_BGA Parameter θJA θJMA θJMA θJC ΨJT ΨJMT ΨJMT Page 65 of 76 | March 2012 Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 29.0 26.1 25.1 8.8 0.23 0.42 0.52 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W ADSP-21477/ADSP-21478/ADSP-21479 Thermal Diode where: The processors incorporate thermal diode/s to monitor the die temperature. The thermal diode is a grounded collector, PNP bipolar junction transistor (BJT). The THD_P pin is connected to the emitter, and the THD_M pin is connected to the base of the transistor. These pins can be used by an external temperature sensor (such as ADM1021A or LM86 or others) to read the die temperature of the chip. n = multiplication factor close to 1, depending on process variations The technique used by the external temperature sensor is to measure the change in VBE when the thermal diode is operated at two different currents. This is shown in the following equation: The two currents are usually in the range of 10 μA to 300 μA for the common temperature sensor chips available. k = Boltzmann constant T = temperature (°C) q = charge of the electron N = ratio of the two currents Table 60 contains the thermal diode specifications using the transistor model. kT ΔV BE = n × ------ × In(N) q Table 60. Thermal Diode Parameters—Transistor Model1 Symbol IFW2 IE nQ3, 4 RT3, 5 Parameter Forward Bias Current Emitter Current Transistor Ideality Series Resistance Min 10 10 1.012 0.12 Typ 1.015 0.2 1 Max 300 300 1.017 0.28 Unit μA μA Ω Analog Devices does not recommend operation of the thermal diode under reverse bias. Analog Devices does not recommend operation of the thermal diode under reverse bias. 3 Specified by design characterization. 4 The ideality factor, nQ, represents the deviation from ideal diode behavior as exemplified by the diode equation: IC = IS × (e qVBE/nqkT – 1) where IS = saturation current, q = electronic charge, VBE = voltage across the diode, k = Boltzmann constant, and T = absolute temperature (Kelvin). 5 The series resistance (RT) can be used for more accurate readings as needed. 2 Rev. B | Page 66 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 88-LFCSP_VQ LEAD ASSIGNMENT Table 62 lists the 88-Lead LFCSP_VQ package lead names. Table 61. 88-Lead LFCSP_VQ Lead Assignments (Numerical by Lead Number) Lead Name CLK_CFG_1 BOOTCFG_0 VDD_EXT VDD_INT BOOTCFG_1 GND CLK_CFG_0 VDD_INT CLKIN XTAL2 VDD_EXT VDD_INT VDD_INT RESETOUT/RUNRSTIN VDD_INT DPI_P01 DPI_P02 DPI_P03 VDD_INT DPI_P05 DPI_P04 DPI_P06 Lead No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Lead Name VDD_EXT DPI_P08 DPI_P07 DPI_P09 DPI_P10 DPI_P11 DPI_P12 DPI_P13 DAI_P03 DPI_P14 VDD_INT DAI_P13 DAI_P07 DAI_P19 DAI_P01 DAI_P02 VDD_INT VDD_EXT VDD_INT DAI_P06 DAI_P05 DAI_P09 Lead No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Lead Name Lead No. VDD_INT 67 FLAG0 68 VDD_INT 69 FLAG1 70 FLAG2 71 FLAG3 72 GND 73 GND 74 VDD_EXT 75 GND 76 VDD_INT 77 TRST 78 EMU 79 TDO 80 VDD_EXT 81 VDD_INT 82 TDI 83 TCK 84 VDD_INT 85 RESET 86 TMS 87 VDD_INT 88 GND 89* * Lead no. 89 is the GND supply (see Figure 55 and Figure 56) for the processor; this pad must be robustly connect to GND in order for the processor to function. Rev. B | Page 67 of 76 | Lead Name DAI_P10 VDD_INT VDD_EXT DAI_P20 VDD_INT DAI_P08 DAI_P04 DAI_P14 DAI_P18 DAI_P17 DAI_P16 DAI_P15 DAI_P12 DAI_P11 VDD_INT GND THD_M THD_P VDD_THD VDD_INT VDD_INT VDD_INT March 2012 Lead No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 ADSP-21477/ADSP-21478/ADSP-21479 Figure 55 shows the top view of the 88-lead LFCSP_VQ pin configuration. Figure 56 shows the bottom view. PIN 88 PIN 67 PIN 1 PIN 66 PIN 1 INDICATOR ADSP-2147x 88-LEAD LFCSP_VQ TOP VIEW PIN 22 PIN 45 PIN 23 PIN 44 Figure 53. 88-Lead LFCSP_VQ Lead Configuration (Top View) PIN 67 PIN 88 PIN 66 PIN 1 ADSP-2147x 88-LEAD LFCSP_VQ BOTTOM VIEW GND PAD (PIN 89) PIN 1 INDICATOR PIN 45 PIN 22 PIN 44 PIN 23 Figure 54. 88-Lead LFCSP_VQ Lead Configuration (Bottom View) Rev. B | Page 68 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 100-LQFP_EP LEAD ASSIGNMENT Table 62 lists the 100-Lead LQFP_EP lead names. Table 62. 100-Lead LQFP_EP Lead Assignments (Numerical by Lead Number) Lead Name VDD_INT CLK_CFG1 BOOT_CFG0 VDD_EXT VDD_INT BOOT_CFG1 GND NC NC CLK_CFG0 VDD_INT CLKIN XTAL VDD_EXT VDD_INT VDD_INT RESETOUT/RUNRSTIN VDD_INT DPI_P01 DPI_P02 DPI_P03 VDD_INT DPI_P05 DPI_P04 DPI_P06 Lead No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Lead Name VDD_EXT DPI_P08 DPI_P07 VDD_INT DPI_P09 DPI_P10 DPI_P11 DPI_P12 DPI_P13 DAI_P03 DPI_P14 VDD_INT VDD_INT VDD_INT DAI_P13 DAI_P07 DAI_P19 DAI_P01 DAI_P02 VDD_INT VDD_EXT VDD_INT DAI_P06 DAI_P05 DAI_P09 Lead No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Lead Name Lead No. VDD_INT 76 FLAG0 77 VDD_INT 78 VDD_INT 79 FLAG1 80 FLAG2 81 FLAG3 82 MLBCLK 83 MLBDAT 84 MLBDO 85 VDD_EXT 86 MLBSIG 87 VDD_INT 88 MLBSO 89 TRST 90 EMU 91 TDO 92 VDD_EXT 93 VDD_INT 94 TDI 95 TCK 96 VDD_INT 97 RESET 98 TMS 99 VDD_INT 100 GND 101* * Lead no. 101 is the GND supply (see Figure 55 and Figure 56) for the processor; this pad must be robustly connected to GND. MLB pins (pins 83, 84, 85, 87, and 89) are available for automotive models only. For non-automotive models, these pins should be connected to ground (GND). Rev. B | Page 69 of 76 | Lead Name DAI_P10 VDD_INT VDD_EXT DAI_P20 VDD_INT DAI_P08 DAI_P04 DAI_P14 DAI_P18 DAI_P17 DAI_P16 DAI_P15 DAI_P12 VDD_INT DAI_P11 VDD_INT VDD_INT GND THD_M THD_P VDD_THD VDD_INT VDD_INT VDD_INT VDD_INT March 2012 Lead No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 ADSP-21477/ADSP-21478/ADSP-21479 Figure 55 shows the top view configuration of the 100-lead LQFP_EP package. Figure 56 shows the bottom view configuration of the 100-lead LQFP_EP package. LEAD 100 LEAD 76 LEAD 1 LEAD 75 LEAD 1 INDICATOR ADSP-2147x 100-LEAD LQFP_EP TOP VIEW LEAD 25 LEAD 51 LEAD 26 LEAD 50 Figure 55. 100-Lead LQFP_EP Lead Configuration (Top View) LEAD 76 LEAD 100 LEAD 75 LEAD 1 ADSP-2147x 100-LEAD LQFP_EP BOTTOM VIEW GND PAD (LEAD 101) LEAD 1 INDICATOR LEAD 51 LEAD 25 LEAD 50 LEAD 26 Figure 56. 100-Lead LQFP_EP Lead Configuration (Bottom View) Rev. B | Page 70 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 196-BGA BALL ASSIGNMENT Table 63. 196-Ball CSP_BGA Ball Assignment (Numerical by Ball No.) Ball No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 Signal GND SDCKE SDDQM SDRAS SDWE DATA12 DATA13 DATA10 DATA9 DATA7 DATA3 DATA1 DATA2 GND ADDR0 CLK_CFG1 BOOT_CFG0 TMS RESET DATA14 DATA11 DATA4 DATA8 DATA6 DATA5 TRST FLAG1 DATA0 ADDR2 ADDR3 RTCLKOUT MS0 SDCAS DATA15 TCK TDI SDCLK EMU TDO FLAG3 ADDR16 WDT_CLKIN Ball No. Signal D1 ADDR6 D2 ADDR4 D3 ADDR1 D4 CLK_CFG0 D5 VDD_EXT D6 VDD_EXT D7 VDD_EXT D8 VDD_EXT D9 VDD_EXT D10 VDD_EXT D11 VDD_EXT D12 ADDR14 D13 ADDR20 D14 WDT_CLKO E1 ADDR8 E2 ADDR7 E3 ADDR5 E4 VDD_EXT E5 VDD_INT E6 VDD_INT E7 VDD_INT E8 VDD_INT E9 VDD_INT E10 VDD_INT E11 VDD_EXT E12 AMI_RD E13 ADDR22 E14 FLAG2 F1 CLKIN F2 ADDR9 F3 BOOT_CFG1 F4 NC F5 NC F6 GND F7 GND F8 GND F9 GND F10 VDD_INT F11 VDD_EXT F12 ADDR15 F13 FLAG0 F14 AMI_WR Ball No. Signal G1 XTAL G2 SDA10 G3 ADDR11 G4 GND G5 VDD_INT G6 GND G7 GND G8 GND G9 GND G10 VDD_INT G11 VDD_EXT G12 ADDR21 G13 ADDR19 G14 RTXO H1 ADDR13 H2 ADDR12 H3 ADDR10 H4 ADDR17 H5 VDD_INT H6 GND H7 GND H8 GND H9 GND H10 VDD_INT H11 VDD_EXT H12 BOOT_CFG2 H13 ADDR23 H14 RTXI J1 DPI_P01 J2 DPI_P03 J3 ADDR18 J4 RESETOUT/RUNRSTIN J5 VDD_INT J6 GND J7 GND J8 GND J9 GND J10 VSS_RTC J11 VDD_RTC J12 DAI_P11 J13 AMI_ACK J14 MS1 Rev. B | Page 71 of 76 | March 2012 Ball No. K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 Signal DPI_P02 DPI_P04 DPI_P05 DPI_P09 VDD_INT GND GND GND GND VDD_INT GND DAI_P16 DAI_P18 DAI_P15 DAI_P03 DPI_P10 DPI_P08 DPI_P06 VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT DAI_P10 DAI_P20 DAI_P17 DAI_P04 DPI_P13 DPI_P12 SR_LDO0 DPI_P07 DPI_P11 SR_LDO5 SR_LDO7 DAI_P07 SR_LDO16 SR_SDO DAI_P06 DAI_P05 DAI_P08 DAI_P12 Ball No. N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 Signal DPI_P14 SR_LDO1 SR_LDO4 SR_LDO8 SR_LDO10 DAI_P01 SR_LDO9 DAI_P02 SR_LDO13 SR_SCLK DAI_P09 SR_SDI SR_LDO17 DAI_P14 GND SR_LDO3 SR_LDO2 SR_LDO6 WDTRSTO DAI_P19 DAI_P13 SR_LDO11 SR_LDO15 SR_CLR SR_LAT SR_LDO14 SR_LDO12 GND ADSP-21477/ADSP-21478/ADSP-21479 OUTLINE DIMENSIONS The processors are available in 88-lead LFCSP_VQ, 100-lead LQFP_EP and 196-ball CSP_BGA RoHS compliant packages. For package assignment by model, see Ordering Guide on Page 75. 12.10 12.00 SQ 11.90 0.60 MAX 0.60 MAX 88 67 66 PIN 1 INDICATOR 1 PIN 1 INDICATOR 12.10 12.00 SQ 11.90 0.50 BSC 0.50 0.40 0.30 45 44 SEATING PLANE 0.70 0.65 0.60 12° MAX 23 0.30 0.23 0.18 10.50 REF 0.045 0.025 0.005 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.139~0.194 REF Figure 57. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ1] (CP-88-5) Dimensions Shown in Millimeters 1 22 BOTTOM VIEW TOP VIEW 0.85 0.80 0.75 6.70 REF SQ EXPOSED PAD For information relating to the exposed pad on the CP-88-5 package, see the table endnote on Page 67. Rev. B | Page 72 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 0.75 0.60 0.45 16.20 16.00 SQ 15.80 1.60 MAX 14.20 14.00 SQ 13.80 100 76 1 SEATING PLANE 76 75 100 1 75 PIN 1 EXPOSED PAD 1.45 1.40 1.35 0.20 0.15 0.09 0.15 0.10 0.05 0.08 COPLANARITY 7° 3.5° 0° TOP VIEW BOTTOM VIEW (PINS DOWN) 25 51 26 26 50 0.27 0.22 0.17 0.50 BSC LEAD PITCH ROTATED 90° CCW (PINS UP) 51 50 VIEW A VIEW A 6.00 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE LEAD ASSIGNMENT AND PIN FUNCTION DESCRIPTIONS SECTIONS OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MS-026-BED-HD Figure 58. 100-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP1] (SW-100-2) Dimensions shown in millimeters 1 For information relating to the exposed pad on the SW-100-2 package, see the table endnote on Page 69. A1 BALL CORNER 12.10 12.00 SQ 11.90 A B C D E F G H J K L M N P 10.40 BSC SQ 0.80 BSC 1.50 1.41 1.32 A1 BALL CORNER 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0.80 REF TOP VIEW BOTTOM VIEW DETAIL A 0.70 REF DETAIL A 0.50 COPLANARITY 0.45 0.12 0.40 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1. Figure 59. 196-Ball Chip Scale Package, Ball Grid Array [CSP_BGA] (BC-196-8) Dimensions shown in millimeters Rev. B | Page 73 of 76 | 1.13 1.06 0.99 0.35 NOM 0.30 MIN 0.36 REF SEATING PLANE 25 March 2012 ADSP-21477/ADSP-21478/ADSP-21479 SURFACE-MOUNT DESIGN AUTOMOTIVE PRODUCTS For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. The ADSP-21477, ADSP-21478, and ADSP-21479 are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models, and designers should review the product Specifications section of this data sheet carefully. Only the automotive grade products shown in Table 64 are available for use in automotive applications. Contact your local ADI account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Table 64. Automotive Product Models Model1 Temperature Range2 On-Chip SRAM Processor Instruction Rate (Max) Package Description Package Option AD21477WYCPZ1xx –40°C to +105°C 2M bits 200 MHz 88-Lead LFCSP_VQ CP-88-5 AD21477WYSWZ1Axx –40°C to +105°C 2M bits 200 MHz 100-Lead LQFP_EP SW-100-2 AD21478WYCPZ1xx –40°C to +105°C 3M bits 200 MHz 88-Lead LFCSP_VQ CP-88-5 AD21478WYSWZ2Axx –40°C to +105°C 3M bits 266 MHz 100-Lead LQFP_EP SW-100-2 AD21478WYSWZ2Bxx –40°C to +105°C 3M bits 266 MHz 100-Lead LQFP_EP SW-100-2 AD21479WYCPZ1xx –40°C to +105°C 5M bits 200 MHz 88-Lead LFCSP_VQ CP-88-5 AD21479WYCPZ1Bxx –40°C to +105°C 5M bits 200MHz 88-Lead LFCSP_VQ CP-88-5 AD21479WYSWZ2Axx –40°C to +105°C 5M bits 266 MHz 100-Lead LQFP_EP SW-100-2 AD21479WYSWZ2Bxx –40°C to +105°C 5M bits 266 MHz 100-Lead LQFP_EP SW-100-2 1 Notes 3, 4 3, 4 3, 4 Z = RoHS compliant part. Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 20 for junction temperature (TJ) specification, which is the only temperature specification. 3 Contains multichannel audio decoders from Dolby and DTS. 4 Contains Digital Transmission Content Protection (DTCP) from DTLA. User must have current license from DTLA to order this product. 2 Rev. B | Page 74 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 ORDERING GUIDE Model1 ADSP-21477KCPZ-1A ADSP-21477KSWZ-1A ADSP-21477BCPZ-1A ADSP-21478KCPZ-1A ADSP-21478BCPZ-1A ADSP-21478BBCZ-2A ADSP-21478BSWZ-2A ADSP-21478KBCZ-1A ADSP-21478KBCZ-2A ADSP-21478KBCZ-3A ADSP-21478KSWZ-1A ADSP-21478KSWZ-2A ADSP-21479KCPZ-1A ADSP-21479BCPZ-1A ADSP-21479BBCZ-2A ADSP-21479BSWZ-2A ADSP-21479KBCZ-1A ADSP-21479KBCZ-2A ADSP-21479KBCZ-3A ADSP-21479KSWZ-1A ADSP-21479KSWZ-2A Temperature Range2 0°C to +70°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C On-Chip SRAM 2M Bits 2M Bits 2M Bits 3M Bits 3M Bits 3M Bits 3M Bits 3M Bits 3M Bits 3M Bits 3M Bits 3M Bits 5M Bits 5M Bits 5M Bits 5M Bits 5M Bits 5M Bits 5M Bits 5M Bits 5M Bits Processor Instruction Rate (Max) 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 266 MHz 266 MHz 200 MHz 266 MHz 300 MHz 200 MHz 266 MHz 200 MHz 200 MHz 266 MHz 266 MHz 200 MHz 266 MHz 300 MHz 200 MHz 266 MHz 1 Package Description 88-Lead LFCSP_VQ 100-Lead LQFP_EP 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ 196-Ball CSP_BGA 100-Lead LQFP_EP 196-Ball CSP_BGA 196-Ball CSP_BGA 196-Ball CSP_BGA 100-Lead LQFP_EP 100-Lead LQFP_EP 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ 196-Ball CSP_BGA 100-Lead LQFP_EP 196-Ball CSP_BGA 196-Ball CSP_BGA 196-Ball CSP_BGA 100-Lead LQFP_EP 100-Lead LQFP_EP Package Option CP-88-5 SW-100-2 CP-88-5 CP-88-5 CP-88-5 BC-196-8 SW-100-2 BC-196-8 BC-196-8 BC-196-8 SW-100-2 SW-100-2 CP-88-5 CP-88-5 BC-196-8 SW-100-2 BC-196-8 BC-196-8 BC-196-8 SW-100-2 SW-100-2 Z =RoHS compliant part. Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 20 for junction temperature (TJ) specification, which is the only temperature specification. 2 Rev. B | Page 75 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09017-0-3/12(B) Rev. B | Page 76 of 76 | March 2012