AK8181C Preliminary 3.3V LVPECL 1:2 Clock Fanout Buffer AK8181C Features Description The AK8181C is a member of AKM’ｓ LVPECL clock fanout buffer family designed for telecom, networking and computer applications, requiring a range of clocks with high performance and low skew. The AK8181C distributes 2 buffered clocks. Two differential 3.3V LVPECL outputs Selectable two LVTTL/LVCMOS inputs Clock output frequency up to 266MHz Output skew : 20ps maximum Part-to-part skew : 200ps maximum Propagation delay : 1.4ns maximum Additive phase jitter(RMS) : 0.03ps(typical) Operating Temperature Range: -40 to +85℃ Package: 14-pin TSSOP (Pb free) Pin compatible with ICS8535I-21 AK8181C are derived from AKM’ｓ long-termexperienced clock device technology, and enable clock output to perform low skew. The AK8181C is available in a 14-pin TSSOP package. Block Diagram draft-E-01 Feb-2013 -1- AK8181C Pin Descriptions Package: 14-Pin TSSOP(Top View) Pin No. 1 2 Pin Name VSS Pin Type PWR CLK_EN IN Pullup down --- Pull up Description Negative power supply Synchronizing clock output enable (LVCMOS/LVTTL) Pin is connected to VDD by internal resistor. (typ. 51kΩ) High (Open): clock outputs follow clock input. Low: Q outputs are forced low, Qn outputs are forced high. CLK Select Input (LVCMOS/LVTTL) 3 CLK_SEL IN Pull down Pin is connected to VSS by internal resistor. (typ. 51kΩ) High: selects CLK1 input Low (Open): selects CLK0 input LVCMOS/LVTTL Clock Input 4 CLK0 IN Pull down Pin is connected to VSS by internal resistor. (typ. 51kΩ) *When using CLK1 input (CLK_SEL=High),it should be connected to VSS or opened. 5 VSS PWR --- Negative power supply LVCMOS/LVTTL Clock Input Pin is connected to VSS by internal resistor. (typ. 51kΩ) 6 CLK1 IN Pill down 7 VDD PWR --- Positive power supply 8 VDD PWR --- Positive power supply 9,10 Q1n, Q1 OUT --- Differential clock output (LVPECL) 11 NC --- --- No connect 12, 13 Q0n, Q0 OUT --- Differential clock output (LVPECL) 14 VDD PWR --- Positive power supply *When using CLK0 input (CLK_SEL=Low), it should be connected to VSS or opened. PWR: Power pin, IN: Input pin, OUT: Output pin Feb-2013 draft-E-01 -2- AK8181C Absolute Maximum Rating Over operating free-air temperature range unless otherwise noted Items Supply voltage Input voltage (2) (2) Symbol Ratings Unit VDD -0.3 to 4.6 V Vin -0.5 to VDD+0.5 V IIN ±10 mA Tstg -55 to 150 C Input current (any pins except supplies) Storage temperature (1) Note (1) Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rating conditions for extended periods may affect device reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. (2) VSS=0V ESD Sensitive Device This device is manufactured on a CMOS process, therefore, generically susceptible to damage by excessive static voltage. Failure to observe proper handling and installation procedures can cause damage. AKM recommends that this device is handled with appropriate precautions. Recommended Operation Conditions Parameter Operating temperature Supply voltage (1) Symbol Conditions Ta VDD Min Typ -40 VDD5%, VSS=0V 3.135 3.3 Max Unit 85 C 3.465 V (1) Power of 3.3V requires to be supplied from a single source. A decoupling capacitor of 0.1μF for power supply line should be located close to each VDD pin. Pin Characteristics Parameter Symbol Conditions Min Typ Max Unit Input Capacitance CIN 4 pF Input Pullup Resistor RPU 51 kΩ Input Pulldown Resistor RPD 51 kΩ draft-E-01 Feb-2013 -3- AK8181C DC Characteristics All specifications at VDD= 3.3V5%, VSS=0V, Ta: -40 to +85°C, unless otherwise noted Parameter Symbol Input High Voltage VIH CLK0, CLK1 Input Low Voltage CLK_EN, CLK_SEL VIL CLK0, CLK1, CLK_SEL Input High Current CLK_EN IH IL CLK_EN Output High Voltage Output Low Voltage MAX Unit 2.0 VDD+0.3 V -0.3 1.3 V -0.3 0.8 V Vin=VDD=3.465V 150 μA Vin=VDD=3.465V 5 μA Vin=VSS, CLK0, CLK1, CLK_SEL Input Low Current Conditions VDD=3.465V Vin=VSS, VDD=3.465V (1) MIN TYP -5 μA -150 μA VOH VDD-1.4 VDD-0.9 V VOL VDD-2.0 VDD-1.7 V VSWING 0.6 1.0 V 50 mA MAX Unit 266 MHz 1.4 ns tsk(O) 20 ps tskPP 200 ps (1) Peak-to-Peak Output Voltage Swing Supply Current IDD (1) Outputs terminated with 50Ω to VDD-2V. AC Characteristics All specifications at VDD= 3.3V5%, VSS=0V, Ta: -40 to +85°C, unless otherwise noted Parameter Symbol Output Frequency Propagation Delay (1) tPD (2)(3) (3)(5) Part-to-Part Skew Buffer Additive Jitter, RMS tjit Output Rise/Fall Time (1) (2) (3) (4) (5) MIN TYP fOUT Output Skew Output Duty Cycle Conditions (4) tr , tf 0.6 12kHz to [email protected] 20% to 80% 0.03 200 DCOUT 48 50 ps 600 ps 52 % Measured from the VDD/2 of the input to the differential output crossing point. Defined as skew between outputs at the same supply voltage and with equal load conditions. This parameter is defined in accordance with JEDEC Standard 65. Design value. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. Feb-2013 draft-E-01 -4- AK8181C Parameter Measurement Information 2.0V Zo = 50W Qx Part 1 Qxn SCOPE Qx 50W Zo = 50W Part 2 Qyn Qxn 50W Qy -1.3V ± 0.165V tsk(pp) Figure 1 3.3V Output Load Test Circuit Figure 2 Part-to-Part Skew Qxn 80% Clock Outputs Qx Qyn 80% VSWING 20% 20% tR tF Qy tsk(o) Figure 3 Output Skew Figure 4 Output Rise/Fall Time Figure 5 Propagation Delay Figure 6 Output Duty/ Pulse Width/ Period draft-E-01 Feb-2013 -5- AK8181C Function Table The following table shows the inputs/outputs clock state configured through the control pins. Table 1: Control Input Function Table Inputs Outputs CLK_EN CLK_SEL Selected Source Q0, Q1 Q0n, Q1n 0 0 (Open) CLK0 Disabled: Low Disabled: High 0 1 CLK1 Disabled: Low Disabled: High 1 (Open) 0 (Open) CLK0 Enabled Enabled 1 (Open) 1 CLK1 Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 7. In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 2. Disabled Enabled CLK0, CLK1 CLK_EN Q0n : Q3n Q0 : Q3 Figure 7 CLK_EN Timing Diagram Table 2 Clock Input Function Table Inputs Outputs CLK0 or CLK1 Q0, Q1 Q0n, Q1n 0 Low High 1 High Low Feb-2013 draft-E-01 -6- AK8181C Package Information Mechanical data : 14pin TSSOP Preliminary Marking 14 b 8 AK8181C XXXXXXX c a: b: c: #1 Pin Index Part number Date code ( 7 digits) a 1 7 RoHS Compliance All integrated circuits form Asahi Kasei Microdevices Corporation (AKM) assembled in “lead-free” packages* are fully compliant with RoHS. (*) RoHS compliant products from AKM are identified with “Pb free” letter indication on product label posted on the anti-shield bag and boxes. draft-E-01 Feb-2013 -7- AK8181C IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. Feb-2013 draft-E-01 -8-