Fairchild DM74ALS137N 3 to 8 line decoder/demultiplexer with address latch Datasheet

Revised February 2000
DM74ALS137
3 to 8 Line Decoder/Demultiplexer with Address Latches
General Description
Features
The ALS137 is a three line to eight line decoder/demultiplexer with latches on the three address inputs. When the
latch-enable input (GL) is LOW, the ALS137 acts as a
decoder/demultiplexer. When GL goes from LOW-to-HIGH,
the address present at the select inputs (A, B, and C) is
stored in the latches. Further address changes are ignored
as long as GL remains HIGH. The output enable controls,
G1 and G2, control the state of the outputs independently
of the select or latch-enable inputs. All of the outputs are
HIGH unless G1 is HIGH and G2 is LOW. The ALS137 is
ideally suited for implementing glitch-free decoders in
strobed (stored-address) applications in bus-oriented systems.
■ Combines decoder and 3-bit address latch
■ Incorporates 3 enable inputs to simplify cascading
■ Low power dissipation:
28 mW typ
■ Switching specifications guaranteed over full temperature and VCC range
■ Advanced oxide-isolated, ion-implanted Schottky TTL
process
Ordering Code:
Order Number
Package Number
Package Description
DM74ALS137M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS137N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Enable
Outputs
Select
GL G1 G2 C
B
A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X
X
H
X
X
X
H
H
H
H
H
H
H
H
X
L
X
X
X
X
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
H
H
H
H
H
H
H
L
H
L
L
L
H
H
L
H
H
H
H
H
H
L
H
L
L
H
L
H
H
L
H
H
H
H
H
L
H
L
L
H
H
H
H
H
L
H
H
H
H
L
H
L
H
L
L
H
H
H
H
L
H
H
H
L
H
L
H
L
H
H
H
H
H
H
L
H
H
L
H
L
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
X
X
X Output corresponding to stored
address, L; all others, H
L = LOW State
H = HIGH State
X = Don't Care
© 2000 Fairchild Semiconductor Corporation
DS006202
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DM74ALS137 3 to 8 Line Decoder/Demultiplexer with Address Latches
February 1991
DM74ALS137
Logic Diagram
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2
Supply Voltage
7V
Input Voltage
7V
0°C to +70°C
Operating Free Air Temperature Range
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
−65°C to +150°C
Storage Temperature Range
Typical θJA
N Package
75.5°C/W
M Package
104.0°C/W
Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
4.5
5
5.5
Units
VCC
Supply Voltage
VIH
HIGH Level Input Voltage
V
VIL
LOW Level Input Voltage
0.8
V
IOH
HIGH Level Output Current
−0.4
mA
IOL
LOW Level Output Current
8
mA
tW
Width of Enabling Pulse
GL LOW
10
ns
tSU
Setup Time (Note 2)
A, B, C
10↑
ns
tH
Hold Time (Note 2)
A, B, C
5↑
TA
Free Air Operating Temperature
2
V
ns
0
°C
70
Note 2: The arrow (↑) indicates the positive edge of the GL input pulse is used for reference.
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C.
Symbol
Parameter
Conditions
VIK
Input Clamp Voltage
VCC = 4.5V, II = −18 mA
VOH
HIGH Level
IOH = −0.4 mA
Output Voltage
VCC = 4.5V to 5.5V
LOW Level
VCC = 4.5V
VOL
Min
Typ
Max
Units
−1.5
V
VCC − 2
Output Voltage
V
IOL = 4 mA
0.25
0.4
IOL = 8 mA
0.35
0.5
II
Input Current @ Maximum
VCC = 5.5V
Enable
0.1
Input Voltage
VIH = 7V
A, B, C
0.1
IIH
HIGH Level
VCC = 5.5V
Enable
20
Input Current
VIH = 2.7V
A, B, C
20
IIL
LOW Level
VCC = 5.5V
Enable
−0.1
Input Current
VIL = 0.4V
A, B, C
−0.1
IO
Output Drive Current
VCC = 5.5V, VO = 2.25V
ICC
Supply Current
VCC = 5.5V
−30
5
3
V
V
mA
µA
mA
−112
mA
11
mA
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DM74ALS137
Absolute Maximum Ratings(Note 1)
DM74ALS137
Switching Characteristics
over recommended operating free air temperature range.
Symbol
tPLH
tPHL
Parameter
Conditions
tPHL
tPLH
tPHL
tPLH
tPHL
To (Output)
Propagation Delay Time
VCC = 4.5V to 5.5V
LOW-to-HIGH Level Output
RL = 500Ω
to Y
Propagation Delay Time
CL = 50 pF
A, B, C
Max
Units
5
20
ns
6
20
ns
4
12
ns
5
15
ns
5
17
ns
5
15
ns
7
22
ns
7
20
ns
to Y
Propagation Delay Time
G2
LOW-to-HIGH Level Output
to Y
Propagation Delay Time
G2
HIGH-to-LOW Level Output
to Y
Propagation Delay Time
G1
LOW-to-HIGH Level Output
to Y
Propagation Delay Time
G1
HIGH-to-LOW Level Output
to Y
Propagation Delay Time
GL
LOW-to-HIGH Level Output
to Y
Propagation Delay Time
GL
HIGH-to-LOW Level Output
to Y
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Min
A, B, C
HIGH-to-LOW Level Output
tPLH
From (Input)
4
DM74ALS137
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
5
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DM74ALS137 3 to 8 Line Decoder/Demultiplexer with Address Latches
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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