Intel EE80C196KC20 Commercial/express chmos microcontroller Datasheet

8XC196KC/8XC196KC20
COMMERCIAL/EXPRESS CHMOS
MICROCONTROLLER
Y
Y
87C196KCÐ16 Kbytes of On-Chip OTPROM
83C196KCÐ16 Kbytes ROM
80C196KCÐROMless
Y Dynamically Configurable 8-Bit or
16 and 20 MHz Available
16-Bit Buswidth
488 Byte Register RAM
Register-to-Register Architecture
Y
Full Duplex Serial Port
28 Interrupt Sources/16 Vectors
Y
High Speed I/O Subsystem
Peripheral Transaction Server
Y
16-Bit Timer
Y
1.4 ms 16 x 16 Multiply (20 MHz)
Y
16-Bit Up/Down Counter with Capture
2.4 ms 32/16 Divide (20 MHz)
Y
Y
3 Pulse-Width-Modulated Outputs
Y
Powerdown and Idle Modes
Y
Four 16-Bit Software Timers
Five 8-Bit I/O Ports
Y
Y
Y
16-Bit Watchdog Timer
8- or 10-Bit A/D Converter with
Sample/Hold
Y
Extended Temperature Available
HOLD/HLDA Bus Protocol
Y
Y
OTPROM One-Time Programmable
Version
Y
Y
Y
The 80C196KC 16-bit microcontroller is a high performance member of the MCSÉ 96 microcontroller family.
The 80C196KC is an enhanced 80C196KB device with 488 bytes RAM, 16 and 20 MHz operation and an
optional 16 Kbytes of ROM/OTPROM. Intel’s CHMOS III process provides a high performance processor
along with low power consumption.
The 87C196KC is an 80C196KC with 16 Kbytes on-chip OTPROM. The 83C196KC is an 80C196KC with 16
Kbytes factory programmed ROM. In this document, the 80C196KC will refer to all products unless otherwise
stated.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an A/D conversion. Events can be based on the timer or up/down counter.
With the commercial (standard) temperature option, operational characteristics are guaranteed over the temperature range of 0§ C to a 70§ C. With the extended (Express) temperature range option, operational characteristics are guaranteed over the temperature range of b 40§ C to a 85§ C. Unless otherwise noted, the specifications are the same for both options.
See the Packaging information for extended temperature designators.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT © INTEL CORPORATION, 1995
November 1994
Order Number: 270942-005
8XC196KC/8XC196KC20
270942 – 1
Figure 1. 8XC196KC Block Diagram
IOC3 (0CH HWIN1 READ/WRITE)
270942 – 45
NOTE:
*RSVÐReserved bits must be e 0
Figure 2. 8XC196KC New SFR Bit (CLKOUT Disable)
2
8XC196KC/8XC196KC20
Table 2. 8XC196KC Memory Map
PROCESS INFORMATION
This device is manufactured on PX29.5 or PX29.9, a
CHMOS III process. Additional process and reliability information is available in the Intel® Quality
System Handbook:
http://developer.intel.com/design/quality/quality.htm
270942 – 43
EXAMPLE: N87C196KC is 68-Lead PLCC OTPROM,
16 MHz.
For complete package dimensional data, refer to the
Intel Packaging Handbook (Order Number 240800).
NOTE:
1. EPROMs are available as One Time Programmable
(OTPROM) only.
Figure 3. The 8XC196KC Family Nomenclature
Description
External Memory or I/O
ija
ijc
PLCC
35§ C/W
13§ C/W
QFP
55§ C/W
16§ C/W
SQFP
TBD
TBD
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel Packaging Handbook (order number 240800) for a
description of Intel’s thermal impedance test methodology.
0FFFFH
06000H
Internal ROM/OTPROM or External
Memory (Determined by EA)
5FFFH
2080H
Reserved. Must contain FFH.
(Note 5)
207FH
205EH
PTS Vectors
205DH
2040H
Upper Interrupt Vectors
203FH
2030H
ROM/OTPROM Security Key
202FH
2020H
Reserved. Must contain FFH.
(Note 5)
201FH
201AH
Reserved. Must Contain 20H
(Note 5)
2019H
CCB
2018H
Reserved. Must contain FFH.
(Note 5)
2017H
2014H
Lower Interrupt Vectors
2013H
2000H
Port 3 and Port 4
1FFFH
1FFEH
External Memory
1FFDH
0200H
488 Bytes Register RAM (Note 1)
01FFH
0018H
CPU SFR’s (Notes 1, 3, 4)
0017H
0000H
Table 1. Thermal Characteristics
Package
Type
Address
NOTES:
1. Code executed in locations 0000H to 01FFH will be
forced external.
2. Reserved memory locations must contain 0FFH unless
noted.
3. Reserved SFR bit locations must contain 0.
4. Refer to 8XC196KC User’s manual for SFR descriptions.
5. WARNING: Reserved memory locations must not be
written or read. The contents and/or function of these locations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
3
8XC196KC/8XC196KC20
270942 – 2
Figure 4. 68-Lead PLCC Package
4
8XC196KC/8XC196KC20
270942 – 40
Figure 5. S8XC196KC 80-Pin QFP Package
5
8XC196KC/8XC196KC20
270942 – 44
Figure 6. 80-Pin SQFP Package
6
8XC196KC/8XC196KC20
PIN DESCRIPTIONS
Symbol
Name and Function
VCC
Main supply voltage (5V).
VSS
VREF
Digital circuit ground (0V). There are multiple VSS pins, all of which must be connected.
Reference voltage for the A/D converter (5V). VREF is also the supply voltage to the analog
portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D
and Port 0 to function.
ANGND
Reference ground for the A/D converter. Must be held at nominally the same potential as
VSS.
VPP
XTAL1
Timing pin for the return from powerdown circuit. This pin also supplies the programming
voltage on the EPROM device.
Input of the oscillator inverter and of the internal clock generator.
XTAL2
Output of the oscillator inverter.
CLKOUT
Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator
frequency.
RESET
BUSWIDTH
Reset input and open drain output.
Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an
8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.
NMI
INST
A positive transition causes a vector through 203EH.
Output high during an external memory read indicates the read is an instruction fetch. INST
is valid throughout the bus cycle. INST is activated only during external memory accesses
and output low for a data fetch.
EA
Input for memory select (External Access). EA equal high causes memory accesses to
locations 2000H through 5FFFH to be directed to on-chip ROM/EPROM. EA equal to low
causes accesses to those locations to be directed to off-chip memory. Also used to enter
programming mode.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by CCR. Both pin options
provide a signal to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during
external memory accesses.
RD
Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL
Write and Write Low output to external memory, as selected by the CCR. WR will go low for
every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL is activated only during external memory writes.
Bus High Enable or Write High output to external memory, as selected by the CCR. BHE will
go low for external writes to the high byte of the data bus. WRH will go low for external
writes where an odd byte is being written. BHE/WRH is activated only during external
memory writes.
Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,
or for bus sharing. When the external memory is not being used, READY has no effect.
BHE/WRH
READY
HSI
HSO
Port 0
Port 1
Port 2
Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2,
HSI.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
8-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter.
8-bit quasi-bidirectional I/O port.
8-bit multi-functional port. All of its pins are shared with other functions in the 80C196KC.
Pins 2.6 and 2.7 are quasi-bidirectional.
7
8XC196KC/8XC196KC20
PIN DESCRIPTIONS (Continued)
Symbol
Ports 3 and 4
HOLD
HLDA
BREQ
PMODE
PACT
CPVER
Bus Hold acknowledge output indicating release of the bus.
Bus Request output activated when the bus controller has a pending external memory
cycle.
Determines the EPROM programming mode.
A low signal in Auto Programming mode indicates that programming is in process. A high
signal indicates programming is complete.
Cummulative Program Output Verification. Pin is high if all locations have programmed
correctly since entering a programming mode.
PALE
A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode
indicates that ports 3 and 4 contain valid programming address/command information
(input to slave).
PROG
A falling edge in Slave Programming Mode indicates that ports 3 and 4 contain valid
programming data (input to slave).
A high signal in Slave Programmig Mode and Auto Configuration Byte Programming Mode
indicates the byte programmed correctly.
PVER
AINC
8
Name and Function
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups.
Bus Hold input requesting control of the bus.
Auto Increment. Active low input signal indicates that the auto increment mode is enabled.
Auto Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write.
8XC196KC/8XC196KC20
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
Ambient Temperature
Under Bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 55§ C to a 125§ C
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65§ C to a 150§ C
Voltage On Any Pin to VSSÀÀÀÀÀÀ b 0.5V to a 7.0V(1)
Voltage from EA or
VPP to VSS or ANGNDÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ a 13.00V
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W(2)
NOTE:
1. This includes VPP and EA on ROM or CPU only devices.
2. Power dissipation is based on package heat transfer limitations, not device power consumption.
OPERATING CONDITIONS
Symbol
TA
Description
Min
Max
Units
Ambient Temperature Under Bias Commercial Temp.
0
a 70
§C
a 85
§C
5.50
V
TA
Ambient Temperature Under Bias Extended Temp.
b 40
VCC
Digital Supply Voltage
4.50
VREF
Analog Supply Voltage
4.00
5.50
V
ANGND
Analog Ground Voltage
VSS b 0.4
VSS a 0.4
V(1)
FOSC
Oscillator Frequency (8XC196KC)
8
16
MHz
FOSC
Oscillator Frequency (8XC196KC20)
8
20
MHz
NOTE:
1. ANGND and VSS should be nominally at the same potential.
DC CHARACTERISTICS
Symbol
(Over Specified Operating Conditions)
Description
VIL
Input Low Voltage
VIH
Input High Voltage (Note 1)
Max
Units
b 0.5
Min
Typ
0.8
V
0.2 VCC a 1.0
VCC a 0.5
V
V
V
VIH1
Input High Voltage on XTAL 1
0.7 VCC
VCC a 0.5
VIH2
Input High Voltage on RESET
2.2
VCC a 0.5
VHYS
Hysteresis on RESET
300
VOL
Output Low Voltage
VOL1
Output Low Voltage
in RESET on P2.5 (Note 2)
VOH
Output High Voltage
(Standard Outputs)
VCC b 0.3
VCC b 0.7
VCC b 1.5
mV
Test Conditions
VCC e 5.0V
0.3
0.45
1.5
V
V
V
IOL e 200 mA
IOL e 2.8 mA
IOL e 7 mA
0.8
V
IOL e a 0.4 mA
V
V
V
IOH e b 200 mA
IOH e b 3.2 mA
IOH e b 7 mA
9
8XC196KC/8XC196KC20
DC CHARACTERISTICS
Symbol
(Over Specified Operating Conditions) (Continued)
Description
Min
Typ
Max
Units
Test Conditions
VCC b 0.3
VCC b 0.7
VCC b 1.5
VOH1
Output High Voltage
(Quasi-bidirectional Outputs)
V
V
V
IOH1
Logical 1 Output Current in Reset.
on P2.0. Do not exceed this
or device may enter test modes.
b 0.8
mA
VIH e VCC b 1.5V
IIL2
Logical 0 Input Current in Reset
on P2.0. Maximum current that
must be sunk by external
device to ensure test mode entry.
TBD
mA
VIN e 0.45V
IIH1
Logical 1 Input Current.
Maximum current that external
device must source to initiate NMI.
a 200
mA
VIN e VCC e 2.4V
ILI
Input Leakage Current (Std. Inputs)
g 10
mA
0 k VIN k VCC b 0.3V
ILI1
Input Leakage Current (Port 0)
g3
mA
ITL
1 to 0 Transition Current (QBD Pins)
b 650
mA
0 k VIN k VREF
VIN e 2.0V
IIL
Logical 0 Input Current (QBD Pins)
b 70
mA
VIN e 0.45V
IIL1
Ports 3 and 4 in Reset
b 70
mA
VIN e 0.45V
ICC
Active Mode Current in Reset
(8XC196KC)
65
75
mA
XTAL1 e 16 MHz
VCC e VPP e VREF e 5.5V
ICC
Active Mode Current in Reset
(8XC196KC20)
80
92
mA
XTAL1 e 20 MHz
VCC e VPP e VREF e 5.5V
IIDLE
Idle Mode Current (8XC196KC)
17
25
mA
XTAL1 e 16 MHz
VCC e VPP e VREF e 5.5V
IIDLE
Idle Mode Current (8XC196KC20)
21
30
mA
XTAL1 e 20 MHz
VCC e VPP e VREF e 5.5V
IPD
Powerdown Mode Current
8
15
mA
IREF
A/D Converter Reference Current
5
mA
VCC e VPP e VREF e 5.5V
VCC e VPP e VREF e 5.5V
RRST
Reset Pullup Resistor
CS
Pin Capacitance (Any Pin to VSS)
2
6K
65K
X
10
pF
IOH e b 10 mA
IOH e b 30 mA
IOH e b 60 mA
VCC e 5.5V, VIN e 4.0V
NOTES:
1. All pins except RESET and XTAL1.
2. Violating these specifications in Reset may cause the part to enter test modes.
3. Commercial specifications apply to express parts except where noted.
4. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7.
5. Standard Outputs include AD0–15, RD, WR, ALE, BHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4,
TXD/P2.0 and RXD (in serial mode 0). The VOH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
6. Standard Inputs include HSI pins, READY, BUSWIDTH, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3 and T2RST/P2.4.
7. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held
below VCC b 0.7V:
IOL on Output pins: 10 mA
IOH on quasi-bidirectional pins: self limiting
IOH on Standard Output pins: 10 mA
8. Maximum current per bus pin (data and control) during normal operation is g 3.2 mA.
9. During normal (non-transient) conditions the following total current limits apply:
IOH is self limiting
Port 1, P2.6
IOL: 29 mA
IOH: 26 mA
HSO, P2.0, RXD, RESET IOL: 29 mA
IOL: 13 mA
IOH: 11 mA
P2.5, P2.7, WR, BHE
IOH: 52 mA
AD0 – AD15
IOL: 52 mA
IOH: 13 mA
RD, ALE, INST–CLKOUT IOL: 13 mA
10
8XC196KC/8XC196KC20
270942 – 17
ICC Max e 4.13 c Frequency a 9 mA
ICC Typ e 3.50 c Frequency a 9 mA
IIDLE Max e 1.25 c Frequency a 5 mA
IIDLE Typ e 0.88 c Frequency a 3 mA
NOTE:
Frequencies below 8 MHz are shown for reference only; no testing is performed.
Figure 7. ICC and IIDLE vs Frequency
AC CHARACTERISTICS
For use over specified operating conditions.
Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 16 MHz
The system must meet these specifications to work with the 80C196KC:
Symbol
Description
Min
Max
2 TOSC b 68
Units
Notes
TAVYV
Address Valid to READY Setup
TYLYH
Non READY Time
TCLYX
READY Hold after CLKOUT Low
TLLYX
READY Hold after ALE Low
TAVGV
Address Valid to Buswidth Setup
TCLGX
Buswidth Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
3 TOSC b 55
ns
(Note 2)
TRLDV
RD Active to Input Data Valid
TOSC b 22
ns
(Note 2)
TCLDV
CLKOUT Low to Input Data Valid
TOSC b 45
ns
TRHDZ
End of RD to Input Data Float
TOSC
ns
TRXDX
Data Hold after RD Inactive
No upper limit
ns
ns
0
TOSC b 30
ns
(Note 1)
TOSC b 15
2 TOSC b 40
ns
(Note 1)
2 TOSC b 68
0
0
ns
ns
ns
NOTES:
1. If max is exceeded, additional wait states will occur.
2. If wait states are used, add 2 TOSC * N, where N e number of wait states.
11
8XC196KC/8XC196KC20
AC CHARACTERISTICS
(Continued)
For user over specified operating conditions.
Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 16 MHz
The 80C196KC will meet these specifications:
Symbol
Description
Min
Max
Units
Notes
FXTAL
Frequency on XTAL1 (8XC196KC)
8
16
MHz
(Note 1)
FXTAL
Frequency on XTAL1 (8XC196KC20)
8
20
MHz
(Note 1)
TOSC
I/FXTAL (8XC196KC)
62.5
125
ns
TOSC
I/FXTAL (8XC196KC20)
50
125
ns
TXHCH
XTAL1 High to CLKOUT High or Low
a 110
ns
TCLCL
CLKOUT Cycle Time
a 20
2 TOSC
ns
TCHCL
CLKOUT High Period
TCLLH
CLKOUT Falling Edge to ALE Rising
b5
a 15
TLLCH
ALE Falling Edge to CLKOUT Rising
b 20
a 15
TLHLH
ALE Cycle Time
4 TOSC
TLHLL
ALE High Period
TOSC b 10
TAVLL
Address Setup to ALE Falling Edge
TOSC b 15
TLLAX
Address Hold after ALE Falling Edge
TOSC b 35
TLLRL
ALE Falling Edge to RD Falling Edge
TOSC b 30
TRLCL
RD Low to CLKOUT Falling Edge
TRLRH
RD Low Period
TRHLH
RD Rising Edge to ALE Rising Edge
TRLAZ
RD Low to Address Float
TLLWL
ALE Falling Edge to WR Falling Edge
TCLWL
CLKOUT Low to WR Falling Edge
TOSC b 10
TOSC a 15
ns
ns
a4
TOSC a 10
ns
ns
a 30
ns
ns
(Note 4)
TOSC a 25
ns
(Note 2)
a5
ns
TOSC b 10
0
ns
a 25
ns
a 15
ns
TOSC b 23
TQVWH
Data Stable to WR Rising Edge
TCHWH
CLKOUT High to WR Rising Edge
TWLWH
WR Low Period
TOSC b 20
ns
TWHQX
Data Hold after WR Rising Edge
TOSC b 25
ns
TWHLH
WR Rising Edge to ALE Rising Edge
TOSC b 10
TWHBX
BHE, INST after WR Rising Edge
TOSC b 10
ns
TWHAX
AD8–15 HOLD after WR Rising
TOSC b 30
ns
TRHBX
BHE, INST after RD Rising Edge
TOSC b 10
ns
TRHAX
AD8–15 HOLD after RD Rising
TOSC b 25
ns
b5
(Note 4)
TOSC a 15
ns
NOTES:
1. Testing performed at 8 MHz. However, the device is static by design and will typically operate below 1 Hz.
2. Assuming back-to-back bus cycles.
3. 8-Bit bus only.
4. If wait states are used, add 2 TOSC * N, where N e number of wait states.
12
(Note 4)
ns
TOSC b 5
TOSC
ns
ns
(Note 4)
(Note 2)
(Note 3)
(Note 3)
8XC196KC/8XC196KC20
System Bus Timings
270942 – 18
13
8XC196KC/8XC196KC20
READY Timings (One Wait State)
270942 – 20
Buswidth Timings
270942 – 35
14
8XC196KC/8XC196KC20
HOLD/HLDA Timings
Symbol
Description
Min
Max
Units
Notes
ns
(Note 1)
THVCH
HOLD Setup
a 55
TCLHAL
CLKOUT Low to HLDA Low
b 15
a 15
ns
TCLBRL
CLKOUT Low to BREQ Low
b 15
a 15
ns
THALAZ
HLDA Low to Address Float
a 15
ns
THALBZ
HLDA Low to BHE, INST, RD, WR Weakly Driven
a 20
ns
TCLHAH
CLKOUT Low to HLDA High
b 15
a 15
ns
TCLBRH
CLKOUT Low to BREQ High
b 15
a 15
THAHAX
HLDA High to Address No Longer Float
b 15
THAHBV
HLDA High to BHE, INST, RD, WR Valid
b 10
a 15
ns
TCLLH
CLKOUT Low to ALE High
b5
a 15
ns
ns
ns
NOTE:
1. To guarantee recognition at next clock.
DC SPECIFICATIONS IN HOLD
Description
Min
Max
Units
Weak Pullups on ADV, RD,
WR, WRL, BHE
50K
250K
VCC e 5.5V, VIN e 0.45V
Weak Pulldowns on
ALE, INST
10K
50K
VCC e 5.5V, VIN e 2.4
15
8XC196KC/8XC196KC20
270942 – 36
Maximum Hold Latency
Bus Cycle Type
Internal Execution
1.5 States
16-Bit External Execution
2.5 States
8-Bit External Execution
4.5 States
EXTERNAL CLOCK DRIVE (8XC196KC)
16
Symbol
Parameter
Min
Max
Units
1/TXLXL
Oscillator Frequency
TXLXL
Oscillator Period
8
16.0
MHz
62.5
125
ns
TXHXX
High Time
20
ns
TXLXX
Low Time
20
ns
TXLXH
Rise Time
10
ns
TXHXL
Fall Time
10
ns
8XC196KC/8XC196KC20
EXTERNAL CLOCK DRIVE (8XC196KC20)
Symbol
Parameter
Min
Max
Units
1/TXLXL
TXLXL
Oscillator Frequency
8
20.0
MHz
Oscillator Period
50
125
ns
TXHXX
High Time
17
ns
TXLXX
Low Time
17
ns
TXLXH
Rise Time
8
ns
TXHXL
Fall Time
8
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
270942 – 21
EXTERNAL CRYSTAL CONNECTIONS
EXTERNAL CLOCK CONNECTIONS
270942 – 41
NOTE:
Keep oscillator components close to chip and use
short, direct traces to XTAL1, XTAL2 and VSS. When
using crystals, C1 e C2 & 20 pF. When using ceramic
resonators, consult manufacturer for recommended circuitry.
AC TESTING INPUT, OUTPUT WAVEFORMS
270942 – 22
AC Testing inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45V for
a Logic ‘‘0’’ Timing measurements are made at 2.0V for a Logic
‘‘1’’ and 0.8V for a Logic ‘‘0’’.
270942 – 42
NOTE:
*Required if TTL driver used.
Not needed if CMOS driver is used.
FLOAT WAVEFORMS
270942 – 23
For Timing Purposes a Port Pin is no Longer Floating when a
150 mV change from Load Voltage Occurs and Begins to Float
when a 150 mV change from the Loaded VOH/VOL Level occurs;
IOL/IOH e g 15 mA.
17
8XC196KC/8XC196KC20
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by ‘‘T’’ for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
Signals:
LÐ
HÐ High
LÐ Low
AÐ
BÐ
Address
BHE
BRÐ BREQ
ALE/ADV
VÐ
Valid
CÐ
CLKOUT
WÐ WR/WRH/WRL
XÐ
ZÐ
No Longer Valid
Floating
DÐ DATA
GÐ Buswidth
RÐ RD
XÐ
XTAL1
YÐ READY
QÐ Data Out
HÐ HOLD
HAÐ HLDA
AC CHARACTERISTICSÐSERIAL PORTÐSHIFT REGISTER MODE
SERIAL PORT TIMINGÐSHIFT REGISTER MODE (MODE 0)
Symbol
Parameter
TXLXL
Serial Port Clock Period (BRR t 8002H)
TXLXH
Serial Port Clock Falling Edge
to Rising Edge (BRR t 8002H)
TXLXL
Serial Port Clock Period (BRR e 8001H)
Min
Serial Port Clock Falling Edge
to Rising Edge (BRR e 8001H)
TQVXH
Output Data Setup to Clock Rising Edge
2 TOSC b 50
TXHQX
Output Data Hold after Clock Rising Edge
2 TOSC b 50
Next Output Data Valid after Clock Rising Edge
Input Data Setup to Clock Rising Edge
TXHDX
Input Data Hold after Clock Rising Edge
TXHQZ
Last Clock Rising to Output Float
4 TOSC a 50
ns
ns
4 TOSC
TXLXH
TDVXH
Units
6 TOSC
4 TOSC b 50
2 TOSC b 50
TXHQV
Max
ns
2 TOSC a 50
ns
ns
ns
2 TOSC a 50
TOSC a 50
ns
ns
0
ns
1 TOSC
ns
WAVEFORMÐSERIAL PORTÐSHIFT REGISTER MODE
SERIAL PORT WAVEFORMÐSHIFT REGISTER MODE (MODE 0)
270942 – 24
18
8XC196KC/8XC196KC20
A to D CHARACTERISTICS
The A/D converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of VREF.
10-BIT MODE A/D OPERATING CONDITIONS
Symbol
TA
Description
Min
Max
Units
Ambient Temperature Commercial Temp.
0
a 70
a 85
§C
§C
V
TA
Ambient Temperature Extended Temp.
b 40
VCC
Digital Supply Voltage
4.50
5.50
VREF
Analog Supply Voltage
4.00
5.50
TSAM
Sample Time
1.0
TCONV
Conversion Time
10
20
ms(1)
FOSC
Oscillator Frequency (8XC196KC)
8.0
16.0
MHz
FOSC
Oscillator Frequency (8XC196KC20)
8.0
20.0
MHz
V
ms(1)
NOTE:
ANGND and VSS should nominally be at the same potential, 0.00V.
1. The value of ADÐTIME is selected to meet these specifications.
10-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions)
Parameter
Typical(1)
Resolution
Absolute Error
Full Scale Error
0.25 g 0.5
Zero Offset Error
0.25 g 0.5
Non-Linearity
1.0 g 2.0
Differential Non-Linearity Error
Channel-to-Channel Matching
g 0.1
Minimum
Maximum
Units*
1024
10
1024
10
Levels
Bits
0
g3
LSBs
LSBs
LSBs
0
g3
LSBs
l b1
a2
LSBs
0
g1
LSBs
Repeatability
g 0.25
LSBs
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.009
0.009
0.009
LSB/§ C
LSB/§ C
LSB/§ C
Off Isolation
b 60
Feedthrough
b 60
VCC Power Supply Rejection
b 60
Input Series Resistance
Voltage on Analog Input Pin
DC Input Leakage
Sampling Capacitor
3
Notes
dB
1, 2
dB
1
dB
1
X
4
VREF a 0.5
V
5, 6
g 3.0
mA
750
1.2K
ANGND b 0.5
0
pF
NOTES:
*An ‘‘LSB’’ as used here has a value of approxiimately 5 mV. (See Embedded Microcontrollers and Processors Handbook
for A/D glossary of terms).
1. These values are expected for most parts at 25§ C but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer Break-Before-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. These values may be exceeded if the pin current is limited to g 2 mA.
6. Applying voltages beyond these specifications will degrade the accuracy of all channels being converted.
7. All conversions performed with processor in IDLE mode.
19
8XC196KC/8XC196KC20
8-BIT MODE A/D OPERATING CONDITIONS
Symbol
TA
Description
Min
Max
Units
Ambient Temperature Commercial Temp.
0
a 70
a 85
§C
§C
V
TA
Ambient Temperature Extended Temp.
b 40
VCC
Digital Supply Voltage
4.50
5.50
VREF
Analog Supply Voltage
4.00
5.50
TSAM
Sample Time
1.0
TCONV
Conversion Time
FOSC
FOSC
V
ms(1)
7
20
ms(1)
Oscillator Frequency (8XC196KC)
8.0
16.0
MHz
Oscillator Frequency (8XC196KC20)
8.0
20.0
MHz
NOTE:
ANGND and VSS should nominally be at the same potential, 0.00V.
1. The value of ADÐTIME is selected to meet these specifications.
8-BIT MODE A/D CHARACTERISTICS
Parameter
Typical
Resolution
Absolute Error
Full Scale Error
g 0.5
Zero Offset Error
g 0.5
Non-Linearity
Differential Non-Linearity Error
(Over Specified Operating Conditions)
Minimum
Maximum
Units*
256
8
256
8
Levels
Bits
0
g1
LSBs
LSBs
LSBs
0
g1
LSBs
l b1
a1
LSBs
g1
LSBs
Channel-to-Channel Matching
Repeatability
g 0.25
LSBs
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.003
0.003
0.003
LSB/§ C
LSB/§ C
LSB/§ C
Off Isolation
Notes
dB
2, 3
Feedthrough
b 60
b 60
dB
2
VCC Power Supply Rejection
b 60
dB
2
Input Series Resistance
750
Voltage on Analog Input Pin
DC Input Leakage
Sampling Capacitor
3
1.2K
VREF a 0.5
Xs
4
VSS b 0.5
V
5, 6
0
g 3.0
mA
pF
NOTES:
*An ‘‘LSB’’ as used here has a value of approximately 20 mV. (See Embedded Microcontrollers and Processors Handbook
for A/D glossary of terms).
1. These values are expected for most parts at 25§ C but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer Break-Before-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. These values may be exceeded if pin current is limited to g 2 mA.
6. Applying voltages beyond these specifications will degrade the accuracy of all channels being converted.
7. All conversions performed with processor in IDLE mode.
20
8XC196KC/8XC196KC20
EPROM SPECIFICATIONS
OPERATING CONDITIONS DURING PROGRAMMING
Symbol
Description
Min
Max
Units
TA
Ambient Temperature During Programming
20
30
C
VCC
Supply Voltage During Programming
4.5
5.5
V(1)
VREF
Reference Supply Voltage During Programming
4.5
5.5
V(1)
VPP
Programming Voltage
12.25
12.75
V(2)
VEA
EA Pin Voltage
12.25
12.75
V(2)
FOSC
Oscillator Frequency During Auto and Slave
Mode Programming
6.0
8.0
MHz
FOSC
Oscillator Frequency During
Run-Time Programming (8XC196KC)
6.0
16.0
MHz
FOSC
Oscillator Frequency During
Run-Time Programming (8XC196KC20)
6.0
20.0
MHz
NOTES:
1. VCC and VREF should nominally be at the same voltage during programming.
2. VPP and VEA must never exceed the maximum specification, or the device may be damaged.
3. VSS and ANGND should nominally be at the same potential (0V).
4. Load capacitance during Auto and Slave Mode programming e 150 pF.
AC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Description
Min
Max
1100
Units
TSHLL
Reset High to First PALE Low
TOSC
TLLLH
PALE Pulse Width
50
TOSC
TAVLL
Address Setup Time
0
TOSC
TLLAX
Address Hold Time
100
TPLDV
PROG Low to Word Dump Valid
TPHDX
Word Dump Data Hold
TDVPL
Data Setup Time
0
TOSC
TPLDX
Data Hold Time
400
TOSC
TPLPH(1)
PROG Pulse Width
50
TOSC
TPHLL
PROG High to Next PALE Low
220
TOSC
TLHPL
PALE High to PROG Low
220
TOSC
TPHPL
PROG High to Next PROG Low
220
TOSC
TPHIL
PROG High to AINC Low
TILIH
AINC Pulse Width
TILVH
TILPL
TPHVL
PROG High to PVER Valid
TOSC
50
50
TOSC
TOSC
0
TOSC
240
TOSC
PVER Hold after AINC Low
50
TOSC
AINC Low to PROG Low
170
TOSC
220
TOSC
NOTE:
1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm. See
user’s manual for further information.
21
8XC196KC/8XC196KC20
DC EPROM PROGRAMMING CHARACTERISTICS
Symbol
IPP
Description
Min
VPP Supply Current (When Programming)
Max
Units
100
mA
NOTE:
Do not apply VPP until VCC is stable and within specifications and the oscillator/clock has stabilized or the device may be
damaged.
EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
270942 – 27
NOTE:
P3.0 must be high (‘‘1’’)
SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT
270942 – 28
NOTE:
P3.0 must be low (‘‘0’’)
22
8XC196KC/8XC196KC20
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM
WITH REPEATED PROG PULSE AND AUTO INCREMENT
270942 – 29
8XC196KB TO 8XC196KC DESIGN
CONSIDERATIONS
1. Memory Map. The 8XC196KC has 512 bytes of
RAM/SFRs
and
an
optional
16K
of
ROM/OTPROM. The extra 256 bytes of RAM will
reside in locations 100H–1FFH and the extra 8K
of ROM/OTPROM will reside in locations
4000H–5FFFH. These locations are external
memory on the 8XC196KB.
2. The CDE pin on the KB has become a VSS pin on
the KC to support 16/20 MHz operation.
3. EPROM programming. The 8XC196KC has a different programming algorithm to support 16K of
on-board memory. When performing Run-Time
Programming, use the section of code in the
8XC196KC User’s Guide.
4. ONCE Mode Entry. The ONCE mode is entered
on the 8XC196KC by driving the TXD pin low on
the rising edge of RESET. The TXD pin is held
high by a pullup that is specified by IOH1. This
Pullup must not be overridden or the 8XC196KC
will enter the ONCE mode.
5. During the bus HOLD state, the 8XC196KC
weakly holds RD, WR, ALE, BHE and INST in
their inactive states. The 8XC196KB only holds
ALE in its inactive state.
6. A RESET pulse from the 8XC196KC is 16 states
rather than 4 states as on the 8XC196KB (i.e., a
watchdog timer overflow). This provides a longer
RESET pulse for other devices in the system.
8XC196KC ERRATA
1. Missed EXTINT on P0.7.
The 80C196KC20 could possibly miss an
EXTINT on P0.7. See techbit MC0893.
2. HSIÐMODE divide-by-eight.
See Faxback Ý2192.
3. IPD hump.
See Faxback Ý2311.
23
8XC196KC/8XC196KC20
DATA SHEET REVISION HISTORY
This data sheet is valid for devices with a ‘‘H’’, ‘‘L’’ or ‘‘M’’ at the end of the topside tracking number. The
topside tracking number consists of nine characters and is the second line on the top side of the device. Data
sheets are changed as new device information becomes available. Verify with your local Intel sales office that
you have the latest version before finalizing a design or ordering devices.
The following are differences between the 270942-004 and 270942-005 datasheets:
1. Removed ‘‘Word Addressable Only’’ from Port 3 and 4 in Table 2.
2. Renamed PVAL to CPVER.
3. Removed TLLYV and TLLGV from the waveform diagrams.
4. Added HSIÐMODE divide-by-eight and IPD hump to 8XC196KC errata.
The following are important differences between the 270942-002 and 270942-004 data sheets:
1. NMI during PTS, QBD port glitch and Divide HOLD/READY erratas were fixed and have been removed
from the data sheet. The HSI errata is also removed as this is now considered normal operation.
2. Combined 16 and 20 MHz data sheets. Data sheet 270924-001 (20 MHz) is now obsolete.
3. Added 80-lead SQFP package pinout.
4. Added documentation for CLKOUT disable bit.
5. iJA for QFP package was changed to 55§ C/W from 42§ C/W.
6. iJC for QFP package was changed to 16§ C/W from TBD§ C/W.
7. TSAM (MIN) in 10-bit mode was changed to 1.0 ms from 3.0 ms.
8. TSAM (MIN) in 8-bit mode was changed to 1.0 ms from 2.0 ms.
9. IIL1 specification for port 2.0 was renamed IIL2.
10. IIL2 (MAX) is changed to TBD from b 6 mA.
11. IIH1 (MAX) is changed to a 200 mA from a 100 mA.
12.
13.
14.
15.
16.
IIH1 test condition changes to VIN e 2.4V from VIN e 5.5V.
VHYS is changed to 300 mV from 150 mV.
ICC (TYP) at 16 MHz is changed to 65 mA from 50 mA.
ICC (MAX) at 16 MHz is changed to 75 mA from 70 mA.
ICC (TYP) at 20 MHz is changed to 80 mA from 60 mA.
17. ICC (MAX) at 20 MHz is changed to 92 mA from 86 mA.
18. IIDLE (TYP) at 16 MHz is changed to 17 mA from 15 mA.
19. IIDLE (MAX) at 16 MHz is changed to 25 mA from 30 mA.
20. IIDLE (TYP) at 20 MHz is changed to 21 mA from 15 mA.
21. IIDLE (MAX) at 20 MHz is changed to 30 mA from 35 mA.
22. IPD (TYP) at 16 MHz is changed to 8 mA from 15 mA.
23.
24.
25.
26.
27.
IPD (MAX) at 16 MHz is changed to 15 mA from TBD.
IPD (TYP) at 20 MHz is changed to 8 mA from 18 mA.
IPD (MAX) at 20 MHz is changed to 15 mA from TBD.
TCLDV (MAX) is changed to TOSC b 45 ns from TOSC b 50 ns.
TLLAX (MIN) is changed to TOSC b 35 ns from TOSC b 40 ns.
28.
29.
30.
31.
TCHWH (MIN) is changed to b 5 ns from b 10 ns.
TRHAX (MIN) is changed to TOSC b 25 ns from TOSC b 30 ns.
THALAZ (MAX) is changed to a 15 ns from a 10 ns.
THALBZ (MAX) is changed to a 20 ns from a 15 ns.
24
8XC196KC/8XC196KC20
32. THAHBV (MAX) is now specified at a 15 ns, was formerly unspecified.
33. The TLLYV and TLLGV specifications were removed. These specifications are not required in high-speed
systems designs.
34. Added EXTINT, P0.7 errata to Errata section.
The following are the important differences between the -001 and -002 versions of data sheet 270942.
1. Express and Commercial devices are combined into one data sheet. The Express only data sheet
270794-001 is obsolete.
2. Removed KB/KC feature set differences, pin definition table, and SFR locations and bitmaps.
3. Added programming pin function to package drawings and pin descriptions.
4. Changed absolute maximum temperature under bias from 0§ C to a 70§ C to b 55§ C to a 125§ C.
5. Replaced VOH2 specification with IOH1 and IIL1 specifications.
6. Added IIH1 specification for NMI pulldown resistors.
7. Added maximum hold latency table.
8. Added external oscillator and external clock circuit drawings.
9. Changed Clock Drive TXHXX and TXLXX Min spec to 20 ns.
10. Fixed Serial Port TXLXH specification.
11. Added 8- and 10-bit mode A/D operating conditions tables.
12. Specified operating range for sample and convert times.
13. Added specification for voltage on analog input pin.
14. Put operating conditions for EPROM programming into tabular format.
25