[AK7780] AK7780 24bit 5ch ADC & SRC + Audio DSP GENERAL DESCRIPTION The AK7780 is a highly integrated audio processor, including a 28-bit floating point DSP, two 24-bit stereo ADC’s and one mono ADC. The stereo ADC’s feature high performance, achieving 96dB dynamic range, they include 8:1 input selectors. The ADC supports sampling frequencies from 7.35 kHz to 96 kHz. The AK7780 also includes a stereo sample rate converter (SRC), so it can be used as a master device when it receives digital audio inputs. The DSP includes 168kbits of SRAM for audio delay data that is suitable for creating simulated surround fields. The programmable DSP block is realized with 2560step/fs DSP. It supports sampling frequencies from 7.35kHz to 96 kHz. The AK7780 is used to implement complete sound field control, such as echo, 3D, parametric equalization, and other sound enhancements. It is packaged in a 100-lead LQFP package. FEATURES [DSP] Main Word length: 28-bit (Data RAM F24.4 limited range floating point) Instruction cycle time: 8.1 ns (2560step/fs fs=48kHz; 1280step/fs fs=96kHz) Multiplier: 24 x 16 → 40-bit (Double precision available) Divider: 24 / 24 → 24-bit ALU: 44-bit arithmetic operation (overflow margin: 4-bits) F24.4 arithmetic and logic operation Shift+Register: Flexible setting Program RAM: 2048 x 36-bit Coefficient RAM: 2048 x 16-bit Data RAM: 2048 x 28-bit (F24.4[sign bit + 23-bit mantissa + 4-bit exponent]) Offset RAM: 64 x 13-bit Internal Delay RAM: 168kbits ( 6144 x 28 bit / 2048 x 28 bit + 8192 x 14 bit / 3072 x 28 bit + 6144 x 14 bit / 4096 x 28 bit + 4096 x 14 bit) 4 pattern setting 28bit = F24.4 [24 bit sign & mantissa: 4 bit exponent] 14bit = F10.4 [10 bit sign & mantissa: 4 bit exponent] Sampling frequency: 7.35kHz ~ 96kHz Serial interface port for microcontroller or I2C BUS control Master Clock: 2560fs (generated by PLL from 32fs ,64fs, 256fs and 384fs) Master/Slave operation Serial signal input port (10ch): MSB justified 24-bit / LSB justified 16/20/24-bit and I2S Serial signal output port(12ch): MSB justified 24-bit / LSB justified 24,16-bit and I2S (SDOUT1,SDOUT2 and SDOUT3) [ADC] 4 channels (2 stereo pairs) 24-bit 64X over-sampling delta-sigma (fs = 7.35kHz ~ 96kHz) DR, S/N: 96dBA (fs = 48kHz, fully-differential input) S/(N+D): 92dB (fs = 48kHz) Digital HPF (fc = 1Hz) MS0581-E-00-PB -1- 2007/09 [AK7780] [ADC] Mono single channel 24-bit 64X over-sampling delta sigma (fs = 7.35kHz ~ 96kHz) DR, S/N: 95dBA ( fs = 48kHz) Includes digital attenuator [SRC] Stereo pair Input frequency 7.35kHz ~ 96kHz → Output frequency 44.1kHz ~ 96kHz [Other] Power supply: +3.3V ±0.3V, +1.7V~+2.0V(typ +1.8V) Operating temperature range: -40°C~85°C Package: 100pin LQFP(0.5mm pitch) MS0581-E-00-PB -2- 2007/09 [AK7780] AINM AINL8,AINR8 AINL7,AINR7 2 2 2 2 2 2 AINL6,AINR6 AINL3,AINR3 2 AINL5,AINR5 AINL2,AINR2 4 AINL4,AINR4 AINL+,AINR+ AINL-,AINR- BLOCK DIAGRAM pull down Hi-z ADC1 ctrl reg sw ADCM ASEL2[2:0] ASEL1[2:0] I/O 3 AVDD VREFH VREF ADC2 VCOM VREFL VOL 3 AVSS MUX SELOA1[1:0] 0 1 OUTA1E_ N SDOUTA1 2 3 SELOA2[1:0] 0 1 2 3 SEL_SDO6 SDIN6 SDOUT6 SDOUT5 SELI5 SDOUT6 SWIRP T SWG1 SDOUT4 SDIN5 SDIN5 SWG0 SELI4 SDIN4 SDIN3 SDOUT1 SDIN2 IRPT GPO1 GPO0 SEL_SDO2 SDOUT3 SDOUT2 OUT2E_ N SELI3 SDOUT1 OUT1E_ N SEL_SDO1 I2CSEL MICIF SELI1 SDIN1 SDOUT4 OUT4E_ N OUT3E_ N SDOUT2 SDIN2 SDOUT5 OUT5E_ N SDOUT3 SDIN4 SDIN3 OUT6E_ N RQ_N/CAD1 SCLK/SCL SDIN1 SI/CAD0 SO SRCI DSP SDA SRCOUT RDY R_SRCSMUTE P_SRCSMUTE R_SRCRST_N P_SRCRST SRC_LRCK SRC JX2 JX2 JX1 JX1 JX0 JX0 WDT SRC_BICK WDTE_N CRC SRCSET[1] STO CRC_E LOCK_E SRCSET[0] SRC_LFLT UNLOCK TESTO LRCLK_O BITCLK_O CONTROLLER TESTI2 TESTI1 CKM[2:0] 3 P_CKRST XTI CKRST_N XTO R_CKRST_N (Master="H",Slave="L") DSPRST_N CLKO2E_N SMODE P_DSPRST CLKO1E_N R_DSPRST_N CLKO2 CLKO1 S_RESET_N 2 BVSS P_ADRST R_ADRST_N 7 DVDD18 3 DVSS 8 3 DVDD 6 ADRST_N INIT_RESET LRCLK_I BITCLK_I LFLT Figure 1. Whole Block Diagram * Figure 1 shows a simplified diagram of the AK7780, which isn’t the perfect same as the actual circuit diagram. Each \ describes the relationship of reset control and target reset blocks. MS0581-E-00-PB -3- 2007/09 [AK7780] CP0,CP1 DLP0,DLP1 DP1 DP0 DLRAM 6kw×28bit (Default) 1024w× 28bit 1024w× 28bit CRAM OFRAM 64w×13bit DRAM 2048w×16bit CBUS(16bit) DBUS(28bit) MPX16 Micon I/F MPX24 X Control PRAM DEC Y Serial I/F 2048w × 36bit Multiply PC Stack : 5level(max) 16bit×24bit→40bit TMP 8×28bit 28bit 40bit PTMP(LIFO) 6×28bit MUL DBUS 2×24bit SDIN6 2×24/20/16bit SDIN5 2×24/20/16bit SDIN4 2×24/20/16bit SDIN3 ALU 2×24/20/16bit SDIN2 44bit 2×24/20/16bit SDIN1 2×24bit SDOUT6 2×24/16bit SDOUT5 2×24/16bit SDOUT4 2×24/16bit SDOUT3 2×24bit SDOUT2 2×24bit SDOUT1 SHIFT 44bit 44bit A B Overflow Margin: 4bit 44bit DR0~3 44bit Over Flow Data Generator Division 24÷24→24 Peak Detector Figure 2. DSP Block Diagram MS0581-E-00-PB -4- 2007/09 [AK7780] ■ Ordering Guide -40 ∼ +85°C 100pin LQFP(0.5mm pitch) Evaluation Board for AK7780 AK7780VQ AKD7780 SDOUTA1 STO RDY SDOUT6 CLKO2 DVDD DVSS DVDD18 JX2 JX1 JX0 SDIN1 SRC_BICK SRC_LRCK P_SRCRST SDA DVDD18 DVSS DVDD BVSS P_SRCSMUT AVSS AVDD TESTI2 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SRC_LFLT ■ Pin layout TESTO AINM 76 50 SO 77 49 DVDD AINR4 78 48 DVSS AINL4 79 47 DVDD18 AINR3 AINL3 80 46 SCLK/SCL 81 45 AINR2 82 44 SI / CAD0 RQ / CAD1 AINL2 83 43 P_DSPRST AVDD 84 42 P_ADRST VREFH 85 VCOM VREFL 86 AVSS 88 AINR- 89 AINR+ 90 AINLAINL+ 100 pin LQFP 87 41 P_CKRST 40 INIT_RESET 39 DVSS 38 DVDD18 37 36 LRCLK_I BITCLK_I 91 35 SDIN5 92 34 SDIN4 AINR5 AINL5 93 33 SDIN3 94 32 SDIN2 AINR6 95 31 DVDD18 AINL6 96 30 DVSS AINR7 97 29 DVDD AINL7 98 28 CLKO1 AINR8 99 27 SDOUT5 AINL8 100 26 SDOUT4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 (TOP VIEW) SDOUT3 SDOUT2 SDOUT1 LRCLK_O BITCLK_O DVDD DVDD18 DVSS CKM[2] CKM[0] CKM[1] DVDD18 XTO DVSS XTI DVSS DVDD BVSS SRCSET[0] I2CSEL SRCSET[1] AVDD TESTI1 AVSS LFLT pin Input Output I/O Power MS0581-E-00-PB -5- 2007/09 [AK7780] PIN FUNCTION No Pin Name I/O 1 LFLT 2 AVSS 3 AVDD Function Classification Filter connection pin for AK7780 core PLL O When using the PLL function, connect with R (1.5kΩ) and C (47nF) in series Analog Output and connected to analog ground (AVSS) see. 9. System design (1) - Analog ground 0V Analog Power Power supply pin for analog section 3.3V (typ) Supply - 4 TESTI1 I TEST pin (Internal pull-down) * Connect to DVSS TEST I2CBUS select pin * I2CSEL= “L”: Normal serial interface I * I2CSEL= “H”: I2CBus selected mode. SCL and SDA are active. I2CSEL must be set to “L (DVSS)” or ”H (DVDD)”. I SRC select pin 1 I SRC select pin 0 5 I2CSEL 6 SRCSET [1] 7 SRCSET [0] 8 BVSS - 9 DVDD - Power supply pin for digital section 3.3V (typ) 10 DVSS 11 XTI - Ground pin for digital section 0V Master clock input pin I Connect a crystal between this pin and the XTO pin, or input an external CMOS clock signal to the XTI pin. Crystal oscillator output pin O When using a crystal, connect it between XTI and XTO. When using an external clock, keep this pin open. Silicon substrate potential 0V Connect to AVSS. SRC Analog Power Supply 12 XTO 13 DVSS 14 DVDD18 - Power supply pin for digital section 1.8V (typ) 15 CKM [1] I Clock mode select pin 1 16 CKM [0] I Clock mode select pin 0 17 CKM [2] I Clock mode select pin 2 18 DVDD18 - Power supply pin for digital section 1.8V (typ) 19 DVSS - Ground pin for digital section 0V 20 DVDD - Power supply pin for digital section 3.3V (typ) MS0581-E-00-PB I2C Select - Ground pin for digital section 0V Digital Power Supply System Clock Digital Power Supply Mode select Digital Power Supply -6- 2007/09 [AK7780] No 21 22 Pin Name I/O Function LR channel select clock output pin LRCLK_O O Master mode: Outputs fs clock. Slave mode: Outputs LRCLK_I clock. Serial bit clock output pin BITCLK_O O Master mode: Outputs 64fs clock. Slave mode: Outputs BITCLK_I clock 23 SDOUT1 O DSP Serial data output pin * Compatible with MSB justified 24 bits / I2S. 24 SDOUT2 O DSP Serial data output pin * Compatible with MSB justified 24 bits / I2S. 25 SDOUT3 O DSP Serial data output pin * Compatible with MSB justified 24 bits / LSB justified 24 and 16 bits/ I2S. 26 SDOUT4 O DSP Serial data output pin * Compatible with MSB justified 24 bits / LSB justified 24 and 16 bits/ I2S. 27 SDOUT5 O DSP Serial data output pin * Compatible with MSB justified 24 bits / LSB justified 24 and 16 bits/ I2S. 28 CLKO1 O Clock output pin 1 Select the output frequency through a control register. 29 DVDD - Power supply pin for digital section 3.3V(typ) 30 DVSS - Ground pin for digital section 0.0V 31 DVDD18 32 SDIN2 33 SDIN3 34 SDIN4 35 SDIN5 MS0581-E-00-PB Classification System Clock Digital section Serial output data Clock output Digital Power Supply - Power supply pin for digital section 1.8V(typ) DSP serial data input pin Compatible with MSB justified 24 bits / LSB justified 24, 20 and 16 bits / I2S. * If not used, connect to DVSS DSP serial data input pin I Compatible with MSB justified 24 bits / LSB justified 24, 20 and 16 bits / I2S. * If not used, connect to DVSS Digital section Serial input data DSP serial data input pin I Compatible with MSB justified 24 bits / LSB justified 24, 20 and 16 bits / I2S. * If not used, connect to DVSS DSP serial data input pin I Compatible with MSB justified 24 bits / LSB justified 24, 20 and 16 bits / I2S. * If not used, connect to DVSS I -7- 2007/09 [AK7780] No Pin Name 36 BITCLK_I I Serial bit clock input pin 37 LRCLK_I I LR channel select clock input pin. 38 DVDD18 - Power supply pin for digital section 1.8V(typ) 39 DVSS 40 INIT_RESET I 41 P_CKRST I 42 P_ADRST I 43 P_DSPRST I 44 RQ I CAD1 45 46 SI I/O Function Classification System Clock - Ground pin for digital section 0.0V Digital power supply Reset pin ( for initialization) Use for initialization. When changing CKM[2:0], XTI or BITCLK_I input frequency, this reset pin must be used. Clock reset pin When changing CKM[2:0] and XTI or BITCLK_I input frequency without using INIT_RESET, pin control is necessary. The control register R_CKRST_N can also rest the clock. Reset ADC Reset pin The control register R_ADRST_N can also reset the ADC. P_ADRST = “L” and P_DSPRST = “L” state causes a system reset (S_RESET). DSP Reset pin The control register R_DSPRST_N can also rest the DSP. P_ADRST = “L” and P_DSPRST = “L” state causes a system reset (S_RESET). I2CSEL= “L” Microcomputer Microcomputer interface write request pin. Interface. After initial reset, if the microcomputer interface is not used, leave RQ = “H” I I2CSEL=”H” I2C Bus address setting pin 1 I2C Microcomputer interface serial data input and serial data output control Microcomputer I pin. Interface. When SI is not used, leave SI = “L”. CAD0 I I2CSEL= “H” I2C Bus address pin 0 I2C SCLK I2CSEL= “L” I Microcomputer interface serial data clock pin. When SCLK is not used, leave SCLK= “H” Microcomputer Interface. I I2CSEL= “H” I2C bus data clock pin I2C SCL - Power supply pin for digital section 1.8V(typ) 47 DVDD18 48 DVSS - Ground pin for digital section 0.0V 49 DVDD - Power supply pin for digital section 3.3V(typ) 50 SO MS0581-E-00-PB O Serial data output pin for microcomputer interfaces. When RQ = “H”, SO = Hi-Z -8- Digital power supply Microcomputer Interface. 2007/09 [AK7780] No Pin Name 51 RDY 52 STO 53 SDOUTA1 I/O Function O Data write ready output pin for microcomputer interface. Status output pin Normal state output “H”. O When WDT, CRC error or SRC UNLOCK occurs, then output “L”. See 3.(1) Whole block diagram. DSP or ADC Serial data output pin O * Compatible with MSB justified 24 bits / I2S. 54 SDOUT6 55 CLKO2 56 DVDD DSP or ADC Serial data output pin O * Compatible with MSB justified 24 bits / I2S. Clock output pin 2 O Select the output frequency through a control register. - Power supply pin for digital section 3.3V(typ) 57 DVSS - Ground pin for digital section 0.0V 58 DVDD18 59 JX2 60 JX1 61 JX0 62 SDIN1 63 SRC_BICK I SRC Serial bit clock input pin. 64 SRC_LRCK I SRC LR channel select clock input pin. - Power supply pin for digital section 1.8V(typ) External condition jump pin I * When not used, connect to DVSS External condition jump pin I * When not used, connect to DVSS External condition jump pin I * When not used, connect to DVSS DSP/SRC Serial input pin I Input pin for SRC. When not used, connect to DVSS. I2CSEL= “L” SDA Outputs “L” level. I2CSEL= “H” I/O 2 I C bus interface data pin SRC Reset pin I The control register R_SRCRST_N can also rest the SRC. - Power supply pin for digital section 1.8V(typ) Classification Microcomputer Interface. Status Digital section Serial output data Clock output Digital power supply Conditional input Digital section Serial input data SRC I I2C 65 SDA 66 P_SRCRST 67 DVDD18 68 DVSS - Ground pin for digital section 0.0V 69 DVDD 70 BVSS 71 P_SRC SMUTE 72 TESTI2 - Power supply pin for digital section 3.3V(typ) Analog power Silicon substrate potential 0V supply Connect to AVSS. SRC Soft mute pin I The control register R_SRCSMUTE can also execute a soft mute on the SRC SRC. TEST pin ( Internal pull-down ) I TEST * Connect to DVSS. 73 AVDD - Power supply pin for analog section 3.3V (typ) 74 AVSS 75 SRC_LFLT - Analog ground 0V RC Filter connection pin for SRC. O See p.86 10-2-5-2: SRC PLL loop filter setting. MS0581-E-00-PB -9- RESET Digital power supply Analog power supply Analog output 2007/09 [AK7780] No Pin Name I/O Function TEST OUT pin Hi-Z Output pin. Leave it open. ADCM single ended analog input ADC1 or ADC2 Rch single ended analog input 4 ADC1 or ADC2 Lch single ended analog input 4 ADC1 or ADC2 Rch single ended analog input 3 ADC1 or ADC2 Lch single ended analog input 3 ADC1 or ADC2 Rch single ended analog input 2 ADC1 or ADC2 Lch single ended analog input 2 76 TESTO O 77 78 79 80 81 82 83 AINM AINR4 AINL4 AINR3 AINL3 AINR2 AINL2 I I I I I I I 84 AVDD - Power supply pin for analog section 3.3V (typ) 85 VREFH I 86 VCOM O 87 VREFL I 88 AVSS - 89 90 91 92 93 94 95 96 97 98 99 100 AINR– AINR+ AINL– AINL+ AINR5 AINL5 AINR6 AINL6 AINR7 AINL7 AINR8 AINL8 I I I I I I I I I I I I Classification TEST Analog input Analog Power Supply Analog reference voltage input pin. Connect to AVDD, and connect 0.1μF and 10μF bypass capacitors between Analog input this pin and AVSS. Common voltage Analog output Connect to 0.1μF and 10μF capacitors between this pin and AVSS. Do not connect to external circuitry. Analog reference voltage input pin for low-level. Analog input Connect to AVSS. Analog Power Analog ground 0V Supply ADC1 or ADC2 Rch inverted input pin ADC1 or ADC2 Rch non- inverted input pin ADC1 or ADC2 Lch inverted input pin ADC1 or ADC2 Lch non- inverted input pin ADC1 or ADC2 Rch single ended analog input 5 ADC1 or ADC2 Lch single ended analog input 5 Analog input ADC1 or ADC2 Rch single ended analog input 6 ADC1 or ADC2 Lch single ended analog input 6 ADC1 or ADC2 Rch single ended analog input 7 ADC1 or ADC2 Lch single ended analog input 7 ADC1 or ADC2 Rch single ended analog input 8 ADC1 or ADC2 Lch single ended analog input 8 Note 1. Digital input pins must not be allowed to float Note 2. If analog input pins (AINR–, AINR+, AINL–, AINL+, AINL2-8, AINR2-8, AINM) are not used, leave them open. Note 3. I2CSEL should be set to “L” (DVSS) or “H” (DVDD). Relationship with I2CSEL and SDA. Normal Microcontroller Interface I2C bus compatible MS0581-E-00-PB I2CSEL INIT_RESET SDA L L L L H H H L H L “Hi-Z” → pull-up function - 10 - 2007/09 [AK7780] ABSOLUTE MAXIMUM RATINGS (AVSS = BVSS = DVSS = 0V: All indicated voltages are with respect to ground.) Item Symbol min Power supply voltage VA Analog(AVDD) -0.3 VD Digital(DVDD) -0.3 VD18 Digital(DVDD18) -0.3 |AVSS(BVSS) – DVSS| (Note 4) ΔGND Input current (except for power supply pin ) IIN Analog input voltage AINL+, AINL–, AINR+, AINR–, VINA -0.3 AINL2-8, AINR2-8, AINM VREFH,VREFL Digital input voltage VIND -0.3 Operating ambient temperature Ta -40 Storage temperature Tstg -65 max Unit 4.3 4.3 2.5 0.3 ±10 V V V V mA VA+0.3 V VD+0.3 85 150 V °C °C Note 4. AVSS (BVSS) should be at the same level as DVSS. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these critical conditions. RECOMMENDED OPERATING CONDITIONS (AVSS = BVSS = DVSS = 0V: All indicated voltages are with respect to ground.) Items Symbol min typ max Unit Power supply voltage AVDD VA 3.0 3.3 3.6 V DVDD VD 3.0 3.3 3.6 V DVDD18 VD18 1.7 1.8 2.0 V Reference voltage (VREF) VREFH (Note 5) VRH VA V VREFL (Note 6) VRL 0.0 V Note 5. VREFH normally connects to AVDD. Note 6. VREFL normally connects to AVSS Note: The analog input voltage and output voltage are proportional to the VREFH-VREFL voltages. * AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. MS0581-E-00-PB - 11 - 2007/09 [AK7780] ELECTRIC CHARACTERISTICS (1) Analog Characteristics 1) ADC Characteristics (Unless otherwise specified, Ta = 25°C; AVDD = DVDD = 3.3V, DVDD18=1.8V; VREFH = AVDD, VREFL = AVSS; BITCLK = 64 fs; signal frequency = 1kHz; Measurement bandwidth = 20Hz to 20kHz @ 48kHz, 20Hz ~ 40kHz @ 96kHz; ADC specified with differential inputs (ADC1, ADC2); CKM Mode 1(CKM[2:0]= “000”), SRC RESET) Parameter min typ max Resolution 24 Dynamic characteristics S/(N+D) fs = 48kHz (-1dBFS) (Note 7) 82 92 ADC1 Fs = 96kHz (-1dBFS) 90 ADC2 Dynamic range fs = 48kHz (A filter) (Note 7, Note 8) 88 96 fs = 96kHz 93 S/N fs = 48kHz (A filter) (Note 7) 88 96 fs = 96kHz 93 Inter-channel isolation (f=1kHz) (Note 9) 90 115 DC accuracy Channel gain mismatch 0.1 0.3 Analog input Input voltage ( Differential input ) (Note 10) ±1.85 ±2.00 ±2.15 Input voltage ( Single-ended input ) (Note 11) 1.85 2.00 2.15 Input impedance (Note 12) 22 33 24 Monaural Resolution ADC part Dynamic characteristics S/(N+D fs = 48kHz (-1dBFS) 78 88 ADCM fs = 96kHz ( -1dBFS) 87 Dynamic range fs = 48kHz (A filter) (Note 8) 87 95 fs = 96kHz 92 S/N fs = 48kHz (A filter) 87 95 fs = 96kHz 92 Analog input Input voltage (Note 13) 1.85 2.00 2.15 Input impedance (Note 14) 22 33 Note 7. This value is not guaranteed for single-ended inputs. Note 8. Indicates S/(N+D) when -60 dBFS signal is applied. Note 9. Indicates isolation between L and R when -1dBFS signal is applied. Note 10. Target input pins are AINL+, AINL-, AINR+ and AINR-. Differential full scale is (±FS=(VREFH-VREFL)x(2.0/3.3)) Note 11. Target input pins are AINL2~L8, AINR2~R8., Single-ended full scale is (FS=(VREFH-VREFL) x (2.0/3.3)) Note 12. Target input pins are AINL+, AINL–, AINR+, AINR–, AINL2-L8, AINR2-R8. Note 13. Target input pin is AINM, The full scale of this pin is (FS=(VREFH-VREFL) x (2.0/3.3)) Note 14. Target input pin is AINM. Stereo ADC MS0581-E-00-PB - 12 - Unit Bits dB dB dB dB dB dB dB dB Vp-p Vp-p kΩ Bits dB dB dB dB dB dB Vp-p kΩ 2007/09 [AK7780] 2) SRC Characteristics (Ta=25°C; AVDD = 3.3V; DVDD=3.3V; DVDD18=1.8V; data = 24-bits; measurement bandwidth = 20Hz∼ FSO/2; unless otherwise specified.) Parameter Symbol min typ max Units Resolution 24 Bits Input Sample Rate FSI 7.35 96 kHz Output Sample Rate FSO 44.1 96 kHz THD+N (Input= 1kHz, 0dBFS) FSO/FSI=44.1kHz/48kHz -113 dB FSO/FSI=44.1kHz/96kHz -112 dB FSO/FSI=48kHz/44.1kHz -113 dB FSO/FSI=48kHz/96kHz -113 dB FSO/FSI=48kHz/8kHz -112 -103 dB Dynamic Range (Input= 1kHz, -60dBFS) FSO/FSI=44.1kHz/48kHz 114 dB FSO/FSI=44.1kHz/96kHz 114 dB FSO/FSI=48kHz/44.1kHz 114 dB FSO/FSI=48kHz/96kHz 114 dB FSO/FSI=48kHz/8kHz 110 114 dB Dynamic Range (Input= 1kHz, -60dBFS, A-weighted FSO/FSI=44.1kHz/48kHz 116 dB Ratio between Input and Output Sample Rate FSO/FSI 0.45 6 - MS0581-E-00-PB - 13 - 2007/09 [AK7780] (2) DC Characteristics (Ta = -40°C ~ 85°C; AVDD = DVDD = 3.0~3.6V; DVDD18 = 1.7~2.0V) Parameter Symbol min High level input voltage (Note 15) VIH 80%DVDD Low level input voltage (Note 15) VIL SCL,SDA High level input voltage VIH 70%DVDD SCL,SDA Low level input voltage VIL VOH DVDD-0.5 High level output voltage Iout=-100μA VOL Low level output voltage Iout=100μA (Note 16) SDA Low level output voltage Iout=3mA VOL Input leak current (Note 17) Iin Input leak current (pull-down) (Note 18) Iid Input leak current (XTI pin ) Iix typ max 20%DVDD 30%DVDD 0.5 0.4 ±10 22 26 Unit V V V V V V V μA μA μA Note 15. SCL (I2CSEL=1) and SDA pins are not included. (SCLK pin is included when I2CSEL=0) Note 16. SDA pin is not included. Note 17. The pull-down pins and XTI pin are not included. Note 18. The pull-down pins (Typ150kΩ) are: TESTI1, TESTI2 (3) Current Consumption (Ta=25°C; AVDD=DVDD=3.0~3.6V(typ=3.3V,max=3.6V); DVDD18=1.7~2.0V(typ=1.8V, max=2.0V)) Power supply Parameter min typ max Power supply current (Note 19) 1) a) AVDD 52 70 b) DVDD 8 15 c) DVDD18 110 165 1 2) INIT_RESET = “L” (reference) (Note 20) Unit mA mA mA mA Note 19. Varies slightly according to the system frequency and contents of the DSP program. Note 20. This is a reference value when using a crystal oscillator. Since most of the supply current at the initial reset state is in the oscillator section, the value may vary slightly according to the crystal type and the external circuit. This is a “reference value” only. MS0581-E-00-PB - 14 - 2007/09 [AK7780] (4) Digital Filter Characteristics 1) ADC Section: ADC1, ADC2 (Ta=-40°C~85°C; AVDD = DVDD =3.0V~3.6V; DVDD18=1.7V~2.0V; fs=48kHz; Note 21) Parameter Symbol min typ max Unit PB 0 21.5 kHz Pass band (±0.005dB) (Note 22) 21.768 kHz (-0.02dB) 24.00 kHz (-6.0dB) Stop band SB 26.5 kHz Pass band ripple (Note 22) PR ±0.005 dB Stop band attenuation (Note 23, Note 24) SA 80 dB Group delay distortion 0 ΔGD μs Group delay (Ts=1/fs) GD 29 Ts Digital filter + SFC Amplitude characteristics (20Hz~20.0kHz) ±0.01 dB Note 21. Each parameter is related to the sampling frequency (fs). HPF response is not included. Note 22. The pass band is from DC to 21.5kHz at fs = 48kHz. Note 23. The stop band is from 26.5kHz to 3.0455MHz at fs = 48kHz. Note 24. When fs = 48kHz, the analog modulator samples the analog input at 3.072MHz. The input signal is not attenuated by the digital filter in multiple bands (n x 3.072MHz ± 21.99kHz; n=0, 1, 2, 3...) of the sampling frequency. 2) ADC Section ADCM (Ta=-40°C~85°C; AVDD = DVDD =3.0V~3.6V; DVDD18=1.7V~2.0V; fs = 48 kHz; Note 25) Parameter Symbol min typ max PB 0 21.5 Pass band (±0.005dB) (Note 26) 21.768 (-0.02dB) 24.00 (-6.0dB) Stop band SB 26.5 Pass band ripple (Note 26) PR ±0.005 Stop band attenuation (Note 27, Note 28) SA 80 Group delay distortion 0 ΔGD Group delay (Ts=1/fs) (Note 29) GD 29 Digital filter + SFC Amplitude characteristics (20Hz~20.0kHz) ±0.1 Unit kHz kHz kHz kHz dB dB μs Ts dB Note 25. Each parameter is related to the sampling frequency (fs). HPF response is not included. Note 26. The pass band is from DC to 21.5kHz at fs = 48kHz. Note 27. The stop band is from 26.5kHz to 3.0455MHz at fs = 48kHz. Note 28. When fs = 48kHz, the analog modulator samples the analog input at 3.072MHz. The input signal is not attenuated by the digital filter in the multiple bands (n x 3.072MHz ± 21.99kHz; n=0, 1, 2, 3...) of the sampling frequency. Note 29. VOL+ MUX path adds one additional Ts. MS0581-E-00-PB - 15 - 2007/09 [AK7780] 3) SRC (Ta=-40°C~85°C; AVDD=DVDD=3.0~3.6V; DVDD18 = 1.7~2.0V) Parameter Range Symbol min typ max Pass band -0.01dB PB 0 0.4583FSI 0.980 ≤ FSO/FSI ≤ 6.000 PB 0 0.4167FSI 0.900 ≤ FSO/FSI < 0.990 PB 0 0.2182FSI 0.533 ≤ FSO/FSI < 0.909 PB 0 0.2177FSI 0.490 ≤ FSO/FSI < 0.539 PB 0 0.1948FSI 0.450 ≤ FSO/FSI < 0.495 Stop band SB 0.5417FSI 0.980 ≤ FSO/FSI ≤ 6.000 SB 0.5021FSI 0.900 ≤ FSO/FSI < 0.990 SB 0.2974FSI 0.533 ≤ FSO/FSI < 0.909 SB 0.2812FSI 0.490 ≤ FSO/FSI < 0.539 SB 0.2604FSI 0.450 ≤ FSO/FSI < 0.495 Pass band ripple PR ±0.01 Stop band attenuation SA 95.2 Group delay (Ts=1/fs) GD 56 (Note 30) Note 30. Measured from the rising edge of SRC_LRCK on the input to the rising edge of LRCLK_O on the output, with there is no phase difference between input and output. MS0581-E-00-PB - 16 - 2007/09 Unit kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz dB dB Ts [AK7780] (5) Switching Characteristics [ #h means hexadecimal code. (#=0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F)] 1) System Clock (Ta = -40~85°C; AVDD=DVDD=3.0V~3.6V; DVDD18 = 1.7V~2.0V) Parameter Symbol min XTI CKM[2:0] 0h,1h,2h,3h a) with a crystal oscillator: CKM[2:0]=0h,2h fXTI CKM[2:0]=1h,3h fXTI b) with an external clock Duty cycle CKM[2:0]=0h,2h CKM[2:0]=1h,3h Clock rise time Clock fall time fXTI fXTI tCR tCF LRCLK_I frequency Clock rise time Clock fall time (Note 31) typ max Unit 11.2896 12.288 16.9344 18.432 - MHz - MHz 40 11.0 16.5 50 60 12.4 18.6 6 6 % MHz MHz ns ns 7.35 48 96 kHz 6 6 ns ns - fs tLR tLF BITCLK_I frequency High level width tBCLKH 64 ns Low level width tBCLKL 64 ns Clock rise time tBR 6 ns Clock fall time tBF 6 ns fBCLK 64 fs a) CKM[2:0]=2h,3h Duty cycle 40 50 60 % CKM[2:0]=2h,3h 0.23 6.2 MHz 64 fs b) CKM[2:0]=4h,5h (Note 32) fBCLK Duty cycle 40 50 60 % CKM[2:0]=4h fBCLK 2.75 3.1 MHz CKM[2:0]=5h fBCLK 5.5 6.2 MHz Note 31. LRCLK and sampling rate (fs) should match. Note 32. When BITCLK_I uses as a resource of master clock, it should be 64 clocks correctly divided within 1fs. MS0581-E-00-PB - 17 - 2007/09 [AK7780] (Ta = -40°C ~85°C; AVDD=DVDD=3.0~3.6V, DVDD18 = 1.7~2.0V) Parameter Symbol min fs 7.35 SRC_LRCK frequency (Note 33) Clock rise time Clock fall time typ 48 tLR tLF SRC_BICK frequency High level width Low level width Clock rise time Clock fall time (Note 34) tBCLKH tBCLKL tBR tBF fBCLK Unit kHz 6 6 ns ns 6 6 128 60 6.2 ns ns ns ns fs % MHz 60 60 32 40 0.23 50 (Ta=-40°C ~85°C; AVDD=DVDD=3.0~3.6V; DVDD18 = 1.7~2.0V) Parameter Symbol min tRST 600 INIT_RESET (Note 35) typ Duty factor max 96 Note 33. SRC_LRCK and sampling rate (fs) should match. Note 34. 128fs is up to fs = 48kHz. 2) Reset max Unit ns P_CKRST tRST 600 ns P_ADRST tRST 600 ns P_DSPRST tRST 600 ns P_SRCRST tRST 600 ns Note 35. “L” is acceptable when power is turned on, but a stable master clock must present before transitioning to “H”. MS0581-E-00-PB - 18 - 2007/09 [AK7780] 3) Audio interface 3-1) SDIN1~SDIN5,SDOUT1~SDOUT6,SDOUTA1 (Up to fs = 96kHz) AKM Normal and I2S Compatible Format (Ta = -40°C~85°C; AVDD=DVDD=3.0~3.6V, DVDD18 = 1.7~2.0V, CL=20pF) Parameter Symbol min Slave mode CKM[2:0]=2h, 3h, 4h, 5h 20 Delay time from BITCLK_I “↑” to LRCLK_I (Note 36) tBLRD tLRBD 20 Delay time from LRCLK_ I to BITCLK_I “↑” (Note 36) Delay time from LRCLK_I, LRCLK_O to serial data output tLRD Delay time from BITCLK_I, BITCLK_O to serial data tBSOD output Serial data input latch setup time tBSIDS 40 Serial data input latch hold time tBSIDH 40 Master mode CKM[2:0]=0h, 1h BITCLK_O frequency fBCLK BITCLK_O duty cycle tBLRD -20 Delay time from BITCLK_O “↓” to LRCLK_O Delay time from LRCLK_O to serial data output tLRD Delay time from BITCLK_O to serial data output tBSOD Serial data input latch setup time tBSIDS 40 Serial data input latch hold time tBSIDH 40 typ max 40 40 Unit ns ns ns ns ns ns 64 50 40 40 40 fs % ns ns ns ns ns Note 36. LRCLK_I edge and BITCLK_I "↑“edge cannot be synchronous. 3-2) SDIN1(SRCI Input) (Up to fs = 96kHz) (Ta=-40°C~85°C; AVDD=DVDD=3.0~3.6V, DVDD18 = 1.7~2.0V) Parameter Symbol Slave mode Delay time from SRC_BICK “↑” to SRC_LRCK (Note 37) tBLRD Delay time from SRC_LRCK to SRC_BICK “↑” (Note 37) tLRBD Serial data input latch setup time tBSIDS Serial data input latch hold time tBSID H min 20 20 40 40 typ max Unit ns ns ns ns Note 37. SRC_BICK edge and SRC_LRCK edge cannot be synchronous. MS0581-E-00-PB - 19 - 2007/09 [AK7780] 3) Microcontroller Interface (Ta = -40~85°C; AVDD=DVDD=3.0V~3.6V, DVDD18 = 1.7~2.0V, CL = 20pF) Parameter Symbol min Microcomputer interface signal typ max Unit RQ Fall time tWRF 30 ns RQ Rise time tWRR 30 ns tSF tSR fSCLK tSCLKL tSCLKH 30 30 2.1 200 200 ns ns MHz ns ns Time from P_DSPRST , P_ADRST “↓” to RQ “↓” tREW 500 ns Time from RQ “↑” to P_DSPRST , P_ADRST “↑” tWRE 500 ns tWRQH 500 ns Time from RQ “↓” to SCLK“↓” tWSC 500 ns Time from SCLK“↑” to RQ “↑” tSCW 800 ns SI latch setup time SI latch hold time AK7780 to Microcomputer Delay time from SCLK“↓” to SO output Hold time from SCLK“↑” to SO output tSIS tSIH 200 200 ns ns SCLK fall time SCLK rise time SCLK frequency SCLK low level width SCLK High level width Microcomputer to AK7780 RQ high level width (Note 38) Time from RQ “↓” to SO Hi-Z (Iout=±360μA) release RQ “↑” to SO Hi-Z set (Iout=±360μA) tSOS tSOH 300 ns ns tRQHR 600 ns tRQHS 600 ns 200 Note 38. Except last 1bit of the command code. MS0581-E-00-PB - 20 - 2007/09 [AK7780] 4) I2C BUS Interface (Ta = -40°C~85°C; AVDD=DVDD=3.0~3.6V, DVDD18 = 1.7~2.0V) Parameter Symbol I2C Timing SCL clock frequency fSCL Bus Free Time Between Transmissions tBUF Start Condition Hold Time (prior to first Clock pulse) tHD:STA Clock Low Time tLOW Clock High Time tHIGH Setup Time for Repeated Start Condition tSU:STA SDA Hold Time from SCL Falling tHD:DAT SDA Setup Time from SCL Rising tSU:DAT Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition tSU:STO Pulse Width of Spike Noise Suppressed By Input Filter tSP Capacitive load on bus Cb Min 1.3 0.6 1.3 0.6 0.6 0 0.1 Typ Max Unit 400 50 kHz μs μs μs μs μs μs μs μs μs μs ns 400 pF 0.9 0.3 0.3 0.6 0 2 Note 39. I C is a registered trademark of Philips Semiconductors. MS0581-E-00-PB - 21 - 2007/09 [AK7780] (6) Timing Diagram 1) System clock 1/fXTI 1/fXTI tXTI=1/fXTI VIH XTI VIL tCF tCR ts=1/fs 1/fs VIH LRCLK_I SRC_LRCK VIL tLR 1/fBCLK 1/fBCLK tLF tBCLK=1/fBCLK VIH BITCLK_I SRC_BICK VIL tBCLKH tBR tBF tBCLKL 2) RESET NIT_RESET tRST P_CKRST P_ADRST VIL P_DSPRST P_SRCRST MS0581-E-00-PB - 22 - 2007/09 [AK7780] 3) Audio Interface c Normal and I2S compatible format LRCLK I 50%DVDD LRCLK_O tBLRD tMB tMBL tLRBD BITCLK_I 50%DVDD BITCLK_O tLRD tBSOD SDOUT * 50%DVDD tBSIDS tBSIDH SDIN * 50%DVDD SDIN * =SDIN1, SDIN2, SDIN3, SDIN4, SDIN5 SDOUT * =SDOUT1, SDOUT2, SDOUT3, SDOUT4, SDOUT5, SDOUT6, SDOUTA1 d SRC SRC_LRCK 50%DVDD tBLRD tLRBD SRC_BICK 50%DVDD tBSIDS SRCI=SDIN1 MS0581-E-00-PB tBSIDH 50%DVDD - 23 - 2007/09 [AK7780] 4) Microcontroller Interface ♦ Microcontroller interface VIH VIL RQ tWRF tWRR tSF tSR VIH VIL SCLK tSCLKL tSCLKH 1/fSCLK 1/fSCLK ♦ Microcontrollerr Æ AK7780 tWRE tREW P_DSPRST VIL P_ADRST VIH tWRQH RQ VIL tWSC VIH SI VIL tSIS tSIH VIH SCLK VIL tSCW MS0581-E-00-PB - 24 - tWSC tSCW 2007/09 [AK7780] ♦ AK7780 Æ Microcontroller VIH VIL SCLK VIH SO VIL tSOH tSOS Note: Timing during the RUN state is identical, except that P_DSPRST and P_ADRST are “H”. VIH VIL RQ tRQHS tRQHR Hi-Z SO 5) I2C Bus Interface VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop MS0581-E-00-PB tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop Start - 25 - 2007/09 [AK7780] PACKAGE • 100 pin LQFP (Unit: mm ) 1.70 Max. 16.0±0.3 14.0 0.20max 51 75 50 100 26 16.0±0.3 76 25 1 0.5 0.22±0.05 0.17±0.05 0.10 M 1.0 0°~10° 0.5±0.2 0.10 ■ Material & Lead finish Package: Epoxy Lead-frame: Cu Lead-finish: Solder (Pb free) plate MS0581-E-00-PB - 26 - 2007/09 [AK7780] MARKING AKM AK7780VT XXXXXXX 1) 2) 3) 4) Pin #1 indication Date Code: XXXXXXX(7digits) Marking Code: AK7780VT Asahi Kasei Logo IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS0581-E-00-PB - 27 - 2007/09 [AK7780] Thank you for your access to AKEMD product informations. More detail product informations are available, please contact our sales office or authorized distributors. MS0581-E-00-PB - 28 - 2007/09