TI BQ24250RGER 2a single input i2c, standalone switch-mode li-ion battery charger with power-path management Datasheet

bq24250
bq24251
bq24253
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SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
2
2A Single Input I C, Standalone Switch-Mode Li-Ion Battery Charger with Power-Path
Management
Check for Samples: bq24250, bq24251, bq24253
FEATURES
1
•
23
•
•
•
•
•
•
•
High-efficiency Switch-mode Charger with
Separate Power Path
Start up System from Deeply Discharged or
Missing Battery
USB Charging Compliant
– Selectable Input Current Limit of 100 mA,
500 mA, 900 mA, 1.5 A, and 2 A
BC1.2 Compatible D+, D– Detection
In Host Mode (after I2C communication starts
and before watchdog timer times out)
– Programmable Battery Charge Voltage,
VBATREG
– Programmable Charge Current (ICHG)
– Programmable Input Current Limit (ILIM)
– Programmable Input Voltage Based
Dynamic Power Management threshold,
(VIN_DPM)
– Programmable Input Overvoltage
Protection Threshold (VOVP)
– Programmable Safety Timer
Resistor Programmable Defaults for:
– ICHG up to 2 A with Current Monitoring
Output (ISET)
– ILIM up to 2 A with Current Monitoring
Output (ILIM)
– VIN_DPM (VDPM)
Watchdog Timer Disable Bit
Integrated 4.9 V, 50 mA LDO
•
•
•
•
•
•
•
•
•
Complete System Level Protection
– Input UVLO, Input Over-voltage Protection
(OVP), Battery OVP, Sleep Mode, VIN_DPM
– Input Current Limit
– Charge Current Limit
– Thermal Regulation
– Thermal Shutdown
– Voltage Based, JEITA Compatible NTC
Monitoring Input
– Safety Timer
20 V Maximum Input Voltage Rating
10.5 V Maximum Operating Input Voltage
Low RDS(on) Integrated Power FETs for up to 2
A Charging Rate
Open Drain Status Outputs
Synchronous Fixed-frequency PWM Controller
Operating at 3MHz for Small Inductor Support
AnyBoot Robust Battery Detection Algorithm
Charge Time Optimizer for improved charge
times at any given charge current
2.4 x 2.0 mm 30-ball WCSP Package
APPLICATIONS
•
•
•
•
Mobile Phones and Smart Phones
MP3 Players
Portable Media Players
Handheld Devices
DESCRIPTION
The bq24250, 1, 3 is a highly integrated single-cell Li-Ion battery charger and system power-path management
device targeted for space-limited, portable applications with high capacity batteries. The single cell charger has a
single input that operates from either a USB port or AC wall adapter for a versatile solution.
The power path management feature allows the bq24250, 1, 3 to power the system from a high efficiency DC/DC
converter while simultaneously and independently charging the battery. The charger monitors the battery current
at all times and reduces the charge current when the system load requires current above the input current limit.
This allows for proper charge termination and enables the system to run with a defective or absent battery pack.
Additionally, this enables instant system turn-on even with a totally discharged battery or no battery. The powerpath management architecture also permits the battery to supplement the system current requirements when the
adapter cannot deliver the peak system currents. This enables the use of a smaller adapter.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
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bq24251
bq24253
SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The battery is charged in four phases: trickle charge, pre-charge, constant current and constant voltage. In all
charge phases, an internal control loop monitors the IC junction temperature and reduces the charge current if
the internal temperature threshold is exceeded. Additionally, a voltage-based, JEITA compatible battery pack
thermistor monitoring input (TS) is included that monitors battery temperature for safe charging.
Typical Application
CPMID
1µF
PMID
IN
VIN
CIN
SW
R1
2.2µF
R2
System Load
CBOOT
33 nF
3 MHz
PWM
VDPM
LO
1.0µH
BOOT
PGND
LDO
SYS
1µF
22μF
STAT
VGPIO
BAT
1 μF
LDO
Host
SCL
SCL
SDA
SDA
GPIO1
INT
GPIO2
/CE
GPIO3
EN1
GPIO4
EN2
R3
TEMP
TS
R4
PACK+
+
RNTC
PACK-
ILIM
ISET
AVAILABLE OPTIONS
2
INT or PG
Default
VOREG
MINSYS
TS Profile
I2C or Stand
Alone
I2C Address
Device
Default OVP
D+/D- or
EN1/EN2
bq24250
10.5V
EN1/EN2
INT
4.2V
3.5V
JEITA
I2C + SA
0x6A
bq24251
10.5V
D+/D-
PG
4.2V
3.5V
JEITA
I2C + SA
0x6A
bq24253
10.5V
D+/Dand
EN1/EN2
PG
4.2V
3.5V
JEITA
SA Only
N/A
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ORDERING INFORMATION (1) (2)
Part Number
IC Marking
bq24250
bq24250
bq24251
bq24251
bq24253
(1)
(2)
(3)
bq24253
Package
Ordering Number
Quantity
DSBGA-YFF
bq24250YFFR
3000
DSBGA-YFF
bq24250YFFT
250
QFN-RGE
bq24250RGER
3000
QFN-RGE
bq24250RGET
250
DSBGA-YFF
bq24251YFFR
3000
DSBGA-YFF
bq24251YFFT
250
QFN-RGE
bq24251RGER
3000
QFN-RGE
bq24251RGET
250
DSBGA-YFF (3)
bq24253YFFR
3000
DSBGA-YFF (3)
bq24253YFFT
250
QFN-RGE
bq24253RGER
3000
QFN-RGE
bq24253RGET
250
This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for
use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including
bromine (Br) or antimony (Sb) above 0.1% of total product weight.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Preview
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
Pin Voltage Range (with
respect to GND)
UNIT
MIN
MAX
IN
–0.3
20
V
SW
–0.7
12
V
BOOT
–0.3
20
V
LDO,STAT, INT, /CHG, /PG, EN1, EN2, EN3, /CE, D+, D-, ILIM, ISET, VDPM,
TS
–0.3
7
V
SYS, BAT
–0.3
5
V
–0.3
7
V
BOOT relative to SW
Output Current
(Continuous)
IN, SW, SYS, BAT
2
A
Output Sink Current
STAT, /CHG, /PG
5
mA
Operating free-air temperature range
–40
85
°C
Junction temperature, TJ
–40
125
°C
Storage temperature, TSTG
–65
150
°C
15
W
Input Power
IN
Lead temperature (soldering, 10 s)
ESD Rating (2)
(1)
(2)
Human body model
300
°C
2
kV
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
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RECOMMENDED OPERATING CONDITIONS
All voltages are with respect to PGND if not specified. Currents are positive into, negative out of the specified terminal.
Consult Packaging Section of the data book for thermal limitations and considerations of packages
VIN
MIN
MAX
UNITS
IN voltage range
4.35
18 (1)
V
IN operating voltage range
4.35
10.5
IIN
Input current
2
A
ICHG
Current in charge mode, BAT
2
A
IDISCHG
Current in discharge mode, BAT
4
A
RISET
Charge current programming resistor range
RILIM
Input current limit programming resistor range
PIN
Input Power
TJ
Operating junction temperature range
(1)
Ω
75
Ω
105
0
12
W
125
°C
The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. Small
routing loops for the power nets in layout minimize switching noise.
THERMAL INFORMATION
bq24250/1/3
THERMAL METRIC (1)
YFF
RGE
θJA
Junction-to-ambient thermal resistance
76.5
32.9
θJCtop
Junction-to-case (top) thermal resistance
0.2
32.8
θJB
Junction-to-board thermal resistance
44
10.6
ψJT
Junction-to-top characterization parameter
1.6
0.3
ψJB
Junction-to-board characterization parameter
43.4
10.7
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
2.3
(1)
4
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS
VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = 0ºC-125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENTS
VDPM < VIN < VOVP AND VIN >
VBAT+VSLP PWM switching, CE Enable
IIN
13
mA
VDPM < VIN < VOVP AND VIN >
VBAT+VSLP PWM switching, CE
Disable
Supply current from IN
5
0°C< TJ < 85°C, High-Z Mode
IBAT
Battery discharge current in
high impedance mode, (BAT,
SW, SYS)
0°C< TJ < 85°C, VBAT = 4.2 V,
VIN = 0V or 5V, High-Z Mode
Battery discharge current in
SYSOFF mode, (BAT, SW,
SYS)
0°C< TJ < 85°C, VBAT = 4.2 V,
VIN < UVLO, SYSOFF Mode
170
225
16
22
μA
μA
1
POWER-PATH MANAGEMENT
MINSYS stage (no DPM or DPPM)
MINSYS stage (DPM or DPPM active)
VSYSREG
System Regulation Voltage
–1%
3.52
1%
–1.50%
VMINSYS
–200mV
1.50%
SYSREG stage
V
VBAT
+ ICHG Ron
BATREG stage
VBATREG
+2.1%
VBATREG
+3.1%
VBATREG
+4.1%
VSPLM
Enter supplement mode
voltage threshold
VBAT = 3.6V
VBAT –
40mV
ISPLM
Exit supplement mode current
threshold
VBAT = 3.6V
20
mA
tDGL(SC1)
Deglitch Time, OUT Short
Circuit during Discharge or
Supplement Mode
Measured from (VBAT – VSYS) = 300
mV
740
μs
tREC(SC1)
Recovery Time, OUT Short
Circuit during Discharge or
Supplement Mode
64
ms
V
BATTERY CHARGER
RON(BAT-SYS)
Internal battery charger
MOSFET on-resistance
30
Measured from BAT to SYS, VBAT =
4.2V (QFN)
30
40
3.5
SA mode or I C default mode
TJ = 0°C to 125°C
VLOWV ≤ VBAT < VBAT(REG)
Fast Charge Current Range
Set via I2C
Low Charge Current Setting
4.44
V
4.2
TJ = 25°C
Fast Charge Current Accuracy I2C mode
ICHG-LOW
mΩ
2
Voltage Regulation Accuracy
ICHG
20
Operating in voltage regulation,
Programmable Range
I2C host mode
VBATREG
Measured from BAT to SYS, VBAT =
4.2V (WCSP)
0.5%
–0.75
0.75
500
2000
–7%
7%
mA
297
330
363
mA
232.5
250
267.5
AΩ
KISET
KISET
Programmable Fast Charge
Current Factor
VISET
Maximum ISET pin voltage (in
regulation)
RISET-SHORT
Short circuit resistance
threshold
VLOWV
Pre-charge to fast charge
threshold
Rising
Hysteresis for VLOWV
Battery voltage falling
ICHG =
–0.5%
RISET
0.42
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V
45
55
75
Ω
2.9
3
3.1
V
100
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ELECTRICAL CHARACTERISTICS (continued)
VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = 0ºC-125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IPRECHG
Pr-charge current (VBATUVLO <
VBAT < VLOWV)
tDGL(LOWV)
Deglitch time for pre-charge to
fast charge transition
VBAT_UVLO
Battery Under voltage lockout
threshold
Ipre-chg is a precentile of the external
fast charge settings.
MIN
TYP
MAX
8
10
12
32
VBAT rising
2.37
Battery UVLO hysteresis
VBATSHRT
1.9
Battery voltage falling
IBATSHRT
Trickle charge mode charge
current (VBAT < VBATSHRT)
tDGL(BATSHRT)
Deglitch time for trickle charge
to pre-charge transition
2
2.63
Termination Current Threshold Termination current on SA only
Termination Current Threshold
Tolerance
35
Deglitch time for charge
termination
Both rising and falling, 2-mV overdrive, tRISE, tFALL = 100 ns
VRCH
Recharge threshold voltage
Below VBATREG
tDGL(RCH)
Deglitch time
VBAT falling below VRCH, tFALL = 100 ns
2.1
mV
50
mA
us
10
%ICHG
10
64
70
V
256
–10
tDGL(TERM)
V
mV
100
25
%
ms
200
Trickle charge to pre-charge
threshold
Hysteresis for VBATSHRT
ITERM
2.5
UNIT
115
%
ms
160
32
mV
ms
BATTERY DETECTION
VBATREG_HI
Battery Detection High
Regulation Voltage
Same as VBATREG
VBATREG
V
VBATREG_LO
Battery Detection Low
Regulation Voltage
360 mV offset from VBATREG
VBATREG
–480mV
V
VBATDET
Hi
Battery detection comparator
VBATREG = VBATREG_HI
VBATREG
–120mV
V
VBATDET
LO
Battery detection comparator
VBATREG = VBATREG_LO
VBATREG
+120mV
V
IDETECT
Battery Detection Current Sink Always on during battery detection
7.5
mA
tDETECT
Battery detection time
32
ms
Tsafe
Safety Timer Accuracy
6
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For both VBATREG_HI and VBATREG_LO
–10
+10
%
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SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS (continued)
VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = 0ºC-125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mA
INPUT PROTECTION
IIN
Input current limiting
IIN_LIMIT = 100 mA
90
95
100
IIN_LIMIT = 150 mA
135
142.5
150
IIN_LIMIT = 500 mA
450
475
500
IIN_LIMIT = 900 mA
810
860
910
IIN_LIMIT = 1500 mA
1400
1475
1550
IIN_LIMIT = 2000 mA
1850
1950
2050
ILIM =
IIN_LIMIT = External
ILIM
Maximum input current limit
programmable range for IN
input
KILIM
Maximum input current factor
for IN input
VILIM
Maximum ILIM pin voltage (in
regulation)
RILIM-SHORT
Short circuit resistance
threshold
500
ILIM = 500 mA to 2.0 A
240
mA
300
AΩ
83
V
4.2
10
I2C mode
4.2
4.76
VIN_DPM threshold with adaptor Must set to external resistor settings
current limit and VDPM
via the EN1/EN2 pins or the I2C
shorted to GND
register interface.
Ω
105
SA mode
USB100, USB150, USB500, USB900,
current limit selected. Also I2C register
default.
VIN_DPM threshold for USB
Input in SA mode
270
2000
0.42
65
VIN_DPM threshold range
VIN_DPM
KILIM
RILIM
4.27
4.36
4.45
VIN_DPM
.
–2%
VIN_DPM
VIN_DPM
.
+2%
2
%
1.2
1.25
V
V
VIN_DPM threshold Accuracy
Both I2C and SA mode
VREF_DPM
DPM regulation voltage
External resistor setting only
VDPM_SHRT
VIN_DPM short threshold
If VDPM is shorted to ground, VIN_DPM
threshold will use internal default value
IC active threshold voltage
VIN rising
IC active hysteresis
VIN falling from above VUVLO
Sleep-mode entry threshold,
VIN-VBAT
2.0 V ≤ VBAT ≤ VBATREG, VIN falling
Sleep-mode exit hysteresis,
VIN-VBAT
2.0 V ≤ VBAT ≤ VBATREG
tDGL(SLP)
Deglitch time for IN rising
above VIN+VSLP_EXIT
Rising voltage, 2-mV over drive, tRISE =
100 ns
VOVP
Input supply OVP threshold
voltage
IN rising
VOVP hysteresis
IN falling from VOVP
Deglitch time for IN Rising
above VOVP
IN rising voltage, tRISE = 100 ns
Battery OVP threshold voltage
VBAT threshold over VBATREG to turn off
charger during charge
VBOVP hysteresis
Lower limit for VBAT falling from above
VBOVP
1
%
VBATREG
BOVP Deglitch
Battery entering/exiting BOVP
1
ms
VUVLO
VSLP
tDGL(OVP)
VBOVP
tDGL(BOVP)
–2
1.15
0.3
3.15
3.35
V
3.5
V
175
mV
0
50
100
mV
40
100
160
mV
32
Input OVP
–200mV
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102.5
Input OVP
ms
Input OVP
+200mV
V
100
mV
32
ms
105
107.5
%
VBATREG
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ELECTRICAL CHARACTERISTICS (continued)
VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = 0ºC-125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
60
100
mΩ
100
150
mΩ
110
165
mΩ
3.2
3.8
A
3
3.3
MHz
PWM CONVERTER
RON(BLK)
Internal blocking MOSFET on- Measured from IN to PMID (WCSP &
resistance
QFN)
RON(HS)
Internal high-side MOSFET
on-resistance
RON(LS)
Internal low-side MOSFET on- Measured from SW to PGND (WCSP
resistance
& QFN)
ICbC
Cycle-by-cycle current limit
fOSC
Oscillator frequency
DMAX
Maximum duty cycle
DMIN
Minimum duty cycle
TSHTDWN
TREG
Measured from PMID to SW (WCSP &
QFN)
VSYS shorted
2.6
2.7
95%
0%
Thermal trip
150
Thermal hysteresis
°C
10
Thermal regulation threshold
Charge current begins to cut off
VLDO
LDO Output Voltage
VIN = 5.5 V, ILDO = 0 to 50 mA
ILDO
Maximum LDO Output Current
VDO
LDO Dropout Voltage (VIN –
VLDO)
125
LDO
4.65
4.85
5.04
50
VIN = 5.0 V, ILDO = 50 mA
V
mA
200
300
29.6
30
30.4
37.9
38.3
mV
BATTERY-PACK NTC MONITOR (1)
VHOT
High temperature threshold
VTS falling
VHYS(HOT)
Hysteresis on high threshold
VTS rising
VWARM
Warm temperature threshold
VTS falling
VHYS(WARM)
Hysteresis on warm
temperature threshold
VTS rising
VCOOL
Cool temperature threshold
VTS rising
VHSY(COOL)
Hysteresis on cool
temperature threshold
VTS falling
VCOLD
Low temperature threshold
VTS rising
VHYS(COLD)
Hysteresis on low threshold
VTS falling
VFRZ
Freeze temperature threshold
VTS rising
VHYS(FRZ)
Hysteresis on freeze threshold VTS falling
VTS_DIS
TS disable threshold
tDGL(TS)
Deglitch time on TS change
1
38.7
1
56.1
56.5
56.9
% VLDO
1
59.6
60
60.4
1
62
62.5
63
1
70
73
32
ms
INPUTS (EN1, EN2, EN2, CE, CE1, CE2, BATREG, SCL, SDA, DBP)
VIH
Input high threshold
VIL
Input low threshold
1
V
0.4
V
0.4
V
1
µA
STATUS OUTPUTS (CHG, PG, STAT, INT, BATRDY)
VOL
Low-level output saturation
voltage
IO = 5 mA, sink current
IIH
High-level leakage current
Hi-Z and 5V applies
TIMERS
45 min safety timer
tSAFETY
tWATCH-DOG
8
2700
6 hr safety timer
21600
9 hr safety timer
32400
Watch dog timer
50
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SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS (continued)
VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = 0ºC-125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
D+/D– DETECTION
IDP_SRC
D+ current source for DCD
DCD
7
13
µA
RDM_DWN
D– pull-down resistance for
DCD
DCD
14.25
24.8
kΩ
VDP_LOW
D+ low comparator threshold
for DCD
DCD
0.85
0.9
0.95
V
VDP_SRC
D+ source voltage for Primary
Detection
Primary Detection
0.5
0.6
0.7
V
IDP_SRC_PD
D+ source voltage output
current for Primary Detection
Primary Detection
200
IDM_SINK
D– sink current for Primary
Detection
Primary Detection
50
100
VDAT_REF
Primary Detection threshold
Primary Detection
250
VLGC
Primary Detection threshold
Primary Detection
0.85
VDM_SRC
D- source voltage for
Secondary Detection
Secondary Detection
0.5
IDM_SRC_PD
D- source voltage output
current for Secondary
Detection
Secondary Detection
200
IDP_SINK
D+ sink current for Secondary
Detection
Secondary Detection
50
100
150
µA
VDAT_REF
Secondary Detection threshold Secondary Detection
250
325
400
mV
VATT_LO
Apple/TomTom detection low
threshold
Apple/TomTom Detection
1.8
1.85
1.975
V
VATT_HI
Apple/TomTom detection high
threshold
Apple/TomTom Detection
3.2
3.5
4.05
V
CI
Input Capacitance
ID_LKG
Leakage Current into D+/D–
µA
150
µA
325
400
mV
0.9
0.95
V
0.6
0.7
V
µA
D– , switch open
4.5
D+, switch open
4.5
pF
D–, switch open
–1
1
D+, switch open
–1
1
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9
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SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
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BLOCK DIAGRAM
PMID
Q1
LDO
LDO
IN
Charge
Pump
Q2
VREF_CBCLIM
ILIM
_
+
BOOT
CbC
Comparator
IIN_LIM
Amp
_
VIN_DPM
Amp
+
VDPM
+
VREF_INLIM
VREF_DPM
PWM
LOOP SELECT
COMPENSATION
DRIVER
_
Host
SW
+
_
VDPM_DAC
V LDO
I2C Only
Q3
TJ
PGND
+
125C
MINSYS
Amp
_
+
ICHG
Amp
VREF_MINSYS
+
VSYSMIN
_
ISET
+
VBATREG
Amp
Sleep
Comparator
_
SYS
_
+
VREF_BATREG
VREF_ICHG
VBAT +V SLP +
VREF_TERM
EN2 / D-
+
EN1 / D+
Input
current limit
decoder /
D+ and DDecoder
LDO
Termination
Comparator
V MINSYS
Reference
Q4
Recharge Comparator
+
VBATREG – 0.12V
VBAT
SCL
MINSYS
ICHG Amp
V OUTMIN Comparator
+
SDA
BAT
+
I2C
Controller
Batt Detect Or
Precharge
Curent Source
V OUT
Charge
Pump
CHARGE
CONTROLLER
INT / PG
-
MINSYS Comparator
+
V SYS
V MINSYS
BATSHORT Comparator
STAT/CHG
,
+
V BAT
VBATSHRT
Supplement Comparator
VSYS
+
DISABLE
VBAT
V BSUP
VLDO
+
/CE
TS -10°C
+
TS 0°C
+
TS 10 °C
+
TS 45 °C
+
TS 60°C
TS
10
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SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
SYS
PGND
SW
IN
B
BAT
SYS
PGND
SW
IN
C
BAT
SYS
PGND
SW
IN
20
19
CE
1
18
SW
EN1
2
17
SW
EN2
3
16
PGND
AGND
4
15
PGND
SDA
5
14
SYS
SCL
6
13
SYS
1
18
SW
D+
2
17
SW
D–
3
16
PGND
AGND
4
15
PGND
SDA
5
14
SYS
SCL
6
13
SYS
18
SW
bq24250
QFN
PMID
F
TS
SDA
PGND
LDO
ILIM
7
8
9
10
11
12
IN
BOOT
BAT
VDPM
BAT
STAT
PMID
SCL
ISET
INT
BOOT
E
TS
/CE
21
ILIM
EN1
22
INT
EN2
23
VDPM
ISET
24
STAT
D
IN
BAT
PMID
5
BOOT
4
ILIM
3
VDPM
2
LDO
A
1
LDO
PIN OUTS
24
23
22
21
20
19
bq24250 WCSP
A
1
2
BAT
SYS
B
BAT
C
BAT
D
ISET
SYS
SYS
D-
3
4
5
PGND
SW
IN
PGND
PGND
D+
SW
SW
/CE
IN
CE
IN
PMID
E
/PG
SCL
STAT
VDPM
BOOT
F
TS
SDA
PGND
LDO
ILIM
bq24251
QFN
ISET
BAT
BAT
PMID
IN
24
23
22
21
20
19
STAT
BOOT
12
TS
11
ILIM
10
PG
9
VDPM
8
LDO
7
bq24251 WCSP
C
BAT
D
ISET
SYS
SYS
D-
SW
IN
PGND
PGND
D+
SW
SW
/CE
IN
CE
1
D+
2
17
SW
D–
3
16
PGND
AGND
4
15
PGND
EN1
5
14
SYS
EN2
6
13
SYS
IN
PMID
E
/PG
EN2
/CHG
VDPM
BOOT
F
TS
EN1
PGND
LDO
ILIM
bq24253
QFN
7
8
9
10
11
12
BAT
BAT
PGND
BAT
B
5
ISET
SYS
4
TS
BAT
3
PG
2
CHG
A
1
bq24253 WCSP
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PIN DESCRIPTIONS
PIN
NAME
bq24250
bq24250
bq24251
bq24251
bq24253
bq24253
YFF
RGE
YFF
RGE
YFF
RGE
IN
A5,B5,C5
19
A5,B5,C5
19
A5,B5,C5
D5
20
D5
20
A4, B4,
C4
17–18
A4, B4,
C4
BOOT
E5
21
PGND
A3, B3,
C3, F3
I/O
DESCRIPTION
19
I
Input power supply. IN is connected to the
external DC supply (AC adapter or USB port).
Bypass IN to PGND with >2μF ceramic capacitor
D5
20
I
Connection between blocking FET and high-side
FET.
17–18
A4, B4,
C4
17–18
O
Inductor Connection. Connect to the switching
side of the external inductor.
E5
21
E5
21
I
High Side MOSFET Gate Driver Supply. Connect
a 0.033μF ceramic capacitor (voltage rating >
15V) from BOOT to SW to supply the gate drive
for the high side MOSFETs.
15–16
A3, B3,
C3, F3
15–16
A3, B3,
C3, F3
15–16
Ground terminal. Connect to the ground plane of
the circuit.
SYS
A2, B2,
C2
13–14
A2, B2,
C2
13–14
A2, B2,
C2
13–14
System Voltage Sense and SMPS output filter
connection. Connect SYS to the system output at
the output bulk capacitors. Bypass SYS locally
with >20μF.
BAT
A1, B1,
C1
11–12
A1, B1,
C1
11–12
A1, B1,
C1
11–12
PMID
SW
TS
F1
9
F1
9
F1
9
I
Battery Connection. Connect to the positive
I/O terminal of the battery. Additionally, bypass BAT
with a >1μF capacitor.
I
Battery Pack NTC Monitor. Connect TS to the
center tap of a resistor divider from LDO to GND.
The NTC is connected from TS to GND. The TS
function provides 4 thresholds for JEITA or PSE
compatibility. See the NTC Monitor section for
more details on operation and selecting the
resistor values.
VDPM
E4
23
E4
23
E4
23
I
Input DPM Programming Input. Connect a resistor
divider between IN and GND with VDPM
connected to the center tap to program the Input
Voltage based Dynamic Power Management
threshold (VIN_DPM). The input current is reduced
to maintain the supply voltage at VIN_DPM. The
reference for the regulator is 1.23V. Short pin to
GND if external resistors are not desired—this
sets a default of 4.36V for the input DPM
threshold.
ISET
D1
10
D1
10
D1
10
I
Charge Current Programming Input. Connect a
resistor from ISET to GND to program the fast
charge current. The charge current is
programmable from 300mA to 2A.
ILIM
F5
22
F5
22
F5
22
I
Input Current Limit Programming Input. Connect a
resistor from ILIM to GND to program the input
current limit for IN. The current limit is
programmable from 0.5A to 2A. ILIM has no
effect on the USB input. If an external resistor is
not desired, short to GND for a 2A default setting.
CE
D4
1
D4
1
D4
1
I
Charge Enable Active-Low Input. Connect CE to
a high logic level to place the battery charger in
standby mode.
EN1
D3
2
–
–
F2
5
I
EN2
D2
3
–
–
E2
6
I
CHG
12
–
–
–
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–
E3
7
O
Input Current Limit Configuration Inputs. Use
EN1, and EN2 to control the maximum input
current and enable USB compliance. See Table 1
for programming details.
Charge Status Open Drain Output. CHG is pulled
low when a charge cycle starts and remains low
while charging. CHG is high impedance when the
charging terminates and when no supply exists.
CHG does not indicate recharge cycles.
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SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
PIN DESCRIPTIONS (continued)
PIN
NAME
PG
STAT
bq24250
bq24250
bq24251
bq24251
bq24253
bq24253
YFF
RGE
YFF
RGE
YFF
RGE
–
E3
–
7
E1
8
E3
7
E1
–
8
–
I/O
DESCRIPTION
O
Power Good Open Drain Output. PG is pulled low
when a valid supply is connected to IN. A valid
supply is between VBAT+VSLP and VOVP. If no
supply is connected or the supply is out of this
range, PG is high impedance.
O
Status Output. STAT is an open-drain output that
signals charging status and fault interrupts. STAT
pulls low during charging. STAT is high
impedance when charging is complete or the
charger is disabled. When a fault occurs, a 256μs
pulse is sent out as an interrupt for the host.
STAT is enabled/disabled using the EN_STAT bit
in the control register. STAT will indicate recharge
cycles. Connect STAT to a logic rail using an LED
for visual indication or through a 10kΩ resistor to
communicate with the host processor.
INT
E1
8
–
–
–
–
O
Status Output. INT is an open-drain output that
signals charging status and fault interrupts. INT
pulls low during charging. INT is high impedance
when charging is complete or the charger is
disabled. When a fault occurs, a 256μs pulse is
sent out as an interrupt for the host. INT will
indicate recharge cycles. Connect INT to a logic
rail through a 10kΩ resistor to communicate with
the host processor.
SCL
E2
6
E2
6
–
–
I
I2C Interface Clock. Connect SCL to the logic rail
through a 10kΩ resistor.
SDA
F2
5
F2
5
–
–
I/O
I2C Interface Data. Connect SDA to the logic rail
through a 10kΩ resistor.
D+
–
–
D3
2
D3
2
I
D–
–
–
D2
3
D2
3
I
F4
24
F4
24
F4
24
O
–
4
–
4
–
4
LDO
AGND
BC1.2 compatible D+/D– Based Adapter
Detection. Detects DCP, SDP, and CDP. Also
complies with the unconnected dead battery
provision clause. D+ and D- are connected to the
D+ and D– outputs of the USB port at power up.
Also includes the detection of Apple™ and
TomTom™ adapters where a 500mA input
current limit is enabled. The PG pin will remain
low until the detection has completed.
LDO output. LDO is regulated to 4.9V and drives
up to 50mA. Bypass LDO with a 1μF ceramic
Capacitor. LDO is enabled when VUVLO < VIN
<18V.
Analog Ground for QFN only. Connect to the
thermal pad and the ground plane of the circuit.
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TYPICAL APPLICATION CIRCUITS
CPMID
1µF
PMID
IN
VIN
CIN
SW
R1
2.2 µF
VDPM
R2
LO
1.0PH
System Load
CBOOT
33 nF
3 MHz
PWM
BOOT
PGND
LDO
SYS
1 PF
22 F
Charge Controller
STAT
VGPIO
BAT
1 F
LDO
SCL
SCL
SDA
SDA
GPIO1
INT
GPIO2
/CE
R3
TEMP
TS
R4
Host
GPIO3
EN1
GPIO4
EN2
PACK+
+
RNTC
PACK-
ILIM
ISET
Figure 1. bq24250 Typical Application Circuit
14
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SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
CPMID
1µF
LO
1.0PH
PMID
IN
VBUS
DD+
GND
SW
System Load
CIN
R1
2.2 µF
VDPM
R2
CBOOT
33 nF
3 MHz
PWM
BOOT
PGND
D-
SYS
22 F
D+
VSYS
LDO
1 PF
BAT
/PG
1 F
LDO
VGPIO
R3
TEMP
TS
SCL
SCL
SDA
SDA
Host GPIO1
PACK+
+
RNTC
R4
PACK-
STAT
GPIO2
/CE
ILIM
ISET
Figure 2. bq24251 Typical Application Circuit
CPMID
1µF
PMID
IN
VBUS
DD+
GND
SW
LO
1.0PH
System Load
CIN
2.2 µF
R1
VDPM
R2
CBOOT
33 nF
3 MHz
PWM
BOOT
PGND
D-
VSYS
SYS
22 F
D+
LDO
1 PF
BAT
/CHG
1 F
LDO
/PG
R3
TEMP
TS
GPIO
EN1
GPIO
EN2
GPIO
/CE
R4
Host
PACK+
+
RNTC
PACK-
ILIM
ISET
Figure 3. bq24253 Typical Application Circuit
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SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
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TYPICAL CHARACTERISTICS
.
Battery Detection
VBAT = 3.8 V
VIN = 5 V
VREG = 4.2 V
ICHG = 0.5 A
ILIM = 1 A
Figure 4.
Battery Removal
VBAT = 3.8 V
VIN = 6 V
VREG = 4.2 V
ICHG = 1 A
ILIM = 1 A
Figure 5.
16
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SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
TYPICAL CHARACTERISTICS (continued)
.
Efficiency
vs
Battery Voltage
System Voltage Regulation
vs
Load Current
4.350
88
ICHG = 2 A
VIN = 5 V
VREG = 4.2 V
86
4.340
4.335
82
VSYS-REG (V)
Efficiency (%)
84
4.345
80
78
76
4.330
4.325
4.320
74
4.310
72
4.305
bq24250
70
4.300
2.9
3.1
3.3
3.5
3.7
3.9
4.1
VBAT (V)
0.0
4.3
0.5
1.0
Figure 7.
Efficiency
vs
Output Current
Efficiency
vs
Output Current
95
90
90
85
85
Efficiency (%)
100
80
75
70
2.0
2.5
C004
Figure 6.
95
65
80
75
70
65
60
VIN ==55V
V
VIN
60
55
VIN ==77V
V
VIN
55
VREG = 4.2 V
VIN ==10
V
VIN
10V
50
0
200
400
600
VIN ==55V
V
VIN
VIN ==77V
V
VIN
VREG = 3.6 V
VIN ==10
V
VIN
10V
50
800 1000 1200 1400 1600 1800 2000
Output Current (mA)
0
200
400
600
800 1000 1200 1400 1600 1800 2000
Output Current (mA)
C002
Figure 8.
C003
Figure 9.
BAT IQ, SYSOFF = 0
BAT IQ, SYSOFF = 1
18
0.7
VIN = 0 V
Charge Enabled
SYSOFF = 0
BAT & SYS are Shorted
16
14
12
VIN = 0 V
Charge Enabled
SYSOFF = 1
BAT & SYS are Shorted
0.6
0.5
10
IBAT ( A)
IBAT ( A)
1.5
ISYS (A)
C001
100
Efficiency (%)
VIN = 5 V
No Battery
ILIM = 2 A
VREG = 4.2 V
No Bat
Charge Disable
4.315
8
6
4
0.4
0.3
0.2
2
0.1
0
0.0
±2
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VBAT (V)
4.0
4.5
5.0
0.0
0.5
1.0
C007
Figure 10.
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VBAT (V)
5.0
C010
Figure 11.
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bq24251
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SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
.
Input IQ With Charge DIS and EN
20
CE EN
Charge EN and DIS
No Battery and System
18
Input IQ with Charge Enable and Hi-Z
500
400
Input Current ( A)
16
Input Current (mA)
Charge EN
Hi-Z EN
450
CE DIS
14
12
10
8
6
350
300
250
200
150
4
100
2
50
0
0
0
5
10
15
20
25
Input Voltage (V)
0
5
10
Figure 12.
2.0
1.0
0.5
0.0
±1.0
1.0
0.5
0.0
500 mA
1A
1.5 A
±1.0
±1.5
10 20 30 40 50 60 70 80 90 100 110 120 130
Temperature (ƒC)
1.5
±0.5
500 mA
1A
1.5 A
±0.5
0
C009
VBAT = 3.8 V
ILIM = 2 A
VIN = 5 V
VREG = 4.2 V
2.5
Accuracy (%)
Accuracy (%)
1.5
25
ICHG Accuracy with Internal Settings, VBAT = 3.8 V
3.0
VBAT = 3.3 V
ILIM = 2 A
VIN = 5 V
VREG = 4.2 V
2.0
20
Figure 13.
ICHG Accuracy with Internal Settings, VBAT = 3.3 V
2.5
15
Input Voltage (V)
C008
0
10 20 30 40 50 60 70 80 90 100 110 120 130
Temperature (ƒC)
C011
Figure 14.
Figure 15.
Startup
Input OVP Event with INT
C012
ICHG = 1 A
ILIM = 1 A
VBAT = 3.9 V
VOVP = 10.5 V
ICHG = 1 A
ILIM = 1.5 A
ISYS = 0 A
VBAT = 3.6 V
Figure 16.
18
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Figure 17.
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bq24253
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SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
TYPICAL CHARACTERISTICS (continued)
.
VDPM Startup, 4.2 V
1.0 µH CCM Operation
ICHG = 2 A
ILIM = 0.5 A
ISYS = 0 A
VBAT = 3.6 V
VDPM = 4.36 V
ICHG = 1 A
ISYS = 0 A
VBAT = 3.3 V
VIN = 5.2 V
Figure 18.
Figure 19.
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bq24251
bq24253
SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
www.ti.com
CHARGE PROFILE
The bq2425x family provides a switch-mode buck regulator with output power path and a charge controller to
provide optimum performance over the full battery charge cycle. The control loop for the buck regulator has 7
primary feedback loops that can set the duty cycle:
1. Constant Current (CC)
2. Constant Voltage (CV)
3. Minimum System Voltage (MINSYS)
4. Input Current (IILIM)
5. Input Voltage (VIN_DPM)
6. Die Temperature
7. Cycle by Cycle Current
The feedback with the minimum duty cycle will be chosen as the active loop. The bq24250, 1, 3 support a
precision Li-Ion or Li-Polymer charging system for single-cell applications. The Dynamic Power Path
Management (DPPM) feature regulates the system voltage to a minimum of VMINSYS, so that startup is enabled
even with a missing or deeply discharged battery. This provides a much better overall user experience in mobile
applications. The figure below illustrates a typical charge profile while also demonstrating the minimum system
output voltage regulation.
Trickle
Charge
Precharge
Current Regulation
Phase(CC)
Voltage Regulation
Phase(CV)
Termination
V BATREG
I CHG
V MINSYS
(3.5V)
ICHG
VSYS
VBAT
V LOWV
V BATSHRT
I PRECHG
I TERM
I BATSHRT
Linear trickle
Linear
charge
Pre- charge
MINSYS
regulation
Linear
fast charger
BATFET on-- PWM fast charge
BATFET off
BATREG
regulation
SYSREG
regulation
Figure 20 demonstrates a measured charge profile with the bq2425X while charging a 2700mAh Li-Ion battery at
a charge rate of 1A.
20
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SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
5.0
1.2
ICHG = 1 A
4.5
1.1
0.9
Voltage (V)
3.5
0.8
3.0
0.7
2.5
0.6
2.0
0.5
0.4
1.5
1.0
0.5
V
VBAT
BAT
0.3
VSYS
V
SYS
0.2
0.1
IIBAT
BAT
0.0
0
2k
4k
6k
Charge Current (A)
1.0
4.0
8k
10k
12k
14k
0.0
16k
Time (s)
C005
Figure 20. bq24250 Charge Profile while Charging a 2700 mAh Battery at a 1A Charge Rate
Figure 21 illustrates the precharge behavior of the above charge profile by narrowing the time axis to 0 – 120
seconds.
3.7
1.2
ICHG = 1 A
1.1
1.0
Voltage (V)
0.9
3.3
0.8
0.7
3.1
0.6
0.5
2.9
0.4
V
VBAT
BAT
2.7
0.3
V
VSYS
SYS
0.2
IIBAT
BAT
0.1
2.5
Charge Current (A)
3.5
0.0
0
20
40
60
80
100
Time (s)
120
C006
Figure 21. bq24250 Charge Profile While Charging a 2700-mAh Battery at a 1A Charge During Precharge
EN1/EN2 PINS
The bq24250 is I2C and Stand Alone part. The EN1 and EN2 pins are available in this IC spin to support USB
2.0 compliance. These pins are used for Input Current Limit Configuration I. Set EN1 and EN2 to control the
maximum input current and enable USB compliance. See Table 1 below for programming details.
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The bq24251 is also an I2C and Stand Alone part. The EN1 and EN2 are not available for this spin but the D+/Dare available to support the BC1.2 D+/D- Based Adapter Detection. It detects DCP, SDP, and CDP. Also it
complies with the unconnected dead battery provision clause. D+ and D- pins are connected to the D+ and Doutputs of the USB port at power up. Also includes the detection of AppleTM and TomTomTM adapters where a
500mA input current limit is enabled. The /PG pin will remain high impedance state until the detection is
completed.
The bq24253 is only Stand Alone part. Both of the D+/D- and EN1/EN2 are available for this spin. During power
up, the device checks first for the D+/D-. The EN1 and EN2 do not take effect until D+/D- detection routine is
over and a change on the status of the EN1 and EN2 occurred.
When the input current limit pins change state, the VIN_DPM threshold changes as well. See Table 1 for the
detailed truth table:
Table 1. EN1, and EN2 Truth Table (1)
(1)
EN2
EN1
0
0
500mA
Input Current Limit
4.36V
VIN_DPM Threshold
0
1
Externally programmed by ILIM (up to 2.0A)
Externally programmed VDPM
1
0
100mA
4.36V
1
1
Input Hi-Z
None
USB3.0 support available. Contact your local TI representative for details.
I2C Operation (Host Mode / Default Mode)
There are two primary modes of operation when interacting with the charge parameters of the bq24250 and
bq24251 chargers: 1) Host mode operation where the I2C registers set the charge parameters, and 2) Default
mode where the register defaults set the charge parameters.
Figure 22 illustrates the behavior of the bq24250 when transitioning between host mode and stand alone mode:
22
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Battery or Input
is Inserted
No
VIN or VBAT GOOD?
Yes
i2c command received?
No
ILIM=EN1/EN2
VDPM=External Default
ISET=External Default
Yes
ILIM=Register Value
VDPM=Register Value
ISET=Register Value
No
32s Watchdog Expired?
Yes
Host Mode
Figure 22. Host Mode and Stand Alone Mode Handoff
Once the battery or input is inserted and above the good thresholds, the device determines if an I2C command
has been received in order to discern whether to operate from the I2C registers or the internal register defaults. In
stand-alone mode the input current limit is set by the EN1/EN2 pins. If the watch dog timer is enabled, the device
will enter stand alone operation once the watchdog timer expires and re-initiate the default charge settings.
External Settings: ISET, ILIM and VIN_DPM
If the external resistor settings are used, the following equations can be followed to configure the charge settings.
The fast charge current resistor (RISET) can be set by using the following formula:
K
250
RISET = ISET =
IFC
IFC
(1)
Where IFC is the desired fast charge current setting in Amperes.
The input current limit resistor (RILIM) can be set by using the following formula:
K
270
RILIM = ILIM =
IIC
IIC
(2)
Where IIC is the desired input current limit in Amperes.
Based on the application diagram reference designators, the resistor R1 and R2 can be calculated as follows to
set VIN_DPM:
R + R2
R + R2
= 1.2V ´ 1
VIN _ DPM = VREF _ DPM ´ 1
R2
R2
(3)
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VIN_DPM should be chosen first along with R1. Choosing R1 first will ensure that R2 will be greater than the
resistance chosen. This is the case since VIN_DPM should be chosen to be greater than 2x VREF_DPM.
If external resistors are not desired in order to reduce the BOM count, the VDPM and the ILIM pins can be
shorted to set the internal defaults. The ISET resistor must be floated in order to avoid an internal fault detection.
Note that floating the ILIM pin will result in zero charge current if the external ISET is configured via the I2C
register. Table 2 summarizes the settings when the ILIM, ISET, and VIN_DPM pins are shorted to GND:
Table 2. ILIM, VDPM, and ISET Short Behaviors
PIN SHORTED
BEHAVIOR
ILIM
Input current limit = 2A
VDPM
VIN_DPM = 4.36V
ISET
Fault—Charging Suspended
BC1.2 D+/D– Detection
The bq24251 and the bq24253 include a fully BC1.2 compatible D+/D– source detection. This detection supports
the following types of ports:
• DCP (dedicated charge port)
• CDP (charging downstream port)
• SDP (standard downstream port)
• Apple™/TomTom™ ports
This D+/D– detection algorithm does not support ACA (accessory charge adapter) identification, but the input
current will default to 500mA when a charge port is attached to the ACA and bq24251/3 is connected to the OTG
port.
The D+/D– detection algorithm is only active when the device is in standalone mode (e.g. the host is not
communicating with the device and the watch dog timer has expired). However, when the device is in host mode
(e.g. host is communicating via I2C to the device) writing a ‘1’ to register 0x04 bit location 4 (DPDM_EN) forces
the device to perform a D+/D– detection on the next power port insertion. This allows the D+/D– detection to be
enabled in both host mode and default mode.
As described previously, the bq24253 is only a Stand Alone part. Both of the D+/D- and EN1/EN2 are available
for this spin. The below flow diagram illustrates the behavior of the bq24253 in D+/D- detection and the effect of
the EN1/EN2. During power up, the device checks first for the D+/D-. The EN1 and EN2 do not take effect until
D+/D- detection routine is over and a change on the status of the EN1 and EN2 occurred.
24
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Battery or Input
Is Inserted
No
VIN or VBAT Good?
Yes
Enable D+/DDetection Algorithm
Set SDP, CDP, DCP,
or Non-Standard port
settings
EN1/EN2 Change State?
No
VIN < UVLO
No
Yes
Yes
EN1/EN2 Truth Table
Becomes Active
VIN < UVLO
No
Yes
Figure 23. bq24253 D+/D- and EN1/EN2
The D+/D– detection algorithm has 5 primary states. These states are termed the following:
1. Data Contact Detect
2. Primary Detection
3. Secondary Detection
4. Non-standard Adapter Detection (for Apple™ / TomTom™)
5. Detection Configuration
The DCD state determines if the device has properly connected to the D+/D– lines. If the device is not in host
mode and VBUS is inserted (or DPDM_EN is true) the device enters the DCD state and enable the appropriate
algorithm. If the DCD timer expires, the device enters the Non-standard Adapter Detection (for Apple™ /
TomTom™) state. Otherwise it enters the Primary Detection state.
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When entering the Primary Detection state, the appropriate algorithm is enabled to determine whether to enter
the secondary detection state for DCP and CDP or the secondary detection state for SDP/Non-Standard
adaptors.
The non-standard adapter detection state for Apple™ / TomTom™ tests for the unique conditions for these nonstandard adapters. If the algorithm passes the unique conditions found with these adapters, it proceeds to the
Detection Configuration state. Otherwise it reverts back to the primary detection state.
The secondary detection state determines whether the input port is a DCP, CDP, SDP, or other non-standard
adapters. If the Primary Detection state indicated that the input port is either a DCP or CDP, the device enables
the appropriate algorithm to differentiate between the two. If the Primary Detection state indicated that the input
port is either a SDP or non-standard adapter, the device enables the appropriate algorithm to differentiate
between these two ports. Once complete, the device continues to the Detection Configuration state.
DCP
Settings
No
Yes
VBAT > VBATGD?
External ILIM
Start 6 hr timer
Yes
VBAT > VBATGD
Turn on VDP_SRC
And keep it on until
CLR_VDP is set to ‘1’ in i2c
DCP
Non
Standard
Adapter
SDP
Settings
CDP
Settings
No
Turn on VDP_SRC
And keep it on until
CLR_VDP is set to ‘1’
SDP and
weak battery
CDP and
good battery
CDP and
weak battery
IILIM=100mA
Start 45 min timer
IILIM=1500mA
Start 6 hr timer
IILIM=100mA
Start 45 min timer
SDP and
good battery
Hi-Z mode
Apple/TT or
Non-Standard
IILIM=0.5A
Start 6 hr timer
Detection Done.
Set detection
status in register
Figure 24. Detection Configuration State
The detection configuration state sets the input current limit of the device along with the charge timer. The
exception to the CDP and the SDP settings are due to the Dead Battery Provision (DBP) clause for unconnected
devices. This clause states that the device can pull a maximum of 100mA when not connected due to a dead
battery. During the battery wakeup time, the device sources a voltage on the D+ pin in order to comply with the
DBP clause. Once the battery is good, the system can clear the D+ pin voltage by writing a ‘1’ to address 0x07
bit position 4 (CLR_VDP). The device must connect to the host within 1sec of clearing the D+ pin voltage per the
DPB clause.
A summary of the input current limits and timer configurations for each charge port type are found in Table 3.
Table 3. D+/D– Detection Results per Charge Port Type
26
CHARGE PORT TYPE
INPUT CURRENT LIMIT
CHARGE TIMER
DCP
External ILIM
6 hours
45 minutes
CDP Dead Battery
100 mA
CDP Good Battery
1500 mA
6 hours
SDP Dead Battery
100 mA
45 minutes
SDP Good Battery
Hi-Z
N/A
Non-Standard
500 mA
6 hours
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Transient Response
The BQ24250/1/3 includes an advanced hybrid switch mode control architecture. When the device is regulating
the charge current (fast-charge), a traditional voltage mode control loop is used with a Type-3 compensation
network. However, the BQ24250/1/3 switches to a current mode control loop when the device enters voltage
regulation. Voltage regulation occurs in three charging conditions: 1) Minimum system voltage regulation (battery
below MINSYS), 2) Battery voltage regulation (IBAT < ICHG), and 3) Charge Done (VSYS = VBAT + 3.5%). This
architecture allows for superior transient performance when regulating the voltage due to the simplification of the
compensation when using current mode control. The below transient response plot illustrates a 0A to 2A load
step with 4.7ms full cycle and 12% duty cycle. A 3.9V Li-Ion battery is used. The input voltage is set to 5V,
charge current is set to 0.5A and the input current is limited to 0.5A. Note that a high line impedance input supply
was used to indicate a realistic input scenario (adapter and cable). This is illustrated by the change in VIN seen at
the input of the IC.
Figure 25 shows a ringing at both the input voltage and the input current. This is caused by the input current limit
speed up comparator.
Figure 25. 2A Load Step Transient
AnyBoot Battery Detection
The bq2425x family includes a sophisticated battery detection algorithm used to provide the system with the
proper status of the battery connection. The AnyBoot battery algorithm also guarantees the detection of voltage
based battery protectors that may have a long closure time (due to the hysteresis of the protection switch and the
cell capacity). The AnyBoot battery detection algorithm utilizes a dual-voltage based detection methodology
where the system rail switches between two primary voltage levels. The period of the voltage level shift is 64ms
and therefore the power supply rejection of the down-system electronics detects this shift as essentially DC.
The AnyBoot algorithm has essentially 3 states. The 1st state is used to determine if the device has terminated
with a battery attached. If it has terminated due to the battery not being present, then the algorithm moves to the
2nd and 3rd states. The 2nd and 3rd states shift the system voltage level between 4.2V and 3.72V. In each state
there are comparator checks to determine if a battery has been inserted. The two states guarantees the
detection of a battery even if the voltage of the cell is at the same level of the comparator thresholds. The
algorithm will remain in states 2 and 3 until a battery has been inserted. The flow diagram details for the Anyboot
algorithm are shown in Figure 26.
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Enter Battery
Detection
BATREG = Vreg
setting – 480mV
No
VBAT >
BATREG+120mV?
Yes
Yes
Battery Detected, STAT
register updated, and PTM
mode aborted (if enabled)
Yes
Battery Detected, STAT
register updated and
Exit Battery Detection
Yes
Battery Detected, STAT
register updated and
Exit Battery Detection
32ms Timer Expired?
No
No
25ms Timer Expired?
Yes
BATREG = 4.2V
No
VBAT < 4.08V?
Yes
32ms Timer Expired?
No
No
25ms Timer Expired?
Yes
ONLY ON FIRST LOOP ITERATION
“No Battery” Condition
BATREG = 4.2V
Update STAT Registers and send Fault Pulse
Yes
EN_PTM=1 and
NVM_EN_PTM=1?
Enter PTM mode
Exit Battery Detection
No
BATREG = 3.72V
No
VBAT > 3.84V?
Yes
32ms Timer Expired?
No
No
25ms Timer Expired?
Yes
Figure 26. AnyBoot Battery Detection Flow Diagram
28
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Input Voltage Based DPM
During normal charging process, if the input power source is not able to support the programmed or default
charging current, the supply voltage deceases. Once the supply drops to VIN_DPM, the input current limit is
reduced down to prevent the further drop of the supply. When the IC enters this mode, the charge current is
lower than the set. This feature ensures IC compatibility with adapters with different current capabilities without a
hardware change.
Sleep Mode
The bq2425x enters the low-power sleep mode if the voltage on VIN falls below sleep-mode entry threshold,
VBAT+VSLP, and VIN is higher than the under-voltage lockout threshold, VUVLO. This feature prevents draining
the battery during the absence of VIN. When VIN < VBAT+VSLP, the bq2425x turns off the PWM converter,
turns on the battery FET, sends a single 256µs pulse is sent on the STAT and INT outputs and the FAULT/STAT
bits of the status registers are updated in the I2C. Once VIN > VBAT+VSLP with the hysteresis, the FAULT bits
are cleared and the device initiates a new charge cycle.
Input Over-Voltage Protection
The bq2425x provides over-voltage protection on the input that protects downstream circuitry. The built-in input
over-voltage protection to protect the device and other components against damage from overvoltage on the
input supply (Voltage from VIN to PGND). When VIN > VOVP, the bq2425x turns off the PWM converter, turns
the battery FET, sends a single 256μs pulse is sent on the STAT and INT outputs and the FAULT/STAT bits of
the status registers and the battery/supply status registers are updated in the I2C. Once the OVP fault is
removed, the FAULT bits are cleared and the device returns to normal operation. The OVP threshold for the
bq24250 is programmable from 6.5V to 10.5V using VOVP bits in register #7.
NTC Monitor
The bq24250/1/3 includes the integration of an NTC monitor pin that complies with the JEITA specification (PSE
also available upon request). The voltage based NTC monitor allows for the use of any NTC resistor with the use
of the circuit shown in Figure 27.
LDO
R2
TS
NTC
R3
Figure 27. Voltage Based NTC circuit
The use of R3 is only necessary when the NTC does not have a beta near 3500K. When deviating from this
beta, error will be introduced in the actual temperature trip thresholds. The trip thresholds are summarized below
which are typical values provided in the specification table.
Table 4. Ratiometric TS Trip Thresholds for JEITA Compliant Charging
VHOT
30.0%
VWARM
38.3%
VCOOL
56.5%
VCOLD
60%
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When sizing for R2 and R3, it is best to solve two simultaneous equations that ensure the temperature profile of
the NTC network will cross the VHOT and VCOLD thresholds. The accuracy of the VWARM and VCOOL thresholds will
depend on the beta of the chosen NTC resistor. The two simultaneous equations are shown below:
%VCOLD
æ R3 RNTC
ö
TCOLD ÷
ç
ç R3 + RNTC
÷
TCOLD ø
= è
´ 100
æ R3 RNTC
ö
TCOLD ÷
ç
+ R2
ç R3 + RNTC
÷
TCOLD ø
è
%VHOT
æ R3 RNTC
ö
THOT ÷
ç
ç R3 + RNTC
÷
THOT ø
= è
´ 100
æ R3 RNTC
ö
THOT ÷
ç
+ R2
ç R3 + RNTC
÷
THOT ø
è
(4)
Where the NTC resistance at the VHOT and VCOLD temperatures must be resolved as follows:
(
b 1
-1
TCOLD To
RNTC
TCOLD
RNTC
THOT
= Ro e
(
β 1
-1
THOT To
=Ro e
)
)
(5)
To be JEITA compliant, TCOLD must be 0°C and THOT must be 60°C. If an NTC resistor is chosen such that the
beta is 4000K and the nominal resistance is 10kΩ, the following R2 and R3 values result from the above
equations:
R2 = 5 kΩ
R3 = 9.82 kΩ
Figure 28 illustrates the temperature profile of the NTC network with R2 and R3 set to the above values.
Example NTC Network Profile of %LDO vs. TEMP
60
Tcool
LDO Percent (%)
55
50
45
40
Twarm
35
30
0
10
20
30
40
50
60
Temperature (C)
Figure 28. Voltage Based NTC Circuit Temperature Profile
For JEITA compliance, the TCOOL and TWARM levels are to be 10°C and 45°C respectively. However, there is
some error due to the variation in beta from 3500K. As shown above, the actual temperature points at which the
NTC network crosses the VCOOL and VWARM are 13°C and 47°C respectively. This error is small but should be
considered when choosing the final NTC resistor.
Once the resistors are configured, the internal JEITA algorithm will apply the below profile at each trip point for
battery voltage regulation and charge current regulation.
30
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4.25V max
4.20V typ
4.10V max
4.06V typ
Charge voltage
No charge
No charge
V BATREG
Maximum Charge Current: 1C
0.5C
Charge current
No charge
No charge
ICHG
0°C
(cold)
10°C
(cool)
Temperature
45°C
(warm)
60°C
(hot)
Figure 29. JEITA Profile for Voltage and Current Regulation Loops
Dynamic Power Path Management
The bq24250/1/3 features a SYS output that powers the external system load connected to the battery. This
output is active whenever a valid source is connected to IN or BAT. The following discusses the behavior of SYS
with a source connected to the supply or a battery source only.
When a valid input source is connected to the input and the charge is enabled, the charge cycle is initiated. In
case of VBAT > ~3.5V, the SYS output is connected to VBAT. If the SYS voltage falls to VMINSYS, it is
regulated to the VSYSREG threshold to maintain the system output even with a deeply discharged or absent
battery. In this mode, the SYS output voltage is regulated by the buck converter and the battery FET is linearly
regulated to regulate the charge current into the battery. The current from the supply is shared between charging
the battery and powering the system load at SYS.
The dynamic power path management (DPPM) circuitry of the bq24250/1/3 monitors the current limits
continuously and if the SYS voltage falls to the VMINSYS voltage, it adjusts charge current to maintain the
minimum system voltage and supply the load on SYS. If the charge current is reduced to zero and the load
increases further, the bq24250/1/3 enters battery supplement mode. During supplement mode, the battery FET is
turned on and the battery supplements the system load.
If the battery is ever 5% above the regulation threshold, the battery OVP circuit shuts the PWM converter off and
the battery FET is turned on to discharge the battery to safe operating levels. Battery OVP FAULT is shown in
the I2C FAULT registers.
When no input source is available at the input and the battery is connected, the battery FET is turned on similar
to supplement mode. The battery must be above VBATUVLO threshold to turn on the SYS output. In this mode,
the current is not regulated; however, there is a short circuit current limit. If the short circuit limit is reached, the
battery FET is turned off for the deglitch time. After the deglitch time, the battery FET is turned on to test and see
if the short has been removed. If it has not, the FET turns off and the process repeats until the short is removed.
This process is to protect the internal FET from over current.
Production Test Mode
To aid in end mobile device product manufacturing, the bq2425x includes a Production Test Mode (PTM), where
the device is essentially a DC-DC buck converter. In this mode the input current limit to the charger is disabled
and the output current limit is limited only by the inductor cycle-by-cycle current (e.g. 3.5A). The PTM mode can
be used to test systems with high transient loads such as GSM transmission without the need of a battery being
present.
As a means of safety, the Anyboot algorithm will determine if a battery is not present at the output prior to
enabling the PTM mode. If a battery is present and the software attempts to enter PTM mode, the device will not
enable PTM mode.
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Safety Timer
At the beginning of charging process, the bq24250/1/3 starts the safety timer. This timer is active during the
entire charging process. If charging has not terminated before the safety timer expires, the IC enters suspend
mode where charging is disabled. The safety timer time is selectable using the I2C interface. A single 256μs
pulse is sent on the STAT and INT outputs and the FAULT/ bits of the status registers are updated in the I2C.
This function prevents continuous charging of a defective battery if the host fails to reset the safety timer. The
safety timer runs at 2x the normal rate under the following conditions: Pre-charge or linear mode (minimum
system voltage mode), during thermal regulation where the charge current is reduced, during TS fault where the
charge current reduced due to temperature rise on the battery, input current limit. The safety timer is suspended
during OVP, TS fault where charge is disabled, thermal shut down, and sleep mode.
Watchdog Timer
In addition to the safety timer, the bq24250/1 contains a 50-second watchdog timer that monitors the host
through the I2C interface. Once a write is performed on the I2C interface, a watchdog timer is reset and started.
The watchdog timer can be disabled by writing “0” on WD_EN bit of register #1. Writing “1” on that bit enables it
and reset the timer.
If the watchdog timer expires, the IC enters DEFAULT mode where the default charge parameters are loaded
and charging continues. The I2C may be accessed again to re-initialize the desired values and restart the
watchdog timer as long as the safety timer has not expired. Once the safety timer expires, charging is disabled.
Thermal Regulation and Thermal Shutdown
During the charging process, to prevent overheat of the chip, bq24250/1/3 monitors the junction temperature, TJ,
of the die and begins to taper down the charge current once TJ reaches the thermal regulation threshold, TREG.
The charge current is reduced when the junction temperature increases above TREG. Once the charge current is
reduced, the system current is reduced while the battery supplements the load to supply the system. This may
cause a thermal shutdown of the IC if the die temperature rises too. At any state, if TJ exceeds TSHTDWN,
bq2425x suspends charging and disables the buck converter. During thermal shutdown mode, PWM is turned
off, all safety timers are suspended, and a single 256μs pulse is sent on the STAT and INT outputs and the
FAULT/STAT bits of the status registers are updated in the I2C. A new charging cycle begins when TJ falls below
TSHTDWN by approximately 10°C.
Fault Modes
The bq2425x family includes several hardware fault detections. This allows for specific conditions that could
cause a safety concern to be detected. With this feature, the host can be alleviated from monitoring unsafe
charging conditions and also allows for a “fail-safe” if the host is not present. The table below summarizes the
faults that are detected and the resulting behavior.
32
FAULT CONDITION
CHARGER BEHAVIOR
SAFETY TIMER BEHAVIOR
Input OVP
VSYS and ICHG Disabled
Suspended
Input UVLO
VSYS and ICHG Disabled
Reset
Sleep (VIN < VBAT)
VSYS and ICHG Disabled
Suspended
TS Fault (Batter Over Temp)
VSYS Active and ICHG Disabled
Suspended
Thermal Shutdown
VSYS and ICHG Disabled
Suspended
Timer Fault
VSYS Active and ICHG Disabled
Reset
No Battery
VSYS Active and ICHG Disabled
Suspended
ISET Short
VSYS Active and ICHG Disabled
Suspended
Input Good
VSYS and ICHG Disabled
Suspended
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SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
Register Mapping and Description
Register #1
Memory location: 00, Reset state: x0xx xxxx
BIT
•
•
•
•
NAME
READ/WRITE
FUNCTION
B7(MSB)
WD_FAULT
Read only
Read:0 – No fault
1 – WD timeout if WD enabled
B6
WD_EN
Read/Write
0 – Disable
1 – Enable (also resets WC timer)
B5
STAT_1
Read only
B4
STAT_0
Read only
B3
FAULT_3
Read only
B2
FAULT_2
Read only
B1
FAULT_1
Read only
B0(LSB)
FAULT_0
Read only
00 –
01 –
10 –
11 –
Ready
Charge in progress
Charge done
Fault
0000 –
0001 –
0010 –
0011 –
0100 –
0101 –
0110 –
0111 –
1000 –
1001 –
1010 –
Normal
Input OVP
Input UVLO
Sleep
Battery Temperature (TS) Fault
Battery OVP
Thermal Shutdown
Timer Fault
No Battery connected
ISET short
Input Fault and LDO low
WD_FAULT – ‘0’ indicates no watch dog fault has occurred, where a ‘1’ indicates a fault has previously
occurred.
WD_EN – Enables or disables the internal watch dog timer. A ‘1’ enables the watch dog timer and a ‘0’
disables it.
STAT – Indicates the charge controller status.
FAULT – Indicates the faults that have occurred. If multiple faults occurred, they can be read by sequentially
addressing this register (e.g. reading the register 2 or more times). Once all faults have been read and the
device is in a non-fault state, the fault register will show “Normal”. Regarding the "Input Fault & LDO Low" the
IC indicates this if LDO is low and at the same time the input is below UVLO or coming out of UVLO with
LDO still low.
Register #2
Memory location: 01, Reset state: 1010 1100
BIT
NAME
READ/WRITE
FUNCTION
B7(MSB)
Reset
Write only
B6
IIN_ILIMIT_2
Read/Write
B5
IIN_ILIMIT_1
Read/Write
B4
IIN_ILIMIT
_0
Read/Write
B3
EN_STAT
Read/Write
0 – Disable STAT function
1 – Enable STAT function
B2
EN_TERM
Read/Write
0 – Disable charge termination
1 – Enable charge termination
B1
CE
Read/Write
0 – Charging is enabled
1 – Charging is disabled
B0 (LSB)
HZ_MODE
Read/Write
0 – Not high impedance mode
1 – High impedance mode
Write:
1 – Reset all registers to default values
0 – No effect
000 – USB2.0 host with 100mA current limit
001 – USB3.0 host with 150mA current limit
010 – USB2.0 host with 500mA current limit
011 – USB3.0 host with 900mA current limit
100 – Charger with 1500mA current limit
101 – Charger with 2000mA current limit
110 – External ILIM current limit(5)
111- No input current limit with internal clamp at 3A (PTM MODE)
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IIN_LIMIT – Sets the input current limit level. When in host mode this register sets the regulation level. However,
when in standalone mode (e.g. no I2C writes have occurred after power up or the WD timer has expired) the
external resistor setting for IILIM sets the regulation level.
EN_STAT – Enables and disables the STAT pin. When set to a ‘1’ the STAT pin is enabled and function
normally. When set to a ‘0’ the STAT pin is disabled and the open drain FET is in HiZ mode.
EN_TERM – Enables and disables the termination function in the charge controller. When set to a ‘1’ the
termination function will be enabled. When set to a ‘0’ the termination function will be disabled. When
termination is disabled, there are no indications of the charger terminating (i.e. STAT pin or STAT registers).
CE – The charge enable bit which enables or disables the charge function. When set to a ‘0’, the charger
operates normally. When set to a ‘1’, the charger is disables by turning off the BAT FET between SYS and
BAT. The SYS pin continues to stay active via the switch mode controller if an input is present.
HZ_MODE – Sets the charger IC into low power standby mode. When set to a ‘1’, the switch mode controller
is disabled but the BAT FET remains ON to keep the system powered. When set to a ‘0’, the charger
operates normally.
Register #3
Memory location: 02, Reset state: 1000 1111
(1)
•
•
BIT
NAME
READ/WRITE
B7(MSB)
VBATREG_5 (1)
Read/Write
Battery Regulation Voltage: 640mV (default 1)
FUNCTION
B6
VBATREG_4 (1)
Read/Write
Battery Regulation Voltage: 320mV (default 0)
B5
VBATREG_3 (1)
Read/Write
Battery Regulation Voltage: 160mV (default 0)
B4
VBATREG_2 (1)
Read/Write
Battery Regulation Voltage: 80mV (default 0)
B3
VBATREG_1
(1)
Read/Write
Battery Regulation Voltage: 40mV (default 1)
B2
VBATREG_0 (1)
Read/Write
Battery Regulation Voltage: 20mV (default 1)
B1(4)(5)
USB_DET_1/EN1
Read Only
B0(LSB)
USB_DET_0/EN0
Read Only
Return USB detection result or pin EN1/EN0 status –
00 – DCP detected / EN1=0, EN0=0
01 – CDP detected / EN1=0, EN0=1
10 – SDP detected / EN1=1, EN0=0
11 – Apple/TT or non-standard adaptor detected / EN1=1, EN0=1
Charge voltage range is 3.5V—4.44V with the offset of 3.5V and step of 20mV (default 4.2V)
VBATREG – Sets the battery regulation voltage
USB_DET/EN – Provides status of the D+/D– detection results for spins that include the D+/D– pins or the
state of EN1/EN2 for spins that include the EN1/EN2 pins
Register #4
Memory location: 03, Reset state: 0000 0000
BIT
(1)
(2)
(3)
34
NAME
READ/WRITE
FUNCTION
B7(MSB)
ICHG_4 (1) (2)
Read/Write
Charge current
800mA – (default 0)
B6
ICHG_3 (1) (2)
Read/Write
Charge current:
400mA – (default 0)
B5
ICHG_2 (1) (2)
Read/Write
Charge current:
200mA – (default 0)
B4
ICHG_1 (1) (2)
Read/Write
Charge current:
100mA – (default 0)
B3
ICHG_0 (1) (2)
Read/Write
Charge current:
50mA – (default 0)
B2
ITERM_2 (3)
Read/Write
Termination current sense threshold: 100mA (default 0)
B1
ITERM_1 (3)
Read/Write
Termination current sense threshold: 50mA (default 0)
B0(LSB)
ITERM_0 (3)
Read/Write
Termination current sense threshold: 25mA (default 0)
Charge current offset is 500 mA and default charge current is 500mA (maximum is 2.0A)
When all bits are 1’s, it is external ISET charging mode
Termination threshold voltage offset is 50mA. The default termination current is 50mA if the charge is selected from I2C. Otherwise,
termination is set to 10% of ICHG in external I_set mode with +/-10% accuracy.
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•
•
SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
ICHG – Sets the charge current regulation
ITERM – Sets the current level at which the charger will terminate
Register #5
Memory location: 04, Reset state: xx00 x010
BIT
•
•
•
•
•
FUNCTION
Read Only
B6
LOOP_STATUS0 (1)
Read Only
B5
LOW_CHG
Read/Write
0 – Normal charge current set by 03h
1 – Low charge current setting 330mA (default 0)
B4
DPDM_EN
Read/Write
0 – Bit returns to 0 after D+/D– detection is performed
1 – Force D+/D– detection (default 0)
B3
CE_STATUS
Read Only
0 – CE low
1 – CE high
B2
VINDPM_2 (2)
Read/Write
Input VIN-DPM voltage: 320mV (default 0)
B1
VINDPM_1 (2)
Read/Write
Input VIN-DPM voltage: 160mV (default 1)
(2)
Read/Write
Input VIN-DPM voltage: 80mV (default 0)
B0(LSB)
(2)
READ/WRITE
(1)
B7(MSB)
(1)
NAME
LOOP_STATUS1
VINDPM_0
00 –
01 –
10 –
11 –
No loop is active that slows down timer
VIN_DPM regulation loop is active
Input current limit loop is active
Thermal regulation loop is active
LOOP_STATUS bits show if there are any loop is active that slow down the safety timer. If a status occurs, these bits announce the
status and do not clear until read. If more than one occurs, the first one is shown.
VIN-DPM voltage offset is 4.20V and default VIN_DPM threshold is 4.36V.
LOOP_STATUS – Provides the status of the active regulation loop. The charge controller allows for only one
loop can regulate at a time.
LOW_CHG – When set to a ‘1’, the charge current is reduced 330mA independent of the charge current
setting in register 0x03. When set to ‘0’, the charge current is set by register 0x03.
DPDM_EN – Forces a D+/D- detection routine to be executed once a ‘1’ is written. This is independent of the
input being supplied.
CE_STATUS – Provides the status of the CE pin level. If the CE pin is forced high, this bit returns a ‘1’. If the
CE pin is forced low, this bit returns a ‘0’.
VINDPM – Sets the input VDPM level.
Register #6
Memory location: 05, Reset state: 101x 1xxx
BIT
NAME
READ/WRITE FUNCTION
B7(MSB)
2XTMR_EN
Read/Write
B6
TMR_1
Read/Write
B5
TMR_2
Read/Write
B4
SYSOFF
Read/Write
0 – SYSOFF disabled
1 – SYSOFF enabled
B3
TS_EN
Read/Write
0 – TS function disabled
1 – TS function enabled (default 1)
B2
TS_STAT2
Read only
B1
TS_STAT1
Read only
B0(LSB)
TS_STAT0
Read only
0 – Timer not slowed at any time
1 – Timer slowed by 2x when in thermal regulation, VIN_DPM or DPPM (default 1)
Safety Timer Time Limit
00 – 0.75 hour fast charge
01 – 6 hour fast charge (default 01)
10 – 9 hour fast charge
11 – Disable safety timers
TS Fault Mode:
000 – Normal, No TS fault
100 – TS temp < TCOLD (Charging suspended for JEITA and Standard TS)
101 – TFREEZE < TS temp < TCOLD (Charging at 3.9V and 100mA and only for PSE option
only)
110 – TS temp < TFREEZE (Charging suspended for PSE option only)
111 – TS open (TS disabled)
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2xTMR_EN – When set to a ‘1’, the 2x Timer function is enabled and allows for the timer to be extended if a
condition occurs where the charge current is reduced (i.e. VIN_DPM, thermal regulation, etc.). When set to a ‘0’,
this function is disabled and the normal timer will always be executed independent of the current reduce
conditions.
SYSOFF – When set to a ‘1’ and the input is removed, the internal battery FET is turned off in order to reduce
the leakage from the BAT pin to less than 1µA. Note that this disconnects the battery from the system. When
set to a ‘0’, this function is disabled.
TS_EN – Enables and disables the TS function. When set to a ‘1’ the TS function is disabled otherwise it is
enabled. Only applies to spins that have a TS pin.
TS_STAT – Provides status of the TS pin state for spins that have a TS pin.
Register #7
Memory location: 06, Reset state: 1110 0000
•
•
•
•
36
BIT
NAME
READ/WRITE
B7(MSB)
VOVP_2
Read/Write
FUNCTION
B6
VOVP_1
Read/Write
B5
VOVP_0
Read/Write
B4
CLR_VDP
Read/Write
0 – Keep D+ voltage source on during DBP charging
1 – Turn off D+ voltage source to release D+ line
B3
FORCE_BAT
DET
Read/Write
0 – Enter the battery detection routine only if TERM is true or EN_PTM is true
1 – Enter the battery detection routine
B2
FORCE_PTM
Read/Write
0 – PTM mode is disabled
1 – PTM mode is enabled if OTP_EN_PTM=1
B1
N/A
Read/Write
Not available. Keep set to 0.
B0(LSB)
N/A
Read/Write
Not available. Keep set to 0.
OVP voltage:
000 – 6.0V; 001 – 6.5V; 010 – 7.0V; 011 – 8.0V
100 – 9.0V; 101 – 9.5V; 110 – 10.0V; 111 –10.5V
VOVP – Sets the OVP level
CLR_VDP – When the D+/D– detection has finished, some cases require the D+ pin to force a voltage of
0.6V. This bit allows the system to clear the voltage prior to any communication on the D+/D– pins. A ‘1’
clears the voltage at the D+ pin if present.
FORCE_BATDET – Forces battery detection and provides status of the battery presence. A logic ‘1’ enables
this function.
FORCE_PTM – Puts the device in production test mode (PTM) where the input current limit is disabled. Note
that a battery must not be present prior to using this function. Otherwise the function will not be allowed to
execute. A logic ‘1’ enables the PTM function.
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SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
APPLICATION INFORMATION
Inductor Selection
The inductor selection depends on the application requirements. The bq2425x is designed to operate at around 1
µH. The value will have an effect on efficiency, and the ripple requirements, stability of the charger, package
size, and DCR of the inductor. The 1μH inductor provides a good tradeoff between size and efficiency and ripple.
Once the inductance has been selected, the peak current is needed in order to choose the saturation current
rating of the inductor. Make sure that the saturation current is always greater than or equal to the calculated
IPEAK. The following equation can be used to calculate the current ripple:
ΔIL = {VBAT (VIN – VBAT)}/(VIN x ƒs x L)
(6)
Then use current ripple to calculate the peak current as follows:
IPEAK = ICHARGE x (1 + ΔIL/2)
(7)
In this design example, the regulation voltage is set to 4.2V, the input voltage is 5V and the inductance is
selected to be 1µH. The maximum charge current that can be used in this application is 1A and can be set by
I2C command. The peak current is needed in order to choose the saturation current rating of the inductor. Using
equation 6 and 7, ΔIL is calculated to be 0.224A and the inductor peak current is 1.112A. A 1µF BAT cap is
needed and 22µF SYS cap is needed on the system trace.
The default settings for external fast charge current and external setting of current limit are chosen to be
IFC=500mA and ILIM=1A. RISET and RILIM need to be calculated using equation 1 and 2 in the data sheet.
The fast charge current resistor (RISET) can be set as follows:
RISET=250/0.5A=500Ω
The input current limit resistor (RILIM) can be set as follows:
RILIM= 270/1A=270Ω
The external settings of VIN_DPM can be designed by calculating R1 and R2 according to equation 3 in this data
sheet and the typical application circuit. VIN_DPM should be chosen first along with R1. VIN_DPM is chosen to
be 4.6V and R1 is set to 274KΩ in this design example. Using equation 3, the value of R2 is calculated to be
100KΩ.
In this design example, the application needs to be JEITA compliant. Thus, TCOLD must be 0°C and THOT must be
60°C. If an NTC resistor is chosen such that the beta is 4500K and the nominal resistance is 13KΩ, the
calculated R2 and R3 values are 5KΩ and 8.8KΩ respectively. These results are obtained from equation 4 and 5
in this data sheet.
Layout Guidelines
1. Place the BOOT, PMID, IN, BAT, and LDO capacitors as close as possible to the IC for optimal performance.
2. Connect the inductor as close as possible to the SW pin, and the SYS/CSIN cap as close as possible to the
inductor minimizing noise in the path.
3. Place a 1-μF PMID capacitor as close as possible to the PMID and PGND pins, making the high frequency
current loop area as small as possible.
4. The local bypass capacitor from SYS/CSIN to GND must be connected between the SYS/CSIN pin and
PGND of the IC. This minimizes the current path loop area from the SW pin through the LC filter and back to
the PGND pin.
5. Place all decoupling capacitors close to their respective IC pins and as close as possible to PGND (do not
place components such that routing interrupts power-stage currents). All small control signals must be routed
away from the high-current paths.
6. To reduce noise coupling, use a ground plane if possible, to isolate the noisy traces from spreading its noise
all over the board. Put vias inside the PGND pads for the IC.
7. The high-current charge paths into IN, Micro-USB, BAT, SYS/CSIN, and from the SW pins must be sized
appropriately for the maximum charge current to avoid voltage drops in these traces.
8. For high-current applications, the balls for the power paths must be connected to as much copper in the
board as possible. This allows better thermal performance because the board conducts heat away from the
IC.
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Board Layout
Figure 30. Recommended bq2425x PCB Layout for WCSP Package
38
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SLUSBA1C – OCTOBER 2012 – REVISED JUNE 2013
PACKAGE SUMMARY
YFF Package
(Top View)
YFF Package Symbol
(Top Side Symbol for bq2425x)
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
C1
C2
C3
C4
C5
D1
D2
D3
D4
D5
E1
E2
E3
E4
E5
F1
F2
F3
F4
F5
D
TI YMLLLLS
bq24250
E
TI YMLLLLS
bq24251
TI YMLLLLS
bq24253
0-Pin A1 Marker, TI-TI Letters, YM- Year Month Date Code,
LLLL-Lot Trace Code, S-Assembly Site Code
The bq2425x devices are available in a 30-bump chip scale package (YFF, NanoFree™). The package
dimensions are:
D – 2.427mm ±0.035mm
E – 2.027mm ±0.035mm
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REVISION HISTORY
Changes from Original (October 2012) to Revision A
Page
•
Changed From: Product Brief To: Full data sheet ................................................................................................................ 1
•
Changed Block Diagram ..................................................................................................................................................... 10
•
Added Typical Characteristics graphs ................................................................................................................................ 16
•
Changed Equation (3) ......................................................................................................................................................... 23
Changes from Revision A (March 2013) to Revision B
•
Page
Added PREVIEW status to devices in the Ordering Information table, except the bq24250RGER and bq24250RGET ..... 3
Changes from Revision B (May 2013) to Revision C
•
40
Page
Deleted PREVIEW status note from devices bq24250YFF, bq24251YFF, bq24251RGE, and bq24253RGE in the
Ordering Information table .................................................................................................................................................... 3
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PACKAGE OPTION ADDENDUM
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4-Jul-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
BQ24250RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24250
BQ24250RGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24250
BQ24250YFFR
ACTIVE
DSBGA
YFF
30
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24250
BQ24250YFFT
ACTIVE
DSBGA
YFF
30
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24250
BQ24251RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ24251
BQ24251RGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ24251
BQ24251YFFR
ACTIVE
DSBGA
YFF
30
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24251
BQ24251YFFT
ACTIVE
DSBGA
YFF
30
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24251
BQ24253RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ24253
BQ24253RGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ24253
BQ24253YFFR
PREVIEW
DSBGA
YFF
30
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24253
BQ24253YFFT
PREVIEW
DSBGA
YFF
30
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24253
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jul-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BQ24250RGER
Package Package Pins
Type Drawing
VQFN
RGE
24
BQ24250RGET
VQFN
RGE
BQ24250YFFR
DSBGA
YFF
BQ24250YFFT
DSBGA
BQ24251RGER
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
30
3000
180.0
8.4
2.09
2.59
0.78
4.0
8.0
Q1
YFF
30
250
180.0
8.4
2.09
2.59
0.78
4.0
8.0
Q1
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ24251RGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ24251YFFR
DSBGA
YFF
30
3000
180.0
8.4
2.09
2.59
0.78
4.0
8.0
Q1
BQ24251YFFT
DSBGA
YFF
30
250
180.0
8.4
2.09
2.59
0.78
4.0
8.0
Q1
BQ24253RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ24253RGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ24250RGER
VQFN
RGE
24
3000
367.0
367.0
35.0
BQ24250RGET
VQFN
RGE
24
250
210.0
185.0
35.0
BQ24250YFFR
DSBGA
YFF
30
3000
210.0
185.0
35.0
BQ24250YFFT
DSBGA
YFF
30
250
210.0
185.0
35.0
BQ24251RGER
VQFN
RGE
24
3000
367.0
367.0
35.0
BQ24251RGET
VQFN
RGE
24
250
210.0
185.0
35.0
BQ24251YFFR
DSBGA
YFF
30
3000
210.0
185.0
35.0
BQ24251YFFT
DSBGA
YFF
30
250
210.0
185.0
35.0
BQ24253RGER
VQFN
RGE
24
3000
367.0
367.0
35.0
BQ24253RGET
VQFN
RGE
24
250
210.0
185.0
35.0
Pack Materials-Page 2
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