Infineon C868 8-bit single-chip microcontroller Datasheet

D a t a S h e e t , V 1 . 0 , Ma y 2 0 0 3
C868
8-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
Edition 2003-05
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2003.
All Rights Reserved.
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D a t a S h e e t , V 1 . 0 , Ma y 2 0 0 3
C868
8-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
C868
Revision History:
2003-05
Previous Version:
-
Page
V 1.0
Subjects (major changes since last revision)
Current data updated
Description of I2C included
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8-Bit Single-Chip Microcontroller
C800 Family
C868
C868
Advance Information
• C800 core :
–Fully compatible to standard 8051 microcontroller
–Superset of the 8051 architecture with 8 datapointers
• 40 MHz internal CPU clock
–external clock of 6.67 - 10.67 MHz at 50% duty cycle
–300 ns instruction cycle time (@37.5 MHz CPU clock)
• 8 Kbyte on-chip Program ROM for C868-1R and 8 KByte on-chip Program RAM for
C868-1S
• In-system programming support for programming the XRAM(C868-1R) or XRAM/
Program RAM(C868-1S)
–This feature is realized through 4KB Boot ROM
• 256 byte on-chip RAM
• 256 byte on-chip XRAM
(further features are on the next page)
RAM
256 × 8
XRAM
256 × 8
Timer 0
Timer 1
Figure 1
Data Sheet
Port 1
I/O
5-bit
Input
3-bit
Port 3
I/O
8-bit
Timer 2
CPU
8 datapointers
ROM/RAM
8K × 8
Boot ROM
4K x 8
8-bit
UART
16-bit
Capture/
Compare
Unit
16-bit Compare
Unit
8-Bit ADC
Watchdog Timer
Analog/
Digital
Input
C868 Functional Units
5
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C868
• One 8-bit and one 5 bits general purpose push-pull I/O ports
– Enhanced sink current of 10 mA on Port 1/3 (total max current of 43 mA @ 100oC)
• Three 16-bit timers/counters
–Timer 0 / 1 (C501 compatible)
–Timer 2 (up/down counter feature)
–Timer 1 or 2 can be used for serial baudrate generator
• Capture/compare unit for PWM signal generation
–3-channel, 16-bit capture/compare unit
–1-channel, 16-bit compare unit
• Full duplex serial interface (UART)
• 5 channel 8-bit A/D Converter
– Start of conversion can be synchronized to capture/compare timer 12/13.
• 13 interrupt vectors with four priority levels
• Programmable 16-bit Watchdog Timer
• Brown out detection
• Power Saving Modes
–Slow-down mode
–Idle mode (can be combined with slow-down mode)
–Power-down mode with wake up capability through INT0 or RxD pins.
• Single power supply of 3.3V, internal voltage regulator for core voltage of 2.5V.
• P-DSO-28-1, P-TSSOP-38-1 packages
• Temperature ranges:
SAF-C868-1RR BA, SAF-C868-1SR BA, SAF-C868-1RG BA, SAF-C868-1SG BA,
SAF-C868A-1RR BA, SAF-C868A-1SR BA, SAF-C868A-1RG BA, SAF-C868A-1SG
BA, SAF-C868P-1SR BA, SAF-C868P-1SG BA TA = – 40 to 85 oC
SAK-C868-1RR BA, SAK-C868-1SR BA, SAK-C868-1RG BA, SAK-C868-1SG BA,
SAK-C868A-1RR BA, SAK-C868A-1SR BA, SAK-C868A-1RG BA, SAK-C868A-1SG
BA, SAK-C868P-1SR BA, SAK-C868P-1SG BA TA = – 40 to 125 oC
Data Sheet
6
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C868
VDDP VSSP
VAREF
VAGND
Port 1
5-bit Digital I/O
3-bit Digial Input
RESET
Port 3
8-bit Digital I/O
C868
ALE/BSL
5 ADC channels
CTRAP
TxD
RxD
4 External
Interrupts
VDDC
Figure 2
Data Sheet
VSSC
Logic Symbol
7
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C868
P1.4/RxD
P1.3/INT3
P1.2
P1.1/EXF2
NC
1
38
RESET
2
37
3
36
P3.7/CC60
P3.6/COUT60
NC
ALE/BSL
4
35
5
34
P1.0/TxD
6
33
P3.1/CTRAP
NC
NC
7
32
P3.0/COUT63
31
P3.4/COUT61
VDDP
VSSP
9
30
XTAL2
XTAL1
8
C868
10
29
P1.5/CCPOS0/T2/INT0/AN0
P1.6/CCPOS1/T2EX/INT1/AN1
P1.7/CCPOS2/INT2/AN2
VAGND
11
28
12
27
VAREF
15
24
AN3
16
23
AN4
17
22
NC
NC
18
21
19
20
Figure 3
Figure 4
Data Sheet
13
26
14
25
VDDC
VSSC
P3.3/CC62
P3.2/COUT62
P3.5/CC61
NC
NC
NC
NC
C868 Pin Configuration P-TSSOP-38 Package (top view)
P3.4/COUT61
1
28
P3.0/COUT63
P3.1/CTRAP
2
27
3
26
ALE/BSL
P3.6/COUT60
P3.7/CC60
4
25
5
24
6
23
RESET
P1.4/RxD
P1.3/INT3
P1.2
P1.1/EXF2
P1.0/TxD
VDDP
VSSP
7
XTAL2
XTAL1
VDDC
VSSC
8
21
9
20
P3.3/CC62
P3.2/COUT62
P3.5/CC61
AN4
AN3
10
19
VAREF
11
18
12
13
17
16
14
15
VAGND
P1.7/CCPOS2/INT2/AN2
P1.6/CCPOS1/T2EX/INT1/AN1
P1.5/CCPOS0/T2/INT0/AN0
C868
22
C868 Pin Configuration P-DSO-28 Package (top view)
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C868
Table 1
Symbol
P1.0–
P1.4
P1.5P1.7
Pin Definitions and Functions
Pin Numbers
I/O*) Function
PDSO28
PTSSOP38
12-8
6,4-1
I/O
15-17
11-13
I
12
11
10
9
8
6
4
3
2
1
Port 1
is a combination of 5 bits of push-pull bidirectional I/
O ports and 3 bits of input ports.
As alternate digital functions, port 1 contains the
interrupt 3, timer 2 overflow flag, receive data input
and transmit data output of serial interface. The
alternate functions are assigned to the pins of port
1 as follows:
P1.0/TxD Transmit data of serial interface
P1.1/EXF2 Timer 2 overflow flag
P1.2
P1.3/INT3 Interrupt 3
P1.4/RxD Receive data of serial interface, Use as
wakeup source from powerdown if bit WS of
PMCON0 is set.
The input ports are also interrupt ports, input to the
timer2, CCU6 modules and ADC:
15
11
I
P1.5/Input to Counter 2/External Interrupt 0 Input/
Analog Input Channel 0
External interrupt input or Hall input signal, counter
2 input or input channel 0 to the ADC unit. Use as
wakeup source from powerdown if bit WS of
PMCON0 is cleared.
16
12
I
P1.6/Timer 2 Trigger/External Interrupt 1 Input/
Analog Input Channel 1
External interrupt input or Hall input signal, input
channel 1 to the ADC unit, trigger to Timer 2.
17
13
I
P1.7/External Interrupt 2 Input/
Analog Input Channel 2
External interrupt input or Hall input signal and input
channel 2 to the ADC unit.
*)I=Input
O=Output
Data Sheet
9
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C868
Table 1
Symbol
Pin Definitions and Functions
Pin Numbers
PDSO28
P3.0–
P3.7
I/O*) Function
PTSSOP38
2,3,23, 32,33,25, I/O
24,1, 26,31,24,
22,5,6 36,37
Port 3
is an 8-bit push-pull bidirectional I/O port. This port
also serves as alternate functions for the CCU6
functions. The functions are assigned to the pins of
port 3 as follows :
2
3
23
24
1
22
5
6
32
33
25
26
31
24
36
37
P3.0/COUT63 16 bit compare channel output
P3.1/CTRAP CCU trap input
P3.2/COUT62 Output of capture/compare ch 2
P3.3/CC62 Input/output of capture/compare ch 2
P3.4/COUT61 Output of capture/compare ch 1
P3.5/CC61 Input/output of capture/compare ch 1
P3.6/COUT60 Output of capture/compare ch 0
P3.7/CC60 Input/output of capture/compare ch 0
VAREF
19
15
–
Reference voltage for the A/D converter.
VAGND
18
14
–
Reference ground for the A/D converter.
AN4
21
17
I
Analog Input Channel 4
is input channel 4 to the ADC unit.
AN3
20
16
I
Analog Input Channel 3
is input channel 3 to the ADC unit.
RESET
7
38
I
RESET
A low level on this pin for two machine cycle while
the oscillator is running resets the device.
ALE/BSL 4
34
I/O
Address Latch Enable/Bootstrap Mode
A low level on this pin during reset allows the device
to go into the bootstrap mode. After reset, this pin
will output the address latch enable signal. The
ALE can be disabled by bit EALE in SFR
SYSCON0.
VSSP
14
10
–
IO Ground (0V)
VDDP
13
9
–
IO Power Supply (+3.3V)
*)I=Input
O=Output
Data Sheet
10
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C868
Table 1
Symbol
Pin Definitions and Functions
Pin Numbers
I/O*) Function
PDSO28
PTSSOP38
VSSC
25
27
–
Core Ground (0V)
VDDC
26
28
O
Core Internal Reference (+2.5V)
Connect 2*68 - 470nF ceramic capacitor across
this pin and core ground.
NC
–
5,7,8,18, –
19,20,21,
22,23,35
Not connected
XTAL1
27
29
I
XTAL1
Output of the inverting oscillator amplifier.
XTAL2
28
30
O
XTAL2
Input to the inverting oscillator amplifier and input to
the internal clock generation circuits.
To drive the device from an external clock source,
XTAL2 should be driven, while XTAL1 is left
unconnected.
*)I=Input
O=Output
Data Sheet
11
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C868
VDDC
VSSC
XTAL1
C868
OSC
XRAM
RAM
ROM/
RAM
256 x 8
256 x 8
8k x 8
XTAL2
PLL
RESET
Boot/
Self
Test
ROM
4k x 8
CPU
8 datapointers
Programmable
Watchdog Timer
Port 1
Timer 0
Timer 1
Port 1
5-bit
digital
I/O
and
3-bit
digital
input
Timer 2
UART
Port 3
Capture/Compare
Unit
4 external
interrupts
VAREF
VAGND
Port 3
8-bit
digital
I/O
Interrupt Unit
VDDP
A/D Converter
8-Bit
VSSP
5-Bit
Analog In
Figure 5
Data Sheet
Block Diagram of the C868
12
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C868
CPU
The C868 is efficient both as a controller and as an arithmetic processor. It has extensive
facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient
use of program memory results from an instruction set consisting of 44% one-byte, 41%
two-byte, and 15% three-byte instructions. With a 10.67 MHz external crystal (giving a
40MHz CPU clock), 58% of the instructions execute in 300 ns.
PSW
Program Status Word Register
[Reset value: 00H]
D7H
D6H
D5H
D4H
D3H
D2H
D1H
D0H
CY
AC
F0
RS1
RS0
OV
F1
P
rwh
rwh
rw
rw
rw
rwh
rw
rwh
Field
Bits
Typ Description
P
0
rwh Parity Flag
Set/cleared by hardware after each instruction to
indicate an odd/even number of "one" bits in the
accumulator, i.e. even parity.
F1
1
rw
OV
2
rwh Overflow Flag
Used by arithmetic instructions.
RS0
RS1
3
4
rw
General Purpose Flag
Register Bank select control bits
These bits are used to select one of the four register
banks.
Table 2 :
RS1 RS0 Function
0
0
Bank 0 selected, data address 00H-07H
0
1
Bank 1 selected, data address 08H-0FH
1
0
Bank 2 selected, data address 10H-17H
1
1
Bank 3 selected, data address 18H-1FH
F0
5
rw
AC
6
rwh Auxiliary Carry Flag
Used by instructions which execute BCD operations.
CY
7
rwh Carry Flag
Used by arithmetic instructions.
Data Sheet
General Purpose Flag
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C868
Memory Organization
The C868 CPU manipulates operands in the following five address spaces:
– up to 8 Kbyte of RAM internal program memory : 8K ROM for C868-1R
: 8K RAM for C868-1S
–
–
–
–
4 Kbyte of internal Self test and Boot ROM
256 bytes of internal data memory
256 bytes of internal XRAM data memory
128 byte special function register area
Figure 0-1 illustrates the memory address spaces of the C868.
Internal
XRAM
FFFFH
FF00H
1FFFH
indirect
addr.
Internal
RAM
Internal
Internal
Self Test
and Boot
ROM
(4 KByte)
Figure 0-1
Data Sheet
Special FFH
Function
Regs.
80H
Internal
RAM
0000H
"Code Space"
direct
addr.
"Data Space"
7FH
00H
"Internal Data Space"
C868 Memory Map
14
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C868
The various chip modes supported are shown in Figure 6.
Normal
Mode
Bootstrap
Mode
Normal
XRAM
Mode
Bootstrap
XRAM
Mode
Hardware
Software
Figure 6
Entry and exit of Chip Modes
A valid hardware reset would, of course, override any of the above entry or exit
procedures.
Table 0-1
Hardware and Software Selection of Chipmodes
Operating Mode
(Chipmode)
Hardware Selection
Software Selection
Normal Mode
ALE/BSL pin = high
RESET rising edge
ALE/BSL = don’t care;
setting bits BSLEN, SWAP = 0,0;
execute unlocking sequence
Normal XRAM Mode
Not possible
setting bits BSLEN,SWAP = 0,1;
execute unlocking sequence
Bootstrap XRAM Mode Not possible
setting bits BSLEN,SWAP = 1,1;
execute unlocking sequence
Bootstrap Mode
ALE/BSL = don’t care;
setting bits BSLEN, SWAP = 1,0;
execute unlocking sequence
Data Sheet
ALE/BSL pin = low
RESET rising edge
15
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C868
Table 3
Normal Memory Configuration
Chip
Mode
Memory Space
Memory Boundary
Normal
Code Space
ROM/RAM: 0000H to 1FFFH
Internal Data Space
XRAM: FF00H to FFFFH
Bootstrap Code Space
Boot ROM: 0000H to 0FFFH
Internal Data Space
XRAM: FF00H to FFFFH
ROM/RAM: 0000H to 1FFFH
Code Space
XRAM: FF00H to FFFFH
Data Space
ROM/RAM: 0000H to 1FFFH
Bootstrap Code Space
XRAM
Boot ROM: 0000H to 0FFFH
XRAM: FF00H to FFFFH
Data Space
ROM/RAM: 0000H to 1FFFH
Normal
XRAM
Data Sheet
16
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C868
Bootstrap loader
The C868, includes a bootstrap mode, which is activated by setting the ALE/BSL pin at
logic low with a pulldown and TxD pin at logic high with a pullup at the rising edge of the
RESET. Or it can be entered by software, that is by setting BSLEN bit and resetting
SWAP bit in SFR SYSCON1 accompany by an unlock sequence.
In the bootstrap mode, software routines of the bootstrap loader located in the boot ROM
will be executed. Its purpose is to allow the easy and quick programming of the internal
SRAM (0000H to 1FFFH) or XRAM (FF00H to FFFFH) via serial interface (UART) while
the MCU is in-circuit. It also provides a way to program SRAM or XRAM through
bootstrapping from an external SPI or I2C EEPROM.
The first action of the bootstrap loader is to detect the presence of EEPROM and its type,
SPI or I2C, and check the first byte of the serial EEPROM. If the first byte is 0A5H, the
MCU would enter Phase A to download from the EEPROM. Otherwise, it will enter
Phase B to establish a serial communication with the connected host. Bootstrapping
from the serial EEPROM can also be done in phase B if it is invoked by the host.
Phase B consists of two functional parts that represent two phases:
• Phase I: Establish a serial connection and automatically synchronize to the transfer
speed (baud rate) of the serial communication partner (host).
• Phase II: Perform the serial communication with the host. The host controls the
communication by sending special header information, which select one of the
working modes. These modes are:
Table 4
Serial Communication Modes of Phase B
Modes
Description
0
Transfer a customer program from the host to the SRAM (0000H to
1FFFH) or XRAM (FF00H -FFFFH). Then return to the beginning of
phase II and wait for the next command from the host.
1
Execute a customer program in the XRAM at start address FF00H.
2
Execute a customer program in the SRAM at start address 0000H.
3
Transfer a customer program from the SPI EEPROM to the SRAM
(0000H to 1FFFH) or XRAM (FF00H -FFFFH). Then return to the
beginning of phase II and wait for the next command from the host.
4
Transfer a customer program from the I2C EEPROM to the SRAM
(0000H to 1FFFH) or XRAM (FF00H -FFFFH). Then return to the
beginning of phase II and wait for the next command from the host.
5-9
reserved
The phases of the bootstrap loader are illustrated in Figure 7.
Data Sheet
17
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C868
Start
Read serial
EEPROM (first byte)
Yes
Phase A
Bootstrap from
serial
EEPROM
byte=A5H?
No
Phase B
Init serial interface 0
and synchronize to
the host baud rate
Receive header
block from host
Activate mode 0
Load custom code
to SRAM/XRAM
Figure 7
Phase B, Phase I
Activate Mode 1
Execute custom
program in XRAM
Phase B, Phase II
Select working
mode
Activate Mode 4
Load program from
I2C serial EEPROM
to SRAM/XRAM
Activate Mode 2
Execute custom
program in SRAM
Activate Mode 3
Load program from SPI serial
EEPROM to SRAM/XRAM
The phases of the Bootstrap Loader
The serial communication is activated in phase B. Using a full duplex serial cable
(RS232), the MCU must be connected to the serial port of the host computer as shown
in Figure 8.
Serial Cable
full duplex, RS232
PC
C868
Host Computer
Serial Interface
(asynchronous, 8N1)
Figure 8
Data Sheet
Serial Interface,
UART Mode 1
(asynchronous, 8N1)
Bootstrap Loader Interface to the PC
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C868
VC C
1
P1.3
6
P1.1
5
P1.2
240R
2
/CS
/HO LD
SCK
/W P
SI
VCC
SO
GN
D
VCC
7
1
3
6
8
5
4
2
a) SPI EEPR OM connection
Figure 9
Data Sheet
A0
VCC
A1
WP
A2
SC L
GN
D
SDA
7
3
3K3
8
P1.1
4
P1.2
b) I2C EEPRO M connection
EEPROM connections for a) SPI and b) I2C
19
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C868
Reset and Brownout
The reset input is an active low input. An internal Schmitt trigger is used at the input for
noise rejection. The RESET pin must be held low for at least tbd usec. But the CPU will
only exit from reset condition after the PLL lock had been detected.
During RESET at transition from low to high, C868 will go into normal mode if ALE/BSL
is high and bootstrap loading mode if ALE/BSL is low. A pullup to VDDP or pulldown to
ground is recommended for pin ALE/BSL. TXD should have a pullup to VDDP and should
not be stimulated externally during reset, as a logic low at this pin will cause the chip to
go into test mode if ALE/BSL is low.
Figure 10 shows the possible reset circuits, note that the RESET pin does not have an
internal pullup resistance.
VDDP
a)
b)
C868 BA
RESET
Figure 10
VDDP
C868 BA
&
RESET
c)
C868 BA
RESET
Reset Circuitries
An on-chip analog circuit detects brownout, if the core voltage VDDC dips below the
threshold voltage VTHRESHOLD momentarily while RESET pin is high. If this detection is
active for tbd usec then the device will reset. When VDDC recovers by exceeding
VTHRESHOLD while RESET is high, the reset is released once PLL is locked for 4096
clocks. Bit BO in the PMCON0 register is set when brownout detected if brownout
detection was enabled, this bit is cleared by hardware reset RESET and software. All
ports are tristated during brownout.
The VTHRESHOLD has a nominal value of 1.47V, a minimum value of 1.1V and a
maximum value of 1.8V.
Data Sheet
20
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C868
Clock system
The C868 clock system consist of the on-chip oscillator, PLL and multiplexer stage. The
programmable Slow Down Divider (SDD) divides the PLL output clock frequency by a
factor of 1...32 which is specified via CMCON.REL. The system clock is switched from
the PLL output to the output from the SDD when slowdown mode is selected.
XTAL1
PLL
On-Chip
Osc
fOSC
clkin
clkout
SDD
fPLL
system
clock (fSYS)
XTAL2
Figure 11
Data Sheet
MUX
Block Diagram of the Clock Generation
21
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C868
The PLL output frequency is determined by:
fPLL = fVCO / K =
15
× fOSC
K
[1]
The range for the VCO frequency is given by:
100 MHz ≤ fVCO ≤ 160 MHz
[2]
The relationship between the input frequency and VCO frequency is given by:
fVCO = 15 × fOSC
[3]
This gives the range for the input frequency which is given by:
6.67 MHz ≤ fOSC ≤ 10.67 MHz
Table 5
[4]
Output Frequencies fPLL Derived from Various Output Factors
K-Factor
fPLL
Duty
Jitter
Cycle [%]
Selected KDIV
Factor
fVCO =
fVCO =
100 MHz 160 MHz
2
000B
50
80
50
4
010B
25
40
50
51)
011B
20
32
40
6
100B
16.67
26.67
50
8
101B
12.5
20
50
91)
110B
11.11
17.78
44
10
111B
10
16
50
001B
6.25
10
50
16
1)
2)
linear depending on fVCO
at fVCO =100MHz: +/-300ps
at fVCO =160MHz: +/-250ps
additional jitter for odd Kdiv
factors tbd.
These odd factors should not be used (not tested because off the unsymmetrical duty cycle).
Shaded combinations should not be used because they are above the maximum CPU frequency of 40MHz.
Data Sheet
22
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C868
Figure 12 shows the recommended oscillator circuitries for crystal and external clock
operation.
Driving from External Source
Crystal Oscillator Mode
External Oscillator
Signal
XTAL2
6.67-10.67
MHz
XTAL2
C868
N.C.
XTAL1
XTAL1
C = 20 pF ± 10 pF for crystal operation
(incl. StrayCapacitance)
Figure 12
Recommended Oscillator Circuit
In this application the on-chip oscillator is used as a crystal-controlled, positivereactance oscillator (a more detailed schematic is given in Figure 13). lt is operated in
its fundamental response mode as an inductive reactor in parallel resonance with a
capacitor external to the chip. The crystal specifications and capacitances are noncritical. In this circuit tbd pF can be used as single capacitance at any frequency together
with a good quality crystal. A ceramic resonator can be used in place of the crystal in
cost-critical applications. If a ceramic resonator is used, the two capacitors normally
have different values depending on the oscillator frequency. We recommend consulting
the manufacturer of the ceramic resonator for value specifications of these capacitors.
Data Sheet
23
V 1.0, 2003-05
C868
To internal
timing circuitry
XTAL2
XTAL1
C868
*)
C1
C2
*) Crystal or ceramic resonator
Figure 13
On-Chip Oscillator Circuitry
To drive the C868 with an external clock source, the external clock signal has to be
applied to XTAL2, as shown in Figure 14. XTAL1 has to be left unconnected. A pullup
resistor is suggested (to increase the noise margin), but is optional if VOH of the driving
gate corresponds to the VIH2 specification of XTAL2.
C868
VDDC
N.C.
External
Clock
Signal
Figure 14
Data Sheet
XTAL1
XTAL2
External Clock Source
24
V 1.0, 2003-05
C868
0.1
Special Function Registers
All registers, except the program counter and the four general purpose register banks,
reside in the special function register area. The special function register area consists
of two portions: the standard special function register area and the mapped special
function register area. For accessing the mapped special function area, bit RMAP in
special function register SYSCON0 must be set. All other special function registers are
located in the standard special function register area which is accessed when RMAP is
cleared (“0“).
SYSCON0
System Control Register 0
[Reset value: XX10XXX1B]
7
6
5
4
3
2
1
0
-
-
EALE
RMAP
-
-
-
XMAP0
r
r
rw
rw
r
r
r
rw
The functions of the shaded bits are not described here
Field
Bits
Typ Description
RMAP
4
rw
Special Function Register Map Control
RMAP = 0 : The access to the non-mapped (standard)
special function register area is enabled.
RMAP = 1 : The access to the mapped special function
register area is enabled.
-
[7:2]
r
reserved;
returns ’0’ if read; should be written with ’0’;
As long as bit RMAP is set, the mapped special function register area can be accessed.
This bit is not cleared automatically by hardware. Thus, when non-mapped/mapped
registers are to be accessed, the bit RMAP must be cleared/set respectively by software.
The 109 special function registers (SFR) include pointers and registers that provide an
interface between the CPU and the other on-chip peripherals. All available SFRs whose
address bits 0-2 are 0 (e.g. 80H, 88H, 90H, ..., F0H, F8H ) are bit- addressable. Totally
there are 128 directly addressable bits within the SFR area.
All SFRs are listed in Table 6 and Table 7.In Table 6 they are organized in groups which
refer to the functional blocks of the C868-1R, C868-1S. Table 7 illustrates the contents
(bits) of the SFRs
Data Sheet
25
V 1.0, 2003-05
C868
Table 6
Special Function Registers - Functional Blocks
Block Symbol
Name
Add- Contents
ress after
Reset
C800 ACC
core B
DPH
DPL
DPSEL
PSW
SP
SCON
SBUF
IEN0
IEN1
IEN2
IP0
IP1
TCON
TMOD
TL0
TL1
TH0
TH1
PCON
Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Data Pointer Select Register
Program Status Word Register
Stack Pointer
Serial Channel Control Register
Serial Data Buffer
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Enable Register 2
Interrupt Priority Register 0
interrupt Priority Register 1
Timer 0/1 Control Register
Timer Mode Register
Timer 0, Low Byte
Timer 1, Low Byte
Timer 0, High Byte
Timer 1, High Byte
Power Control Register
E0H1)
F0H1)
83H
82H
84H
D0H1)
81H
98H1)
99H
A8H1)
A9H
AAH
B8H1)
ACH
88H1)
89H
8AH
8BH
8CH
8DH
87H
00H
00H
00H
00H
00H
00H
07H
00H
00H
0X000000B2)
XXXXX000B2)
XX0000XXB2)
XX000000B2)
XX000000B2)
00H
00H
00H
00H
00H
00H
0XXX0000B 2)
System
Wake-up Control Register
Clock Control Register
External Interrupt Control Register
External Interrupt Request Register
Peripheral Interrupt Request Register
Peripheral Management Ctrl Register
Peripheral Management Status Register
SCU/Watchdog Control Register
ROM Version Register
System Control Register 0
System Control Register 1
8EH
8FH
91H
92H
93H
E8H1)
F8H1)
C0H1)
F9H
ADH
AFH
XXX00000B2)
10011111B
XXXXXX00B2)
XXXXXX00B2)
XX0000X0B2)
XXXXX000B2)
XXXXX000B2)
X0X00000B2)
00H
XX10XXX1B2)
00XXX0X0B2)
PMCON0
CMCON
EXICON
IRCON0
IRCON1
PMCON1
PMCON2
SCUWDT
VERSION
SYSCON0
SYSCON1
1) Bit-addressable special function registers
2) “X“ means that the value is undefined and the location is reserved
3) Register is mapped by bit RMAP in SYSCON0.4=1
4) Register is mapped by bit RMAP in SYSCON0.4=0
Data Sheet
26
V 1.0, 2003-05
C868
Table 6
Special Function Registers - Functional Blocks (cont’d)
Block Symbol
Name
Add- Contents
ress after
Reset
A/D- ADCON0
Con- ADCON1
verter ADDATH
A/D Converter Control Register 0
A/D Converter Control Register 1
A/D Converter Data Register
D8H1) 00H
D9H XX000000B2)
DBH 00H
Ports P1 4)
P1DIR 3)
P3 4)
P3DIR 3)
P3ALT
P1ALT
Port 1 Register
Port 1 Direction Register
Port 3 Register
Port 3 Direction Register
Port 3 Alternate Function Register
Port 1 Alternate Function Register
90H1)
90H1)
B0H1)
B0H1)
B1H
B4H
FFH
FFH
FFH
FFH
00H
XXX00X00B2)
Watch WDTCON
dog
WDTREL
WDTL
WDTH
Watchdog Timer Control Register
Watchdog Timer Reload Register
Watchdog Timer, Low Byte
Watchdog Timer, High Byte
A2H
A3H
B2H
B3H
XXXXXX00B2)
00H
00H
00H
Timer T2CON
2
T2MOD
RC2H
RC2L
T2H
T2L
Timer 2 Control Register
Timer 2 Mode Register
Timer 2 Reload/Capture, High Byte
Timer 2 Reload/Capture, Low Byte
Timer 2, High Byte
Timer 2, Low Byte
C8H1)
C9H
CBH
CAH
CDH
CCH
00H
XXXXXXX0B2)
00H
00H
00H
00H
1) Bit-addressable special function registers
2) “X“ means that the value is undefined and the location is reserved
3) Register is mapped by bit RMAP in SYSCON0.4=1
4) Register is mapped by bit RMAP in SYSCON0.4=0
Data Sheet
27
V 1.0, 2003-05
C868
Table 6
Special Function Registers - Functional Blocks (cont’d)
Block Symbol
Name
Add- Contents
ress after
Reset
Capture/
Compare
Unit
Timer T12 Counter Register, Low Byte
Timer T12 Counter Register, High Byte
Timer T13 Counter Register, Low Byte
Timer T13 Counter Register, High Byte
Timer T12 Period Register, Low Byte
Timer T12 Period Register, High Byte
Timer T13 Period Register, Low Byte
Timer T13 Period Register, High Byte
Capture/Compare Ch 0 Reg, Low Byte
Capture/Compare Ch 0 Reg, High Byte
Capture/Compare Ch 1 Reg, Low Byte
Capture/Compare Ch 1 Reg, High Byte
Capture/Compare Ch 2 Reg, Low Byte
Capture/Compare Ch 2 Reg, High Byte
T13 Compare Register, Low Byte
T13 Compare Register, High Byte
Timer T12 Dead Time Ctrl, Low Byte
Timer T12 Dead Time Ctrl, High Byte
Compare Timer Status, Low Byte
Compare Timer Status, High Byte
Compare Timer Modification, Low Byte
Compare Timer Modification, High Byte
Timer Control Register 0, Low Byte
Timer Control Register 0, High Byte
Timer Control Register 2, Low Byte
Timer Control Register 4, Low Byte
Timer Control Register 4, High Byte
Cap/Com Interrupt Register, Low Byte
Cap/Com Interrupt Register, High Byte
Port Input Selector Register, High Byte
ECH
EDH
EEH
EFH
DEH
DFH
D2H
D3H
C2H
C3H
C4H
C5H
C6H
C7H
D4H
D5H
E6H
E7H
F4H
F5H
EAH
EBH
E2H
E3H
F2H
F2H
F3H
E4H
E5H
BBH
T12L
T12H
T13L
T13H
T12PRL
T12PRH
T13PRL
T13PRH
CC60RL
CC60RH
CC61RL
CC61RH
CC62RL
CC62RH
CC63RL
CC63RH
T12DTCL
T12DTCH
CMPSTATL
CMPSTATH
CMPMODIFL
CMPMODIFH
TCTR0L
TCTR0H
TCTR2L3)
TCTR4L4)
TCTR4H4)
ISL
ISH
PISELH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
0H
00H
00H
00H
00H
1) Bit-addressable special function registers
2) “X“ means that the value is undefined and the location is reserved
3) Register is mapped by bit RMAP in SYSCON0.4=1
4) Register is mapped by bit RMAP in SYSCON0.4=0
Data Sheet
28
V 1.0, 2003-05
C868
Table 6
Special Function Registers - Functional Blocks (cont’d)
Block Symbol
Name
Add- Contents
ress after
Reset
Capture/
Compare
Unit
Cap/Com Int Status Set Reg, Low Byte
Cap/Com Int Status Set Reg, High Byte
Cap/Com Int Status Reset Reg, Low Byte
Cap/Com Int Status Reset Reg,High Byte
Cap/Com Int Node Ptr Reg, Low Byte
Cap/Com Int Node Ptr Reg, High Byte
Cap/Com Interrupt Register, Low Byte
Cap/Com Interrupt Register, High Byte
Cap/Com Channel 0 Shadow, Low Byte
Cap/Com Channel 0 Shadow, High Byte
Cap/Com Channel 1 Shadow, Low Byte
Cap/Com Channel 1 Shadow, High Byte
Cap/Com Channel 2 Shadow, Low Byte
Cap/Com Channel 2 Shadow, High Byte
T13 Compare Shadow Reg, Low Byte
T13 Compare Shadow Reg, High Byte
Modulation Control Register, Low Byte
Modulation Control Register, High Byte
Trap Control Register, Low Byte
Trap Control Register, High Byte
Passive State Level Register, Low Byte
MCM Output Register, Low Byte
MCM Output Register, High Byte
MCM Output Shadow Register, Low Byte
MCM Output Shadow Register,High Byte
MCM Control Register, Low Byte
T12 Cap/Com Mode Sel Reg, Low Byte
T12 Cap/Com Mode Sel Reg, High Byte
BCH
BDH
BCH
BDH
BEH
BFH
BEH
BFH
FAH
FBH
FCH
FDH
FEH
FFH
B6H
B7H
D6H
D7H
CEH
CFH
A6H
DCH
DDH
DCH
DDH
D6H
F6H
F7H
ISSL3)
ISSH3)
ISRL4)
ISRH4)
INPL3)
INPH3)
IENL4)
IENH4)
CC60SRL
CC60SRH
CC61SRL
CC61SRH
CC62SRL
CC62SRH
CC63SRL
CC63SRH
MODCTRL3)
MODCTRH3)
TRPCTRL
TRPCTRH
PSLRL
MCMOUTL3)
MCMOUTH3)
MCMOUTSL4)
MCMOUTSH4)
MCMCTRLL4)
T12MSELL
T12MSELH
00H
00H
00H
00H
40H
39H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
1) Bit-addressable special function registers
2) “X“ means that the value is undefined and the location is reserved
3) Register is mapped by bit RMAP in SYSCON0.4=1
4) Register is mapped by bit RMAP in SYSCON0.4=0
Data Sheet
29
V 1.0, 2003-05
C868
Table 7
Addr Register
Contents of the SFRs, SFRs in numeric order of their addresses
Content
after
Reset1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
81H
SP
07H
.7
.6
.5
.4
.3
.2
.1
.0
82H
DPL
00H
.7
.6
.5
.4
.3
.2
.1
.0
83H
DPH
00H
.7
.6
.5
.4
.3
.2
.1
.0
84H
DPSE 00H
L
–
–
–
–
–
D2
D1
D0
87H
PCON 0XX0 SMOD –
0000B
–
SD
GF1
GF0
PDE
IDLE
88H
TF1
TF0
TR0
IE1
IT1
IE0
IT0
89H
TCON 00H
TMOD 00H
8AH
TL0
00H
.7
.6
.5
.4
.3
.2
.1
.0
8BH
TL1
00H
.7
.6
.5
.4
.3
.2
.1
.0
8CH
TH0
00H
.7
.6
.5
.4
.3
.2
.1
.0
8DH
TH1
00H
.7
.6
.5
.4
.3
.2
.1
.0
8EH
PMCO XXX0 –
N0
0000B
–
–
EBO
BO
SDST WS
AT
EPWD
8FH
CMCO 1001 KDIV2 KDIV1 KDIV0 REL4
N
1111B
REL3
REL2
REL1
REL0
90H2) P1
GATE C/NT1 M1(1) M0(1) GATE C/NT0 M1(0) M0(0)
1
0
.7
.6
.5
.4
.3
.2
.1
.0
90H3) P1DIR FFH
.7
91H EXICO XXXX –
N
XX00B
.6
.5
.4
.3
.2
.1
.0
–
–
–
–
–
ESEL3 ESEL2
92H
IRCO
N0
XXXX –
XX00B
–
–
–
–
–
EXINT EXINT
3
2
93H
IRCO
N1
XX00 –
00X0B
–
INP3
INP2
INP1
INP0
–
IADC
98H
SCON 00H
SBUF 00H
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
.7
.6
.5
.4
.3
.2
.1
.0
99H
FFH
TR1
1) X means that the value is undefined and the location is reserved
2) This register is mapped with RMAP (SYSCON0.4)=0
3) This register is mapped with RMAP (SYSCON0.4)=1
Shaded registers are bit-addressable special function registers
Data Sheet
30
V 1.0, 2003-05
C868
Table 7
Addr Register
Contents of the SFRs, SFRs in numeric order of their addresses
Content
after
Reset1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A2H
WDTC XXXX –
ON
XX00B
–
–
–
–
–
–
WDTI
N
A3H
WDTR 00H
EL
.7
.6
.5
.4
.3
.2
.1
.0
A6H
PSLRL 00H
PSL63 –
PSL5
PSL4
PSL3
PSL2
PSL1
PSL0
A8H
IEN0
0X00 EA
0000B
–
ET2
ES
ET1
EX1
ET0
EX0
A9H
IEN1
XXXX –
X000B
–
–
–
–
EX3
EX2
EADC
AAH
IEN2
XX00 –
00XXB
–
EINP3 EINP2 EINP1 EINP0 –
–
ACH
IP1
XX00 –
0000B
–
.5
ADH
SYSC XX10 –
–
ON0 XXX1B
SYSC 00XX ESWC SWC
ON1 X0X0B
AFH
B0H2) P3
B0H
B1H
B2H
B3H
3)
.4
.3
.2
.1
.0
EALE RMAP –
–
–
XMAP
0
_
_
_
BSLE _
N
SWAP
FFH
.7
.6
.5
.4
.3
.2
.1
.0
P3DIR FFH
P3ALT 00H
.7
.6
.5
.4
.3
.2
.1
.0
CC60
COUT CC61
60
COUT CC62
61
COUT CTRA COUT
62
P
63
WDTL 00H
WDTH 00H
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
B4H
P1ALT XXX0 _
0X00B
_
_
RxD
INT3
_
EXF2
TxD
B6H
CC63 00H
SRL
.7
.6
.5
.4
.3
.2
.1
.0
B7H
CC63 00H
SRH
.7
.6
.5
.4
.3
.2
.1
.0
1) X means that the value is undefined and the location is reserved
2) This register is mapped with RMAP (SYSCON0.4)=0
3) This register is mapped with RMAP (SYSCON0.4)=1
Shaded registers are bit-addressable special function registers
Data Sheet
31
V 1.0, 2003-05
C868
Table 7
Contents of the SFRs, SFRs in numeric order of their addresses
Addr Register
Content
after
Reset1)
B8H
IP0
XX00 –
0000B
BBH
PISEL 00H
H
Bit 7
–
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
.5
.4
.3
.2
.1
.0
–
ISPOS ISPOS ISPOS ISPOS ISPOS ISPOS
2.1
2.0
1.1
1.0
0.1
0.0
BCH3) ISSL
00H
ST12P ST12O SCC62 SCC62 SCC61 SCC61 SCC60 SCC60
M
M
F
R
F
R
F
R
BCH2) ISRL
00H
RT12P RT12O RCC6 RCC6 RCC6 RCC6 RCC6 RCC6
M
M
2F
2R
1F
1R
0F
0R
BDH3) ISSH
00H
–
SIDLE SWHE SCHE –
STRP ST13P ST13C
F
M
M
BDH2) ISRH
00H
–
RIDLE RWHE RCHE –
RTRP RT13P RT13C
F
M
M
BEH2) IENL
00H
ENT12 ENT12 ENCC ENCC ENCC ENCC ENCC ENCC
PM
OM
62F
62R
61F
61R
60F
60R
BEH3) INPL
00H
INPCH INPCH INPCC INPCC INPCC INPCC INPCC INPCC
E.1
E.0
62.1
62.0
61.1
61.0
60.1
60.0
BFH2) IENH
00H
–
ENIDL ENWH ENCH –
E
E
E
BFH3) INPH
00H
–
–
INPT1 INPT1 INPT1 INPT1 INPER INPER
3.1
3.0
2.1
2.0
R.1
R.0
C0H
SCUW 00H
DT
–
PLLR
–
WDTR WDTE WDTD WDTR WDTR
OI
IS
S
E
C2H
CC60 00H
RL
.7
.6
.5
.4
.3
.2
.1
.0
C3H
CC60 00H
RH
.7
.6
.5
.4
.3
.2
.1
.0
C4H
CC61 00H
RL
.7
.6
.5
.4
.3
.2
.1
.0
C5H
CC61 00H
RH
.7
.6
.5
.4
.3
.2
.1
.0
ENTR ENT13 ENT13
PF
PM
CM
1) X means that the value is undefined and the location is reserved
2) This register is mapped with RMAP (SYSCON0.4)=0
3) This register is mapped with RMAP (SYSCON0.4)=1
Shaded registers are bit-addressable special function registers
Data Sheet
32
V 1.0, 2003-05
C868
Table 7
Addr Register
Contents of the SFRs, SFRs in numeric order of their addresses
Content
after
Reset1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C6H
CC62 00H
RL
.7
.6
.5
.4
.3
.2
.1
.0
C7H
CC62 00H
RH
.7
.6
.5
.4
.3
.2
.1
.0
C8H
T2CO 00H
N
TF2
EXF2
RCLK TCLK EXEN TR2
2
C/T2
CP/
RL2
C9H
T2MO XXXX –
D
XXX0B
–
–
–
–
–
–
DCEN
CAH
.7
.6
.5
.4
.3
.2
.1
.0
CBH
RC2L 00H
RC2H 00H
.7
.6
.5
.4
.3
.2
.1
.0
CCH
TL2
00H
.7
.6
.5
.4
.3
.2
.1
.0
CDH
TH2
00H
.7
.6
.5
.4
.3
.2
.1
.0
CEH
TRPC 00H
TRL
–
–
–
–
–
TRPM TRPM TRPM
2
1
0
CFH
TRPC 00H
TRH
TRPP TRPE TRPE TRPE TRPE TRPE TRPE TRPE
EN
N13
N5
N4
N3
N2
N1
N0
D0H
PSW
CY
AC
F0
RS1
RS0
OV
F1
P
D2H
T13PR 00H
L
.7
.6
.5
.4
.3
.2
.1
.0
D3H
T13PR 00H
H
.7
.6
.5
.4
.3
.2
.1
.0
D4H
CC63 00H
RL
.7
.6
.5
.4
.3
.2
.1
.0
D5H
CC63 00H
RH
.7
.6
.5
.4
.3
.2
.1
.0
D6H2) MCMC 00H
TRLL
–
–
SWSY SWSY –
N1
N0
D6H3) MODC 00H
TRL
MCME –
N
00H
SWSE SWSE SWSE
L2
L1
L0
T12M T12M T12M T12M T12M T12M
ODEN ODEN ODEN ODEN ODEN ODEN
5
4
3
2
1
0
1) X means that the value is undefined and the location is reserved
2) This register is mapped with RMAP (SYSCON0.4)=0
3) This register is mapped with RMAP (SYSCON0.4)=1
Shaded registers are bit-addressable special function registers
Data Sheet
33
V 1.0, 2003-05
C868
Table 7
Addr Register
Contents of the SFRs, SFRs in numeric order of their addresses
Content
after
Reset1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D7H3) MODC 00H
TRH
ECT13 –
O
D8H
ADCO 00H
N0
ADST ADBS ADM1 ADM0 CCU- ADCH ADCH ADCH
Y
ADEX 2
1
0
D9H
ADCO XX00 –
N1
0000B
–
ADST ADST ADST ADCT ADCT ADCT
C2
C1
C0
C2
C1
C0
DBH
ADDA 00H
TH
.7
.6
.5
DCH3) MCMO 00H
UTL
–
R
MCMP MCMP MCMP MCMP MCMP MCMP
5
4
3
2
1
0
DCH2) MCMO 00H
UTSL
STRM –
CM
MCMP MCMP MCMP MCMP MCMP MCMP
S5
S4
S3
S2
S1
S0
DDH3) MCMO 00H
UTH
–
–
CURH CURH CURH EXPH EXPH EXPH
2
1
0
2
1
0
DDH2) MCMO 00H
UTSH
STRH –
P
CURH CURH CURH EXPH EXPH EXPH
S2
S1
S0
S2
S1
S0
DEH
T12PR 00H
L
.7
.6
.5
.4
.3
.2
.1
.0
DFH
T12PR 00H
H
.7
.6
.5
.4
.3
.2
.1
.0
E0H
ACC
.7
.6
.5
.4
.3
.2
.1
.0
E2H
TCTR 00H
0L
CTM
CDIR
STE12 T12R
T12PR T12CL T12CL T12CL
E
K2
K1
K0
E3H
TCTR 10H
0H
–
–
STE13 T13R
T13PR T13CL T13CL T13CL
E
K2
K1
K0
E4H
ISL
00H
T12PM T12O
M
ICC62 ICC62 ICC61 ICC61 ICC60 ICC60
F
R
F
R
F
R
E5H
ISH
00H
–
WHE
00H
IDLE
T13M T13M T13M T13M T13M T13M
ODEN ODEN ODEN ODEN ODEN ODEN
5
4
3
2
1
0
.4
CHE
.3
.2
.1
.0
TRPS TRPF T13PM T13C
M
1) X means that the value is undefined and the location is reserved
2) This register is mapped with RMAP (SYSCON0.4)=0
3) This register is mapped with RMAP (SYSCON0.4)=1
Shaded registers are bit-addressable special function registers
Data Sheet
34
V 1.0, 2003-05
C868
Table 7
Addr Register
Contents of the SFRs, SFRs in numeric order of their addresses
Content
after
Reset1)
E6H
T12DT 00H
CL
E7H
T12DT 00H
CH
E8H
Bit 7
–
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
–
DTM5 DTM4 DTM3 DTM2 DTM1 DTM0
DTE1
Bit 0
DTR2 DTR1 DTR0 –
DTE2
DTE0
PMCO XXXX –
N1
X000B
–
–
–
–
CCUDI T2DIS ADCDI
S
S
EAH
CMPM 00H
ODIFL
–
MCC6 –
3S
–
–
MCC6 MCC6 MCC6
2S
1S
0S
EBH
CMPM 00H
ODIFH
–
MCC6 –
3R
–
–
MCC6 MCC6 MCC6
2R
1R
0R
ECH
T12L
00H
.7
.6
.5
.4
.3
.2
.1
.0
EDH
T12H
00H
.7
.6
.5
.4
.3
.2
.1
.0
EEH
T13L
00H
.7
.6
.5
.4
.3
.2
.1
.0
EFH
T13H
00H
.7
.6
.5
.4
.3
.2
.1
.0
F0H
B
00H
.7
.6
.5
.4
.3
.2
.1
.0
F2H2) TCTR 00H
4L
T12ST T12ST –
D
R
–
DTRE T12RE T12RS T12RR
S
S
F2H3) TCTR 00H
2L
–
F3H2) TCTR 00H
4H
T13ST T13ST –
D
R
–
–
T13RE T13RS T13RR
S
–
–
CC62S CC61S CC60S
T
T
T
T13TE T13TE T13TE T13TE T13TE T13SS T12SS
D1
D0
C2
C1
C0
C
C
F4H
CMPS 00H
TATL
–
CC63S –
T
F5H
CMPS 00H
TATH
T13IM COUT COUT CC62P COUT CC61P COUT CC60P
63PS 62PS S
61PS S
60PS S
F6H
T12M 00H
SELL
MSEL MSEL MSEL MSEL MSEL MSEL MSEL MSEL
613
612
611
610
603
602
601
600
F7H
T12M 00H
SELH
–
–
–
–
MSEL MSEL MSEL MSEL
623
622
621
620
1) X means that the value is undefined and the location is reserved
2) This register is mapped with RMAP (SYSCON0.4)=0
3) This register is mapped with RMAP (SYSCON0.4)=1
Shaded registers are bit-addressable special function registers
Data Sheet
35
V 1.0, 2003-05
C868
Table 7
Addr Register
Contents of the SFRs, SFRs in numeric order of their addresses
Content
after
Reset1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
–
–
–
–
CCUS T2ST
T
Bit 0
F8H
PMCO XXXX –
N2
X000B
ADCS
T
F9H
VERSI 00H
ON
PROT VER6 VER5 VER4 VER3 VER2 VER1 VER0
FAH
CC60 00H
RL
.7
.6
.5
.4
.3
.2
.1
.0
FBH
CC60 00H
RH
.7
.6
.5
.4
.3
.2
.1
.0
FCH
CC61 00H
RL
.7
.6
.5
.4
.3
.2
.1
.0
FDH
CC61 00H
RH
.7
.6
.5
.4
.3
.2
.1
.0
FEH
CC62 00H
RL
.7
.6
.5
.4
.3
.2
.1
.0
FFH
CC62 00H
RH
.7
.6
.5
.4
.3
.2
.1
.0
1) X means that the value is undefined and the location is reserved
2) This register is mapped with RMAP (SYSCON0.4)=0
3) This register is mapped with RMAP (SYSCON0.4)=1
Shaded registers are bit-addressable special function registers
Data Sheet
36
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C868
Ports
The C868 has two kinds of ports. The first kind is push-pull ports instead of the traditional
quasi-bidirectional ports. The ports belonging to this kind are lsb of port 1 which is a 5bit I/O port and port 3 which is an eight-bit I/O port. When configured as inputs, these
ports will be high impedance with Schmitt trigger feature. Port 3 is alternate for capture/
compare functions whereas, port 1 has alternate functions for some of the pins.
The second kind is input ports which are shared by msb of port 1 which is a 3-bit input
port, the interrupts, timer 2 inputs, capture/compare hall inputs and analog inputs.
Data Sheet
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C868
Timer 0 and 1
Timer 0 and 1 can be used in four operating modes as listed in Table 8:
Table 8
Timer 0 and 1 Operating Modes
Mode
Description
TMOD
System Clock
M1
M0
0
8-bit timer with a divide-by-32 prescaler
0
0
1
16-bit timer
0
1
2
8-bit timer with 8-bit autoreload
1
0
3
Timer 0 used as one 8-bit timer and one 8-bit 1
timer
timer 1 stops
1
fSYS/(12*32)
fSYS/12
The register is incremented every machine cycle. Since the machine cycle consist of
twelve oscillator periods, the count rate is 1/12th of the system frequency. External
inputs INT0 and INT1 can be programmed to function as a gate to facilitate pulse width
measurements. Figure 15 illustrates the input clock logic.
fSYS ÷ 12
C/T = 0
Timer 0/1
Input Clock
Control
TR0
=1
Gate
INT0
Figure 15
Data Sheet
&
≥1
Pin
Timer 0 and 1 Input Clock Logic
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C868
Timer/Counter 2 with Compare/Capture/Capture
Timer 2 is a 16-bit timer/counter with an up/down count feature. It has three operating
modes:
• 16-bit auto-reload mode (up or down counting)
• 16-bit capture mode
• Baudrate generator
Table 9
Timer/Counter 2 Operating Modes
Mode
T2CON
RCLK CP/
or
RL2
TCLK
16-bit
Autoreload
T2MOD T2CON
TR2
DCEN
T2EX Remarks
EXEN
Inte- T2
rnal
0
0
1
0
0
0
0
X
0
1
0
0
1
1
X
0
down counting
0
0
1
1
X
1
up counting
0
1
1
X
0
X
16-bit Timer/
Counter (only
up-counting)
0
1
1
X
1
Baudrate 1
Generator
X
1
X
0
1
X
1
X
1
X
X
0
X
X
16-bit
Capture
off
Note:
System
Clock
X
reload upon
overflow
fSYS max
/12 fSYS
/24
reload trigger
(falling edge)
fSYS max
/12 fSYS
/24
capture
T2H,T2L->
RC2H,RC2L
X
no overflow
interrupt
request(TF2)
fSYS /2
extra external
interrupt
(“Timer 2“)
X
Timer 2 stops
-
-
denotes a falling edge
Data Sheet
39
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C868
Serial Interface (UART)
The serial port is a full duplex port capable of simultaneous transmit and receive
functions. It is also receive-buffered; it can commence reception of a second byte before
a previously-received byte has been read from the receive register. The serial port can
operate in 3 modes as illustrated in Table 10.
Table 10
Mode
UART Operating Modes
SCON
Description
SM1
SM0
0
0
0
Reserved
1
0
1
8-bit UART, variable baudrate
10 bits are transmitted (through TxD) or received (RxD)
2
1
0
9-bit UART, fixed baudrate
11 bits are transmitted (through TxD) or received (RxD)
3
1
1
9-bit UART, variable baudrate
Similar to mode 2, except for the variable baudrate.
For clarification, some terms regarding the difference between “baudrate clock“ and
“baudrate“ should be mentioned.
The serial interface requires a clock rate which is 16 times the baudrate for internal
synchronization. Therefore, the baudrate generators must provide a “baudrate clock“ to
the serial interface which divides it by 16, thereby resulting in the actual “baudrate“.
Data Sheet
40
V 1.0, 2003-05
C868
The baudrates in Mode 1 and 3 are determined by the timer overflow rate. These
baudrates can be determined by Timer 1 or by Timer 2 or both (one for transmit, the other
for receive.
Table 11
Serial Interface - Baud Rate Dependencies
Serial Interface
Operating Modes
Mode 1 (8-bit UART)
Mode 3 (9-bit UART)
Mode 2 (9-bit UART)
Active Control Bits Baud Rate Calculation
TCLK/
RCLK
SMOD
0
x
Controlled by timer 1 overflow:
(2SMOD × Timer 1 overflow rate) / 32
1
x
Controlled by baud rate generator
(2SMOD × Timer 21) overflow rate) / 32
–
0
fSYS / 64
fSYS / 32
1
1)
Timer 2 functioning as baudrate generator
Data Sheet
41
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C868
Capture/Compare Unit (CCU6)
The CCU6 provides two independent timers (T12, T13), which can be used for PWM
generation, especially for AC-motor control. Additionally, special control modes for block
commutation and multi-phase machines are supported.
Timer 12 Features
• Three capture/compare channels, each channel can be used either as capture or as
compare channel.
• Generation of a three-phase PWM supported (six outputs, individual signals for
highside and lowside switches)
• 16 bit resolution, maximum count frequency = system clock
• Dead-time control for each channel to avoid short-circuits in the power stage
• Concurrent update of the required T12/13 registers
• Center-aligned and edge-aligned PWM can be generated
• Single-shot mode supported
• Many interrupt request sources
• Hysteresis-like control mode
Timer 13 Features
•
•
•
•
•
One independent compare channel with one output
16 bit resolution, maximum count frequency = system clock
Can be synchronized to T12
Interrupt generation at period-match and compare-match
Single-shot mode supported
Additional Features
•
•
•
•
•
•
•
•
Block commutation for Brushless DC-drives implemented
Position detection via Hall-sensor pattern
Automatic rotational speed measurement for block commutation
Integrated error handling
Fast emergency stop without CPU load via external signal (CTRAP)
Control modes for multi-channel AC-drives
Output levels can be selected and adapted to the power stage
Capture/compare unit can be powerdown in normal, idle and slow-down modes
The timer T12 can work in capture and/or compare mode for its three channels. The
modes can also be combined. The timer T13 can work in compare mode only. The multichannel control unit generates output patterns which can be modulated by T12 and/or
T13. The modulation sources can be selected and combined for the signal modulation.
Data Sheet
42
V 1.0, 2003-05
C868
Switching Examples
T12clk
T12P
T12P
T12P-1
T12P-1
T12P-2
T12P-2
compare-match =
compare-match =
period-match zero-match
period-match
zero-match
1
1
0
0
0
1
0
< T12P-3
1
0
0
CDIR
0
STE12
T12P
CC6x
T12P
passive
active
compare
state
active
T12 shadow transfer
Figure 16
T12
T12 shadow transfer
Edge-aligned mode with duty cycles near 100% and near 0%.
Applicable to T13 as well.
T12clk
compare-match
compare-match
2
2
1
2
1
2
1
0
T12
1
0
1
0
1
0
CDIR
1
0
1
0
STE12
1
2
1
0
CC6x
active
passive
T12 shadow transfer
Figure 17
Data Sheet
compare
state
active
T12 shadow transfer
Centre-aligned mode with duty cycles near 100% and near 0%.
43
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C868
Dead-time Generation
The dead-time generation logic is built in a similar way for all three channels of T12.
Each of the three channels works independently with its own dead-time counter and the
trigger and enable signals.
T12
Centre-aligned
T12
Edge-aligned
CC6xST
CC6xST
DTCx_o
COUT6x (CC6xPS=0)
CC6x (CC6xPS=0)
Figure 18
Dead-time generation for centre and edge aligned modes
Capture Mode
In capture mode the bits CC6xST indicate the occurrence of the selected capture event
according to the bit fields MSEL6x. A rising and/or a falling edge on the pins CC6x can
be selected as capture event, that is used to transfer the contents of timer T12 to the
CC6xR and CC6xSR registers. In order to work in capture mode, the capture pins have
to be configured as inputs.
Data Sheet
44
V 1.0, 2003-05
C868
Single Shot Mode
In single shot mode, the timer T12 stops automatically at the end of the its counting
period.
edge-aligned mode
T12P
center-aligned mode
period-match
while counting up
T12P-1
T12P-2
one-match while
counting down
2
if T12SSC = ’1’
1
0
T12
0
if T12SSC = ’1’
T12
T12R
T12R
CC6xST
Figure 19
CC6xST
Single Shot Mode of T12, T13 is edge-aligned mode only.
Hysteresis-Like Control Mode
The hysteresis-like control mode (MSEL6x = ’1001’) offers the possibility to switch off the
PWM output if the input CCPOSx becomes ’0’. This can be used as a simple motor
control feature by using a comparator indicating e.g. over current.
T12
COUT6x
CC6x
CCPOSx
Figure 20
Hysteresis-like control mode
Data Sheet
45
V 1.0, 2003-05
C868
Synchronization of T13 to T12
The timer T13 can be synchronized on a T12 event. Combined with the single shot
mode, this feature can be used to generate a programmable delay after a T12 event.
5
compare-match while
counting up
T12
4
3
2
1
0
2
1
T13
0
T13R
Synchronization of T13 to T12
Multi-channel Mode
The multi-channel mode offers a possibility to modulate all six T12-related output signals
within one instruction. The bits in bit field MCMP are used to select the outputs that may
become active. If the multi-channel mode is enabled (bit MCMEN=’1’), only those
outputs may become active, which have a ’1’ at the corresponding bit position in bit field
MCMP.
This bit field has its own shadow bit field MCMPS, which can be written by SW. The
transfer of the new value in MCMPS to the bit field MCMP can be triggered by and
synchronized to T12 or T13 events. This structure permits the SW to write the new value,
which is then taken into account by the HW at a well-defined moment and synchronized
to a PWM period. This avoids unintended pulses due to unsynchronized modulation
sources (T12, T13, SW).
Data Sheet
46
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C868
Trap Handling
The trap functionality permits the PWM outputs to react on the state of the input pin
CTRAP. This functionality can be used to switch off the power devices if the trap input
becomes active (e.g. as emergency stop).
T12
T13
TRPF
Figure 21
Data Sheet
CTRAP active
TRPS
sync. to T13
TRPS
sync. to T12
TRPS
no sync.
Trap State Synchronization (with TRM2=’0’)
47
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C868
Modulation control
The modulation control part combines the different modulation sources, six T12-related
signals from the three compare channels, the T13-related signal and the multi-channel
modulation signals. each modulation source can be individually enabled for each output
line. Furthermore, the trap functionality is taken into account to disable the modulation of
the corresponding output line during the trap state (if enabled).
T13
CC60 (MCMP0, no modulation)
COUT60 (MCMP1, no modulation)
CC60 (T12, no modulation)
COUT60 (T12, no modulation)
CC60
(MCMP0 modulated with T12)
COUT60
(MCMP1 modulated with T12)
CC60
(MCMP0 modulated with T12 and 13)
COUT60
(MCMP1 modulated with T12 and T13)
Figure 22
Data Sheet
Modulation Control example for CC60 and COUT60.
48
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C868
Hall Sensor Mode
In Brushless-DC motors the next multi-channel state values depend on the pattern of
the Hall inputs. There is a strong correlation between the Hall pattern (CURH) and the
modulation pattern (MCMP). Because of different machine types the modulation
pattern for driving the motor can be different. Therefore it is wishful to have a wide
flexibility in defining the correlation between the Hall pattern and the corresponding
modulation pattern. The CCU6 offers this by having a register which contains the actual
Hall pattern (CURHS), the next expected Hall pattern (EXPHS) and its output pattern
(MCMPS). At every correct Hall event (CHE, see figure Hall Event Actions) a new Hall
pattern with its corresponding output pattern can be loaded (from a predefined table) by
software into the register MCMOUTS. Loading this shadow register can also be done by
a write action on MCMOUTS with bit STRHP = ’1’
The sampling of the Hall pattern (on CCPOSx) is done with the T12 clock. By using the
dead-time counter DTC0 (mode MSEL6x= ’1000’) a hardware noise filter can be
implemented to suppress spikes on the Hall inputs due to high di/dt in rugged inverter
environment. In case of a Hall event the DTC0 is reloaded and starts counting. When the
counter value of one is reached, the CCPOSx inputs are sampled (without noise and
spikes) and are compared to the current Hall pattern (CURH) and to the expected Hall
pattern (EXPH). If the sampled pattern equals to the current pattern the edge on
CCPOSx was due to a noise spike and no action will be triggered (implicit noise filter). If
the sampled pattern equals to the next expected pattern the edge on CCPOSx was a
correct Hall event, the bit CHE is set which causes an interrupt and the resets T12 (for
speed measurement, see description mode ’1000’ below).
This correct Hall event can be used as a transfer request event for register MCMOUTS.
The transfer from MCMOUTS to MCMOUT transfers the new CURH-pattern as well as
the next EXPH-pattern. In case of the sampled Hall inputs were neither the current nor
the expected Hall pattern, the bit WHE (wrong Hall event) is set which also can cause
an interrupt and sets the IDLE mode clearing MCMP (modulation outputs are inactive).
To restart from IDLE the transfer request of MCMOUTS have to be initiated by software
(bit STRHP and bitfields SWSEL/SWSYN).
Data Sheet
49
V 1.0, 2003-05
C868
Below is a table listing output (MCMP) for a BLDC motor.
Block Commutation Control Table
Mode
CCPOS0CCPOS2 Inputs
CC60 - CC62
Outputs
CCP CCP CCP CC60
OS0 OS1 OS2
CC61
CC62
COUT60 - COUT62
Outputs
COUT6 COUT6 COUT6
0
1
2
Rotate left,
1
0° phase shift 1
0
1
inactive inactive active
inactive active
0
0
inactive inactive active
active
inactive inactive
1
1
0
inactive active
inactive active
inactive inactive
0
1
0
inactive active
inactive inactive inactive active
0
1
1
active
inactive inactive inactive inactive active
0
0
1
active
inactive inactive inactive active
inactive
1
1
0
active
inactive inactive inactive active
inactive
1
0
0
active
inactive inactive inactive inactive active
1
0
1
inactive active
inactive inactive inactive active
0
0
1
inactive active
inactive active
0
1
1
inactive inactive active
active
inactive active
Rotate right
inactive
inactive inactive
inactive inactive
0
1
0
inactive inactive active
Slow down
X
X
X
inactive inactive inactive active
Idle1)
X
X
X
inactive inactive inactive inactive inactive inactive
1)
active
inactive
active
In case of the sampled Hall inputs were neither the current nor the expected Hall pattern, the bit WHE (wrong
Hall event) is set which also can cause an interrupt and sets the IDLE mode clearing MCMP (modulation
outputs are inactive).
Data Sheet
50
V 1.0, 2003-05
C868
For Brushless-DC motors there is a special mode (MSEL6x = ’1000b’) which is
triggered by a change of the Hall-inputs (CCPOSx). This mode shows the capabilities of
the CCU6. Here T12’s channel 0 acts in capture function, channel 1 and 2 in compare
function (without output modulation) and the multi-channel-block is used to trigger the
output switching together with a possible modulation of T13.
After the detection of a valid Hall edge the T12 count value is captured to channel 0
(representing the actual motor speed) and resets the T12. When the timer reaches the
compare value in channel 1, the next multi-channel state is switched by triggering the
shadow transfer of bit field MCMP (if enabled in bit field SWEN). This trigger event can
be combined with several conditions which are necessary to implement a noise filtering
(correct Hall event) and to synchronize the next multi-channel state to the modulation
sources (avoiding spikes on the output lines). This compare function of channel 1 can be
used as a phase delay for the position input to the output switching which is necessary
if a sensorless back-EMF technique is used instead of Hall sensors. The compare value
in channel 2 can be used as a time-out trigger (interrupt) indicating that the motors
destination speed is far below the desired value which can be caused by a abnormal load
change. In this mode the modulation of T12 has to be disabled (T12MODENx = ’0’).
CC60
act. speed
CC61
phase delay
CC62
timeout
ch0 gets
captured
value for
act. speed
ch2 compare
for timeout
capture
event resets
T12
ch1 compare
for phase delay
CCPOS0
1
1
1
0
0
CCPOS1
0
0
1
1
1
CCPOS2
1
0
0
0
1
0
0
1
CC6x
COUT6y
Figure 0-2
Data Sheet
Timer T12 Brushless-DC Mode (MSEL6x = 1000)
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C868
A/D Converter
The C868 includes a high performance / high speed 8-bit A/D-Converter (ADC) with 5
analog input channels. It operates with a successive approximation technique and uses
self calibration mechanisms for reduction and compensation of offset and linearity errors.
The A/D converter provides the following features:
–
–
–
–
–
–
–
5 multiplexed input channels, which can also be used as digital inputs
8-bit resolution with TUE of +/- 2 LSB8.
Single or continuous conversion mode
Start of conversion by software and hardware
Interrupt request generation after each conversion
Using successive approximation conversion technique via a capacitor array
Powerdown in normal, idle and slow-down modes
The ADC supports two conversion modes - single and continuous conversions. For
each mode, there are two ways in which conversion can be started - by software and by
the T13PM signal from the CCU module.
Writing a ‘0’ to bit CCU_ADEX select conversion control by ADST. Writing a ’1’ to bit
field ADST starts conversion on the channel that is specified by ADCH. In single
conversion mode, bit field ADM is cleared to ’0’. This is the default mode selected after
hardware reset. When a conversion is started, the channel specified is sampled. The
busy flag ADBSY is set and ADST is cleared. When the conversion is completed, the
interrupt request signal ADCIRQ is asserted possitively for 2 clocks and the 8-bit result
together with the number of the converted channel is transferred to the result register
ADDATH.
In continuous conversion mode, bit field ADM is set to ’1’. In this mode, the ADC
repeatedly converts the channel specified by ADCH. Bit ADST is cleared at the
beginning of the first conversion. The busy flag ADBSY is asserted until the last
conversion is completed. At the end of each conversion, the interrupt request signal
ADCIRQ will be activated. To stop conversion, ADM has to be reset by software. If the
channel number ADCH is changed while continuous conversion is in progress, the new
channel specified will be sampled in the conversions that follow.
A new request to start conversion will be allowed only after the completion of any
conversion that is in progress.
Writing a ‘1’ to bit CCU_ADEX select conversion control by T13PM trigger signal from
the CCU module.
Note: Caution must be taken when changing conversion start source. To change
conversion source from software to hardware trigger, it is best to let remaining
software conversion to complete before changing. To change conversion source
from hardware trigger to software, it is best to change source first, let any
Data Sheet
52
V 1.0, 2003-05
C868
remaining hardware conversion to complete before beginning a software
conversion.
Conversion and sample time control
The conversion and sample times are programmed via the bit fields ADCTC and ADSTC
respectively of the register ADCON1. Bit field ADCTC (conversion time control) selects
the internal ADC clock - adc_clk. Bit field ADSTC (sample time control) selects the
sample time.
The total A/D conversion time is given by:
tADCC = 2/fSYS + tS + 8/adc_clk
[5]
The sample time tS is configured in periods of the selected internal ADC clock. The table
below lists the possible combinations.
ADCTC
ADC Basic Clock
adc_clk
ADSTC
000 (default) 32
fSYS / 32
000 (default) 2
001
28
fSYS / 28
001
4
010
24
fSYS / 24
010
6
011
20
fSYS / 20
011
8
100
16
fSYS / 16
100
10
101
12
fSYS / 12
101
12
110
8
fSYS / 8
110
14
111
4
fSYS / 4
111
16
Data Sheet
Clock
Divider
(TVC)
53
Sample Time tS
(Periods of
adc_clk, STC)
V 1.0, 2003-05
C868
Interrupt System
The C868 provides 13 interrupt vectors with four priority levels. Nine interrupt requests
are generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial channel, A/D
converter, and the capture/compare unit with 4 interrupts) and four interrupts may be
triggered externally.
The wake-up from power-down mode interrupt has a special functionality which allows
the software power-down mode to be terminated by a short negative pulse at pins
CCPOS0/T2/INT0/AN0 or P1.4/RxD.
The 13 interrupt sources are divided into six groups. Each group can be programmed to
one of the four interrupt priority levels. Additionally, 4 of these interrupt sources are
channeled from 7 Capture/Compare (CCU6) interrupt sources.
Figure 23 to Figure 28 give a general overview of the interrupt sources and illustrate
the request and control flags.
Data Sheet
54
V 1.0, 2003-05
C868
ICC60R
P3.7/
CC0
ISL.0
ICC60F
ISL.1
ENCC60R
IENL.0
ENCC60F
ISL.2
ICC61F
ISL.3
ENCC61R
IENL.2
ISL.4
ICC62F
ISL.5
T12
One Match
T12
Period
Match
T12PM
ISL.7
T13
Compare
Match
T13CM
T13
Period Match
T13PM
ISH.0
ISH.1
P3.1/
CTRAP
WHE
ISH.5
Correct
Hall Event
CHE
ISH.4
INPL.3 INPL.2
≥1
ENCC62F
IENL.5
ENT12OM
IENL.6
INPL.5 INPL.4
≥1
ENT12PM
IENL.7
ENT13CM
IENH.0
INPH.3 INPH.2
≥1
ENT13PM
IENH.1
TRPF
ISH.2
Wrong
Hall Event
ENCC62R
IENL.4
T12OM
ISL.6
≥1
ENCC61F
IENL.3
ICC62R
P3.3/
CC2
INPL.1 INPL.0
IENL.1
ICC61R
P3.5/
CC1
≥1
ENTRPF
IENH.2
ENWHE
IENH.5
INPH.5 INPH.4
≥1
INPH.1 INPH.0
ENCHE
IENH.4
INPL.7 INPL.6
Capcom Interrupt node 0
Capcom Interrupt node 1
Capcom Interrupt node 2
Capcom Interrupt node 3
Figure 23
Data Sheet
Capture/Compare module interrupt structure
55
V 1.0, 2003-05
C868
Highest
Priority Level
INT0_
CORE_N
(CCPOS /
IT0
T2 /
INT0 /
TCON.0
AN0)
A/D Converter
IE0
TCON.1
EX0
0003H
Lowest
Priority Level
IEN0.0
IADC
IRCON1.0
EADC
0033H
IEN1.0
Timer 0
Overflow
IP1.0
IP0.0
IP1.1
IP0.1
TF0
TCON.5
ET0
000BH
IEN0.1
CCPOS2 /
INT2 /
AN2
P
o
l
l
i
n
g
S
e
q
u
e
n
c
EX2
ESEL2
IRCON0.0 EX2
003BH
IEN1.1
EXICON.0
EA
Bit addressable
IEN0.7
Request flag is cleared by hardware
Figure 24
Data Sheet
Interrupt Structure, Overview Part 1
56
V 1.0, 2003-05
C868
Priority Level
Highest
CCPOS1 /
T2EX /
INT1 /
AN1
IE1
TCON.3
IT1
EX1
0013H
Lowest
Priority Level
IEN0.2
TCON.2
P
o
l
l
i
n
g
S
e
q
u
e
n
c
EXINT3
P1.3 /
INT3
ESEL3
IRCON0.1 EX3
0043H
IEN1.2
EXICON.1
Capture/compare
interrupt node 0
INP0
IRCON1.2
EINP0
0083H
IEN2.2
EA
IP1.2
IP0.2
IEN0.7
Bit addressable
Request flag is cleared by hardware
Figure 25
Data Sheet
Interrupt Structure, Overview Part 2
57
V 1.0, 2003-05
C868
Highest
Priority Level
Lowest
Priority Level
Timer 1
Overflow
P
o
l
l
i
n
g
S
e
q
u
e
n
c
TF1
TCON.7
ET1
001BH
IEN0.3
Capture/compare
interrupt node 1
INP1
IRCON1.3
EINP1
008BH
IEN2.3
IP1.3
EA
IP0.3
IEN0.7
Bit addressable
Request flag is cleared by hardware
Figure 26
Data Sheet
Interrupt Structure, Overview Part 3
58
V 1.0, 2003-05
C868
Highest
Priority Level
Priority Level
RI
UART
SCON.0
ES
TI
0023H
IEN0.4
SCON.1
Capture/compare
interrupt node 2
P
o
l
l
i
n
g
S
e
q
u
e
n
c
≥1
INP2
IRCON1.4
EINP2
0093H
IEN2.4
EA
Bit addressable
IP1.4
IP0.4
IEN0.7
Request flag is cleared by hardware
Figure 27
Data Sheet
Interrupt Structure, Overview Part 4
59
V 1.0, 2003-05
C868
Highest
Priority Level
Timer 2
Overflow
TF2
IRCON0.6
ET2
002BH
Priority Level
IEN0.5
Capture/compare
interrupt node 3
P
o
l
l
i
n
g
S
e
q
u
e
n
c
INP3
IRCON1.5
EINP3
009BH
IEN2.5
EA
IP1.5
IP0.5
IEN0.7
Bit addressable
Request flag is cleared by hardware
Figure 28
Data Sheet
Interrupt Structure, Overview Part 5
60
V 1.0, 2003-05
C868
Table 12
Interrupt Source and Vectors
Interrupt Source
Interrupt Vector
Address(core
connections)
Interrupt Request Flags
External Interrupt 0
0003H(EX0)
IE0
Timer 0 Overflow
000BH(ET0)
TF0
External Interrupt 1
0013H(EX1)
IE1
Timer 1 Overflow
001BH(ET1)
TF1
Serial Channel
0023H(ES)
RI / TI
Timer 2 Overflow
002BH(EX5)
TF2
A/D Converter
0033H(EX6)
IADC
External Interrupt 2
003BH(EX7)
IEX2
External Interrupt 3
0043H(EX8)
IEX3
004BH(EX9)
0053H(EX10)
005BH(EX11)
0063H(EX12)
006BH(EX13)
CAPCOM interrupt node 0
0083H(EX14)
INP01)
CAPCOM interrupt node 1
008BH(EX15)
INP11)
CAPCOM interrupt node 2
0093H(EX16)
INP21)
CAPCOM interrupt node3
009BH(EX17)
INP31)
00A3H(EX18)
00ABH(EX19)
00D3H(EX20)
00DBH(EX21)
00E3H(EX22)
Wake-up from power-down
mode
1)
007BH
–
Capture/compare has 10 interrupt sources channeled to the 4 interrupt nodes INP0..3. The 3 capture/compare
ports has 3 pairs of interrupt request flags, ICC60R, ICC60F, ICC61R, ICC61F, ICC62R, ICC62F. The other
flags are T12OM, T12PM, T13CM, T13PM, TRPF, WHE, CHE.
Data Sheet
61
V 1.0, 2003-05
C868
lf two or more requests of different priority levels are received simultaneously, the
request of the highest priority is serviced first. lf requests of the same priority level are
received simultaneously, an internal polling sequence determines which request is to be
serviced first. Thus, within each priority level there is a second priority structure
determined by the polling sequence. This is illustrated in Table 13
.
Table 13
Interrupt Source Structure
Interrupt Priority Bits
Group of Interrupt
Group
Interrupt Source Priority
0
IP0.0
EXINT0
IADC
1
IP0.1
TF0
EXINT2
2
IP0.2
EXINT1
EXINT3
3
IP0.3
TF1
INP11)
4
IP0.4
RI + TI
INP21)
5
IP0.5
TF2
INP31)
1)
High Priority
Priority
Priority
Low
High
INP01)
Low
Capture/compare has 10 interrupt sources channeled to the 4 interrupt nodes INP0..3. The 3 capture/
compare ports has 3 pairs of interrupt request flags, ICC60R, ICC60F, ICC61R, ICC61F, ICC62R, ICC62F.
The other flags are T12OM, T12PM, T13CM, T13PM, TRPF, WHE, CHE.
Within a column, the topmost interrupt is serviced first, then the second and the third,
when available. The interrupt groups are serviced from left to right of the table. A lowpriority interrupt can itself be interrupted by a higher-priority interrupt, but not by another
interrupt of the same or a lower priority. An interrupt of the highest priority level cannot
be interrupted by another interrupt source.
Data Sheet
62
V 1.0, 2003-05
C868
Fail Save Mechanisms
The C868 offers enhanced fail save mechanisms, which allow an automatic recovery
from software upset or hardware failure :
a programmable watchdog timer (WDT), with variable time-out period from 12.8µs to
819.2µs at fSYS = 40 MHz.
Programmable Watchdog Timer
To protect the system against software failure, the user’s program has to clear this
watchdog within a previously programmed time period. lf the software fails to do this
periodical refresh of the watchdog timer, an internal reset will be initiated. The software
can be designed so that the watchdog times out if the program does not work properly.
lt also times out if a software error is based on hardware-related problems.
The watchdog timer in the C868 is a 16-bit timer, which is incremented by a count rate
of fSYS/2 upto fSYS/128. The machine clock of the C868 is divided by a prescaler, a divideby-two or a divide-by-128 prescaler. The upper 8 bits of the Watchdog Timer can be
preset to a user-programmable value via a watchdog service access in order to vary the
watchdog expire time. The lower 8 bits are reset on each service access. Figure 29
shows the block diagram of the watchdog timer unit.
WDT
Control
1:2
fSYS
WDTREL
Clear
MUX
WDT Low Byte
WDT High Byte
WDTRST
1:128
DISWDT
WDTIN
Figure 29
Block Diagram of the Programmable Watchdog Timer
After a reset, the Watchdog Timer is automatically enabled. If it is disabled, it cannot be
enabled again during active mode of the device. If the software fails to clear the
watchdog timer an internal reset will be initiated. The reset cause (external reset or reset
caused by the watchdog) can be examined by software (status flag WDTR in SCUWDT
is set). A refresh of the watchdog timer is done by setting bits WDTRE and WDTRS (in
Data Sheet
63
V 1.0, 2003-05
C868
SFR SCUWDT) consecutively. This double instruction sequence has been implemented
to increase system security.
It must be noted, however, that the watchdog timer is halted during the idle mode and
power-down mode of the processor (see section "Power Saving Modes"). It is not
possible to use the idle mode in combination with the watchdog timer function.
Therefore, even the watchdog timer cannot reset the device when one of the power
saving modes has been entered accidentally.
The time period for an overflow of the Watchdog Timer is programmable in two ways :
– the input frequency to the Watchdog Timer can be selected via bit WDTIN in
register WDTCON to be either fSYS/2 or fSYS/128.
– the reload value WDTREL for the high byte of WDT can be programmed in register
WDTCON.
The period PWDT between servicing the Watchdog Timer and the next overflow can
therefore be determined by the following formula:
[0.1]
PWDT =
2(1 +WDTIN*6)
*
(216
- WDTREL *
2 8)
fSYS
Table 14 lists the possible ranges for the watchdog time which can be achieved using a
certain module clock. Some numbers are rounded to 3 significant digits.
Table 14
Watchdog Time Ranges
Reload value
in WDTREL
Prescaler for fSYS
2 (WDTIN = ‘0’)
128 (WDTIN = ‘1’)
40 MHz
20 MHz
16 MHz
40 MHz
20 MHz
16 MHz
FFH
12.8 µs
25.6 µs
32.0 µs
819.2 µs 1.64 ms 2.05 ms
7FH
1.65 ms 3.3 ms
4.13 ms
105.7 ms 211.3 ms 264 ms
00H
3.28 ms 6.55 ms 8.19 ms 209.7 ms 419.4 ms 524 ms
For safety reasons, the user is advised to rewrite WDTCON each time before the
Watchdog Timer is serviced.
Data Sheet
64
V 1.0, 2003-05
C868
Power Saving Modes
The C868 provides two basic power saving modes, the idle mode and the power down
mode. Additionally, a slow down mode is available. This power saving mode reduces the
internal clock rate in normal operating mode and it can also be used for further power
reduction in idle mode.
• Idle Mode
In the idle mode, the oscillator of the C868 continues to run, but the CPU is gated off
from the clock signal. However, the interrupt system, the serial port, the A/D converter,
the capture/compare unit, and all timers are further provided with the clock. The CPU
status is preserved in its entirety: the stack pointer, program counter, program status
word, accumulator, and all other registers maintain their data during idle mode.
• Slow Down Mode
In some applications, where power consumption and dissipation are critical, the
controller might run for a certain time at reduced speed (for example, if the controller
is waiting for an input signal). Since in CMOS devices, there is an almost linear
dependence of the operating frequency and the power supply current, so, a reduction
of the operating frequency results in reduced power consumption.
• Software Power Down Mode
In the software power down mode, the on-chip oscillator which operates with the XTAL
pins and the PLL are all stopped. Therefore, all functions of the microcontroller are
stopped and only the contents of the on-chip RAM, XRAM and the SFR's are
maintained. The port pins, which are controlled by their port latches, output the values
that are held by their SFR's. The port pins which serve the alternate output functions
show the values they had at the end of the last cycle of the instruction which initiated
the power down mode. ALE is held at logic low level or high impedance if disabled. In
the power down mode of operation, VDDP can be reduced to minimize power
consumption. It must be ensured, however, that VDDP is not reduced before the power
down mode is invoked, and that VDDP is restored to its normal operating level before
the power down mode is terminated.
Data Sheet
65
V 1.0, 2003-05
C868
Table 15
Power Saving Modes Overview
Mode
Entering
Leaving by
Remarks
Idle
Mode
ORL PCON,#01H
Occurance of any
enabled interrupt
CPU clock is stopped;
CPU maintains its
data;
peripheral units are
active (if enabled) and
provided with clock
Hardware Reset
Slow
Down
Mode
In normal mode:
ORL PCON,#10H
ANL PCON,#0EFH
or Hardware Reset
Internal clock rate is
reduced to a
configurable factor of
1/ to 1/ of the
2
32
system clock rate
With idle mode:
ORL PCON,#11H
Occurance of any
enabled interrupt to
exit idle mode and
the instruction
ANL PCON,#0EFH
to terminate slow
down mode
CPU clock is stopped;
CPU maintains all its
data;
Peripheral units are
active (if enabled) and
provided with a
configurable factor of
1/ to 1/ of the
2
32
system clock rate
Hardware Reset
Software
Power
Down
mode
Data Sheet
With external wake-up
capability from power down
enabled
ORL PMCON0,#01H
(to wake-up via pin INT0)
or
ORL PMCON0,#03H
(to wake-up via pin RxD)
ORL PCON,#02H
Hardware Reset
Oscillator is stopped;
Contents
of on-chip
When INT0 or RxD
RAM
and
SFR’s are
goes low for at least
maintained
10 µs (latch phase).
But it is desired that
the corresponding
pin must be held at
high level during the
power down mode
entry and up to the
wake-up.
With external wake-up
capability from power down
disabled
ORL PCON,#02H
Hardware Reset
66
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C868
Device Specifications
Absolute Maximum Ratings
Absolute Maximum Rating Parameters
Parameter
Symbol
Limit Values
min.
TA
Storage temperature
TSTG
Voltage on VDDP pins with respect VDDP
to ground (VSSP)
Voltage on any pin except int/
VIN0
-40
Ambient temperature under bias
Unit Notes
max.
125
°C
-65
150
°C
-
-0.3
4.6
V
-
-0.5
4.6
V
-
Voltage on any int/analog pin with VIN1
respect to ground (VSSP)
-0.5
4.6
V
-
Voltage on XTAL pins with
respect to ground (VSSC)
VIN2
-0.5
4.6
V
-
Input current on any pin during
overload condition
ΙOV
-10
10
mA
-1)
Absolute sum of all input currents Σ|ΙOV|
during overload condition
-
43
mA
-
PDISS
-
tbd
W
-
analog and XTAL with respect to
ground (VSSP)
Power dissipation
1)
Proper operation is not guaranteed if overload conditions occur on functional pins like XTAL2 etc.
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN>VDDP or VIN<VSSP,
VIN2>VDDC or VIN2<VSSC) the voltage on VDDP pin with respect to ground (VSSP)
must not exceed the values defined by the absolute maximum ratings.
Data Sheet
67
V 1.0, 2003-05
C868
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the C868. All parameters specified in the following sections refer to these
operating conditions, unless otherwise noticed.
Operating Condition Parameters
Parameter
Symbol
Limit Values
min.
Digital supply voltage VDDP
3.0
Unit Notes
max.
3.6
V
Active mode,
fSYSmax = 40 MHz
tbd
Digital ground
voltages
VSSC,VSSP
Ambient temperature
TA
3.6
0
V
PowerDown
mode1)
V
-
-40
85
°C
SAF-C868...
-40
125
°C
SAK-C868...
3.0V
VDDP +
V
-
V
-
Analog reference
voltage
VAREF
Analog ground
voltage
VAGND
Analog input voltage
VAIN
fOSC
VAGND
VAREF
V
6.67
10.67
MHz -
Input current on any
pin during overload
condition except int/
analog and XTAL
ΙOV0
-5
5
mA
-2)3)
int/analog pin
ΙOV1
-2
5
mA
-3)4)
XTAL pin
ΙOV2
-5
5
mA
-3)5)
Absolute sum of all
input currents during
overload condition
ΣΙOV
-
|20|
mA
-3)
External Clock
0.1
VSSP - 0.1 VSSP +
0.1
Notes:
1)
Oscillator or external clock disabled.
2)
Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the
specified operating range (i.e. VOV > VDDP +0.5V or VOV < VSSP -0.5V). The absolute sum of input currents
on all port pins may not exceed 20mA. The suply voltages VDDP and VSSP must remain within the specified
limits.
3)
Not 100% tested, but guaranteed by design characterization.
Data Sheet
68
V 1.0, 2003-05
C868
4)
Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the
specified operating range (i.e. VOV > tbd or VOV < VSSC -0.5V). The absolute sum of input currents on all
port pins may not exceed 20mA. The suply voltages VDDP and VSSP must remain within the specified limits.
5)
Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the
specified operating range (i.e. VOV > VDDC +0.5V or VOV < VSSC -0.5V). The absolute sum of input currents
on all port pins may not exceed 20mA. The suply voltages VDDP and VSSP must remain within the specified
limits.
Data Sheet
69
V 1.0, 2003-05
C868
DC Characteristics
(Operating Conditions apply)
Parameter
Symbol
Limit Values
min.
Input low voltages
all except XTAL2, int/analog
int/analog
XTAL2
Input high voltages
all except XTAL2, int/analog
int/analog
XTAL2
Output low voltage
Unit Test Condition
max.
–1)
VIL0
VIL1
VIL2
-0.5
-0.5
-0.5
VIH0
VIH1
VIH2
VOL
0.7VDDP VDDP+0.5 V
0.7VDDC VDDP+0.5 V
0.7VDDC VDDC+0.5 V
0.3VDDP
0.3VDDC
0.1VDDC
V
V
V
–
–
0.45
V
SAF-C868...
IOL=10mA
–
0.55
V
SAK-C868...
IOL=10mA
VOH
ILI0
2.4
–
V
IOH=10mA
–
±0.5
uA
0.4<VIN<VDDP
Input leakage current (int/
analog)
ILI1
–
±0.5
uA
0.4<VIN<VDDP2)
Input low current (XTAL2)
ILI2
VDDC
–
±10
uA
0.4<VIN<VDDC
2.253)
2.75
V
–
136
470
nF
–4)
-
10
pF
fC = 1MHz
TA= 250C
Output high voltage
Input leakage current (all
except int/analog)
Digital supply voltage
Blocking capacitor for VDDC
Pin capacitance
CIO
Note:
1)
Interrupt/analog pins are input only and has CMOS characteristics whereas the other I/O pins have TTL
characteristics.
2)
The leakage current of interrupt/analog pins depends on the leakage current of the CMOS pad for the digital
functions and the analog pad.
3)
The VDDC is measured under the following conditions:
Microcontroller in power down mode;RESET = VDDP; XTAL2 = VSSC; XTAL1 = N.C.; VAGND= VSSP; VAREF=
VDDP; RxD/INT0 = VDDP; all other pins are set to input and connected to gnd; ALE output disabled and
connected to gnd; 20mA current sourced from the VDDC pin.
4)
Ceramic type (±20%) max ESR: 25mΩ ,max trace length to capacitor is 10mm.
Data Sheet
70
V 1.0, 2003-05
C868
Power Supply Current
Parameter
Symbol
Limit Values
1)
typ.
max.
Unit Test Condition
2)
4)
40
IDDP
MHz3)
13.1
15.6
mA
C868-1R 40
IDDP
MHz3)
13.5
15.5
mA
IDDP
40
MHz3)
7.8
9.6
mA
C868-1R 40
IDDP
MHz3)
7.9
9.1
mA
IDDP
40
MHz3)
3.5
4.4
mA
C868-1R 40
IDDP
MHz3)
3.6
4.1
mA
IDDP
40
MHz3)
3.4
4.2
mA
C868-1R 40
IDDP
MHz3)
3.6
4.1
mA
PowerC868-1S
down mode
IPDP
240
300
uA
SAF-C868...8)
240
400
uA
SAK-C868...8)
C868-1R
IPDP
240
300
uA
SAF-C868...8)
240
400
uA
SAK-C868...8)
Active
mode
Idle mode
C868-1S
C868-1S
Active
mode with
slow-down
enabled
C868-1S
Idle mode
with slowdown
enabled
C868-1S
5)
6)
7)
Note:
1)
The typical IDDP values are periodically measured at TA = + 25 °C but not 100% tested.
2)
The maximum IDDP values are measured under worst case conditions (TA = – 40 °C and VDDP = 3.6 V).
3)
System clock, set by using external clock of 10.67MHz and setting KDIV in CMCON to 010 (factor of 4)
4)
IDDP (active mode) is measured with:
XTAL2 driven with tR, tF = 5 ns, VIL1,VIL2 = VSSP + 0.5 V, VIH1,VIH2 = VDDP – 0.5 V; XTAL1 = N.C.;
RESET = VDDP; all other pins are disconnected. ?IDDP would be slightly higher if the crystal oscillator is used
(approx. 1 mA).
Data Sheet
71
V 1.0, 2003-05
C868
5)
IDDP (idle mode) is measured with all output pins disconnected and with all peripheral disabled:
XTAL2 driven with tR, tF = 5 ns, VIL1,VIL2 = VSSP + 0.5 V, VIH1,VIH2 = VDDP – 0.5 V; XTAL1 = N.C.;
RESET = VDDP; all other pins are disconnected.
6)
IDDP (active mode with slow down mode) is measured with all output pins disconnected:
XTAL2 driven with tR, tF = 5 ns, VIL1,VIL2 = VSSP + 0.5 V, VIH1,VIH2 = VDDP – 0.5 V; XTAL1 = N.C.;
RESET = VDDP; all other pins are disconnected; the microcontroller is put into slow-down mode by software
with the slow-down clock set to 1/32 of system clock.
7)
IDDP (idle mode with slow down mode) is measured with all output pins disconnected and with all peripheral
disabled:
XTAL2 driven with tR, tF = 5 ns, VIL1,VIL2 = VSSP + 0.5 V, VIH1,VIH2 = VDDP – 0.5 V; XTAL1 = N.C.;
RESET = VDDP; all other pins are disconnected; the microcontroller is put into slow-down mode by software
with the slow-down clock set to 1/32 of system clock.
8)
IPDC and IPDP (power-down mode) are measured under the following conditions:
RESET = VDDP; XTAL2 = VSSC; XTAL1 = N.C.; VAGND= VSSP; VAREF= VDDP; RxD/INT0 = VDDP; all other pins
are set to input and connected to gnd; ALE output disabled and connected to gnd.
Data Sheet
72
V 1.0, 2003-05
C868
Power Supply Current Calculation Formulae
Parameter
Active mode
C868-1S
C868-1R
Idle mode
C868-1S
C868-1R
Active mode with
slow-down enabled
C868-1S
C868-1R
Idle mode with slowdown enabled
C868-1S
C868-1R
1)
Symbol
Formula1)
IDDPtyp
IDDPmax
IDDPtyp
IDDPmax
IDDPtyp
IDDPmax
IDDPtyp
IDDPmax
IDDPtyp
IDDPmax
IDDPtyp
IDDPmax
IDDPtyp
IDDPmax
IDDPtyp
IDDPmax
0.25* fSYS + 3.1
0.26 * fSYS + 5.2
0.27* fSYS + 2.7
0.29 * fSYS + 3.9
0.13* fSYS + 2.6
0.13 * fSYS + 4.0
0.13* fSYS + 3.7
0.15 * fSYS + 3.1
0.01 * fSYS + 3.1
0.02 * fSYS + 3.6
0.01 * fSYS + 3.2
0.01 * fSYS + 3.7
0.01* fSYS + 3.0
0.01 * fSYS + 3.8
0.02* fSYS + 2.8
0.02 * fSYS + 3.3
fSYS is in MHz and results in mA.
Data Sheet
73
V 1.0, 2003-05
C868
A/D Converter Characteristics
(Operating Condition Parameters)
Parameter
Symbol
Limits
min
max
Unit Test Condition
1)
Analog input voltage
VAIN
VAGND
VAREF
Sample time
tS
64*tSYS
52*tSYS
48*tSYS
40*tSYS
32*tSYS
24*tSYS
16*tSYS
8*tSYS
512*tSYS ns
448*tSYS
384*tSYS
320*tSYS
256*tSYS
192*tSYS
128*tSYS
64*tSYS
Prescaler/32
Prescaler/28
Prescaler/24
Prescaler/20
Prescaler/16
Prescaler/12
Prescaler/8
Prescaler/4
Conversion cycle time
tADCC
322*tSYS
282*tSYS
242*tSYS
202*tSYS
162*tSYS
122*tSYS
82*tSYS
42*tSYS
770*tSYS ns
674*tSYS
578*tSYS
482*tSYS
386*tSYS
290*tSYS
194*tSYS
98*tSYS
Prescaler/32
Prescaler/28
Prescaler/24
Prescaler/20
Prescaler/16
Prescaler/12
Prescaler/8
Prescaler/4
Total unadjusted error
TUE
–
±2
±3
LSB VAGND ≤ VAIN ≤ VAREF2)
VAGND ≤ VAIN ≤ VAREF3)
ADC input resistance
RAIN
–
1.5
kΩ
ADC input capacitance CAIN
–
10
pF
5)
ADC reference pin
capacitance
–
40
pF
5)
CAREF
V
4)5)
Note:
1)
VAIN may exceed VAGND or VAREF up to the maximum ratings. However, the conversion result in these
cases will be 00H or FFH, respectively.
2)
TUE (max.) is tested at – 20 ≤ TA ≤ 125 °C; VDDP = 3.3 V; VAREF = VDDP V and VSSP = VAGND. It is guaranteed
by design characterization for all other voltages within the defined voltage range.
3)
TUE (max.) is tested at – 40 ≤ TA < – 20 °C; VDDP ≤ 3.3 V; VAREF = VDDP and VSSP = VAGND. It is guaranteed
by design characterization for all other voltages within the defined voltage range.
Data Sheet
74
V 1.0, 2003-05
C868
4)
During the sample time the input capacitance CAIN must be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS.
After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result.
5)
Not 100% tested, but guaranteed by design characterization.
Data Sheet
75
V 1.0, 2003-05
C868
Clock calculation table for ADC
TVC1)
32
STC2)
2
4
6
8
10
12
14
16
tADC3)
tADCC
322
386
450
514
578
642
706
770
tSYS
tS
64
128
192
256
320
384
448
512
tSYS
TVC1)
28
STC2)
2
4
6
8
10
12
14
16
tADC3)
tADCC
282
338
394
450
506
562
618
674
tSYS
tS
56
112
168
224
280
336
392
448
tSYS
TVC1)
24
STC2)
2
4
6
8
10
12
14
16
tADC3)
tADCC
242
290
338
386
434
482
530
578
tSYS
tS
48
96
144
192
240
288
336
384
tSYS
TVC1)
20
STC2)
2
4
6
8
10
12
14
16
tADC3)
tADCC
202
242
282
322
362
402
442
482
tSYS
tS
40
80
120
160
200
240
280
320
tSYS
STC2)
2
4
6
8
10
12
14
16
tADC3)
tADCC
162
194
226
258
290
322
354
386
tSYS
tS
32
64
96
128
160
192
224
256
tSYS
STC2)
2
4
6
8
10
12
14
16
tADC3)
tADCC
122
146
170
194
218
242
266
290
tSYS
tS
24
48
72
96
120
144
168
192
tSYS
TVC1)
16
TVC1)
Data Sheet
12
76
V 1.0, 2003-05
C868
TVC1)
8
STC2)
2
4
6
8
10
12
14
16
tADC3)
tADCC
82
98
114
130
146
162
178
194
tSYS
tS
16
32
48
64
80
96
112
128
tSYS
STC2)
2
4
6
8
10
12
14
16
tADC3)
tADCC
42
50
58
66
74
82
90
98
tSYS
tS
8
16
24
32
40
48
56
64
tSYS
TVC1)
4
1)
TVC is the clock divider specified by bit fields ADCTC.
2)
STC is the sample time control specified by bit fields ADSTC.
3)
tADC is tSYS*TVC
Data Sheet
77
V 1.0, 2003-05
C868
AC Characteristics
(Operating Condition Apply)
External Clock Drive Characteristics
Parameter
Symbol
Limit Values
Unit
Variable Ext Clock
6.67 to 10.67 MHz
min
max
Oscillating period
tOSC
93.75
150
ns
High time
t1
46.875
75
ns
Low time
t2
46.875
75
ns
Rise time
tR
-
10
ns
Fall time
tF
-
10
ns
ALE Characteristics
Parameter
Symbol
Limit Values
Unit
System freq = 6.25MHz to 40MHz
Duty Cycle 0.5
min
max
ALE pulse width
tAWD
50
320
ns
ALE period
tACY
150
960
ns
Data Sheet
78
V 1.0, 2003-05
C868
tR
t1
tF
0.7 VDD c
0.2 VDDc- 0.1
t2
tOSC
Figure 30
MCT04105
External Clock Drive on XTAL2
tAWD
tACY
Figure 31
Data Sheet
ALE Characteristic
79
V 1.0, 2003-05
C868
Package Outlines
1.27
0.1
0.35 +0.15 2)
1
8˚ MAX.
7.6 -0.2 1)
0.4 +0.8
10.3 ±0.3
0.2 28x
28
0.35 x 45˚
0.23 +0.09
2.45 -0.2
2.65 MAX.
0.2 -0.1
Plastic Package, P-DSO-28-1 for SAF-C868-1RG BA, SAF-C868-1SG BA
SAF-C868A-1RG BA, SAF-C868A-1SG BA and SAF-C868P-1SG BA,
SAK-C868-1RG BA, SAK-C868-1SG BA, SAK-C868A-1RG BA,
SAK-C868A-1SG BA and SAK-C868P-1SG BA.
15
18.1 -0.4
1)
14
Index Marking
1)
2)
Figure 32
Data Sheet
Does not include plastic or metal protrusion of 0.15 max. per side
Does not include dambar protrusion of 0.05 max. per side
DSO-28-1 Package Outlines
80
V 1.0, 2003-05
C868
Plastic Package, P-TSSOP-38-1 for SAF-C868-1RR BA,
SAF-C868-1SR BA, SAF-C868A-1RR BA, SAF-C868A-1SR BA,
SAF-C868P-1SR BA, SAK-C868-1RR BA, SAK-C868-1SR BA,
SAK-C868A-1RR BA, SAK-C868A-1SR BA, and SAK-C868P-1SR BA.
B
0.125 +0.075
0˚...8˚
-0.035
1.2 MAX.
0.1 ±0.05
1 +0.05
-0.2
4.4 ±0.1 3)
0.5
C
2)
0.2 +0.07
-0.03
0.08
M
0.1
0.6 ±0.15
A C 38x
6.4
38
1
20
0.2 B 38x
19
9.7 ±0.1 1)
A
Index Marking
1)
Does not include plastic or metal protrusion of 0.15 max. per side
Does not include dambar protrusion of 0.08 max. per side
3)
Does not include plastic or metal protrusion of 0.25 max. per side
2)
Figure 33
Data Sheet
TSSOP-38-1 Package Outlines
81
V 1.0, 2003-05
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