CD4049UB, CD4050B August 1998 - Revised May 2004 Data sheet acquired from Harris Semiconductor SCHS046I CMOS Hex Buffer/Converters Applications The CD4049UB and CD4050B devices are inverting and non-inverting hex buffers, respectively, and feature logiclevel conversion using only one supply voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic-level conversions. These devices are intended for use as CMOS to DTL/TTL converters and can drive directly two DTL/TTL loads. (VCC = 5V, VOL ≤ 0.4V, and IOL ≥ 3.3mA.) • CMOS to DTL/TTL Hex Converter • CMOS Current “Sink” or “Source” Driver • CMOS High-To-Low Logic Level Converter [ /Title (CD40 49UB, CD405 The CD4049UB and CD4050B are designated as 0B) replacements for CD4009UB and CD4010B, respectively. Because the CD4049UB and CD4050B require only one /Subpower supply, they are preferred over the CD4009UB and ject CD4010B and should be used in place of the CD4009UB (CMO and CD4010B in all inverter, current driver, or logic-level S Hex conversion applications. In these applications the Buffer/ CD4049UB and CD4050B are pin compatible with the CD4009UB and CD4010B respectively, and can be Consubstituted for these devices in existing as well as in new verters) designs. Terminal No. 16 is not connected internally on the /Autho CD4049UB or CD4050B, therefore, connection to this terminal is of no consequence to circuit operation. For r () applications not requiring high sink-current or voltage /Keyconversion, the CD4069UB Hex Inverter is recommended. words (Harris Features Semi- • CD4049UB Inverting con• CD4050B Non-Inverting ductor, • High Sink Current for Driving 2 TTL Loads CD400 • High-To-Low Level Logic Conversion • 100% Tested for Quiescent Current at 20V 0, • Maximum Input Current of 1µA at 18V Over Full Package metal Temperature Range; 100nA at 18V and 25oC gate, • 5V, 10V and 15V Parametric Ratings CMOS Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE CD4049UBF3A -55 to 125 16 Ld CERDIP CD4050BF3A -55 to 125 16 Ld CERDIP CD4049UBD -55 to 125 16 Ld SOIC CD4049UBDR -55 to 125 16 Ld SOIC CD4049UBDT -55 to 125 16 Ld SOIC CD4049UBDW -55 to 125 16 Ld SOIC CD4049UBDWR -55 to 125 16 Ld SOIC CD4049UBE -55 to 125 16 Ld PDIP CD4049UBNSR -55 to 125 16 Ld SOP CD4049UBPW -55 to 125 16 Ld TSSOP CD4049UBPWR -55 to 125 16 Ld TSSOP CD4050BD -55 to 125 16 Ld SOIC CD4050BDR -55 to 125 16 Ld SOIC CD4050UBDT -55 to 125 16 Ld SOIC CD4050BDW -55 to 125 16 Ld SOIC CD4050BDWR -55 to 125 16 Ld SOIC CD4050BE -55 to 125 16 Ld PDIP CD4050NSR -55 to 125 16 Ld SOP CD4050BPW -55 to 125 16 Ld TSSOP CD4050BPWR -55 to 125 16 Ld TSSOP NOTE: When ordering, use the entire part number. The suffix R denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinouts CD4049UB (PDIP, CERDIP, SOIC, SOP, TSSOP) TOP VIEW 16 NC VCC 1 15 L = F G=A 2 14 F A 3 13 NC H=B 4 B 5 12 K = E 11 E I=C 6 10 J = D C 7 9 D VSS 8 1 CD4050B (PDIP, CERDIP, SOIC, SOP) TOP VIEW VCC 1 G=A 2 A 3 H=B 4 B 5 I=C 6 C 7 VSS 8 16 NC 15 L = F 14 F 13 NC 12 K = E 11 E 10 J = D 9 D CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright © 2004, Texas Instruments Incorporated CD4049UB, CD4050B Functional Block Diagrams CD4049UB A B C D E F 3 2 5 4 7 6 9 10 11 12 14 15 VCC VSS CD4050B G=A A H=B B I=C C J=D D K=E E L=F F 1 3 2 5 4 7 6 9 10 11 12 14 15 VCC 8 VSS NC = 13 NC = 16 G=A H=B I=C J=D K=E L=F 1 8 NC = 13 NC = 16 Schematic Diagrams VCC VCC P OUT R IN P P N N R IN N VSS FIGURE 1A. SCHEMATIC DIAGRAM OF CD4049UB, 1 OF 6 IDENTICAL UNITS 2 OUT VSS FIGURE 1B. SCHEMATIC DIAGRAM OF CD4050B, 1 OF 6 IDENTICAL UNITS CD4049UB, CD4050B Absolute Maximum Ratings Thermal Information Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . -0.5V to 20V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mA Package Thermal Impedance, θJA (see Note1): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W D (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W DW (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . . 65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265oC SOIC - Lead Tips Only Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications LIMITS AT INDICATED TEMPERATURE (oC) TEST CONDITIONS PARAMETER Quiescent Device Current IDD (Max) Output Low (Sink) Current IOL (Min) Output High (Source) Current IOH (Min) Out Voltage Low Level VOL (Max) Output Voltage High Level VOH (Min) Input Low Voltage, VIL (Max) CD4049UB Input Low Voltage, VIL (Max) CD4050B 3 25 VO (V) VIN (V) VCC (V) -55 -40 85 125 MIN TYP MAX UNITS - 0,5 5 1 1 30 30 - 0.02 1 µA - 0,10 10 2 2 60 60 - 0.02 2 µA - 0,15 15 4 4 120 120 - 0.02 4 µA - 0,20 20 20 20 600 600 - 0.04 20 µA 0.4 0,5 4.5 3.3 3.1 2.1 1.8 2.6 5.2 - mA 0.4 0,5 5 4 3.8 2.9 2.4 3.2 6.4 - mA 0.5 0,10 10 10 9.6 6.6 5.6 8 16 - mA 1.5 0,15 15 26 25 20 18 24 48 - mA 4.6 0,5 5 -0.81 -0.73 -0.58 -0.48 -0.65 -1.2 - mA 2.5 0,5 5 -2.6 -2.4 -1.9 -1.55 -2.1 -3.9 - mA 9.5 0,10 10 -2.0 -1.8 -1.35 -1.18 -1.65 -3.0 - mA 13.5 0,15 15 -5.2 -4.8 -3.5 -3.1 -4.3 -8.0 - mA - 0,5 5 0.05 0.05 0.05 0.05 - 0 0.05 V - 0,10 10 0.05 0.05 0.05 0.05 - 0 0.05 V - 0,15 15 0.05 0.05 0.05 0.05 - 0 0.05 V - 0,5 5 4.95 4.95 4.95 4.95 4.95 5 - V - 0,10 10 9.95 9.95 9.95 9.95 9.95 10 - V - 0,15 15 14.95 14.95 14.95 14.95 14.95 15 - V 4.5 - 5 1 1 1 1 - - 1 V 9 - 10 2 2 2 2 - - 2 V 13.5 - 15 2.5 2.5 2.5 2.5 - - 2.5 V 0.5 - 5 1.5 1.5 1.5 1.5 - - 1.5 V 1 - 10 3 3 3 3 - - 3 V 1.5 - 15 4 4 4 4 - - 4 V CD4049UB, CD4050B DC Electrical Specifications (Continued) LIMITS AT INDICATED TEMPERATURE (oC) 25 TEST CONDITIONS PARAMETER Input High Voltage, VIH Min CD4049UB Input High Voltage, VIH Min CD4050B Input Current, IIN Max VO (V) VIN (V) VCC (V) -55 -40 85 125 MIN TYP MAX UNITS 0.5 - 5 4 4 4 4 4 - - V 1 - 10 8 8 8 8 8 - - V 1.5 - 15 12.5 12.5 12.5 12.5 12.5 - - V 4.5 - 5 3.5 3.5 3.5 3.5 3.5 - - V 9 - 10 7 7 7 7 7 - - V 13.5 - 15 11 11 11 11 11 - - V - ±10-5 ±0.1 µA - AC Electrical Specifications 0,18 18 ±0.1 Propagation Delay Time Low to High, tPLH CD4049UB Propagation Delay Time Low to High, tPLH CD4050B Propagation Delay Time High to Low, tPHL CD4049UB Propagation Delay Time High to Low, tPHL CD4050B Transition Time, Low to High, tTLH Transition Time, High to Low, tTHL 4 ±1 ±1 TA = 25oC, Input tr , tf = 20ns, CL = 50pF, RL = 200kΩ TEST CONDITIONS PARAMETER ±0.1 LIMITS (ALL PACKAGES) VIN VCC TYP MAX UNITS 5 5 60 120 ns 10 10 32 65 ns 10 5 45 90 ns 15 15 25 50 ns 15 5 45 90 ns 5 5 70 140 ns 10 10 40 80 ns 10 5 45 90 ns 15 15 30 60 ns 15 5 40 80 ns 5 5 32 65 ns 10 10 20 40 ns 10 5 15 30 ns 15 15 15 30 ns 15 5 10 20 ns 5 5 55 110 ns 10 10 22 55 ns 10 5 50 100 ns 15 15 15 30 ns 15 5 50 100 ns 5 5 80 160 ns 10 10 40 80 ns 15 15 30 60 ns 5 5 30 60 ns 10 10 20 40 ns 15 15 15 30 ns CD4049UB, CD4050B AC Electrical Specifications TA = 25oC, Input tr , tf = 20ns, CL = 50pF, RL = 200kΩ (Continued) TEST CONDITIONS LIMITS (ALL PACKAGES) VIN VCC TYP MAX UNITS Input Capacitance, CIN CD4049UB - - 15 22.5 pF Input Capacitance, CIN CD4050B - - 5 7.5 pF PARAMETER TA = 25oC TA = 25oC SUPPLY VOLTAGE (VCC) = 5V SUPPLY VOLTAGE (VCC) = 5V VO , OUTPUT VOLTAGE (V) VO , OUTPUT VOLTAGE (V) Typical Performance Curves 5 4 MINIMUM MAXIMUM 3 2 5 MINIMUM 4 MAXIMUM 3 2 1 1 0 1 2 3 0 4 1 2 VI , INPUT VOLTAGE (V) 3 4 FIGURE 2. MINIMUM AND MAXIMUM VOLTAGE TRANSFER CHARACTERISTICS FOR CD4049UB FIGURE 3. MINIMUM AND MAXIMUM VOLTAGE TRANSFER CHARACTERISTICS FOR CD4050B IOL, OUTPUT LOW (SINK) CURRENT (mA) IOL, OUTPUT LOW (SINK) CURRENT (mA) VI , INPUT VOLTAGE (V) TA = 25oC 70 15V 60 10V 50 40 30 GATE TO SOURCE VOLTAGE (VGS) = 5V 20 10 0 1 2 3 4 5 6 7 8 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 5 TA = 25oC 70 15V 10V 60 50 40 30 20 GATE TO SOURCE VOLTAGE (VGS) = 5V 10 0 1 2 3 4 5 6 7 8 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT DRAIN CHARACTERISTICS CD4049UB, CD4050B Typical Performance Curves (Continued) VDS, DRAIN TO SOURCE VOLTAGE (V) -8 -7 -6 -5 -4 -3 -2 -1 VDS, DRAIN TO SOURCE VOLTAGE (V) -8 -7 -6 -5 -4 -3 -2 0 -20 -25 -10V -30 -15V -10 VGS = -5V -15 -10V -20 -15V -25 -30 -35 OUTPUT HIGH (SOURCE) -15 GATE TO SOURCE VOLTAGE CURRENT CHARACTERISTICS -10 GATE TO SOURCE VOLTAGE VGS = -5V -35 FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 10 9 VO, OUTPUT VOLTAGE (V) 10 VO, OUTPUT VOLTAGE (V) 0 -5 OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS -5 SUPPLY VOLTAGE 8 VCC = 10V 125oC 7 6 TA = -55oC VCC = 5V 5 4 -55oC 3 125oC 2 9 SUPPLY VOLTAGE 125oC 8 VCC = 10V 7 6 VCC = 5V 5 TA = -55oC 4 3 125oC 2 -55oC 1 1 0 0 0 1 2 3 4 0 5 6 7 8 9 10 VI , INPUT VOLTAGE (V) 105 TA = 25oC V C 104 Y PL GE TA L VO 5 =1 VC V 10 V 10 5V P SU 103 LOAD CAPACITANCE CL = 50pF (11pF FIXTURE + 39pF EXT) CL = 15pF (11pF FIXTURE + 4pF EXT) 102 10 10 102 103 104 f, INPUT FREQUENCY (kHz) 105 FIGURE 10. TYPICAL POWER DISSIPATION vs FREQUENCY CHARACTERISTICS 6 1 2 3 4 5 6 7 8 9 10 VI , INPUT VOLTAGE (V) FIGURE 9. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS AS A FUNCTION OF TEMPERATURE FOR CD4050B POWER DISSIPATION PER INVERTER (µW) FIGURE 8. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS AS A FUNCTION OF TEMPERATURE FOR CD4049UB POWER DISSIPATION PER INVERTER (µW) -1 TA = 25oC TA = 25oC TA = 25oC 105 15V; 1MHz 15V; 100kHz 10V; 100kHz 15V; 10kHz 10V; 10kHz 15V; 1kHz 104 103 102 10 SUPPLY VOLTAGE VCC = 5V FREQUENCY (f) = 10kHz 10 102 103 104 105 106 107 tr, tf , INPUT RISE AND FALL TIME (ns) 108 FIGURE 11. TYPICAL POWER DISSIPATION vs INPUT RISE AND FALL TIMES PER INVERTER FOR CD4049UB CD4049UB, CD4050B POWER DISSIPATION PER INVERTER (µW) Typical Performance Curves (Continued) 106 TA = 25oC 105 15V; 1MHz 15V; 100kHz 10V; 100kHz 15V; 10kHz 10V; 10kHz 15V; 1kHz 104 103 102 10 SUPPLY VOLTAGE VCC = 5V FREQUENCY (f) = 10kHz 1 10 102 103 104 105 106 107 tr, tf , INPUT RISE AND FALL TIME (ns) 108 FIGURE 12. TYPICAL POWER DISSIPATION vs INPUT RISE AND FALL TIMES PER INVERTER FOR CD4050B Test Circuits VCC VCC VCC INPUTS INPUTS OUTPUTS VIH VSS + DVM VIL IDD VSS VSS NOTE: Test any one input with other inputs at VCC or VSS. FIGURE 13. QUIESCENT DEVICE CURRENT TEST CIRCUIT FIGURE 14. INPUT VOLTAGE TEST CIRCUIT CMOS 10V LEVEL TO DTL/TTL 5V LEVEL VCC = 5V VCC INPUTS COS/MOS IN OUTPUTS VCC OUTPUT TO DTL/TTL CD4049 INPUTS I 5V = VOH 10V = VIH 0 = VIL VSS VSS NOTE: Measure inputs sequentially, to both VCC and VSS connect all unused inputs to either VCC or VSS. FIGURE 15. INPUT CURRENT TEST CIRCUIT 7 VSS 0 = VOL In Terminal - 3, 5, 7, 9, 11, or 14 Out Terminal - 2, 4, 6, 10, 12 or 15 VCC Terminal - 1 VSS Terminal - 8 FIGURE 16. LOGIC LEVEL CONVERSION APPLICATION CD4049UB, CD4050B (Continued) VDD 0.1µF 500µF CL 10kHz, 100kHz, 1MHz I 1 2 3 4 5 6 7 8 CD4049UB Test Circuits 16 15 14 13 12 11 10 9 CL INCLUDES FIXTURE CAPACITANCE FIGURE 17. DYNAMIC POWER DISSIPATION TEST CIRCUITS 8 CD4049UB, CD4050B 9 PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) CD4049UBD ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD4049UBDR ACTIVE SOIC D 16 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD4049UBDT ACTIVE SOIC D 16 250 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD4049UBDW ACTIVE SOIC DW 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM CD4049UBDWR ACTIVE SOIC DW 16 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM CD4049UBE ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD4049UBF ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC CD4049UBF3A ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC CD4049UBM OBSOLETE SOIC D 16 None Call TI Call TI Call TI CD4049UBM96 OBSOLETE SOIC D 16 None Call TI CD4049UBNSR ACTIVE SO NS 16 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD4049UBPW ACTIVE TSSOP PW 16 90 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM CD4049UBPWR ACTIVE TSSOP PW 16 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM CD4050BD ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD4050BDR ACTIVE SOIC D 16 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD4050BDT ACTIVE SOIC D 16 250 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD4050BDW ACTIVE SOIC DW 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM CD4050BDWR ACTIVE SOIC DW 16 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM CD4050BE ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD4050BF ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC CD4050BF3A ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC Call TI CD4050BM OBSOLETE SOIC D 16 None Call TI CD4050BNSR ACTIVE SO NS 16 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD4050BPW ACTIVE TSSOP PW 16 90 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM CD4050BPWR ACTIVE TSSOP PW 16 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM JM38510/05553BEA ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC JM38510/05554BEA ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. 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