Catalyst CAT24WC66WE-TE13 64k-bit i2c serial cmos eeprom Datasheet

H
CAT24WC66
EE
GEN FR
ALO
64K-Bit I2C Serial CMOS EEPROM
LE
A D F R E ETM
FEATURES
■ Commercial, industrial and automotive
■ 400 kHz I2C bus compatible*
temperature ranges
■ 1.8 to 6 volt read and write operation
■ Write protection
■ Cascadable for up to eight devices
–Top 1/4 array protected when WP at VIH
■ 32-byte page write buffer
■ 1,000,000 program/erase cycles
■ Self-timed write cycle with auto-clear
■ 100 year data retention
■ Schmitt trigger inputs for noise protection
■ 8-pin DIP or 8-pin SOIC packages
DESCRIPTION
The CAT24WC66 is a 64K-bit Serial CMOS EEPROM
internally organized as 8192 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The
CAT24WC66 features a 32-byte page write buffer. The
device operates via the I2C bus serial interface and is
available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
BLOCK DIAGRAM
DIP Package (P, L)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
EXTERNAL LOAD
SENSE AMPS
SHIFT REGISTERS
DOUT
ACK
VCC
WP
SCL
SDA
VCC
WORD ADDRESS
BUFFERS
VSS
COLUMN
DECODERS
256
SOIC Package (J, K, W, X)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
START/STOP
LOGIC
SDA
VCC
WP
SCL
SDA
XDEC
256
EEPROM
256 X 256
CONTROL
LOGIC
WP
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
Device Address Inputs
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
VCC
+1.8V to +6V Power Supply
VSS
Ground
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1037, Rev. H
1
CAT24WC66
ABSOLUTE MAXIMUM RATINGS*
Lead Soldering Temperature (10 secs) ............ 300°C
Temperature Under Bias ................. –55°C to +125°C
Output Short Circuit Current(2) ........................ 100mA
Storage Temperature ....................... –65°C to +150°C
*COMMENT
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
NEND(3)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
TDR(3)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
VZAP(3)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
ILTH(3)(4)
Latch-up
JEDEC Standard 17
100
mA
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
fSCL = 100 kHz
3
mA
ICC
Power Supply Current
ISB(5)
Standby Current (VCC = 5V)
VIN = GND or VCC
1
µA
ILI
Input Leakage Current
VIN = GND to VCC
10
µA
ILO
Output Leakage Current
VOUT = GND to VCC
10
µA
VIL
Input Low Voltage
-1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low Voltage
(VCC = +3.0V)
IOL = 3.0 mA
0.4
V
VOL2
Output Low Voltage
(VCC = +1.8V)
IOL = 1.5 mA
0.5
V
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CI/O(3)
Input/Output Capacitance
(SDA)
VI/O = 0V
8
pF
CIN(3)
Input Capacitance
(A0, A1, A2, SCL, WP)
VIN = 0V
6
pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1037, Rev. H
2
CAT24WC66
A.C. CHARACTERISTICS
VCC = +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
1.8V - 2.5V
Symbol
Units
Min
FSCL
4.5V - 5.5V
Parameter
Max
Min
Max
Clock Frequency
100
400
kHz
TI(1)
Noise Suppression Time Constant at
SCL, SDA Inputs
200
200
ns
tAA
SCL Low to SDA Data Out and
ACK Out
3.5
1
µs
tBUF(1)
Time the Bus Must be Free Before a
New Transmission Can Start
tHD:STA
Start Condition Hold Time
4.7
1.2
µs
4
0.6
µs
tLOW
Clock Low Period
4.7
1.2
µs
tHIGH
Clock High Period
4
0.6
µs
4.7
0.6
µs
tSU:STA
Start Condition Setup Time (for a
Repeated Start Condition)
tHD:DAT
Data In Hold Time
0
0
ns
tSU:DAT
Data In Setup Time
50
50
ns
tR(1)
SDA and SCL Rise Time
1
0. 3
µs
tF(1)
SDA and SCL Fall Time
300
300
ns
tSU:STO
tDH
Stop Condition Setup Time
Data Out Hold Time
4
0.6
µs
100
100
ns
Power-Up Timing (1)(2)
Symbol
Parameter
Min
Typ
Max
Units
tPUR
Power-Up to Read Operation
1
ms
tPUW
Power-Up to Write Operation
1
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Write Cycle Limits
Symbol
tWR
Parameter
Min
Write Cycle Time
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Typ
Max
Units
10
ms
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
3
Doc. No. 1037, Rev. H
CAT24WC66
FUNCTIONAL DESCRIPTION
The CAT24WC66 supports the I2C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. The
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24WC66 operates
as a Slave device. Both the Master device and Slave
device can operate as either transmitter or receiver, but
the Master device controls which mode is activated.
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
PIN DESCRIPTIONS
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the top
1/4 array of memory is write protected. When left
floating, memory is unprotected.
A0, A1, A2: Device Address Inputs
These pins are hardwired or left unconnected (for
hardware compatibility with CAT24WC16). When
hardwired, up to eight CAT24WC66 devices may be
addressed on a single bus system (refer to Device
Addressing ). When the pins are left unconnected, the
default values are zeros.
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
Figure 1. Bus Timing
tF
tHIGH
tLOW
tR
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
SDA IN
tAA
tBUF
tDH
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
Doc. No. 1037, Rev. H
STOP BIT
4
ADDRESS
CAT24WC66
I2C BUS PROTOCOL
to the hardwired input pins, A2, A1 and A0. The last bit
of the slave address specifies whether a Read or Write
operation is to be performed. When this bit is set to 1, a
Read operation is selected, and when set to 0, a Write
operation is selected.
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
After the Master sends a START condition and the slave
address byte, the CAT24WC66 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC66 then performs a Read or Write operation
depending on the state of the R/W bit.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
Acknowledge
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC66 monitors the
SDA and SCL lines and will not respond until this
condition is met.
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24WC66 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8bit byte.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
When the CAT24WC66 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this acknowledge, the CAT24WC66 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition. The master must then issue a stop condition
to return the CAT24WC66 to the standby power mode
and place the device in a known state.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The next three bits (A2, A1, A0) are the
device address bits; up to eight 64K devices may to be
connected to the same bus. These bits must compare
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
0
5
A1
A0
R/W
Doc. No. 1037, Rev. H
CAT24WC66
If the Master transmits more than 32 bytes before sending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24WC66. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24WC66 acknowledges once
more and the Master generates the STOP condition. At
this time, the device begins an internal programming
cycle to nonvolatile memory. While the cycle is in
progress, the device will not respond to any request from
the Master device.
When all 32 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT24WC66 in a single write cycle.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24WC66 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issuing
the start condition followed by the slave address for a
write operation. If CAT24WC66 is still busy with the write
operation, no ACK will be returned. If
CAT24WC66 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
Page Write
The CAT24WC66 writes up to 32 bytes of data, in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 31 additional bytes. After each byte has
been transmitted, CAT24WC66 will respond with an
acknowledge, and internally increment the five low order
address bits by one. The high order bits remain
unchanged.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the top 1/4 of the memory
array (locations 1800H to 1FFF) is protected and
Figure 6. Byte Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE ADDRESS
A15–A8
A7–A0
S
S
T
O
P
DATA
P
X XX *
A
C
K
A
C
K
A
C
K
A
C
K
Figure 7. Page Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE ADDRESS
A15–A8
A7–A0
S
DATA
DATA n+31
P
X XX *
A
C
K
A
C
K
A
C
K
* = Don't care bit for 24WC33
X= Don't care bit
Doc. No. 1037, Rev. H
DATA n
S
T
O
P
6
A
C
K
A
C
K
A
C
K
A
C
K
CAT24WC66
tion, slave address and byte addresses of the location it
wishes to read. After CAT24WC66 acknowledges, the
Master device sends the START condition and the slave
address again, this time with the R/W bit set to one. The
CAT24WC66 then responds with its acknowledge and
sends the 8-bit byte requested. The master device does
not send an acknowledge but will generate a STOP
condition.
becomes read only. The CAT24WC66 will accept both
slave and byte addresses, but the memory location
accessed is protected from programming by the device’s
failure to send an acknowledge after the first byte of data
is received.
READ OPERATIONS
The READ operation for the CAT24WC66 is initiated in
the same manner as the write operation with one exception, that R/W bit is set to one. Three different READ
operations are possible: Immediate/Current Address
READ, Selective/Random READ and Sequential READ.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24WC66 sends the initial 8-bit
byte requested, the Master will respond with an acknowledge which tells the device it requires more data.
The CAT24WC66 will continue to output an 8-bit byte for
each acknowledge sent by the Master. The operation
will terminate when the Master fails to respond with an
acknowledge, thus sending the STOP condition.
Immediate/Current Address Read
The CAT24WC66’s address counter contains the address of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would access data from address N+1. If N=E (where E=8191),
then the counter will ‘wrap around’ to address 0 and
continue to clock out data. After the CAT24WC66 receives its slave address information (with the R/W bit set
to one), it issues an acknowledge, then transmits the 8
bit byte requested. The master device does not send an
acknowledge, but will generate a STOP condition.
The data being transmitted from CAT24WC66 is outputted sequentially with data from address N followed by
data from address N+1. The READ operation address
counter increments all of the CAT24WC66 address bits
so that the entire memory array can be read during one
operation. If more than E (where E=8191) bytes are read
out, the counter will ‘wrap around’ and continue to clock
out data bytes.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condiFigure 8. Immediate Address Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
DATA
S
P
A
C
K
SCL
SDA
S
T
O
P
8
N
O
A
C
K
9
8TH BIT
DATA OUT
NO ACK
7
STOP
Doc. No. 1037, Rev. H
CAT24WC66
Figure 9. Selective Read Timing
S
T
A
R
T
BUS ACTIVITY:
MASTER
SDA LINE
SLAVE
ADDRESS
S
T
A
R
T
BYTE ADDRESS
A15–A8
A7–A0
S
SLAVE
ADDRESS
S
T
O
P
DATA
S
XXX
A
C
K
A
C
K
P
A
C
K
A
C
K
N
O
A
C
K
X= Don't care bit
Figure 10. Sequential Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
S
T
O
P
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc. No. 1037, Rev. H
8
CAT24WC66
ORDERING INFORMATION
Prefix
Device #
CAT
24WC66
Optional
Company ID
Product
Number
Suffix
J
-1.8
I
Temperature Range
Blank = Commercial (0˚ to 70˚C)
I = Industrial (-40˚ to 85˚C)
A = Automotive (-40˚ to 105˚C)
E = Extended Automotive (-40˚ to 125˚C)
Package
P: PDIP
K: SOIC (EIAJ)
J: SOIC (JEDEC)
L: PDIP (Lead free, Halogen free)
W: SOIC (JEDEC, Lead free, Halogen free)
X: SOIC (EIAJ, Lead free, Halogen free)
Rev C(2)
TE13
Tape & Reel
Die Revision
Operating Voltage
Blank: 2.5V - 6.0V
1.8: 1.8V - 6.0V
Notes:
(1) The device used in the above example is a 24WC66JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating
Voltage, Tape & Reel)
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g. AYWWC). For additional
information, please contact your Catalyst sales office.
9
Doc. No. 1037, Rev. H
REVISION HISTORY
Date
Rev.
Reason
3/4/2004
D
Added Commercial temp range in all areas
04/03/04
E
Update Pin Configuration
Update Ordering Information
Eliminate data sheet designation
7/22/2004
F
Added Die Revision to Ordering Information
8/3/2004
G
Update Features
Update DC Operating Characteristics table & notes
03/10/2005
H
Update Ordering Information
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Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
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Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
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Publication #:
Revison:
Issue date:
1037
H
03/10/05
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