AD AD677BD 16-bit 100 ksps sampling adc Datasheet

a
FEATURES
Autocalibrating
On-Chip Sample-Hold Function
Serial Output
16 Bits No Missing Codes
61 LSB INL
–99 dB THD
92 dB S/(N+D)
1 MHz Full Power Bandwidth
16-Bit 100 kSPS
Sampling ADC
AD677
FUNCTIONAL BLOCK DIAGRAM
VIN
AGND SENSE
VR E F
AGND
A CHIP
10
9
11
INPUT
BUFFERS
16-BIT
DAC
COMP
CAL
DAC
8
LOGIC TIMING
LEVEL TRANSLATORS
15 BUSY
14 SCLK
CAL 16
CLK
2
SAMPLE
1
MICROCODED
CONTROLLER
SAR
3 SDATA
ALU
RAM
D CHIP
AD677
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD677 is a multipurpose 16-bit serial output analog-todigital converter which utilizes a switched-capacitor/charge
redistribution architecture to achieve a 100 kSPS conversion
rate (10 µs total conversion time). Overall performance is optimized by digitally correcting internal nonlinearities through
on-chip autocalibration.
1. Autocalibration provides excellent dc performance while
eliminating the need for user adjustments or additional external circuitry.
2. ± 5 V to ± 10 V input range (± VREF).
3. Available in 16-pin 0.3" skinny DIP or 28-lead SOIC.
The AD677 circuitry is segmented onto two monolithic chips—
a digital control chip fabricated on Analog Devices DSP CMOS
process and an analog ADC chip fabricated on our BiMOS II
process. Both chips are contained in a single package.
4. Easy serial interface to standard ADI DSPs.
The AD677 is specified for ac (or “dynamic”) parameters such
as S/(N+D) Ratio, THD and IMD which are important in signal processing applications. In addition, dc parameters are
specified which are important in measurement applications.
7. Industry leading dc performance: 1.0 LSB INL, ± 1 LSB full
scale and offset.
5. TTL compatible inputs/outputs.
6. Excellent ac performance: –99 dB THD, 92 dB S/(N+D)
peak spurious –101 dB.
The AD677 operates from +5 V and ± 12 V supplies and typically consumes 450 mW using a 10 V reference (360 mW with
5 V reference) during conversion. The digital supply (VDD) is
separated from the analog supplies (VCC, VEE) for reduced digital crosstalk. An analog ground sense is provided to remotely
sense the ground potential of the signal source. This can be useful if the signal has to be carried some distance to the A/D converter. Separate analog and digital grounds are also provided.
The AD677 is available in a 16-pin narrow plastic DIP, 16-pin
narrow side-brazed ceramic package, or 28-lead SOIC. A parallel output version, the AD676, is available in a 28-pin ceramic
or plastic DIP. All models operate over a commercial temperature range of 0°C to +70°C or an industrial range of –40°C to
+85°C.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD677* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DOCUMENTATION
• Quality And Reliability
Application Notes
• Symbols and Footprints
• AN-101: Cross Plot Generator Allows Quick A/D Converter
Evaluation
DISCUSSIONS
• AN-347: Shielding and Guarding
View all AD677 EngineerZone Discussions.
Data Sheet
• AD677: 16-Bit Serial 100 kSPS Sampling ADC Data Sheet
SAMPLE AND BUY
• AD677: Military Data Sheet
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REFERENCE MATERIALS
TECHNICAL SUPPORT
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• MS-2210: Designing Power Supplies for High Speed ADC
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AD677–SPECIFICATIONS
AC SPECIFICATIONS (T
MIN
to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)1
Parameter
Min
Total Harmonic Distortion (THD)2
@ 83 kSPS, TMIN to TMAX
@ 100 kSPS, +25°C
@ 100 kSPS, TMIN to TMAX
Signal-to-Noise and Distortion Ratio (S/(N+D))2, 3
@ 83 kSPS, TMIN to TMAX
@ 100 kSPS, +25°C
@ 100 kSPS, TMIN to TMAX
Peak Spurious or Peak Harmonic Component
Intermodulation Distortion (IMD)4
2nd Order Products
3rd Order Products
Full Power Bandwidth
Noise
–97
–97
–93
89
89
MIN
LOGIC INPUTS
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIH
High Level Input Current
IIL
Low Level Input Current
CIN
Input Capacitance
LOGIC OUTPUTS
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
Max
Min
AD677K/B
Typ
Max
–92
–92
91
91
89
–101
–99
–99
–95
90
90
–102
–98
1
160
DIGITAL SPECIFICATIONS (for all grades T
Parameter
AD677J/A
Typ
dB
dB
dB
92
92
90
–101
dB
dB
dB
dB
–102
–98
1
160
dB
dB
MHz
µV rms
to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)
Test Conditions
Min
VIH = VDD
VIL = 0 V
2.0
–0.3
–10
–10
Typ
Max
Units
VDD + 0.3
0.8
+10
+10
V
V
µA
µA
pF
10
IOH = 0.1 mA
IOH = 0.5 mA
IOL = 1.6 mA
–95
–95
Units
VDD – 1 V
2.4
0.4
V
V
V
NOTES
1
VREF = 10.0 V, Conversion Rate = 100 kSPS, f lN = 1.0 kHz, V IN = –0.05 dB, Bandwidth = 50 kHz unless otherwise indicated. All measurements referred to a 0 dB
(20 V p-p) input signal. Values are post-calibration.
2
For other input amplitudes, refer to Figure 12.
3
For dynamic performance with different reference values see Figure 11.
4
fa = 1008 Hz, fb = 1055 Hz. See Definition of Specifications section and Figure 16.
Specifications subject to change without notice.
–2–
REV. A
AD677
DC SPECIFICATIONS (T
1
MIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 1O%)
Parameter
AD677J/A
Typ
Max
Min
TEMPERATURE RANGE
J, K Grades
A, B Grades
ACCURACY
Resolution
Integral Nonlinearity (INL)
@ 83 kSPS, TMIN to TMAX
@ 100 kSPS, +25°C
@ 100 kSPS, TMIN to TMAX
Differential Nonlinearity (DNL)–No Missing Codes
Bipolar Zero Error2
Positive, Negative FS Errors2
@ 83 kSPS
@ 100 kSPS, +25°C
@ 100 kSPS
0
–40
+70
+85
16
AD677K/B
Typ
Max
0
–40
+70
+85
16
±1
±1
±2
16
±2
±2
±2
±4
TEMPERATURE DRIFT3
Bipolar Zero
Postive Full Scale
Negative Full Scale
VOLTAGE REFERENCE INPUT RANGE4 (VREF)
Min
±4
16
±4
±4
± 0.5
± 0.5
± 0.5
5
°C
°C
Bits
±1
+1
±2
± 1.5
± 1.5
±1
±3
±1
±1
±4
±3
±3
± 0.5
± 0.5
± 0.5
10
Units
5
LSB
LSB
LSB
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
10
V
± VREF
V
50*
5
ANALOG INPUT
Input Range (VIN)
Input Impedance
Input Settling Time
Input Capacitance During Sample
Aperture Delay
Aperture Jitter
± VREF
*
2
*
2
6
100
6
100
µs
pF
ns
ps
± 0.5
± 0.5
± 0.5
± 0.5
± 0.5
± 0.5
LSB
LSB
LSB
50*
POWER SUPPLIES
Power Supply Rejection6
VCC = +12 V ± 5%
VEE = –12 V ± 5%
VDD = +5 V ± 10%
Operating Current
VREF = +5 V
ICC
IEE
IDD
Power Consumption
VREF = +10 V
ICC
IEE
IDD
Power Consumption
14.5
14.5
3
360
18
18
5
480
14.5
14.5
3
360
18
18
5
480
mA
–mA
mA
mW
18
18
3
450
24
24
5
630
18
18
3
450
24
24
5
630
mA
–mA
mA
mW
NOTES
1
VREF = 10.0 V, Conversion Rate = 100 kSPS unless otherwise noted. Values are post-calibration.
2
Values shown apply to any temperature from T MIN to TMAX after calibration at that temperature at nominal supplies.
3
Values shown are based upon calibration at +25°C with no additional calibration at temperature. Values shown are the typical variation from the value at +25 °C.
4
See “APPLICATIONS” section for recommended voltage reference circuit, and Figure 11 for dynamic performance with other reference voltage values.
5
See “APPLICATIONS” section for recommended input buffer circuit.
6
Typical deviation of bipolar zero, –full scale or +full scale from min to max rating.
*For explanation of input characteristics, see “ANALOG INPUT” section.
Specifications subject to change without notice.
REV. A
–3–
AD677
TIMING SPECIFICATIONS (T
MIN
to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)1
Parameter
2, 3
Conversion Period
CLK Period4
Calibration Time
Sampling Time
Last CLK to SAMPLE Delay5
SAMPLE Low
SAMPLE to Busy Delay
1st CLK Delay
CLK Low6
CLK High6
CLK to BUSY Delay
CLK to SDATA Valid
CLK to SCLK High
SCLK Low
SDATA to SCLK High
CAL High Time
CAL to BUSY Delay
Symbol
Min
tC
tCLK
tCT
tS
tLCS
tSL
tSS
tFCD
tCL
tCH
tCB
tCD
tCSH
tSCL
tDSH
tCALH
tCALB
10
480
Typ
Max
Units
1000
µs
ns
tCLK
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
85532
2
2.1
100
30
75
180
100
180
80
80
300
175
300
15
50
50
50
50
50
100
50
50
50
NOTES
1
See the “CONVERSION CONTROL” and “AUTOCALIBRATION” sections for detailed explanations of the above timing.
2
Depends upon external clock frequency; includes acquisition time and conversion time. The maximum conversion period is specified to account for the droop of the
internal sample/hold function. Operation at slower rates may degrade performance.
3
tC = tFCD + 16 × tCLK + tLCS.
4
580 ns is recommended for optimal accuracy over temperature (not necessary during calibration cycle).
5
If SAMPLE goes high before the 17th CLK pulse, the device will start sampling approximately 100 ns after the rising edge of the 17th CLK pulse.
6
tCH + tCL = tCLK and must be greater than 480 ns.
CAL
(INPUT)
tCALH
tCT
tCALB
BUSY
(OUTPUT)
tFCD
tCB
CLK*
(INPUT)
2
1
3
85531
85530
tCH
85532
tCL
tCLK
*SHADED PORTIONS OF INPUT SIGNALS ARE OPTIONAL. FOR BEST PERFORMANCE, WE
RECOMMEND THAT THESE SIGNALS BE HELD LOW EXCEPT WHEN EXPLICITY SHOWN HIGH.
Figure 1. Calibration Timing
tS
tC
tSL
SAMPLE*
(INPUT)
tS
tSB
BUSY
(OUTPUT)
tCB
tFCD
tLCS
tCH
CLK*
(INPUT)
1
tCLK
tCL
2
15
3
16
17
tCSH
SCLK
(OUTPUT)
tSCL
tDSH
tCD
SDATA
(OUTPUT)
OLD BIT 16
MSB
BIT
2
BIT
13
BIT
14
BIT
15
BIT
16
*SHADED PORTIONS OF INPUT SIGNALS ARE OPTIONAL. FOR BEST PERFORMANCE, WE
RECOMMEND THAT THESE SIGNALS BE HELD LOW EXCEPT WHEN EXPLICITY SHOWN HIGH.
Figure 2. General Conversion Timing
–4–
REV. A
AD677
ORDERING GUIDE
Model
Temperature
Range
S/(N+D)
Max INL
Package Description
Package
Option*
AD677JN
AD677KN
AD677JD
AD677KD
AD677JR
AD677KR
AD677AD
AD677BD
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
89 dB
90 dB
89 dB
90 dB
89 dB
90 dB
89 dB
90 dB
Typ Only
± 1.5 LSB
Typ Only
± 1.5 LSB
Typ Only
± 1.5 LSB
Typ Only
± 1.5 LSB
Plastic 16-Pin DIP
Plastic 16-Pin DIP
Ceramic 16-Pin DIP
Ceramic 16-Pin DIP
Plastic 28-Lead SOIC
Plastic 28-Lead SOIC
Ceramic 16-Pin DIP
Ceramic 16-Pin DIP
N-16
N-16
D-16
D-16
R-28
R-28
D-16
D-16
*D = Ceramic DIP; N = Plastic DIP; R = Small Outline IC (SOIC).
ABSOLUTE MAXIMUM RATINGS*
VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +26.4 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Vcc to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V
VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V
Digiul Inputs to DGND . . . . . . . . . . . . . . . . . . . . . . 0 to +5.5 V
Analog Inputs, VREF to AGND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . (VCC +0.3 V) to (VEE –0.3 V)
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD677 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
–5–
WARNING!
ESD SENSITIVE DEVICE
AD677
PIN DESCRIPTION
DIP Pin
SOIC Pin
Type
Name
Description
1
1
SAMPLE
DI
VIN Acquisition Control Pin. Active HIGH. During conversion, SAMPLE
controls the suite of the internal sample-hold amplifier and the falling edge
initiates conversion. During calibration, SAMPLE should be held LOW. If
HIGH during calibration, diagnostic information will appear on SDATA.
2
2
CLK
DI
Master Clock Input. The AD677 requires 17 clock pulses to execute a
conversion. CLK is also used to derive SCLK.
3
3
SDATA
DO
Serial Output Data Controlled by SCLK.
4
6, 7
DGND
P
Digital Ground.
5
8
VCC
P
+12 V Analog Supply Voltage.
8
12
AGND
P
Analog Ground.
.9
15
AGND SENSE
AI
Analog Ground Sense.
10
16
VIN
AI
Analog Input Voltage.
11
17
VREF
AI
External Voltage Reference Input.
12
21
VEE
P
–12 V Analog Supply Voltage.
13
22, 23
VDD
P
+5 V Logic Supply Voltage.
14
26
SCLK
DO
Clock Output for Data Read, derived from CLK.
15
27
BUSY
DO
Status Line for Converter. Active HIGH, indicating a conversion or
calibration in progress.
16
28
CAL
DI
Calibration Control Pin.
6, 7
4, 5, 9, 10, 11,
13, 14, 18, 19,
20, 24, 25
NC
_
No Connection. No connections should be made to these pins.
Type: AI = Analog Input
DI = Digital Input
DO = Digital Output
P = Power
SAMPLE
CLK
1
16 CAL
2
15 BUSY
SDATA
3
DGND
4
VCC
5
14
SCLK
AD677
13
VDD
TOP VIEW
(Not to Scale)
12
VEE
1
28
CAL
CLK
2
27
BUSY
SDATA
3
26
SCLK
NC
4
25
NC
NC
5
24
NC
DGND1
6
23
VDD1
DGND2
7
AD677
22
VDD2
VCC
8
TOP VIEW
(Not to Scale)
21
VEE
20
NC
VREF
NC
6
11
NC
7
10 VIN
AGND
8
9
SAMPLE
AGND
SENSE
NC = NO CONNECT
DIP Pinout
NC
9
NC
10
19
NC
NC
11
18
NC
AGND
12
17
VREF
NC
13
16
VIN
NC
14
15
AGND
SENSE
NC = NO CONNECT
SOIC Pinout
–6–
REV. A
Definition of Specifications–AD677
NYQUIST FREQUENCY
INTERMODULATION DISTORTION (IMD)
An implication of the Nyquist sampling theorem, the “Nyquist
frequency’’ of a converter is that input frequency which is one
half the sampling frequency of the converter.
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m+n), at sum and difference frequencies of mfa ± nfb,
where m, n = 0, 1, 2, 3 . . . . Intermodulation terms are those
for which m or n is not equal to zero. For example, the second
order terms are (fa + fb) and (fa – fb), and the third order terms
are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). The IMD
products are expressed as the decibel ratio of the rms sum of the
measured input signals to the rms sum of the distortion terms.
The two signals applied to the converter are of equal amplitude,
and the peak value of their sum is –0.5 dB from full scale. The
IMD products are normalized to a 0 dB input signal.
TOTAL HARMONIC DISTORTION
Total harmonic distortion (THD) is the ratio of the rms sum of
the harmonic components to the rms value of a full-scale input
signal and is expressed in percent (%) or decibels (dB). For input signals or harmonics that are above the Nyquist frequency,
the aliased components are used.
SIGNAL-TO-NOISE PLUS DISTORTION RATIO
Signal-to-noise plus distortion is defined to be the ratio of the
rms value of the measured input signal to the rms sum of all
other spectral components below the Nyquist frequency, including harmonics but excluding dc.
APERTURE DELAY
Aperture delay is the time required after SAMPLE pin is taken
LOW for the internal sample-hold of the AD677 to open, thus
holding the value of VIN.
+/– FULL-SCALE ERROR
The last + transition (from 011 . . . 10 to 011 . . . 11) should
occur for an analog voltage 1.5 LSB below the nominal full
scale (4.99977 volts for a ± 5 V range). The full-scale error is
the deviation of the actual level of the last transition from the
ideal level.
BIPOLAR ZERO ERROR
Bipolar zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the midscale output code.
DIFFERENTIAL NONLINEARITY (DNL)
In an ideal ADC, code transitions are one LSB apart. Differential nonlinearity is the maximum deviation from this ideal value.
It is often specified in terms of resolution for which no missing
codes are guaranteed.
INTEGRAL NONLINEARITY (INL)
The ideal transfer function for an ADC is a straight line bisecting the center of each code drawn between “zero” and “full
scale.” The point used as “zero” occurs 1/2 LSB before the
most negative code transition. “Full scale” is defined as a level
1.5 LSB beyond the most positive code transition. Integral nonlinearity is the worst-case deviation of a code center average
from the straight line.
BANDWIDTH
The full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
REV. A
APERTURE JITTER
Aperture jitter is the variation in the aperture delay from sample
to sample.
POWER SUPPLY REJECTION
DC variations in the power supply voltage will affect the overall
transfer function of the ADC, resulting in zero error and fullscale error changes. Power supply rejection is the maximum
change in either the bipolar zero error or full-scale error value.
Additionally, there is another power supply variation to consider. AC ripple on the power supplies can couple noise into the
ADC, resulting in degradation of dynamic performance. This is
displayed in Figure 15.
INPUT SETTLING TIME
Settling time is a function of the SHA’s ability to track fast
slewing signals. This is specified as the maximum time required
in track mode after a full-scale step input to guarantee rated
conversion accuracy.
NOISE/DC CODE UNCERTAINTY
Ideally, a fixed dc input should result in the same output code
for repetitive conversions. However, as a consequence of unavoidable circuit noise within the wideband circuits in the ADC,
there is a range of output codes which may occur for a given input voltage. If you apply a dc signal to the ADC and record a
large number of conversions, the result will be a distribution of
codes. If you fit a Gaussian probability distribution to the histogram, the standard deviation is approximately equivalent to the
rms input noise of the ADC.
–7–
AD677
FUNCTIONAL DESCRIPTION
The AD677 is a multipurpose 16-bit analog-to-digital converter
and includes circuitry which performs an input sample/hold
function, ground sense, and autocalibration. These functions
are segmented onto two monolithic chips—an analog signal processor and a digital controller. Both chips are contained within
the AD677 package.
The AD677 employs a successive-approximation technique to
determine the value of the analog input voltage. However, instead of the traditional laser-trimmed resistor-ladder approach,
this device uses a capacitor-array, charge redistribution technique. Binary-weighted capacitors subdivide the input sample to
perform the actual analog-to-digital conversion. The capacitor
array eliminates variation in the linearity of the device due to
temperature-induced mismatches of resistor values. Since a
capacitor array is used to perform the data conversions, the
sample/hold function is included without the need for additional
external circuitry.
Initial errors in capacitor matching are eliminated by an
autocalibration circuit within the AD677. This circuit employs
an on-chip microcontroller and a calibration DAC to measure
and compensate capacitor mismatch errors. As each error is
determined, its value is stored in on-chip memory (RAM).
Subsequent conversions use these RAM values to improve conversion accuracy. The autocalibration routine may be invoked
at any time. Autocalibration insures high performance while
eliminating the need for any user adjustments and is described
in detail below.
The microcontroller controls all of the various functions within
the AD677. These include the actual successive approximation
algorithm, the autocalibration routine, the sample/hold operation, and the internal output data latch.
AUTO CALIBRATION
The AD677 achieves rated performance without the need for
user trims or adjustments. This is accomplished through the use
of on-chip autocalibration.
In the autocalibration sequence, sample/hold offset is nulled by
internally connecting the input circuit to the ground sense circuit. The resulting offset voltage is measured and stored in
RAM for later use. Next, the capacitor representing the most
significant bit (MSB) is charged to the reference voltage. This
charge is then transferred to a capacitor of equal size (composed
of the sum of the remaining lower weight bits). The voltage that
results represents the amount of capacitor mismatch. A calibration digital-to-analog converter (DAC) adds an appropriate
value of error correction voltage to cancel this mismatch. This
correction factor is also stored in RAM. This process is repeated
for each of the eight remaining capacitors representing the top
nine bits. The accumulated values in RAM are then used during
subsequent conversions to adjust conversion results accordingly.
As shown in Figure 1, when CAL is taken HIGH the AD677
internal circuitry is reset, the BUSY pin is driven HIGH, and
the ADC prepares for calibration. This is an asynchronous hardware reset and will interrupt any conversion or calibration currently in progress. Actual calibration begins when CAL is taken
LOW and completes in 85,532 clock cycles, indicated by BUSY
going LOW. During calibration, it is preferable for SAMPLE to
be held LOW. If SAMPLE is HIGH, diagnostic data will appear
on SDATA. This data is of no value to the user.
In most applications, it is sufficient to calibrate the AD677 only
upon power-up, in which case care should be taken that the
power supplies and voltage reference have stabilized first. If
calibration is not performed, the AD677 may come up in an unknown state, or performance could degrade to as low as 10 bits.
CONVERSION CONTROL
The AD677 is controlled by two signals: SAMPLE and CLK,
as shown in Figure 2. It is assumed that the part has been calibrated and the digital I/O pins have the levels shown at the start
of the timing diagram.
A conversion consists of an input acquisition followed by 17
clock pulses which execute the 16-bit internal successive approximation routine. The analog input is acquired by taking the
SAMPLE line HIGH for a minimum sampling time of tS. The
actual sample taken is the voltage present on VIN one aperture
delay after the SAMPLE line is brought LOW, assuming the
previous conversion has completed (signified by BUSY going
LOW). Care should be taken to ensure that this negative edge is
well defined and jitter free in ac applications to reduce the uncertainty (noise) in signal acquisition. With SAMPLE going
LOW, the AD677 commits itself to the conversion—the input
at VIN is disconnected from the internal capacitor array, BUSY
goes HIGH, and the SAMPLE input will be ignored until the
conversion is completed (when BUSY goes LOW). SAMPLE
must be held LOW for a minimum period of time tSL. A period
of time tFCD after bringing SAMPLE LOW, the 17 CLK cycles
are applied; CLK pulses that start before this period of time are
ignored. BUSY goes HIGH tSB after SAMPLE goes LOW, signifying that a conversion is in process, and remains HIGH until
the conversion is completed. As indicated in Figure 2, the twos
complement output data is presented MSB first. This data may
be captured with the rising edge of SCLK or the falling edge of
CLK, beginning with pulse #2. The AD677 will ignore CLK
after BUSY has gone LOW and SDATA or SCLK will not
change until a new sample is acquired.
CONTINUOUS CONVERSION
For maximum throughput rate, the AD677 can be operated in a
continuous convert mode. This is accomplished by utilizing the
fact that SAMPLE will no longer be ignored after BUSY goes
LOW, so an acquisition may be initiated even during the HIGH
time of the 17th CLK pulse for maximum throughput rate
while enabling full settling of the sample/hold circuitry. If
SAMPLE is already HIGH during the rising edge of the 17th
CLK, then an acquisition is immediately initiated approximately 100 ns after the rising edge of the 17th clock pulse.
Care must be taken to adhere to the minimum/maximum timing requirements in order to preserve conversion accuracy.
GENERAL CONVERSION GUIDELINES
During signal acquisition and conversion, care should be taken
with the logic inputs to avoid digital feedthrough noise. It is
possible to run CLK continuously, even during the sample
period. However, CLK edges during the sampling period, and
especially when SAMPLE goes LOW, may inject noise into the
sampling process. The AD677 is tested with no CLK cycles
during the sampling period. The BUSY signal can be used to
prevent the clock from running during acquisition, as illustrated
–8–
REV. A
AD677
in Figure 3. In this circuit BUSY is used to reset the circuitry
which divides the system clock down to provide the AD677
CLK. This serves to interrupt the clock until after the input signal has been acquired, which has occurred when BUSY goes
HIGH. When the conversion is completed and BUSY goes
LOW, the circuit in Figure 3 truncates the 17th CLK pulse
width which is tolerable because only its rising edge is critical.
12.288MHz
SYSTEM
CLOCK
11 3Q
2Q 7
4 1D
3D 12
9 CLK
CLR 1
1Q 2
BUSY
6 1QD
2QC 9
Output Code
<Full Scale
Full Scale
Full Scale – 1 LSB
Midscale + 1 LSB
Midscale
Midscle – 1 LSB
–Full Scale + 1 LSB
–Full Scale
<–Full Scale
011 . . . 11
011 . . . 11
011 . . . 10
000 . . . 01
000 . . . 00
111 . . . 11
100 . . . 01
100 . . . 00
100 . . . 00
POWER SUPPLIES AND DECOUPLING
AD677
1 1CLK
13 2CLK
VIN
CLK
2D 5
74HC175
Table I. Serial Output Coding Format (Twos Complement)
SAMPLE
2QD 8
12 2CLR
2 1CLR
74HC393
Figure 3.
Figure 3 also illustrates the use of a counter (74HC393) to derive the AD677 SAMPLE command from the system clock
when a continuous convert mode is desirable. Pin 9 (2QC) provides a 96 kHz sample rate for the AD677 when used with a
12.288 MHz system clock. Alternately, Pin 8 (2QD) could be
used for a 48 kHz rate.
If a continuous clock is used, then the user must avoid CLK
edges at the instant of disconnecting VIN which occurs at the
falling edge of SAMPLE (see tFCD specification). The duty cycle
of CLK may vary, but both the HIGH (tCH) and LOW (tCL)
phases must conform to those shown in the timing specifications. The internal comparator makes its decisions on the rising
edge of CLK. To avoid a negative edge transition disturbing the
comparator’s settling, tCL should be at least half the value of
tCLK. It is not recommended that the SAMPLE pin change state
toward the end of a CLK cycle, in order to avoid transitions disturbing the internal comparator’s settling.
During a conversion, internal dc error terms such as comparator
voltage offset are sampled, stored on internal capacitors and
used to correct for their corresponding errors when needed. Because these voltages are stored on capacitors, they are subject to
leakage decay and so require refreshing. For this reason there is
a maximum conversion time tC (1000 µs). From the time
SAMPLE goes HIGH to the completion of the 17th CLK pulse,
no more than 1000 µs should elapse for specified performance.
However, there is no restriction to the maximum time between
individual conversions.
The AD677 has three power supply input pins. VCC and VEE
provide the supply voltages to operate the analog portions of the
AD677 including the capacitor DAC, input buffers and comparator. VDD provides the supply voltage which operates the
digital portions of the AD677 including the data output buffers
and the autocalibration controller.
As with most high performance linear circuits, changes in the
power supplies can produce undesired changes in the performance of the circuit. Optimally, well regulated power supplies
with less than 1% ripple should be selected. The ac output impedance of a power supply is a complex function of frequency,
and in general will increase with frequency. In other words, high
frequency switching such as that encountered with digital circuitry requires fast transient currents which most power supplies
cannot adequately provide. This results in voltage spikes on the
supplies. If these spikes exceed the ± 5% tolerance of the ± 12 V
supplies or the ± 10% limits of the +5 V supply, ADC performance will degrade. Additionally, spikes at frequencies higher
than 100 kHz will also degrade performance. To compensate for
the finite ac output impedance of the supplies, it is necessary to
store “reserves” of charge in bypass capacitors. These capacitors
can effectively lower the ac impedance presented to the AD677
power inputs which in turn will significantly reduce the magnitude of the voltage spikes. For bypassing to be effective, certain
guidelines should be followed. Decoupling capacitors, typically
0.1 µF, should be placed as closely as possible to each power
supply pin of the AD677. It is essential that these capacitors be
placed physically close to the IC to minimize the inductance of
the PCB trace between the capacitor and the supply pin. The
logic supply (VDD) should be decoupled to digital common and
the analog supplies (VCC and VEE) to analog common. The reference input is also considered as a power supply pin in this regard and the same decoupling procedures apply. These points
are displayed in Figure 4.
+5V
AD677
VDD
DGND
VCC
AGND
VEE
VREF
0.1µF
0.1µF
0.1µF
Output coding for the AD677 is twos complement as shown in
Table I. The AD677 is designed to limit output coding in the
event of out-of-range input.
0.1µF
SYSTEM
DIGITAL
COMMON
SYSTEM
ANALOG
COMMON
+12V
–12V
Figure 4. Grounding and Decoupling the AD677
REV. A
–9–
AD677
Additionally, it is beneficial to have large capacitors (>47 µF)
located at the point where the power connects to the PCB with
10 µF capacitors located in the vicinity of the ADC to further
reduce low frequency ripple. In systems that will be subjected to
particularly harsh environmental noise, additional decoupling
may be necessary. RC-filtering on each power supply combined
with dedicated voltage regulation can substantially decrease
power supply ripple effects (this is further detailed in Figure 7).
AD677
VIN
SOURCE
VS
∆V
TO POWER
SUPPLY GND
GROUND LEAD
IGROUND > 0
Figure 5a. Input to the A/D is Corrupted by IR Drop in
Ground Leads: VIN = VS + ∆V.
BOARD LAYOUT
Designing with high resolution data converters requires careful
attention to board layout. Trace impedance is a significant issue.
A 1.22 mA current through a 0.5 Ω trace will develop a voltage
drop of 0.6 mV, which is 4 LSBs at the 16-bit level for a 10 V
full-scale span. In addition to ground drops, inductive and capacitive coupling need to be considered, especially when high accuracy analog signals share the same board with digital signals.
Analog and digital signals should not share a common return
path. Each signal should have an appropriate analog or digital
return routed close to it. Using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise.
Wide PC tracks, large gauge wire, and ground planes are highly
recommended to provide low impedance signal paths. Separate
analog and digital ground planes are also desirable, with a single
interconnection point at the AD677 to minimize interference
between analog and digital circuitry. Analog signals should be
routed as far as possible from digital signals and should cross
them, if at all, only at right angles. A solid analog ground plane
around the AD677 will isolate it from large switching ground
currents. For these reasons, the use of wire wrap circuit construction will not provide adequate performance; careful printed
circuit board construction is preferred.
AGND
SHIELDED CABLE
AD677
VIN
SOURCE
VS
AGND
SENSE
AGND
GROUND LEAD
I GROUND > 0
TO POWER
SUPPLY GND
Figure 5b. AGND SENSE Eliminates the Problem in
Figure 5a.
shielded in a noisy environment to avoid capacitive coupling. If
inductive (magnetic) coupling is expected to be dominant such
as where motors are present, twisted-pair wires should be used
instead.
The digital ground pin is the reference point for all of the digital
signals that operate the AD677. This pin should be connected
to the digital common point in the system. As Figure 4 illustrated, the analog and digital grounds should be connected
together at one point in the system, preferably at the AD677.
GROUNDING
The AD677 has three grounding pins, designated ANALOG
GROUND (AGND), DIGITAL GROUND (DGND) and
ANALOG GROUND SENSE (AGND SENSE). The analog
ground pin is the “high quality” ground reference point for the
device, and should be connected to the analog common point in
the system.
AGND SENSE is intended to be connected to the input signal
ground reference point. This allows for slight differences in level
between the analog ground point in the system and the input
signal ground point. However no more than 100 mV is recommended between the AGND and the AGND SENSE pins for
specified performance.
Using AGND SENSE to remotely sense the ground potential of
the signal source can be useful if the signal has to be carried
some distance to the A/D converter. Since all IC ground currents have to return to the power supply and no ground leads
are free from resistance and inductance, there are always some
voltage differences from one ground point in a system to another.
Over distance this voltage difference can easily amount to several LSBs (in a 10 V input span, 16-bit system each LSB is
about 0.15 mV). This would directly corrupt the A/D input signal if the A/D measures its input with respect to power ground
(AGND) as shown in Figure 5a. To solve this problem the
AD677 offers an AGND SENSE pin. Figure 5b shows how the
AGND SENSE can be used to eliminate the problem in Figure
5a. Figure 5b also shows how the signal wires should be
VOLTAGE REFERENCE
The AD677 requires the use of an external voltage reference.
The input voltage range is determined by the value of the reference voltage; in general, a reference voltage of n volts allows an
input range of ± n volts. The AD677 is specified for a voltage
reference between +5 V and +10 V. A 10 V reference will typically require support circuitry operated from ± 15 V supplies; a
5.0 V reference may be used with ± 12 V supplies. Signal-tonoise performance is increased proportionately with input signal
range (see Figure 12). In the presence of a fixed amount of system noise, increasing the LSB size (which results from increasing the reference voltage) will increase the effective S/(N+D)
performance. Figure 11 illustrates S/(N+D) as a function of reference voltage. In contrast, dc accuracy will be optimal at lower
reference voltage values (such as 5 V) due to capacitor nonlinearity at higher voltage values.
During a conversion, the switched capacitor array of the AD677
presents a dynamically changing current load at the voltage reference as the successive-approximation algorithm cycles through
various choices of capacitor weighting. (See the following section “Analog Input” for a detailed discussion of the VREF input
characteristics.) The output impedance of the reference circuitry
must be low so that the output voltage will remain sufficiently
constant as the current drive changes. In some applications, this
may require that the output of the voltage reference be buffered
by an amplifier with low impedance at relatively high frequencies. In choosing a voltage reference, consideration should be
–10–
REV. A
AD677
made for selecting one with low noise. A capacitor connected
between REF IN and AGND will reduce the demands on the
reference by decreasing the magnitude of high frequency components required to be sourced by the reference.
regulator prevents very large voltage spikes from entering the
regulators. Any power line noise which the regulators cannot
eliminate will be further filtered by an RC filter (10 Ω/10 µF)
having a –3 dB point at 1.6 kHz. For best results the regulators
should be within a few centimeters of the AD677.
Figures 6 and 7 represent typical design approaches.
ANALOG INPUT
+12V
As previously discussed, the analog input voltage range for the
AD677 is ± VREF. For purposes of ground drop and common
mode rejection, the VIN and VREF inputs each have their own
ground. VREF is referred to the local analog system ground
(AGND), and VIN is referred to the analog ground sense pin
(AGND SENSE) which allows a remote ground sense for the
input signal.
2
VIN
8
CN
6
AD586
1.0µF
VREF
10µF
AD677
0.1µF
4
AGND
Figure 6.
Figure 6 shows a voltage reference circuit featuring the 5 V output AD586. The AD586 is a low cost reference which utilizes a
buried Zener architecture to provide low noise and drift. Over
the 0°C to +70°C range, the AD586M grade exhibits less than
1.0 mV output change from its initial value at +25°C. A noise
reduction capacitor, CN, reduces the broadband noise of the
AD586 output, thereby optimizing the overall performance of
the AD677. It is recommended that a 10 µF to 47 µF high quality tantalum capacitor and a 0.1 µF capacitor be tied between
the VREF input of the AD677 and ground to minimize the impedance on the reference.
Using the AD677 with ± 10 V input range (VREF = 10 V) typically requires ± 15 V supplies to drive op amps and the voltage
reference. If ± 12 V is not available in the system, regulators
such as 78L12 and 79L12 can be used to provide power for the
AD677. This is also the recommended approach (for any input
range) when the ADC system is subjected to harsh environments such as where the power supplies are noisy and where
voltage spikes are present. Figure 7 shows an example of such a
system based upon the 10 V AD587 reference, which provides a
300 µV LSB. Circuitry for additional protection against power
supply disturbances has been shown. A 100 µF capacitor at each
2 VIN
10µF
VO 6
NR 8
GND
4
0.1µF
In most cases, these characteristics require the use of an external
op amp to drive the input of the AD677. Care should be taken
with op amp selection; even with modest loading conditions,
most available op amps do not meet the low distortion requirements necessary to match the performance capabilities of the
AD677. Figure 8 represents a circuit, based upon the AD845,
which will provide excellent overall performance.
For applications optimized more for low distortion and low
noise, the AD845 of Figure 8 may be replaced by the AD743.
AD587
10Ω
The AD677 analog inputs (VIN, VREF and AGND SENSE) exhibit dynamic characteristics. When a conversion cycle begins,
each analog input is connected to an internal, discharged 50 pF
capacitor which then charges to the voltage present at the corresponding pin. The capacitor is disconnected when SAMPLE is
taken LOW, and the stored charge is used in the subsequent
conversion. In order to limit the demands placed on the external
source by this high initial charging current, an internal buffer
amplifier is employed between the input and this capacitance for
a few hundred nanoseconds. During this time the input pin exhibits typically 20 kΩ input resistance, 10 pF input capacitance
and ± 40 µA bias current. Next, the input is switched directly to
the now precharged capacitor and allowed to fully settle. During
this time the input sees only a 50 pF capacitor. Once the sample
is taken, the input is internally floated so that the external input
source sees a very high input resistance and a parasitic input
capacitance of typically only 2 pF. As a result, the only dominant input characteristic which must be considered is the high
current steps which occur when the internal buffers are switched
in and out.
1k Ω
1µF
±5V
INPUT
10Ω
+15V
78L12
100µF
0.01µF
VCC
VDD
+5V
VEE
10Ω
–15V
100µF
3
10µF
0.1µF
AD677
4
6
–12V
AGND
SENSE
79L12
0.01µF
VIN
0.1µF
AGND
VIN
10µF
0.1µF
Figure 8.
VIN
Figure 7.
REV. A
0.1µF
7
AD845
499 Ω
VREF
AD677
0.1µF
100µF
2
0.1µF
10µF
10Ω
+12V
1k Ω
–11–
AD677
AC parameters, which include S/(N+D), THD, etc., reflect the
AD677’s effect on the spectral content of the analog input signal. Figures 11 through 18 provide information on the AD677’s
ac performance under a variety of conditions.
A perfect n-bit ADC with no errors will yield a theoretical quantization noise of q/√12, where q is the weight of the LSB. This
relationship leads to the well-known equation for theoretical
full-scale rms sine wave signal-to-noise plus distortion level of
S/(N + D) = 6.02 n + 1.76 dB, here n is the bit resolution. An
actual ADC, however, will yield a measured S/(N + D) less than
the theoretical value. Solving this equation for n using the measured S/(N + D) value yields the equation for effective number
of bits (ENOB):
ENOB =
[S / ( N + D )]
ACTUAL
– 1.76 dB
6.02
As a general rule, averaging the results from several conversions
reduces the effects of noise, and therefore improves such parameters as S/(N+D). AD677 performance may be optimized by
operating the device at its maximum sample rate of 100 kSPS
and digitally filtering the resulting bit stream to the desired signal bandwidth. This succeeds in distributing noise over a wider
frequency range, thus reducing the noise density in the frequency band of interest. This subject is discussed in the following section.
OVERSAMPLING AND NOISE FILTERING
The Nyquist rate for a converter is defined as one-half its sampling rate. This is established by the Nyquist theorem, which
requires that a signal be sampled at a rate corresponding to at
least twice its highest frequency component of interest in order
to preserve the informational content. Oversampling is a conversion technique in which the sampling frequency is more than
twice the frequency bandwidth of interest. In audio applications,
the AD677 can operate at a 2 × FS oversampling rate, where
FS = 48 kHz.
In quantized systems, the informational content of the analog
input is represented in the frequency spectrum from dc to the
Nyquist rate of the converter. Within this same spectrum are
higher frequency noise and signal components. Antialias, or low
pass, filters are used at the input to the ADC to reduce these
noise and signal components so that their aliased components
do not corrupt the baseband spectrum. However, wideband
noise contributed by the AD677 will not be reduced by the
antialias filter. The AD677 quantization noise is evenly distributed from dc to the Nyquist rate, and this fact can be used to
minimize its overall affect.
FS is the sampling frequency, and Fa is the signal bandwidth of
interest. For audio bandwidth applications, the AD677 is capable of operating at a 2 × oversample rate (96 kSPS), which
typically produces an improvement in S/(N+D) of 3 dB compared with operating at the Nyquist conversion rate of 48 kSPS.
Oversampling has another advantage as well; the demands on
the antialias filter are lessened. In summary, system performance is optimized by running the AD677 at or near its maximum sampling rate of 100 kHz and digitally filtering the
resulting spectrum to eliminate undesired frequencies.
DC PERFORMANCE
The self-calibration scheme used in the AD677 compensates for
bit weight errors that may exist in the capacitor array. This mismatch in capacitor values is adjusted (using the calibration coefficients) during conversion and provides for excellent dc
linearity performance. Figure 19 illustrates the DNL plot of a
typical AD677 at +25°C. A histogram test is a statistical method
for deriving an A/D converter’s differential nonlinearity. A ramp
input is sampled by the ADC and a large number of conversions
are taken and stored. Theoretically the codes would all be the
same size and, therefore, have an equal number of occurrences.
A code with an average number of occurrences would have a
DNL of “0”. A code with more or less than average will have a
DNL of greater than or less than zero LSB. A DNL of –1 LSB
indicates missing code (zero occurrences).
Figure 20 illustrates the code width distribution of the DNL
plots of Figure 19.
DC CODE UNCERTAINTY
Ideally, a fixed dc input should result in the same output code
for repetitive conversions. However, as a consequence of unavoidable circuit noise within the wideband circuits in the ADC,
there is range of output codes which may occur for a given input
voltage. If you apply a dc signal to the AD677 and record
10,000 conversions, the result will be a distribution of codes as
shown in Figure 9 (using a 10 V reference). If you fit a Gaussian
probability distribution to the histogram, the standard deviation
is approximately equivalent to the rms input noise of ADC.
7649
7000
The AD677 quantization noise effects can be reduced by oversampling—sampling at a rate higher than that defined by the
Nyquist theorem. This spreads the noise energy over a bandwidth wider than the frequency band of interest. By judicious
selection of a digital decimation filter, noise frequencies outside
the bandwidth of interest may be eliminated.
The process of analog to digital conversion inherently produces
noise, known as quantization noise. The magnitude of this noise
is a function of the resolution of the converter, and manifests itself as a limit to the theoretical signal-to-noise ratio achievable.
This limit is described by S/(N + D) = (6.02n + 1.76 + 10 log
FS/2FA) dB, where n is the resolution of the converter in bits,
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAAAAAAAAAAA
8000
NUMBER OF CODE HITS
AC PERFORMANCE
6000
5000
4000
3000
2000
1000
1267
1081
3
0
–2
–1
0
1
DEVIATION FROM CORRECT CODE – LSBs
Figure 9. Distribution of Codes from 10,000 Conversions
Relative to the Correct Code
–12–
REV. A
AD677
The standard deviation of this distribution is approximately
0.5 LSBs. If less uncertainty is desired, averaging multiple conversions will narrow this distribution by the inverse of the square
root of the number of samples; i.e., the average of 4 conversions
would have a standard deviation of 0.25 LSBs.
105
100
90
80
THD
70
dB
DSP INTERFACE
Figure 10 illustrates the use of the Analog Devices ADSP-2101
digital signal processor with the AD677. The ADSP-2101 FO
(flag out) pin of Serial Port 1 (SPORT 1) is connected to the
SAMPLE line and is used to control acquisition of data. The
ADSP-2101 timer is used to provide precise timing of the FO
pin.
60
S/(N+D)
50
40
30
20
10
–80
ADSP-2101
FO
SAMPLE
RFS0
BUSY
AMPLITUDE – dB
The AD677 BUSY signal is connected to RF0 to notify
SPORT0 when a new data word is coming. SPORT0 should be
configured in normal, external, noninverting framing mode and
can be programmed to generate an interrupt after the last data
bit is received. To maximize the conversion rate, SAMPLE
should be brought HIGH immediately after the last data bit is
received.
dB
82
3.5
4.5
5.5
6.5
7.5
8.5
9.5
10.0
VREF – Volts
Figure 11. S/(N+D) and THD vs. VREF, fS = 100 kHz (Calibration is not guaranteed below +5 VREF)
REV. A
–40
–60
–80
–100
–140
0
5
10
15
20
25
30
FREQUENCY – kHz
35
40
45
50
Figure 13. 4096 Point FFT at 100 kSPS, fIN = 1 kHz,
VREF = 5 V
0
–20
–40
–60
–80
–100
0
5
10
15
20
25
30
FREQUENCY – kHz
35
40
45
Figure 14. 4096 Point FFT at 100 kSPS, fIN = 1 kHz,
VREF = 10 V
S/(N+D)
2.5
0
–20
–140
THD
86
–10
–120
AA
AA
AA
90
–20
–120
AMPLITUDE – dB
The SCLK pin of the ADSP-2101 SPORT0 provides the CLK
input for the AD677. The clock should be programmed to be
approximately 2 MHz to comply with AD677 specifications. To
minimize digital feedthrough, the clock should be disabled (by
setting Bit 14 in SPORT0 control register to 0) during data acquisition. Since the clock floats when disabled, a pulldown resistor of 12 kΩ–15 kΩ should be connected to SCLK to ensure it
will be LOW at the falling edge of SAMPLE. To maximize the
conversion rate, the serial clock should be enabled immediately
after SAMPLE is brought LOW (hold mode).
94
–30
0
DT0
Figure 10. ADSP-2101 Interface
98
–40
Figure 12. S/(N+D) and THD vs. Input Amplitude,
fS = 100 kHz
TFS0
102
–50
SDATA
DR0
106
–60
INPUT LEVEL – dB
CLK
SCLK0
SERIAL
PORT 0
–70
AD677
–13–
48
AD677
106
+5V
THD, 5V
104
90
THD, 10V
102
80
+12V
100
98
–12V
60
96
dB
S/(N+D) – dB
70
S/(N+D), 10V
94
50
92
40
S/(N+D), 5V
90
30
88
86
20
0
100
1k
10k
RIPPLE FREQUENCY – Hz
100k
1M
–40
Figure 15. AC Power Supply Rejection (fIN = 1.06 kHz)
fSAMPLE = 96 kSPS, VRIPPLE = 0.13 V p-p
AMPLITUDE – dB
AMPLITUDE – dB
–30
–50
–70
–90
–110
–130
0
5
10
15
20
25
30
FREQUENCY – kHz
35
40
45
–0.2
–0.4
–0.6
–0.8
–1.0
0
32000
NUMBER OF CODES WITH EACH DNL
102
100
98
dB
5
10
THD, 10V
S/(N+D), 10V
92
90
S/(N+D), 5V
26000
22000
18000
12000
8000
510
530
CLK PERIOD – ns
550
570
590
Figure 17. AC Performance vs. Clock Period, TA = +85°C
(5 V and 10 V Reference)
45
50
55
60
65
30671
14113
2993
0
490
25
30
35
40
FREQUENCY – kHz
AA
AA
AA
AAA
AA
AA
AAA
AA
A
AA
AA
AA
AA
A
AA
AA
AA
AA
AA
AAAAAA
AAAAAAAAA
2500
2
86
470
20
14645
14000
4000
88
450
15
Figure 19. DNL Plot at VREF = 10 V, TA = +25°C, fS =
100 kSPS
THD, 5V
94
80
0.2
0.0
106
96
60
1.0
0.8
0.6
0.4
48
Figure 16. IMD Plot for fIN = 1008 Hz (fa), 1055 Hz (fb) at
96 kSPS
104
0
20
40
TEMPERATURE – Degree °C
Figure 18. AC Performance Using Minimum Clock Period
vs. Temperature (tCLK = 480 ns), 5 V and 10 V Reference
0
–150
–20
–.35
392
152
–.25
–.15 –.05 0 .05 .15
DNL – LSBs
.25
.35
60
6
.40
Figure 20. DNL Error Distribution (Taken from Figure 19)
–14–
REV. A
AD677
OUTLINE DIMENSIONS
Dimensions shown in inchcs and (mm)
D-16
16-Lead Side Brazed Ceramic DIP Package
0.005 (0.13) MIN
0.080 (2.03) MAX
9
16
0.310 (7.87)
0.220 (5.59)
PIN 1
1
8
0.840 (21.34) MAX
0.060 (1.52)
0.015 (0.38)
0.200
(5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
SEATING
PLANE
0.023 (0.58)
0.110 (2.79)
0.070 (1.78)
0.014 (0.36)
0.090 (2.29)
0.030 (0.76)
0.015 (0.38)
0.008 (0.20)
0.320 (8.13)
0.290 (7.37)
N-16
16-Lead Plastic DIP
9
16
0.280 (7.11)
0.240 (6.10)
PIN 1
1
8
0.840 (21.33)
0.745 (18.93)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.150
(3.81)
MIN
0.200 (5.05)
0.125 (3.18)
0.022 (0.558)
0.014 (0.356)
0.100 (2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
R-28
28-Lead Wide Body SOIC (SOIC-28)
0.7125 (18.10)
0.6969 (17.70)
28
15
0.2992 (7.60)
0.2914 (7.40)
PIN 1
0.4193 (10.65)
0.3937 (10.00)
14
1
0.1043 (2.65)
0.0926 (2.35)
0.0500 (1.27)
BSC
0.0291 (0.74)
0.0098 (0.25)
X
45°
0°- 8°
0.0118 (0.30)
0.0040 (0.10)
REV. A
0.0192 (0.49)
0.0138 (0.35)
0.0125 (0.32)
0.0091 (0.23)
–15–
0.0500 (1.27)
0.0157 (0.40)
–16–
PRINTED IN U.S.A.
C1786–18–4/93