Features
•
•
•
•
•
•
•
•
•
Contactless Read/Write Data Transmission
Radio Frequency fRF from 100 kHz to 150 kHz
e5550, e5551, T5557 Binary Compatible
Extended Mode
Small Size, Configurable for ISO/IEC 11784/785 Compatibility
75 pF On-chip Resonant Capacitor (Mask Option)
7 × 32-bit EEPROM Data Memory Including 32-bit Password
Separate 64-bit Memory for Traceability Data
32-bit Configuration Register in EEPROM to Setup:
– Data Rate
• RF/2 to RF/128, Binary Selectable, or
• Fixed e5550 Data Rates
– Modulation/Coding
• FSK, PSK, Manchester, Bi-phase, NRZ
– Other Options
• Password Mode
• Max Block Feature
• Answer-On-Request (AOR) Mode
• Inverse Data Output
• Direct Access Mode
• Sequence Terminator(s)
• Write Protection (Through Lock-bit per Block)
• Fast Write Method (5 Kbps versus 2 Kbps)
• OTP Functionality
• POR Delay up to 67 ms
Multifunctional
330-bit
Read/Write RF
Identification IC
ATA5567
1. Description
The ATA5567 is a contactless R/W IDentification IC (IDIC®) for applications in the
125-kHz frequency range. A single coil, connected to the chip, serves as the IC’s
power supply and bi-directional communication interface. The antenna and chip
together form a transponder or tag.
The on-chip 330-bit EEPROM (10 blocks, 33 bits each) can be read and written blockwise from a reader. Block 0 is reserved for setting the operation modes of the
ATA5567 tag. Block 7 may contain a password to prevent unauthorized writing.
Data is transmitted from the IDIC using load modulation. This is achieved by damping
the RF field with a resistive load between the two terminals Coil 1 and Coil 2. The IC
receives and decodes 100% amplitude-modulated (OOK) pulse-interval-encoded bit
streams from the base station or reader.
4874F–RFID–07/08
2. System Block Diagram
Figure 2-1.
RFID System Using ATA5567 Tag
Reader
or
Base station
1)
Data
Controller
Power
Coil interface
Transponder
Memory
ATA5567
1) Mask option
3. ATA5567 – Building Blocks
Figure 3-1.
Block Diagram
POR
Modulation
Write
decoder
Mode register
Memory
(330-bit
EEPROM)
Controller
Bit-rate
generator
1)
Analog front end
Coil 1
Coil 2
Input register
Test logic
HV generator
1) Mask option
3.1
Analog Front End (AFE)
The AFE includes all circuits which are directly connected to the coil. It generates the IC’s power
supply and handles the bi-directional data communication with the reader. It consists of the following blocks:
• Rectifier to generate a DC supply voltage from the AC coil voltage
• Clock extractor
• Switchable load between Coil 1 and Coil 2 for data transmission from the tag to the reader
• Field gap detector for data transmission from the base station to the tag
• ESD protection circuitry
2
ATA5567
4874F–RFID–07/08
ATA5567
3.2
Data-rate Generator
The data rate is binary programmable to operate at any data rate between RF/2 and RF/128 or
equal to any of the fixed e5550/e5551 and T5554 bit rates (RF/8, RF/16, RF/32, RF/40, RF/50,
RF/64, RF/100, and RF/128).
3.3
Write Decoder
This function decodes the write gaps and verifies the validity of the data stream according to the
Atmel e555x write method (pulse interval encoding).
3.4
HV Generator
This on-chip charge pump circuit generates the high voltage required for programming of the
EEPROM.
3.5
DC Supply
Power is externally supplied to the IDIC via the two coil connections. The IC rectifies and regulates this RF source and uses it to generate its supply voltage.
3.6
Power-On Reset (POR)
This circuit delays the IDIC functionality until an acceptable voltage threshold has been reached.
3.7
Clock Extraction
The clock extraction circuit uses the external RF signal as its internal clock source.
3.8
Controller
The control-logic module executes the following functions:
• Loads mode register with configuration data from EEPROM block 0 after power-on and also
during reading
• Controls memory access (read, write)
• Handles write data transmission and write error modes
The first two bits of the reader to tag data stream are the opcode, for example, write, direct
access, or reset.
In password mode, the 32 bits received after the opcode are compared with the password stored
in memory block 7.
3.9
Mode Register
The mode register stores the configuration data from the EEPROM block 0. It is continually
refreshed at the start of every block read and (re-)loaded after any POR event or reset command. On delivery, the mode register is preprogrammed with the value 0014 8000h which
corresponds to continuous read of block 0, Manchester coded, RF/64.
3
4874F–RFID–07/08
Block 0 Configuration Mapping – e5550 Compatibility Mode
0
1
1 2
3 4
5 6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
0 1
1 0
0 0
0 0
0 0
Data
Bit Rate
Unlocked
Locked
0
Modulation
PSK
CF
RF/8
0 0 0
0 0 RF/2
RF/16
0 0 1
0 1 RF/4
RF/32
0 1 0
1 0 RF/8
RF/40
0 1 1
1 1 Res
RF/50
1 0 0
0 0 0 0 0 Direct
RF/64
1 0 1
0 0 0 0 1 PSK1
RF/100 1 1 0
0 0 0 1 0 PSK2
RF/128 1 1 1
0 0 0 1 1 PSK3
0
Max
Block
0
POR delay
Master Key
Note 1), 2)
0
PWD
0
ST-sequence Terminator
Lock Bit
L
AOR
Figure 3-2.
0 0 1 0 0 FSK1
0 0 1 0 1 FSK2
0 0 1 1 0 FSK1a
0 0 1 1 1 FSK2a
0 1 0 0 0 Manchester
1 0 0 0 0 Bi-phase ('50)
1 1 0 0 0 Reserved
1) If Master Key = 6 then test mode write commands are ignored
2) If Master Key < > 6 or 9 then extended function mode is disabled
3.10
Modulator
The modulator consists of data encoders for the following basic types of modulation:
Table 3-1.
Mode
Direct Data Output
(1)
FSK1a
FSK/8-/5
0 = RF/8;
1 = RF/5
FSK2a(1)
FSK/8-/10
0 = RF/8;
1 = RF/10
FSK1
(1)
FSK/5-/8
0 = RF/5;
1 = RF/8
FSK2
(1)
FSK/10-/8
0 = RF/10;
1 = RF/8
(2)
PSK1
Phase change when input changes
PSK2(2)
Phase change on bit clock if input high
(2)
PSK3
Phase change on rising edge of input
Manchester
0 = falling edge, 1 = rising edge
Bi-phase
1 creates an additional mid-bit change
NRZ
1 = damping on, 0 = damping off
Notes:
4
Types of e5550-compatible Modulation Modes
1. A common multiple of bit rate and FSK frequencies is recommended.
2. In PSK mode the selected data rate has to be an integer multiple of the PSK sub-carrier
frequency.
ATA5567
4874F–RFID–07/08
ATA5567
3.11
Memory
The memory is a 330-bit EEPROM, which is arranged in 10 blocks of 33 bits each. All 33 bits of
a block, including the lock bit, are programmed simultaneously.
Block 0 of page 0 contains the mode/configuration data, which is not transmitted during regular-read operations. Block 7 of page 0 may be used as a write protection password.
Bit 0 of every block is the lock bit for that block. Once locked, the block (including the lock bit
itself) is not re-programmable through the RF field.
Blocks 1 and 2 of page 1 contain traceability data and are transmitted with the modulation
parameters defined in the configuration register after the opcode “11” is issued by the reader
(see Figure 4-6 on page 11). These traceability data blocks are programmed and locked by
Atmel.
Figure 3-3.
Memory Map
Page 0
Page 1
0 1
32
1
Traceability data
Block 2
1
Traceability data
Block 1
L
User data or password
Block 7
L
User data
Block 6
L
User data
Block 5
L
User data
Block 4
L
User data
Block 3
L
User data
Block 2
User data
Block 1
L
L
Configuration data
Block 0
32 bits
Not transmitted
3.12
Traceability Data Structure
Blocks 1 and 2 of page 1 contain the traceability data and are programmed and locked by Atmel
during production testing(1). The most significant byte of block 1 is fixed to E0h, the allocation
class (ACL) as defined in ISO/IEC 15963-1. The second byte is therefore defined as Atmel®’s
manufacturer ID (15h). The following 8 bits are used as IC reference byte (ICR bits 47 to 40).
The 3 most significant bits define the IC version of the ATA5567, the foundry version, or both.
The lower 5 bits are by default reset (00) as the Atmel standard value. Other values may be
assigned, by request, to high volume customers as tag issuer identification.
The lower 40 bits of the data encode Atmel’s traceability information, and conform to a unique
numbering system. These 40 data bits are divided in two sub-groups, a 5-digit lot ID number,
and the binary wafer number (5 bits) concatenated with the sequential die number per wafer.
Note:
1. This is only valid for sawn wafer “DDB, DDT” delivery.
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4874F–RFID–07/08
Figure 3-4.
ATA5567 Traceability Data Structure
Example:
"E0"
"15"
"00"
"41"
8
Bit No.
...
1
8
...
9
ACL
Block 1
16
...
17
MFC
CID
63 MSB
...
31
...
24
25
ICR
...
32
LotID
32
Bit value
LotID
Block 2
Bit No.
...
1
12
LSB
Wafer #
12
13
...
17
0
DW
18
...
31 32
20
"557"
ACL
MFC
UID
CID
ICR
LotID
Wafer#
DW
Allocation class as defined in ISO/IEC 15963-1 = E0h
Manufacturer code of Atmel Corporation as defined in ISO/IEC 7816-6 = 15h
UID issuer identifier on request (respectively 5 bit CID and 3 bit ICR)
Customer ID on request
IC revision
5-digit lot number, e.g., “41557”
5 bits for wafer#
15 bits encoded as sequential die on wafer number
4. Operating the ATA5567
4.1
Initialization and POR Delay
The Power-On-Reset (POR) circuit remains active until an adequate voltage threshold has been
reached. This threshold will be reached also if the coil voltage ramps up in terms of a few volts
per second. It means that the tag can be moved slowly towards the reader without performance
loss. This in turn triggers the default start-up delay sequence. During this configuration period of
about 192 field clocks, the ATA5567 is initialized with the configuration data stored in EEPROM
block 0. During initialization of the configuration block 0, for all ATA55670x variants the load
damping is active permanently (see Figure 4-5 on page 10). The ATA55671x types (without
damping option) achieve a longer read range based on the lower activation field strength.
If the POR-delay bit is reset, no additional delay is observed after the configuration period. Tag
modulation in regular-read mode will be observed about 3 ms after entering the RF field. If the
POR delay bit is set, the ATA5567 remains in a permanent damping state until 8190 internal
field clocks have elapsed.
TINIT = (192 + 8190 × POR delay) × TC ≈ 67 ms; TC = 8 µs at 125 kHz
Any field gap occurring during this initialization phase will restart the complete sequence. After
this initialization time the ATA5567 enters regular-read mode and modulation starts automatically using the parameters defined in the configuration register.
6
ATA5567
4874F–RFID–07/08
ATA5567
4.2
Tag to Reader Communication
During normal operation, the data stored within the EEPROM is cycled and the Coil 1 and Coil 2
terminals are load modulated. This resistive load modulation can be detected at the reader
module.
4.3
Regular-read Mode
In regular-read mode, data from the memory is transmitted serially, starting with block 1, bit 1,
up to the last block (for example, 7), bit 32. The last block which will be read is defined by the
mode parameter field MAXBLK in EEPROM block 0. When the data block addressed by MAXBLK has been read, data transmission restarts with block 1, bit 1.
The user may limit the cyclic data stream in regular-read mode by setting the MAXBLK between
0 and 7 (representing each of the 8 data blocks). If set to 7, blocks 1 through 7 can be read. If
set to 1, only block 1 is transmitted continuously. If set to 0, the contents of the configuration
block (normally not transmitted) can be read. In the case of MAXBLK = 0 or 1, regular-read
mode can not be distinguished from block-read mode.
Figure 4-1.
MAXBLK = 5
Examples for Different MAXBLK Settings
0
Block 1
Block 4
Block 5
Block 1
Block 2
Block 2
Block 1
Block 2
Block 1
Block 0
Block 0
Block 0
Block 0
Loading block 0
MAXBLK = 2
0
Block 1
Loading block 0
MAXBLK = 0
0
Block 0
Loading block 0
Every time the ATA5567 enters regular-read or block-read mode, the first bit transmitted is a
logical 0. The data stream starts with block 1, bit 1, continues through MAXBLK, bit 32, and
cycles continuously if in regular-read mode.
Note:
4.4
This behavior is different from the original e555x and helps to decode PSK-modulated data.
Block-read Mode
With the direct access command, only the addressed block is repetitively read. This mode is
called block-read mode. Direct access is entered by transmitting the page access opcode (“10”
or “11”), a single “0” bit and the requested 3-bit block address when the tag is in normal mode.
In password mode (PWD bit set), the direct access to a single block needs the valid 32-bit password to be transmitted after the page access opcode, whereas a “0” bit and the 3-bit block
address follow afterwards. In case the transmitted password does not match with the contents of
block 7, the ATA5567 tag returns to the regular-read mode.
Note:
A direct access to block 0 of page 1 will read the configuration data of block 0, page 0.
A direct access to blocks 3 to 7 of page 1 reads all data bits as zero.
7
4874F–RFID–07/08
4.5
e5550 Sequence Terminator
The sequence terminator ST is a special damping pattern which is inserted before the first block
and may be used to synchronize the reader. This e5550-compatible sequence terminator consists of 4 bit periods with underlaying data values of “1”. During the second and the fourth bit
periods, modulation is switched off (Manchester encoding – switched on). Bi-phase modulated
data blocks need fixed leading and trailing bits in combination with the sequence terminator to
be identified reliably.
The sequence terminator may be individually enabled by setting mode bit 29 (ST = 1) in the
e5550-compatibility mode (X-mode = 0).
In the regular-read mode, the sequence terminator is inserted at the start of each
MAXBLK-limited read data stream.
In block-read mode – after any block-write or direct access command – or if MAXBLK was set to
0 or 1, the sequence terminator is inserted before the transmission of the selected block.
This behavior is especially different from former e5550-compatible ICs (T5551, T5554).
Figure 4-2.
Read Data Stream with Sequence Terminator
No terminator
Block 1
Block 2
MAXBLK
Block 1
Block 2
Regular read mode
Sequence terminator
St = on
Figure 4-3.
Block 1
Sequence terminator
Block 2
MAXBLK
Block 1
Block 2
e5550-compatible Sequence Terminator Waveforms
Bit period
Sequence
Data 1
Data 1
Data 1
Data 1
Last bit
First bit
Modulation
off (on)
Modulation
off (on)
Waveforms per different modulation types
bit 1 or 0
Manchester
VCoilPP
FSK
Sequence terminator not suitable for Bi-phase or PSK modulation
8
ATA5567
4874F–RFID–07/08
ATA5567
4.6
Reader to Tag Communication
Data is written to the tag by interrupting the RF field with short field gaps (on-off keying) in accordance with the e5550 write method. The time between two gaps encodes the “0” or “1”
information to be transmitted (pulse interval encoding). The duration of the gaps is usually 50 µs
to 150 µs. The time between two gaps is nominally 24 field clocks for a “0” and 54 field clocks for
a “1”. When there is no gap for more than 64 field clocks after a previous gap, the ATA5567 exits
the write mode. The tag starts with the command execution if the correct number of bits were
received. If a failure is detected, the ATA5567 does not continue and will enter regular-read
mode.
4.7
Start Gap
The initial gap is referred to as the start gap. This triggers the reader to tag communication. During this mode of operation, the receive damping is permanently enabled to ease gap detection.
The start gap may need to be longer than subsequent gaps in order to be detected reliably.
A start gap will be accepted at any time after the mode register has been loaded (≥ 3 ms). A single gap will not change the previously selected page (by former opcode “10” or “11”).
Figure 4-4.
Start of Reader to Tag Communication
Read mode
Write mode
d1
dn
Sgap
Table 4-1.
Wgap
Write Data Decoding Scheme
Parameters
Remark
Symbol
Min.
Max.
Unit
Sgap
10
50
FC
Normal write mode
Wgap
8
30
FC
“0” data
d0
16
31
FC
“1” data
d1
48
63
FC
Start gap
Write gap
Write data in normal mode
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4874F–RFID–07/08
4.8
Write Data Protocol
The ATA5567 expects to receive a dual bit opcode as the first two bits of a reader command
sequence. There are three valid opcodes:
• The opcodes “10” and “11” precede all block write and direct access operations for page 0
and page 1
• The RESET opcode “00” initiates a POR cycle
• The opcode “01” precedes all test mode write operations. Any test mode access is ignored
after the master key (bits 1 to 4) in block 0 has been set to “6”. Any further modifications of
the master key are prohibited by setting the lock bit of block 0 or the OTP bit
Writing must follow these rules:
• Standard write needs the opcode, the lock bit, 32 data bits, and the 3-bit address (38 bits
total)
• Protected write (PWD bit set) requires a valid 32-bit password between the opcode and data
bits or address bits
• For the AOR wake-up command, an opcode and a valid password are necessary to select
and activate a specific tag
Note:
The data bits are read in the same order as written.
If the transmitted command sequence is invalid, the ATA5567 enters regular-read mode with the
previously selected page (by former opcode “10” or “11”).
Figure 4-5.
Complete Writing Sequence
Read mode
Write mode
Read mode
ATA55671x
ATA556701
Block 0
loading
Opcode
Start gap
Block data
Block address
Programming
Lock bit
POR
10
ATA5567
4874F–RFID–07/08
ATA5567
Figure 4-6.
ATA5567 Command Formats
OP
Standard write
1p1) L
Protected write
1p1) 1
Data
32
Password
32
1
Password
32
Direct access (PWD = 1)
1p1) 1
Password
32
Direct access (PWD = 0)
1p1) 0
AOR (wake-up command)
Page 0/1 regular read
Reset command
4.9
1
10
2 Addr
2 Addr
L
1
0
2 Addr
0
Data
32
2
Addr 0
0
0
1p1)
00
1)
p = page selector
Password
When password mode is active (PWD = 1), the first 32 bits after the opcode are regarded as the
password. They are compared bit by bit with the contents of block 7, starting at bit 1. If the comparison fails, the ATA5567 will not program the memory, instead it will restart in regular-read
mode once the command transmission is finished.
Note:
In password mode, MAXBLK should be set to a value below 7 to prevent the password from being
transmitted by the ATA5567.
Each transmission of the direct access command (two opcode bits, 32-bit password, “0” bit plus
3 address bits = 38 bits) needs about 18 ms. Testing all possible combinations (about 4.3 billion)
would take about two years.
4.10
Answer-On-Request (AOR) Mode
When the AOR bit is set, the ATA5567 does not start modulation in the regular-read mode after
loading configuration block 0. The tag waits for a valid AOR data stream (wake-up command)
from the reader before modulation is enabled. The wake-up command consists of the opcode
(“10”) followed by a valid password. The selected tag will remain active until the RF field is
turned off or a new command with a different password is transmitted which may address
another tag in the RF field.
Table 4-2.
PWD
ATA5567 — Modes of Operation
AOR
Behavior of Tag after Reset Command or POR
De-activate Function
Command with non-matching password
deactivates the selected tag
1
1
Answer-On-Request (AOR) mode:
• Modulation starts after wake-up with a matching password
• Programming needs valid password
1
0
Password mode:
• Modulation in regular-read mode starts after reset
• Programming and direct access needs valid password
0
--
Normal mode:
• Modulation in regular-read mode starts after reset
• Programming and direct access without password
11
4874F–RFID–07/08
Figure 4-7.
Answer-On-Request (AOR) Mode
ATA55671x
Modulation
ATA556701
VCoil1 - Coil2
Block 0
loading
No modulation
because AOR = 1
AOR wake-up command
(with valid PWD)
POR
Figure 4-8.
Coil Voltage after Programming of a Memory Block
VCoil 1 - Coil 2
Write data to tag
5.6 ms
Programming and
data verification
12
Read programmed
memory block
POR
or
(Block-read mode)
Single
gap
Read block 1 to MAXBLK
(Regular-read mode)
ATA5567
4874F–RFID–07/08
ATA5567
Figure 4-9.
Anticollision Procedure Using AOR Mode
Reader
Tag
Initialize tags with
AOR = 1, PWD = 1
Field OFF
ON
Power on reset
read configuration
Wait for tW > 2.5 ms
Enter AOR mode
Wait for opcode +
PWD
"wake up
command"
"Select a single tag"
send opcode + PWD
"wake up command"
Receive damping ON
No
Password correct ?
Yes
Decode data
No
Send block 1 to MAXBLK
All tags read ?
Yes
Field ON
OFF
Exit
13
4874F–RFID–07/08
4.11
Programming
When all necessary information has been received by the ATA5567, programming may proceed.
There is a clock delay between the end of the writing sequence and the start of programming.
Typical programming time is 5.6 ms. This cycle includes a data verification read to grant secure
and correct programming. After programming was executed successfully, the ATA5567 enters
block-read mode transmitting the block just programmed (see Figure 4-8 on page 12).
Note:
This timing and behavior is different from the e555x-family predecessors.
5. Error Handling
Several error conditions can be detected to ensure that only valid bits are programmed into the
EEPROM. There are two error types, which lead to two different actions.
5.1
Errors During Writing
The following detectable errors could occur during writing data to the ATA5567:
• Wrong number of field clocks between two gaps (that is, not a valid “1” or “0” pulse stream)
• Password mode is activated and the password does not match the contents of block 7
• The number of bits received in the command sequence is incorrect
Valid bit counts accepted by the ATA5567 are:
Password write
Standard write
AOR wake up
Direct access with PWD
Direct access
Reset command
Page 0/1 regular-read
70 bits
38 bits
34 bits
38 bits
6 bits
2 bits
2 bits
(PWD = 1)
(PWD = 0)
(PWD = 1)
(PWD = 1)
(PWD = 0)
If any of these erroneous conditions were detected, the ATA5567 enters regular-read mode,
starting with block 1 of the page defined in the command sequence.
5.2
Errors Before or During Programming
If the command sequence was received successfully, the following error could still prevent
programming:
• The lock bit of the addressed block is set already
In case of a locked block, programming mode will not be entered. The ATA5567 reverts to
block-read mode, continuously transmitting the currently addressed block.
If the command sequence is validated and the addressed block is not write protected, the new
data will be programmed into the EEPROM memory. The new state of the block write protection
bit (lock bit) will be programmed at the same time accordingly.
Each programming cycle consists of 4 consecutive steps: erase block, erase verification
(data = 0 ), programming, write verification (corresponding data bits = 1).
• If a data verification error is detected after an executed data block programming, the tag will
stop modulation (modulation defeat) until a new command is transmitted.
14
ATA5567
4874F–RFID–07/08
ATA5567
Figure 5-1.
ATA5567 Functional Diagram
Power-on reset
AOR = 1
Setup modes
AOR mode
AOR = 0
Regular-read mode
Page 0
Page 0 or 1
addr = 1 to MAXBLK
Block-read mode
Gap
Start
gap
addr = current
Command mode
Gap
Modulation
defeat
Single gap
Page 1
OP(00)
Reset
to page 0
Direct access
OP(1p) 1)
Command decode
OP(11..)
OP(1p) 1)
Page 0
OP(10..)
OP(01)
Write
OP(1p) 1)
Test mode
if master key < > 6
Write
Number of bits
Password check
Lock bit check
Data verification failed
1)
Program and verify
Fail
data = old
Fail
data = old
Fail
data = old
Ok
data = new
p = page selector
6. ATA5567 in Extended Mode (X-mode)
In general, the block 0 setting of the master key (bits 1 to 4) to the value “6” or “9” together with
the X-mode bit will enable the extended mode functions.
• Master key = 9: Test mode access and extended mode are both enabled.
• Master key = 6: Any test mode access will be denied but the extended mode is still enabled.
Any other master key setting will prevent the activation of the ATA5567 extended mode options,
even when the X-mode bit is set.
15
4874F–RFID–07/08
6.1
Binary Bit-rate Generator
In extended mode the data rate is binary programmable to operate at any data rate between
RF/2 and RF/128 as given in the formula below.
Data rate = RF / (2n + 2)
6.2
OTP Functionality
If the OTP bit is set to “1”, all memory blocks are write protected and behave as if all lock bits are
set to 1. If the master key is set to “6” additionally, the ATA5567 mode of operation is locked forever (= OTP functionality).
If the master key is set to “9”, the test-mode access allows the re-configuration of the tag again.
Block 0 — Configuration Map in Extended Mode (X-mode)
0 0
Master Key
Note 1), 2)
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1
n5 n4 n3 n2 n1 n0
Data Bit Rate
RF/(2n+2)
Unlocked
Locked
Modulation
PSK
CF
Max
Block
0 0 RF/2
Direct
0 0 0 0 0
0 1 RF/4
PSK1
0 0 0 0 1
1 0 RF/8
PSK2
PSK3
0 0 0 1 0
0 0 0 1 1
1 1 Res
FSK1
0 0 1 0 0
FSK2
0 0 1 0 1
Manchester
0 1 0 0 0
POR delay
7 8
0 0
Fast Write
Inverse Data
5 6
PWD
3 4
0 1
SST-sequence Start Marker
0
1
1 2
1 0
AOR
OTP
Lock Bit
L
X-mode
Figure 6-1.
Bi-phase ('50) 1 0 0 0 1
Bi-phase ('57) 1 1 0 0 0
1) If Master Key = 6 and bit 15 is set, then test mode access is disabled and extended mode is active
2) If Master Key = 9 and bit 15 is set, then extended mode is enabled
Table 6-1.
ATA5567 Types of Modulation in Extended Mode
Mode
Direct Data Output Encoding
Inverse Data Output Encoding
FSK1
(1)
FSK/5-/8
0 = RF/5; 1 = RF/8
FSK/8-/5
0 = RF/8; 1 = RF/5
(= FSK1a)
FSK2
(1)
FSK/10-/8
0 = RF/10; 1 = RF/8
FSK/8-/10
0 = RF/8; 1 = RF/10
(= FSK2a)
(2)
PSK1
Phase change when input changes
Phase change when input changes
PSK2(2)
Phase change on bit clock if input high
Phase change on bit clock if input low
PSK3(2)
Phase change on rising edge of input
Phase change on falling edge of input
Manchester
0 = falling edge, 1 = rising edge on mid-bit
1 = falling edge, 0 = rising edge on mid-bit
Bi-phase 1 (’50)
“1” creates an additional mid-bit change
“0” creates an additional mid-bit change
Bi-phase 2 (’57)
“0” creates an additional mid-bit change
“1” creates an additional mid-bit change
NRZ
1 = damping on, 0 = damping off
0 = damping on, 1 = damping off
Notes:
1. A common multiple of bit rate and FSK frequencies is recommended.
2. In PSK mode the selected data rate has to be an integer multiple of the PSK sub-carrier frequency.
16
ATA5567
4874F–RFID–07/08
ATA5567
6.3
Sequence Start Marker
Figure 6-2.
ATA5567 Sequence Start Marker in Extended Mode
Sequence Start Marker
Block read mode
10
Block n
Regular read mode
10
Block 1
01
Block n
Block 2
10
Block n
01
Block n
MAXBLK
01
Block 1
Block 2
10
Block n
MAXBLK
01
10
The ATA5567 sequence start marker is a special damping pattern, which may be used to synchronize the reader. The sequence start marker consists of two bits (“01” or “10”) which are
inserted as a header before the first block to be transmitted if bit 29 in extended mode is set. At
the start of a new block sequence, the value of the two bits is inverted.
6.4
Inverse Data Output
The ATA5567 supports in its extended mode (X-mode) an inverse data output option. If inverse
data is enabled, the modulator as shown in Figure 6-3 works on inverted data (see Table 6-1 on
page 16). This function is supported for all basic types of encoding.
Figure 6-3.
Data Encoder for Inverse Data Output
PSK1
PSK2
PSK3
Intern out
data
D
Direct/NRZ
Sync
XOR
Data output
MUX
FSK1
Data clock
CLK
R
FSK2
Manchester
Biphase
Inverse data output
Modulator
17
4874F–RFID–07/08
6.5
Fast Write
In the optional fast write mode, the time between two gaps is nominally 12 field clocks for a “0”
and 27 field clocks for a “1”. When there is no gap for more than 32 field clocks after a previous
gap, the ATA5567 will exit the write mode. Please refer to Table 6-2 and Figure 4-3 on page 8.
Table 6-2.
Fast Write Data Decoding Schemes
Parameters
Start gap
Write gap
Write data in normal
mode
Write data in fast
mode
18
Remark
Symbol
Min.
Max.
Unit
–
Sgap
10
50
FC
Normal write mode
Wngap
8
30
FC
Fast write mode
Wfgap
8
20
FC
“0” data
d0
16
31
FC
“1” data
d1
48
63
FC
“0” data
d0
8
15
FC
“1” data
d1
24
31
FC
ATA5567
4874F–RFID–07/08
4874F–RFID–07/08
RF-field
Inverted modulator
signal
Manchester coded
Data stream
1
12
8 FC
8
9
8 FC
16 1
8
9
0
16
1
8
0
16 1
8
9
1
16
12
8
9
1
16 1
8
9
0
16
Figure 6-4.
Data rate =
16 field clocks (FC)
ATA5567
Example of Manchester Coding with Data Rate RF/16
19
20
RF-field
Inverted modulator
signal
Bi-phase coded
Data stream
1
12
8 FC
8
9
8 FC
16
Data rate =
16 field clocks (FC)
1
8 9
0
16
1
8
0
16
1
8
9
1
16
12
8
9
1
16
1
8 9
0
16
Figure 6-5.
Example of Bi-phase Coding with Data Rate RF/16
ATA5567
4874F–RFID–07/08
4874F–RFID–07/08
RF-field
f1 = RF/5
f0 = RF/8
Inverted modulator
signal
Data stream
1
1 5
1
8
0
1
8
0
1 5
1
1 5
1
1
8
0
Figure 6-6.
Data rate =
40 field clocks (FC)
ATA5567
Example: FSK1a Coding with Data Rate RF/40, Subcarrier f0 = RF/8, f1 = RF/5
21
22
RF-field
Subcarrier RF/2
Inverted modulator
signal
Data stream
1
12
8 FC
8 9
8 FC
16 1
Data rate =
16 field clocks (FC)
8
0
16 1
8
0
16 1
8
1
16 1
8
1
16 1
8
0
Figure 6-7.
Example of PSK1 Coding with Data Rate RF/16
ATA5567
4874F–RFID–07/08
4874F–RFID–07/08
RF-field
Subcarrier RF/2
Inverted
modulator signal
Data stream
1
12
8 FC
8 9
8 FC
16 1
8
0
16 1
8
0
16 1
8
1
16 1
8
1
16 1
8
0
Figure 6-8.
Data rate =
16 field clocks (FC)
ATA5567
Example of PSK2 Coding with Data Rate RF/16
23
24
RF-field
Inverted
modulator signal
Subcarrier RF/2
Data stream
1
12
8 FC
8 9
8 FC
16 1
Data rate =
16 field clocks (FC)
8
0
16 1
8
0
16 1
8
1
16 1
8
1
16 1
8
0
Figure 6-9.
Example of PSK3 Coding with Data Rate RF/16
ATA5567
4874F–RFID–07/08
ATA5567
7. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Value
Unit
Maximum DC current into Coil 1/Coil 2
Icoil
20
mA
Maximum AC current into Coil 1/Coil 2
f = 125 kHz
Icoil p
20
mA
Power dissipation (die)
(free-air condition, time of application: 1s)
Ptot
100
mW
Electrostatic discharge maximum to
MIL-Standard 883 C method 3015
Vmax
4000
V
Operating ambient temperature range
Tamb
–40 to +85
°C
Storage temperature range (data retention reduced)
Tstg
–40 to +150
°C
8. Electrical Characteristics
Tamb = +25°C; fcoil = 125 kHz; unless otherwise specified
No.
1
Parameters
2.3
Supply current
(without current consumed Read – full temperature
by the external LC tank
range
circuit)
Programming – full
temperature range
Coil voltage (AC supply)
Typ.
Max.
Unit
100
125
150
kHz
1.5
3
µA
T
2
4
µA
Q
25
40
µA
Q
3.6
4.0
V
Q
Vclamp
V
Q
IDD
Read mode and write
command(2)
3.2
Vcoil pp
Program EEPROM(2)
3.3
4.1
Start-up time
Vcoil pp = 6V
4.2
Start-up voltage ramp
Vcoil pp = 0 to 6V
Clamp voltage
10 mA current into
Coil 1/Coil 2
5
Min.
fRF
POR threshold
(50 mV hysteresis)
3.1
3.2
Symbol
Tamb = 25°C(1)
(see Figure 6-9 on page 24)
2.1
2.2
Test Conditions
RF frequency range
6
8
tstartup
2.5
tmax
Vclamp
17
Type*
Vclamp
V
Q
3
ms
Q
1
s
Q
23
V
T
*) Type means: T: directly or indirectly tested during production; Q: guaranteed based on initial product qualification data
Notes:
1. IDD measurement setup R = 100 kΩ; VCLK = Vcoil = 5V: EEPROM programmed to 00 ... 000 (erase all); chip in modulation
defeat. IDD = (VOUTmax – VCLK) / R
2. Current into Coil 1/Coil 2 is limited to 10 mA. The damping circuitry has the same structure as the e5550. The damping
characteristics are defined by the internally limited supply voltage (= minimum AC coil voltage)
3. Vmod measurement setup: R = 2.3 kΩ; VCLK = 3V; setup with modulation enabled (see Figure 8-1 on page 26).
4. Since EEPROM performance is influenced by assembly processes, Atmel confirms the parameters for DOW (tested die on
uncut wafer) delivery.
5. The tolerance of the on-chip resonance capacitor Cr is ±10% at 3σ over whole production. The capacitor tolerance is
±3% at 3σ on a wafer basis.
6. The tolerance of the micromodule resonance capacitor Cr is ±5% at 3σ over whole production.
25
4874F–RFID–07/08
8. Electrical Characteristics (Continued)
Tamb = +25°C; fcoil = 125 kHz; unless otherwise specified
No.
Parameters
Test Conditions
Symbol
V mod pp
Modulation parameters
Vcoilpp = 6V on test circuit
generator and modulation
ON(3)
6.1
6.2
6.3
Thermal stability
I mod pp
Min.
400
Vmod/Tamb
7
Programming time
From last command gap to
re-enter read mode
(64 + 648 internal clocks)
Tprog
5
8
Endurance
Erase all/Write all(4)
ncycle
100,000
(4)
9.1
9.2
Data retention
10
Resonance capacitor
11.1
Micromodule capacitor
11.2
parameters
11.3
Max.
Unit
Type*
4.2
4.8
V
T
600
µA
T
–6
mV/°C
Q
ms
T
Cycles
Q
5.7
6
tretention
10
(4)
Top = 150°C
tretention
96
hrs
T
Top = 250°C(4)
tretention
24
hrs
Q
Mask option(5)
Cr
70
78
86
pF
T
Capacitance tolerance Tamb
Cr
313.5
330
346.5
pF
T
Top = 55°C
9.3
Typ.
Temperature coefficient
20
50
Years
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
*) Type means: T: directly or indirectly tested during production; Q: guaranteed based on initial product qualification data
Notes:
1. IDD measurement setup R = 100 kΩ; VCLK = Vcoil = 5V: EEPROM programmed to 00 ... 000 (erase all); chip in modulation
defeat. IDD = (VOUTmax – VCLK) / R
2. Current into Coil 1/Coil 2 is limited to 10 mA. The damping circuitry has the same structure as the e5550. The damping
characteristics are defined by the internally limited supply voltage (= minimum AC coil voltage)
3. Vmod measurement setup: R = 2.3 kΩ; VCLK = 3V; setup with modulation enabled (see Figure 8-1 on page 26).
4. Since EEPROM performance is influenced by assembly processes, Atmel confirms the parameters for DOW (tested die on
uncut wafer) delivery.
5. The tolerance of the on-chip resonance capacitor Cr is ±10% at 3σ over whole production. The capacitor tolerance is
±3% at 3σ on a wafer basis.
6. The tolerance of the micromodule resonance capacitor Cr is ±5% at 3σ over whole production.
Figure 8-1.
Measurement Setup for IDD and Vmod
R
BAT68
Coil 1
750Ω
VOUTmax
750Ω
Coil 2
Substrate
BAT68
26
ATA5567
4874F–RFID–07/08
ATA5567
9. Ordering Information(1)
ATA5567
Note:
ab
-xxx
Package
- DDW
- Die on wafer, 6” unsawn wafer, thickness 300 µm
(on request)
- DDT 1
- Die in tray (waffle pack), thickness 300 µm
- DDB
- Die on foil, 6” sawn wafer with ring, thickness 150 µm
Figure 10-3 on page 30
11N
- 2 pads without on-chip capacitor
Figure 10-1 on page 28
14N
- 4 pads with on-chip 75 pF capacitor
Figure 10-2 on page 29
01N
- 2 pads without capacitor, damping during initialization
Figure 10-1 on page 28
1. For available order codes, contact your local Atmel Sales/Marketing office.
ATA556711
-xxx
Package
- TASY
ATA556715
-xxx
Drawing
- SO8 package (lead-free)
Package
- PAE
9.1
Drawing
Drawing
- NOA3 micromodule (lead-free)
Figure 10-5 on page 32 and
Figure 10-6 on page 33
Ordering Examples
ATA556714N-DDB
9.2
Figure 10-7 on page 34
Tested die on sawn 6” wafer on foil with ring, thickness 150 µm, 75 pF
on-chip capacitor, no damping during POR initialization; especially for
ISO 11784/785 and access control applications
Available Order Codes
ATA556711N-DDT 1
ATA556711N-DDB
ATA556714N-DDB
ATA556715-PAE
ATA556711-TASY
New order codes will be created by customer request if order quantities are over 250k pieces.
27
4874F–RFID–07/08
10. Package Information
Figure 10-1. 2-pad Layout
Dimensions in µm
124
134.5
94
994
149.5
934
ATA5567
87
72
C2
125
125
497
28
ATA5567
4874F–RFID–07/08
ATA5567
Figure 10-2. 4-pad Layout
Dimensions in µm
124
60
142
82
94
994
97
60
157
934
ATA5567
107
92
C2
100
100
497
29
4874F–RFID–07/08
Figure 10-3. 6” Sawn Wafer with Ring, Thickness 150 µm
59.5
63.6
30
˚
30 ˚
30
A
212
86.5
87.5
˚
A
∅1
94
.5
∅227.7
212
2.5:1
(∅194.5)
2.5
A-A
1.5x45˚
30
ATA5567
4874F–RFID–07/08
ATA5567
Figure 10-4. Wafer Map
Die: 0.894 × 0.864, Step: 0.994 × 0.934, N: 14 × 7, Frame Step: 13.916 × 15.878
> Shift-ASML = [0.3; –6.9]: 15539 dice, 87 shots (11 columns × 9 rows)
> Shift-CANON/ALARM/SEM = [0.3; –6.9] – W2 = [–13.152; 6.9] – W1 = [–6.648; 6.9]
10.1
Failed Die Identification
Every die on the wafer not passing Atmel’s test sequence is marked with ink.
The ink dot specification:
• Dot size: 200 µm
• Position: center of die
• Color: black
31
4874F–RFID–07/08
Figure 10-5. NOA3 Micromodule
9.5±0.03
4.75+0.02
4.625
1.42±0.05
0.03 A B
1.42±0.05
31.83
25.565
21.815
∅ 2±0.05
Note 1
15.915
12.165
6.265
B
technical drawings
according to DIN
specifications
2.515
0
1.585
A
Dimensions in mm
X
2.375
2.375
0.05 A
0.38-0.035
Note 3
5.15±0.03
Note 2
8-0.02
Note 4
0.03 B
8.1±0.03
Note 2
Note:
1. Reject hole by testing device
2. Punching cutline
recommendation for singulation
3. Total package thickness
exclusive punching burr
4. Module dimension
after electrical disconnection
R1.5±0.03
0.09-0.01
R0.2 max.
0.05 B
4.8±0.05
5.1±0.05
X5:1
R1.1±0.03 (4x)
Drawing-No.: 6.549-5035.01-4
Issue: 1; 28.04.06
Subcontractor: NedCard
Drawing refers to following types: Micromodule NOA-3
32
5.06±0.03
Note 4
ATA5567
4874F–RFID–07/08
ATA5567
Figure 10-6. Shipping Reel
41.4 to
max 43.0
0
˚ (3
x)
Ø 329.6
Ø 298.5
12
R1.14
Ø13
2.3
Ø171
Ø175
16.7
2
2.2
33
4874F–RFID–07/08
Figure 10-7. SO8 Package
Package: SO 8
Dimensions in mm
5±0.2
4.9±0.1
0.1+0.15
1.4
0.2
3.7±0.1
0.4
1.27
3.8±0.1
6±0.2
3.81
8
5
technical drawings
according to DIN
specifications
1
4
Drawing-No.: 6.541-5031.01-4
Issue: 1; 15.08.06
Figure 10-8. Pinning SO8
COIL2
NC
NC
NC
34
1
2
3
4
8
7
6
5
COIL1
NC
NC
NC
ATA5567
4874F–RFID–07/08
ATA5567
11. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
4874F-RFID-07/08
• Section 3.12 “Traceability Data Structure” on page 5 changed
• Section 6 “ATA5567 in Extended Mode (X-mode) on page 15 changed
• Section 9 “Ordering Information” on page 27 changed
4874E-RFID-10/07
• Put datasheet in a new template
• Section 9 “Ordering Information” on page 27 changed
• Old Figure 10-3 “Solder Bump on NiAu” replaced with new Figure 10-3
“6” Sawn Wafer with Ring, Thickness 150 µm”
35
4874F–RFID–07/08
Headquarters
International
Atmel Corporation
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Tel: 1(408) 441-0311
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Fax: (81) 3-3523-7581
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www.atmel.com/contacts
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www.atmel.com/literature
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4874F–RFID–07/08