Burr-Brown ADS1218Y250 8-channel, 24-bit analog-to-digital converter with flash memory Datasheet

ADS1218
ADS
121
8
SBAS187 – SEPTEMBER 2001
8-Channel, 24-Bit
ANALOG-TO-DIGITAL CONVERTER
with FLASH Memory
FEATURES
DESCRIPTION
● 24 BITS NO MISSING CODES
● 0.0015% INL
● 22 BITS EFFECTIVE RESOLUTION
(PGA = 1), 19 BITS (PGA = 128)
● 4K BYTES OF FLASH MEMORY
PROGRAMMABLE FROM 2.7V TO 5.25V
● PGA FROM 1 TO 128
● SINGLE CYCLE SETTLING MODE
● PROGRAMMABLE DATA OUTPUT RATES
UP TO 1kHz
● PRECISION ON-CHIP 1.25V/2.5V REFERENCE:
ACCURACY: 0.2%
DRIFT: 5ppm/°C
● EXTERNAL DIFFERENTIAL REFERENCE
OF 0.1V TO 2.5V
● ON-CHIP CALIBRATION
● PIN COMPATIBLE WITH ADS1216
● SPI™ COMPATIBLE
● 2.7V TO 5.25V
● < 1mW POWER CONSUMPTION
The ADS1218 is a precision, wide dynamic range, delta-sigma, Analog-toDigital (A/D) converter with 24-bit resolution and FLASH memory operating
from 2.7V to 5.25V supplies. The delta-sigma, A/D converter provides up to
24 bits of no missing code performance and effective resolution of 22 bits.
The eight input channels are multiplexed. Internal buffering can be selected
to provide a very high input impedance for direct connection to transducers
or low-level voltage signals. Burn out current sources are provided that allow
for the detection of an open or shorted sensor. An 8-bit Digital-to-Analog (D/
A) converter provides an offset correction with a range of 50% of the FSR
(Full-Scale Range).
The PGA (Programmable Gain Amplifier) provides selectable gains of 1 to
128 with an effective resolution of 19 bits at a gain of 128. The A/D
conversion is accomplished with a second-order delta-sigma modulator and
programmable sinc filter. The reference input is differential and can be used
for ratiometric conversion. The on-board current DACs (Digital-to-Analog
Converters) operate independently with the maximum current set by an
external resistor.
The serial interface is SPI compatible. Eight bits of digital I/O are also provided
that can be used for input or output. The ADS1218 is designed for high-resolution
measurement applications in smart transmitters, industrial process control, weight
scales, chromatography, and portable instrumentation.
AGND
APPLICATIONS
●
●
●
●
●
●
●
INDUSTRIAL PROCESS CONTROL
LIQUID /GAS CHROMATOGRAPHY
BLOOD ANALYSIS
SMART TRANSMITTERS
PORTABLE INSTRUMENTATION
WEIGHT SCALES
PRESSURE TRANSDUCERS
RDAC
AVDD
IDAC2
8-Bit
IDAC
IDAC1
8-Bit
IDAC
AVDD
2µA
VREFOUT
VRCAP
VREF+
VREF–
XIN
XOUT
Clock Generator
1.25V or
2.5V
Reference
Offset
DAC
AIN0
A = 1:128
AIN1
Registers
IN+
AIN2
AIN3
MUX
IN–
AIN4
BUF
+
PGA
AIN5
2nd-Order
Modulator
Programmable
Digital
Filter
Controller
RAM
4K Bytes
FLASH
WREN
AIN6
SPI is a registered trademark of Motorola.
AIN7
AINCOM
POL
2µA
Serial Interface
Digital I/O
Interface
AGND
DVDD
DGND
BUFEN
SCLK
DIN
DOUT
CS
D0
... D7
PDWN
DSYNC
RESET
DRDY
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
AVDD to AGND ...................................................................... –0.3V to +6V
DVDD to DGND ...................................................................... –0.3V to +6V
Input Current ............................................................... 100mA, Momentary
Input Current ................................................................. 10mA, Continuous
AIN ................................................................... GND –0.5V to AVDD + 0.5V
AVDD to DVDD ........................................................................... –6V to +6V
AGND to DGND ................................................................. –0.3V to +0.3V
Digital Input Voltage to GND .................................... –0.3V to DVDD + 0.3V
Digital Output Voltage to GND ................................. –0.3V to DVDD + 0.3V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –60°C to +100°C
Lead Temperature (soldering, 10s) .............................................. +300°C
This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation
procedures can cause damage.
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Texas Instruments
recommends that all integrated circuits be handled and stored using
appropriate ESD protection methods.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS1218Y/250
ADS1218Y/2K
Tape and Reel, 250
Tape and Reel, 2000
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
ADS1218Y
TQFP-48
PFB
–40°C to +85°C
ADS1218Y
"
"
"
"
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., / 2K indicates 2000 devices per reel). Ordering 2000 pieces
of “ADS1218Y/2K” will get a single 2000-piece Tape and Reel.
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer ON, RDAC = 150kΩ, fDATA = 10Hz,
VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
ADS1218
PARAMETER
ANALOG INPUT (AIN0 – AIN7, AINCOM)
Analog Input Range
Full-Scale Input Voltage Range
Differential Input Impedance
Input Current
Bandwidth
Fast Settling Filter
Sinc2 Filter
Sinc3 Filter
Programmable Gain Amplifier
Input Capacitance
Input Leakage Current
Burnout Current Sources
CONDITIONS
MIN
Buffer OFF
Buffer ON
(In+) – (In–), See Block Diagram
Buffer OFF
Buffer ON
AGND – 0.1
AGND + 0.05
–3dB
–3dB
–3dB
User Selectable Gain Ranges
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Non-Linearity
Offset Error(1)
Offset Drift(1)
Gain Error
Gain Error Drift(1)
Common-Mode Rejection
Normal-Mode Rejection
Output Noise
Power-Supply Rejection
2
MAX
UNITS
AVDD + 0.1
AVDD – 1.5
±VREF /PGA
5/PGA
0.5
V
V
V
MΩ
nA
0.469 • fDATA
0.318 • fDATA
0.262 • fDATA
Hz
Hz
Hz
1
Modulator OFF, T = 25°C
OFFSET DAC
Offset DAC Range
Offset DAC Monotonicity
Offset DAC Gain Error
Offset DAC Gain Error Drift
TYP
128
9
5
2
pF
pA
µA
±VREF /(2 • PGA)
V
Bits
%
ppm/°C
8
±10
1
24
sinc3
End Point Fit
Before Calibration
24
±0.0015
7.5
0.02
0.005
0.5
After Calibration
fCM =
fCM =
fCM =
fSIG =
fSIG =
at DC
60Hz, fDATA = 10Hz
50Hz, fDATA = 50Hz
60Hz, fDATA = 60Hz
50Hz, fDATA = 50Hz
60Hz, fDATA = 60Hz
at DC, dB = –20 log(∆VOUT /∆VDD)(2)
100
80
130
120
120
100
100
See Typical Characteristics
95
Bits
Bits
% of FS
ppm of FS
ppm of FS/°C
%
ppm/ °C
dB
dB
dB
dB
dB
dB
dB
ADS1218
SBAS187
ELECTRICAL CHARACTERISTICS: AVDD = 5V (Cont.)
All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer ON, RDAC = 150kΩ, fDATA =10Hz,
VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
ADS1218
PARAMETER
VOLTAGE REFERENCE INPUT
Reference Input Range
VREF
Common-Mode Rejection
Common-Mode Rejection
Bias Current(3)
ON-CHIP VOLTAGE REFERENCE
Output Voltage
Short-Circuit Current Source
Short-Circuit Current Sink
Short-Circuit Duration
Drift
Noise
Output Impedance
Startup Time
IDAC
Full-Scale Output Current
Maximum Short-Circuit Current Duration
Monotonicity
Compliance Voltage
Output Impedance
PSRR
Absolute Error
Absolute Drift
Mismatch Error
Mismatch Drift
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
Analog Current (IADC + IVREF + IDAC)
ADC Current (IADC)
VREF Current (IVREF)
IDAC Current (IDAC)
Digital Current
Power Dissipation
TEMPERATURE RANGE
Operating
Storage
CONDITIONS
MIN
REF IN+, REF IN–
VREF ≡ (REF IN+) – (REF IN–)
at DC
fVREFCM = 60Hz, fDATA = 60Hz
VREF = 2.5V
0
0.1
REF HI = 1 at 25°C
REF HI = 0
2.495
Sink or Source
BW = 0.1Hz to 100Hz
Sourcing 100µA
RDAC = 150kΩ, Range = 1
RDAC = 150kΩ, Range = 2
RDAC = 150kΩ, Range = 3
RDAC = 15kΩ, Range = 3
RDAC = 10kΩ
RDAC = 0Ω
RDAC = 150kΩ
2.5
120
120
1.3
2.50
1.25
8
50
Indefinite
5
10
3
50
MAX
UNITS
AVDD
2.6
V
V
dB
dB
µA
2.505
V
V
mA
µA
ppm/°C
µVp-p
Ω
µs
0.5
1
2
20
Indefinite
8
0
mA
mA
mA
mA
10
Minutes
AVDD – 1
Bits
V
see Typical Characteristics
400
5
75
0.25
15
VOUT = AVDD /2
Individual IDAC
Individual IDAC
Between IDACs, Same Range and Code
Between IDACs, Same Range and Code
AVDD
PDWN = 0, or SLEEP
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
PGA = 128, Buffer ON
TYP
4.75
ppm/V
%
ppm/°C
%
ppm/°C
5.25
V
nA
µA
µA
µA
µA
µA
µA
Excludes Load Current
1
175
500
250
900
250
480
Normal Mode, DVDD = 5V
SLEEP Mode, DVDD = 5V
Read Data Continuous Mode, DVDD = 5V
PDWN= LOW
180
150
230
1
275
µA
µA
µA
nA
PGA = 1, Buffer OFF, REFEN = 0,
IDACS OFF, DVDD = 5V
1.8
2.8
mW
+85
+100
°C
°C
–40
–60
275
750
350
1375
375
675
NOTES: (1) Calibration can minimize these errors. (2) ∆ VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.
ADS1218
SBAS187
3
ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer ON, RDAC = 75kΩ, fDATA=10Hz,
VREF ≡ (REF IN+) – (REF IN–) = +1.25V unless otherwise specified.
ADS1218
PARAMETER
ANALOG INPUT (AIN0 – AIN7, AINCOM)
Analog Input Range
Full-Scale Input Voltage Range
Input Impedance
Input Current
Bandwidth
Fast Settling Filter
Sinc2 Filter
Sinc3 Filter
Programmable Gain Amplifier
Input Capacitance
Input Leakage Current
Burnout Current Sources
CONDITIONS
MIN
Buffer OFF
Buffer ON
(In+) – (In–) See Block Diagram
Buffer OFF
Buffer ON
AGND – 0.1
AGND + 0.05
–3dB
–3dB
–3dB
User Selectable Gain Ranges
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Non-Linearity
Offset Error(1)
Offset Drift(1)
Gain Error
Gain Error Drift(1)
Common-Mode Rejection
Normal-Mode Rejection
Output Noise
Power-Supply Rejection
VOLTAGE REFERENCE INPUT
Reference Input Range
VREF
Common-Mode Rejection
Common-Mode Rejection
Bias Current(3)
ON-CHIP VOLTAGE REFERENCE
Output Voltage
Short-Circuit Current Source
Short-Circuit Current Sink
Short-Circuit Duration
Drift
Noise
Output Impedance
Startup Time
IDAC
Full-Scale Output Current
Maximum Short-Circuit Current Duration
Monotonicity
Compliance Voltage
Output Impedance
PSRR
Absolute Error
Absolute Drift
Mismatch Error
Mismatch Drift
4
MAX
UNITS
AVDD + 0.1
AVDD – 1.5
±VREF /PGA
5/ PGA
0.5
V
V
V
MΩ
nA
0.469 • fDATA
0.318 • fDATA
0.262 • fDATA
Hz
Hz
Hz
1
Modulator OFF, T = 25°C
OFFSET DAC
Offset DAC Range
Offset DAC Monotonicity
Offset DAC Gain Error
Offset DAC Gain Error Drift
TYP
128
9
5
2
pF
pA
µA
±VREF /(2 • PGA)
V
Bits
%
ppm/°C
8
±10
2
24
24
±0.0015
End Point Fit
Before Calibration
15
0.04
0.010
1.0
After Calibration
fCM =
fCM =
fCM =
fSIG =
fSIG =
at DC
60Hz, fDATA =
50Hz, fDATA =
60Hz, fDATA =
50Hz, fDATA =
60Hz, fDATA =
100
10Hz
50Hz
60Hz
50Hz
60Hz
at DC, dB = –20 log(∆VOUT /∆VDD)(2)
75
REF IN+, REF IN–
VREF ≡ (REF IN+) – (REF IN–)
at DC
fVREFCM = 60Hz, fDATA = 60Hz
VREF = 1.25V
0
0.1
REF HI = 0 at 25°C
1.245
BW = 0.1Hz to 100Hz
Sourcing 100µA
= 75kΩ, Range
= 75kΩ, Range
= 75kΩ, Range
= 15kΩ, Range
RDAC = 10kΩ
RDAC = 0Ω
RDAC = 75kΩ
=
=
=
=
1
2
3
3
VOUT = AVDD /2
Individual IDAC
Individual IDAC
Between IDACs, Same Range and Code
Between IDACs, Same Range and Code
dB
AVDD
1.25
V
V
dB
dB
µA
1.255
V
mA
µA
120
120
0.65
Sink or Source
RDAC
RDAC
RDAC
RDAC
130
120
120
100
100
see Typical Characteristics
90
1.25
3
50
Indefinite
5
10
3
50
ppm/°C
µVp-p
Ω
µs
0.5
1
2
20
Indefinite
mA
mA
mA
mA
10
8
0
AVDD – 1
see Typical Characteristics
600
5
75
0.25
15
Bits
Bits
% of FS
ppm of FS
ppm of FS/°C
%
ppm/°C
dB
dB
dB
dB
dB
dB
Minute
Bits
V
ppm/V
%
ppm/°C
%
ppm/°C
ADS1218
SBAS187
ELECTRICAL CHARACTERISTICS: AVDD = 3V (Cont.)
All specifications TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer ON, RDAC = 75kΩ, fDATA=10Hz,
VREF ≡ (REF IN+) – (REF IN–) = +1.25V unless otherwise specified.
ADS1218
PARAMETER
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
Analog Current (IADC + IVREF + IDAC)
ADC Current (IADC)
VREF Current (IVREF)
IDAC Current (IDAC)
Digital Current
Power Dissipation
CONDITIONS
MIN
AVDD
PDWN = 0, or SLEEP
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
PGA = 128, Buffer ON
2.7
1
160
450
230
850
250
480
90
75
113
1
0.8
Excludes Load Current
Normal Mode, DVDD = 3V
SLEEP Mode, DVDD = 3V
Read Data Continuous Mode, DVDD = 3V
PDWN = 0
PGA = 1, Buffer OFF, REFEN = 0,
IDACS OFF, DVDD = 3V
TEMPERATURE RANGE
Operating
Storage
TYP
–40
–60
MAX
UNITS
3.3
1.4
V
nA
µA
µA
µA
µA
µA
µA
µA
µA
µA
nA
mW
+85
+100
°C
°C
250
700
325
1325
375
675
200
NOTES: (1) Calibration can minimize these errors. (2) ∆ VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.
DIGITAL CHARACTERISTICS: TMIN to TMAX, DVDD = 2.7V to 5.25V
PARAMETER
Digital Input/Output
Logic Family
Logic Level: VIH
VIL
VOH
VOL
Input Leakage: IIH
IIL
Master Clock Rate: fOSC(1)
Master Clock Period: tOSC(1)
CONDITIONS
MIN
TYP
MAX
UNITS
DVDD
0.2 • DVDD
V
V
V
V
µA
µA
MHz
ns
CMOS
IOH = 1mA
IOL = 1mA
VI = DVDD
VI = 0
1/fOSC
0.8 • DVDD
DGND
DVDD – 0.4
DGND
DGND + 0.4
10
–10
1
200
5
1000
NOTE: (1) For FLASH E/W operations, the SPEED bit in the SETUP register must be set appropriately and the device operating frequency must be:
2.3MHz < FOSC < 4.13MHz.
FLASH CHARACTERISTICS: TMIN to TMAX, DVDD = 2.7V to 5.25V, unless otherwise specified.
PARAMETER
Operating Current
Page Write
Page Read
Endurance
Data Retention
DVDD for Erase/Write
ADS1218
SBAS187
CONDITIONS
MIN
DVDD = 5V, During WR2F Command
DVDD = 3V, During WR2F Command
DVDD = 5V, During RF2R Command
DVDD = 3V, During RF2R Command
at 25°C
TYP
MAX
UNITS
5.25
mA
mA
mA
mA
E/W Cycles
Years
V
6.5
3.75
4.0
1.2
100,000
100
2.7
5
DOUT
DIN
SCLK
CS
DRDY
DVDD
DGND
DSYNC
POL
PDWN
XOUT
XIN
PIN CONFIGURATION (TQFP-48)
36
35
34
33
32
31
30
29
28
27
26
25
D0 37
24 RESET
D1 38
23 BUFEN
D2 39
22 DGND
D3 40
21 DGND
D4 41
20 DGND
D5 42
19 DGND
ADS1218
D6 43
18 WREN
D7 44
17 RDAC
5
6
7
8
9
10
11
12
AGND
4
AINCOM
3
AIN7
2
AIN4
1
AIN6
13 AVDD
AIN5
VREF– 48
AIN3
14 VRCAP
AIN2
VREF+ 47
AIN1
15 IDAC1
AIN0
VREFOUT 46
AGND
16 IDAC2
AVDD
AGND 45
PIN DESCRIPTIONS
6
PIN
NUMBER
NAME
DESCRIPTION
Analog Power Supply
24
RESET
Active LOW, resets the entire chip.
AGND
Analog Ground
25
XIN
AIN0
Analog Input 0
26
XOUT
Clock Output, used with crystal or resonator.
4
AIN1
Analog Input 1
27
PDWN
5
AIN2
Analog Input 2
6
AIN3
Analog Input 3
Active LOW. Power Down. The power down
function shuts down the analog and digital
circuits.
7
AIN4
Analog Input 4
8
AIN5
Analog Input 5
9
AIN6
Analog Input 6
10
AIN7
Analog Input 7
PIN
NUMBER
NAME
DESCRIPTION
1
AVDD
2
3
11
AINCOM
Analog Input Common
12
AGND
Analog Ground
13
AVDD
Analog Power Supply
14
VRCAP
VREF Bypass CAP
15
IDAC1
Current DAC1 Output
16
IDAC2
Current DAC2 Output
17
RDAC
Current DAC Resistor
18
WREN
19-22
DGND
Active High, FLASH Write Enable
Digital Ground
23
BUFEN
Buffer Enable
Clock Input
28
POL
29
DSYNC
Serial Clock Polarity
Active LOW, Synchronization Control
30
DGND
Digital Ground
31
DVDD
Digital Power Supply
32
DRDY
Active LOW, Data Ready
33
CS
34
SCLK
35
DIN
36
DOUT
37-44
D0-D7
Active LOW, Chip Select
Serial Clock, Schmitt Trigger
Serial Data Input, Schmitt Trigger
Serial Data Output
Digital I/O 0-7
45
AGND
46
VREFOUT
Analog Ground
47
VREF+
Positive Differential Reference Input
48
VREF–
Negative Differential Reference Input
Voltage Reference Output
ADS1218
SBAS187
TIMING SPECIFICATIONS
CS
t3
t1
t2
t10
SCLK
(POL = 0)
SCLK
(POL = 1)
t4
DIN
MSB
t2
t6
t5
t11
LSB
(Command or Command and Data)
DOUT
t7
t8
t9
MSB(1)
LSB(1)
NOTE: (1) Bit Order = 0.
ADS1218
Resets On
Falling Edge
SCLK Reset Waveform
t13
t13
SCLK
t12
t14
t16
t15
RESET, DSYNC, PDWN
DDR Update Timing
t17
DRDY
TIMING SPECIFICATION TABLES
SPEC
DESCRIPTION
t1
SCLK Period
t2
t3
t4
t5
t6
SCLK Pulse Width, HIGH and LOW
CS LOW to first SCLK Edge; Setup Time
DIN Valid to SCLK Edge; Setup Time
Valid DIN to SCLK Edge; Hold Time
Delay between last SCLK edge for DIN and first SCLK
edge for DOUT:
RDATA, RDATAC, RREG, WREG, RRAM, WRAM
CSREG, CSRAMX, CSRAM
CHKARAM, CHKARAMX
SCLK Edge to Valid New DOUT
SCLK Edge to DOUT, Hold Time
Last SCLK Edge to DOUT Tri-State
NOTE: DOUT goes tri-state immediately when CS goes HIGH.
CS LOW time after final SCLK edge
Final SCLK edge of one op code until first edge SCLK
of next command:
RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX,
CSRAM, CSARAM, CSREG, SLEEP,
RDATA, RDATAC, STOPC
DSYNC, RESET
CSFL
CREG, CRAM
RF2R
CREGA
WR2F
MIN
MAX
4
3
t7 (1)
t8 (1)
t9
t10
t11
t12
t13
t14
t15
t16
t17
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL
SELFCAL
RESET (Command, SCLK, or Pin)
SCLK Reset, First HIGH Pulse
SCLK Reset, LOW Pulse
SCLK Reset, Second HIGH Pulse
SCLK Reset, Third HIGH Pulse
Pulse Width
DOR Data Not Valid
200
0
50
50
50
200
1100
50
0
6
10
UNITS
tOSC Periods
DRDY Periods
ns
ns
ns
ns
tOSC Periods
tOSC Periods
tOSC Periods
ns
ns
tOSC Periods
0
ns
4
16
33,000
220
1090
1600
76,850 (SPEED = 0)
101,050 (SPEED = 1)
7
14
16
300
5
550
1050
4
4
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
DRDY Periods
DRDY Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
4
500
750
1250
NOTE: (1) Load = 20pF 10kΩ to DGND.
ADS1218
SBAS187
7
TYPICAL CHARACTERISTICS
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
22
PGA1
PGA2
PGA4
PGA1 PGA2
PGA8
20
20
19
19
18
PGA16
PGA32
PGA64
PGA128
17
16
14
18
17
16
PGA64
PGA128
Sinc3 Filter, Buffer ON
13
12
12
0
500
1000
1500
Decimation Ratio =
0
2000
500
fMOD
1000
Decimation Ratio =
fDATA
1500
fMOD
2000
fDATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
22
PGA1
21
PGA2
PGA4
PGA1 PGA2
PGA8
20
20
19
19
18
17
PGA16
PGA64
PGA32
PGA4
PGA128
16
18
17
16
15
15
14
Sinc3 Filter,
13
PGA32
14
VREF = 1.25V, Buffer OFF
1000
Decimation Ratio =
1500
fMOD
0
2000
PGA128
Sinc3 Filter, VREF = 1.25V, Buffer ON
12
500
PGA64
PGA16
13
12
0
PGA8
21
ENOB (rms)
ENOB (rms)
PGA32
PGA16
14
Sinc3 Filter
13
500
1000
Decimation Ratio =
fDATA
1500
fMOD
2000
fDATA
FAST SETTLING FILTER
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
22
PGA1
21
PGA2
PGA4
PGA8
21
20
20
19
19
ENOB (rms)
ENOB (rms)
PGA8
15
15
18
17
PGA32
16
PGA64
PGA128
PGA16
18
17
16
15
15
14
Sinc2 Filter
13
14
Fast Settling Filter
13
12
12
0
500
1000
Decimation Ratio =
8
PGA4
21
ENOB (rms)
ENOB (rms)
21
1500
fMOD
fDATA
2000
0
500
1000
Decimation Ratio =
1500
2000
fMOD
fDATA
ADS1218
SBAS187
TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
CMRR vs FREQUENCY
NOISE vs INPUT SIGNAL
0.8
0.6
0.5
CMRR (dB)
Noise (rms, ppm of FS)
0.7
0.4
0.3
0.2
0.1
0
–2.5
–1.5
–0.5
0.5
1.5
130
120
110
100
90
80
70
60
50
40
30
20
10
0
2.5
1
10
100
VIN (V)
120
110
100
90
80
70
60
50
40
30
20
10
0
100k
50
PGA16
PGA1
0
Offset (ppm of FS)
PSRR (dB)
10k
OFFSET vs TEMPERATURE
PSRR vs FREQUENCY
–50
PGA64
–100
PGA128
–150
–200
1
10
100
1k
10k
–50
100k
–30
–10
10
30
50
70
90
Temperature (°C)
Frequency of Power Supply (Hz)
GAIN vs TEMPERATURE
INTEGRAL NON-LINEARITY vs INPUT SIGNAL
1.00010
10
8
1.00006
–40°C
6
1.00002
INL (ppm of FS)
Gain (Normalized)
1k
Frequency of CM Signal (Hz)
0.99998
0.99994
4
+85°C
2
0
–2
–4
+25°C
–6
0.99990
–8
0.99986
–50
–30
–10
10
30
Temperature (°C)
ADS1218
SBAS187
50
70
90
–10
–2.5
–2
–1.5
–1
–0.5
0
0.5
1
1.5
2
2.5
VIN (V)
9
TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
CURRENT vs TEMPERATURE
ADC CURRENT vs PGA
250
900
IDIGITAL
Buffer = OFF
700
IANALOG
600
150
IADC (µA)
Current (µA)
200
AVDD = 5V, Buffer = ON
800
IANALOG
IDIGITAL
100
500
AVDD = 3V, Buffer = ON
400
Buffer = OFF
300
200
50
100
0
0
–50
–30
–10
10
30
50
70
90
0
1
2
Temperature (°C)
8
16
32
64
128
PGA Setting
DIGITAL CURRENT
HISTOGRAM OF OUTPUT DATA
4500
SPEED = 0
350
SLEEP
fOSC = 4.91MHz
300
Normal
fOSC = 4.91MHz
4000
Number of Occurrences
400
Current (µA)
4
Normal
fOSC = 2.45MHz
250
200
150
100
Power
Down
50
SLEEP
fOSC = 2.45MHz
3500
3000
2500
2000
1500
1000
500
0
0
3.0
4.0
–2
5.0
–1.5
–1
–0.5
0
0.5
1
1.5
2
ppm of FS
VDD (V)
OFFSET DAC - OFFSET vs TEMPERATURE
VREFOUT vs LOAD CURRENT
200
2.55
170
Offset (ppm of FSR)
VREFOUT (V)
140
2.50
110
80
50
20
–10
–40
–70
2.45
–0.5
–100
0
0.5
1.0
1.5
VREFOUT Current Load (mA)
10
2.0
2.5
–50
–30
–10
10
30
50
70
90
Temperature (°C)
ADS1218
SBAS187
TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
IDAC ROUT vs VOUT
OFFSET DAC - GAIN vs TEMPERATURE
1.00020
1.000
1.00016
+85°C
1.000
1.00008
IOUT (Normalized)
Normalized Gain
1.00012
1.00004
1.00000
0.99996
0.99992
0.99988
+25°C
0.999
0.999
0.99984
–40°C
0.99980
0.99976
0.998
–50
–30
–10
10
30
50
70
90
0
1
2
Temperature (°C)
3
4
5
VDD – VOUT (V)
IDAC MATCHING vs TEMPERATURE
IDAC NORMALIZED vs TEMPERATURE
3000
1.01
2000
1000
IDAC Match (ppm)
IOUT (Normalized)
1.005
1
0.995
0
–1000
–2000
–3000
–4000
0.99
–5000
–6000
0.985
–30
–10
10
30
50
70
–50
90
–30
–10
10
30
50
70
Temperature (°C)
Temperature (°C)
IDAC DIFFERENTIAL NON-LINEARITY
RANGE = 1, RDAC = 150kΩ, VREF = 2.5V
IDAC INTEGRAL NON-LINEARITY
RANGE = 1, RDAC = 150kΩ, VREF = 2.5V
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
INL (LSB)
DNL (LSB)
–50
0
–0.1
0.1
0
–0.1
–0.2
–0.2
–0.3
–0.3
–0.4
–0.4
–0.5
90
–0.5
0
32
64
96
128
160
IDAC Code
ADS1218
SBAS187
192
224
255
0
32
64
96
128
160
192
224
255
IDAC Code
11
OVERVIEW
BURNOUT CURRENT SOURCES
INPUT MULTIPLEXER
The input multiplexer provides for any combination of
differential inputs to be selected on any of the input channels, as shown in Figure 1. For example, if channel 1 is
selected as the positive differential input channel, any other
channel can be selected as the negative differential input
channel. With this method, it is possible to have up to eight
fully differential input channels.
In addition, current sources are supplied that will source or
sink current to detect open or short circuits on the input pins.
INPUT BUFFER
The input impedance of the ADS1218 without the buffer
is 5MΩ/PGA. With the buffer enabled, the input voltage range
is reduced and the analog power-supply current is higher. The
buffer is controlled by ANDing the state of the BUFEN pin
with the state of the BUFFER bit in the ACR register.
IDAC1 AND IDAC2
AIN0
AIN1
When the Burnout bit is set in the ACR configuration register,
two current sources are enabled. The current source on the
positive input channel sources approximately 2µA of current.
The current source on the negative input channel sinks approximately 2µA. This allows for the detection of an open
circuit (full-scale reading) or short circuit (0V differential
reading) on the selected input differential pair.
AVDD
Burnout Current Source On
AIN2
AIN3
AIN4
The ADS1218 has two 8-bit current output DACs that can be
controlled independently. The output current is set with
RDAC, the range select bits in the ACR register, and the 8-bit
digital value in the IDAC register. The output current
= VREF /(8 • RDAC)(2RANGE–1)(DAC CODE). With VREFOUT
= 2.5V and RDAC = 150kΩ to AGND the full-scale output
can be selected to be 0.5, 1, or 2mA. The compliance voltage
range is 0 to within 1V of AVDD. When the internal voltage
reference of the ADS1218 is used, it is the reference for the
IDAC. An external reference may be used for the IDACs by
disabling the internal reference and tying the external reference input to the VREFOUT pin.
AIN5
PGA
Burnout Current Source On
AIN6
AGND
IDAC1
AIN7
AINCOM
FIGURE 1. Input Multiplexer Configuration.
TEMPERATURE SENSOR
An on-chip diode provides temperature sensing capability.
When the configuration register for the input MUX is set to
all 1s, the diode is connected to the input of the A/D
converter. All other channels are open. The anode of the
diode is connected to the positive input of the A/D converter,
and the cathode of the diode is connected to negative input
of the A/D converter. The output of IDAC1 is connected to
the anode to bias the diode and the cathode of the diode is
also connected to ground to complete the circuit.
In this mode, the output of IDAC1 is also connected to the
output pin, so some current may flow into an external load
from IDAC1, rather than the diode.
12
The Programmable Gain Amplifier (PGA) can be set to gains
of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can actually
improve the effective resolution of the A/D converter. For
instance, with a PGA of 1 on a 5V full-scale range, the A/D
converter can resolve to 1µV. With a PGA of 128, on a 40mV
full-scale range, the A/D converter can resolve to 75nV. With
a PGA of 1 on a 5V full-scale range, it would require a 26-bit
A/D converter to resolve 75nV.
PGA OFFSET DAC
The input to the PGA can be shifted by half the full-scale input
range of the PGA by using the ODAC register. The ODAC
(Offset DAC) register is an 8-bit value; the MSB is the sign
and the seven LSBs provide the magnitude of the offset. Using
the ODAC register does not reduce the performance of the
A/D converter.
MODULATOR
The modulator is a single-loop second-order system. The
modulator runs at a clock speed (fMOD) that is derived from
the external clock (fOSC). The frequency division is determined by the SPEED bit in the SETUP register.
SPEED BIT
fMOD
0
fOSC / 128
1
fOSC / 256
ADS1218
SBAS187
The offset and gain errors in the ADS1218, or the complete
system, can be reduced with calibration. Internal calibration of
the ADS1218 is called self calibration. This is handled with
three commands. One command does both offset and gain
calibration. There is also a gain calibration command and an
offset calibration command. Each calibration process takes
seven tDATA periods to complete. Therefore, it takes 14 tDATA
periods to complete both an offset and gain calibration.
For system calibration, the appropriate signal must be
applied to the inputs. The system offset command requires a
“zero” differential input signal. It then computes an offset that
will nullify offset in the system. The system gain command
requires a positive “full-scale” differential input signal. It then
computes a value to nullify gain errors in the system. Each of
these calibrations will take seven tDATA periods to complete.
settling filter for the next two conversions, the first of which
should be discarded. It will then use the sinc2 followed by the
sinc3 filter to improve noise performance. This combines the
low-noise advantage of the sinc3 filter with the quick response
of the fast settling time filter. The frequency response of each
filter is shown in Figure 3.
SINC3 FILTER RESPONSE
(–3dB = 0.262 • fDATA = 15.76Hz)
0
–20
–40
Gain (dB)
CALIBRATION
–60
–80
Calibration should be performed after power on, a change in
temperature, a change in decimation ratio, or a change in the
PGA. Calibration will remove the offset in the ODAC register.
Therefore, changes to the ODAC register must be done after
calibration.
–100
–120
0
30
60
90
120
150 180
210 240 270 300
Frequency (Hz)
At the completion of calibration, the DRDY signal will go
LOW to indicate that calibration is complete and valid data is
available.
SINC2 FILTER RESPONSE
(–3dB = 0.318 • fDATA = 19.11Hz)
0
DIGITAL FILTER
–20
–40
Gain (dB)
The Digital Filter can use either the fast settling, sinc2, or sinc3
filter, as shown in Figure 2. In addition, the Auto mode
changes the sinc filter after the input channel or PGA is
changed. When switching to a new channel, it will use the fast
–60
–80
Adjustable Digital Filter
–100
–120
Sinc3
0
30
60
90
120
150 180
210 240 270 300
Frequency (Hz)
Modulator
Output
Sinc2
Data Out
FAST SETTLING FILTER RESPONSE
(–3dB = 0.469 • fDATA = 28.125Hz)
0
Fast Settling
–20
FILTER SETTLING TIME
FILTER
Sinc3
Sinc2
Fast
3(1)
2(1)
1(1)
Gain (dB)
–40
SETTLING TIME
(Conversion Cycles)
–60
–80
NOTE: (1) With Synchronized Channel Changes.
–100
AUTO MODE FILTER SELECTION
–120
CONVERSION CYCLE
0
1
2
3
4+
Discard
Fast
Sinc2
Sinc3
FIGURE 2. Filter Step Responses.
ADS1218
SBAS187
30
60
90
120
150 180
210 240 270 300
Frequency (Hz)
NOTE: fDATA = 60Hz.
FIGURE 3. Filter Frequency Responses.
13
VOLTAGE REFERENCE
DIGITAL I/O INTERFACE
The voltage reference used for the ADS1218 can either be
internal or external. The power-up configuration for the
voltage reference is 2.5V internal. The selection for the
voltage reference is made through the status configuration
register.
The ADS1218 has eight pins dedicated for digital I/O. The
default power-up condition for the digital I/O pins are as
inputs. All of the digital I/O pins are individually configurable
as inputs or outputs. They are configured through the DIR
control register. The DIR register defines whether the pin is an
input or output, and the DIO register defines the state of the
digital output. When the digital I/O are configured as inputs,
DIO is used to read the state of the pin.
The internal voltage reference is selectable as either 1.25V
or 2.5V (AVDD = 5V only). The VREFOUT pin should have a
0.1µF capacitor to AGND.
The external voltage reference is differential and is represented by the voltage difference between the pins: +VREF
and –VREF. The absolute voltage on either pin (+VREF and
–VREF) can range from AGND to AVDD, however, the
differential voltage must not exceed 2.5V. The differential
voltage reference provides easy means of performing
ratiometric measurement.
VRCAP PIN
This pin provides a bypass cap for noise filtering on internal
VREF circuitry only. The recommended capacitor is a 0.001µF
ceramic cap. If an external VREF is used, this pin can be left
unconnected.
SERIAL INTERFACE
The serial interface is standard four-wire SPI compatible (DIN,
DOUT, SCLK, and CS). The ADS1218 also offers the flexibility to select the polarity of the serial clock through the POL
pin. The serial interface can be clocked up to fOSC/4. If CS
goes HIGH, the serial interface is reset. When CS goes LOW,
a new command is expected.
The serial interface operates independently of DRDY. DRDY
is used to indicate availability of data in the DOR. In order to
ensure the validity of the data being read, DOR timing
requirements must be met.
DSYNC OPERATION
CLOCK GENERATOR
The clock source for the ADS1218 can be provided from a
crystal, ceramic resonator, oscillator, or external clock. When
the clock source is a crystal or ceramic resonator, external
capacitors must be provided to ensure start-up and a stable
clock frequency. This is shown in Figure 4 and Table I.
C1
Crystal
or
Ceramic Resonator
C2
XIN
XOUT
DSYNC is used to provide for synchronization of the A/D
conversion with an external event. Synchronization can be
achieved either through the DSYNC pin or the DSYNC
command. When the DSYNC pin is used, the filter counter
is reset on the falling edge of DSYNC. The modulator is held
in reset until DSYNC is taken HIGH. Synchronization
occurs on the next rising edge of the system clock after
DSYNC is taken HIGH.
When the DSYNC command is sent, the filter counter is
reset after the last SCLK on the DSYNC command. The
modulator is held in RESET until the next edge of SCLK is
detected. Synchronization occurs on the next rising edge of
the system clock after the first SCLK after the DSYNC
command.
POWER-UP—SUPPLY VOLTAGE RAMP RATE
FIGURE 4. Crystal or Ceramic Resonator Connection.
CLOCK
SOURCE
FREQUENCY
C1
C2
PART
NUMBER
Crystal
2.4576
0-20pF
0-20pF
ECS, ECSD 2.45 - 32
Crystal
4.9152
0-20pF
0-20pF
ECS, ECSL 4.91
Crystal
4.9152
0-20pF
0-20pF
ECS, ECSD 4.91
Crystal
4.9152
0-20pF
0-20pF
CTS, MP 042 4M9182
TABLE I. Typical Clock Sources.
14
The power-on reset circuitry was designed to accommodate
digital supply ramp rates as slow as 1V/10ms. To ensure
proper operation, the power supply should ramp monotonically. The POR issues the RESET command as described
below.
RESET
There are three methods of reset. The RESET pin, the
RESET command, and the SCLK Reset pattern. They all
perform the same function. After a reset, the FLASH data
values from Page 0 are loaded into RAM, subsequently data
values from Bank 0 of RAM are loaded into the configuration registers.
ADS1218
SBAS187
MEMORY
Three types of memory are used on the ADS1218: registers,
RAM, and FLASH. 16 registers directly control the various
functions (PGA, DAC value, Decimation Ratio, etc.) and can
be directly read or written to. Collectively, the registers contain
all the information needed to configure the part, such as data
format, mux settings, calibration settings, decimation ratio, etc.
Additional registers, such as conversion data, are accessed
through dedicated instructions.
basis. Also, the RAM can be directly read or written through
the serial interface on power-up. The banks allow separate
storage of settings for each input.
Configuration
Register Bank
16 bytes
SETUP
MUX
ACR
IDAC1
IDAC2
ODAC
DIO
DIR
DEC0
M/DEC1
OCR0
OCR1
OCR2
FSR0
FSR1
FSR2
The on-chip FLASH can be used to store non-volatile data. The
FLASH data is separate from the configuration registers and
therefore can be used for any purpose, in addition to device
configuration. The FLASH page data is read and written in 128
byte blocks through the RAM banks, i.e. all RAM banks map
to a single page of FLASH, as shown in Figure 5.
RAM
128 Bytes
FLASH
4k Bytes
Bank 0
16 bytes
Bank 2
16 bytes
REGISTER BANK TOPOLOGY
The operation of the device is set up through individual
registers. The set of the 16 registers required to configure the
device is referred to as a Register Bank, as shown in Figure 5.
RAM
Reads and Writes to Registers and RAM occur on a byte
basis. However, copies between registers and RAM occurs
on a bank basis. The RAM is independent of the Registers,
i.e.: the RAM can be used as general-purpose RAM.
Page 0
128 bytes
Bank 7
16 bytes
The ADS1218 supports any combination of eight analog
inputs. With this flexibility, the device could easily support
eight unique configurations—one per input channel. In order
to facilitate this type of usage, eight separate register banks are
available. Therefore, each configuration could be written once
and recalled as needed without having to serially retransmit all
the configuration data. Checksum commands are also included, which can be used to verify the integrity of RAM.
The RAM provides eight “banks”, with a bank consisting of
16 bytes. The total size of the RAM is 128 bytes. Copies
between the registers and RAM are performed on a bank
ADDRESS
REGISTER
BIT 7
BIT 6
Page 31
128 bytes
FIGURE 5. Memory Organization.
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00H
SETUP
ID
ID
ID
SPEED
REF EN
REF HI
BUF EN
BIT ORDER
01H
MUX
PSEL3
PSEL2
PSEL1
PSEL0
NSEL3
NSEL2
NSEL1
NSEL0
02H
ACR
BOCS
IDAC2R1
IDAC2R0
IDAC1R1
IDAC1R0
PGA2
PGA1
PGA0
03H
IDAC1
IDAC1_7
IDAC1_6
IDAC1_5
IDAC1_4
IDAC1_3
IDAC1_2
IDAC1_1
IDAC1_0
04H
IDAC2
IDAC2_7
IDAC2_6
IDAC2_5
IDAC2_4
IDAC2_3
IDAC2_2
IDAC2_1
IDAC2_0
05H
ODAC
SIGN
OSET_6
OSET_5
OSET_4
OSET_3
OSET_2
OSET_1
OSET_0
06H
DIO
DIO_7
DIO_6
DIO_5
DIO_4
DIO_3
DIO_2
DIO_1
DIO_0
07H
DIR
DIR_7
DIR_6
DIR_5
DIR_4
DIR_3
DIR_2
DIR_1
DIR_0
08H
DEC0
DEC07
DEC06
DEC05
DEC04
DEC03
DEC02
DEC01
DEC00
09H
M/DEC1
DRDY
U/B
SMODE1
SMODE0
WREN
DEC10
DEC09
DEC08
0AH
OCR0
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
0BH
OCR1
OCR15
OCR14
OCR13
OCR12
OCR11
OCR10
OCR09
OCR08
0CH
OCR2
OCR23
OCR22
OCR21
OCR20
OCR19
OCR18
OCR17
OCR16
0DH
FSR0
FSR07
FSR06
FSR05
FSR04
FSR03
FSR02
FSR01
FSR00
0EH
FSR1
FSR15
FSR14
FSR13
FSR12
FSR11
FSR10
FSR09
FSR08
0FH
FSR2
FSR23
FSR22
FSR21
FSR20
FSR19
FSR18
FSR17
FSR16
TABLE II. Registers.
ADS1218
SBAS187
15
The RAM address space is linear, therefore accessing RAM
is done using an auto-incrementing pointer. Access to RAM
in the entire memory map can be done consecutively without
having to address each bank individually. For example, if
you were currently accessing bank 0 at offset 0xF (the last
location of bank 0), the next access would be bank 1 and
offset 0x0. Any access after bank 7 and offset 0xF will wrap
around to bank 0 and Offset 0x0.
Although the Register Bank memory is linear, the concept of
addressing the device can also be thought of in terms of bank
and offset addressing. Looking at linear and bank addressing
syntax, we have the following comparison: in the linear
memory map, the address 0x14 is equivalent to bank 1 and
offset 0x4. Simply stated, the most significant four bits
represent the bank, and the least significant four bits represent the offset. The offset is equivalent to the register
address for that bank of memory.
FLASH
Reads and Writes to FLASH occur on a Page basis.
Therefore, the entire contents of RAM is used for both
Read and Write operations. The FLASH is independent of
the Registers, i.e., the FLASH can be used as generalpurpose FLASH.
Upon power-up or reset, the contents of FLASH Page 0 are
loaded into RAM subsequently the contents of RAM Bank
0 are loaded into the configuration register. Therefore, the
user can customize the power-up configuration for the device. Care should be taken to ensure that data for FLASH
Page 0 is written correctly, in order to prevent unexpected
operation upon power-up.
16
The ADS1218 supports any combination of eight analog
inputs and the FLASH memory supports up to 32 unique Page
configurations. With this flexibility, the device could support
32 unique configurations for each of the eight analog input
channels. For instance, the on-chip temperature sensor could
be used to monitor temperature then different calibration
coefficients could be recalled for each of the eight analog
input channels based on the change in temperature. This
would enable the user to recall calibration coefficients for
every 4°C change in temperature over the industrial temperature range which could be used to correct for drift errors.
Checksum commands are also included, which can be used to
verify the integrity of FLASH.
The following two commands can be used to manipulate the
FLASH. First, the contents of FLASH can be written to with
the WR2F (write RAM to FLASH) command. This command first erases the designated FLASH page and then
writes the entire content of RAM (all banks) into the designated FLASH page. Second, the contents of FLASH can be
read with the RF2R (read FLASH to RAM) command. This
command reads the designated FLASH page into the entire
contents of RAM (all banks). In order to ensure maximum
endurance and data retention, the SPEED bit in the SETUP
register must be set for the appropriate fOSC frequency.
Writing to or erasing FLASH can be disabled either through
the WREN pin or the WREN register bit. If the WREN pin
is LOW OR the WREN bit is cleared, then the WR2F
command has no effect. This protects the integrity of the
FLASH data from being inadvertently corrupted.
Accessing the FLASH data either through read, write, or
erase may effect the accuracy of the conversion result.
Therefore, the conversion result should be discarded when
accesses to FLASH are done.
ADS1218
SBAS187
DETAILED REGISTER DEFINITIONS
SETUP (Address 00H) Setup Register
Reset Value = iii01110
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
ID
ID
ID
SPEED
REF EN
REF HI
ACR (Address 02H) Analog Control Register
Reset Value = 00H
bit 7
bit 1
bit 0
BUF EN BIT ORDER
bit 7-5 Factory Programmed Bits
bit 4
SPEED: FLASH Access Clock Speed
0 : 2.30MHz > fOSC > 3.12MHz (default)
1 : 3.12MHz > fOSC > 4.13MHz
bit 3
REF EN: Internal Voltage Reference Enable
0 = Internal Voltage Reference Disabled
1 = Internal Voltage Reference Enabled (default)
bit 2
REF HI: Internal Reference Voltage Select
0 = Internal Reference Voltage = 1.25V
1 = Internal Reference Voltage = 2.5V (default)
bit 1
BUF EN: Buffer Enable
0 = Buffer Disabled
1 = Buffer Enabled (default)
bit 0
BIT ORDER: Set Order Bits are Transmitted
0 = Most Significant Bit Transmitted First (default)
1 = Least Significant Bit Transmitted First
Data is always shifted into the part most significant
bit first. Data is always shifted out of the part most
significant byte first. This configuration bit only
controls the bit order within the byte of data that is
shifted out.
MUX (Address 01H) Multiplexer Control Register
Reset Value = 01H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSEL3
PSEL2
PSEL1
PSEL0
NSEL3
NSEL2
NSEL1
NSEL0
bit 7-4 PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel
Select
0000 = AIN0 (default)
0001 = AIN1
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1xxx = AINCOM (except when all bits are 1’s)
1111 = Temperature Sensor Diode Anode
bit 3-0 NSEL3: NSEL2: NSEL1: NSEL0: Negative Channel Select
0000 = AIN0
0001 = AIN1 (default)
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1xxx = AINCOM (except when all bits are 1’s)
1111 = Temperature Sensor Diode Cathode Analog GND
ADS1218
SBAS187
BOCS
bit 7
bit 6
bit 5
bit 4
IDAC2R1 IDAC2R0 IDAC1R1
bit 3
bit 2
bit 1
bit 0
IDAC1R0
PGA2
PGA1
PGA0
BOCS: Burnout Current Source
0 = Disabled (default)
1 = Enabled
 VREF  RANGE −1
IDAC Current = 
(DAC Code)
 2
 8 • R DAC 
(
)
bit 6-5 IDAC2R1: IDAC2R0: Full-Scale Range Select for
IDAC2
00 = Off (default)
01 = Range 1
10 = Range 2
11 = Range 3
bit 4-3 IDAC1R1: IDAC1R0: Full-Scale Range Select for
IDAC1
00 = Off (default)
01 = Range 1
10 = Range 2
11 = Range 3
bit 2-0 PGA2: PGA1: PGA0: Programmable Gain Amplifier
Gain Selection
000 = 1 (default)
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = 64
111 = 128
IDAC1 (Address 03H) Current DAC 1
Reset Value = 00H
bit 7
bit 6
IDAC1_7
IDAC1_6
bit 5
bit 4
IDAC1_5 IDAC1_4
bit 3
bit 2
IDAC1_3 IDAC1_2
bit 1
bit 0
IDAC1_1
IDAC1_0
The DAC code bits set the output of DAC1 from 0 to fullscale. The value of the full-scale current is set by this Byte,
VREF, RDAC, and the DAC1 range bits in the ACR register.
IDAC2 (Address 04H) Current DAC 2
Reset Value = 00H
bit 7
bit 6
IDAC2_7
IDAC2_6
bit 5
bit 4
IDAC2_5 IDAC2_4
bit 3
bit 2
IDAC1_3 IDAC1_2
bit 1
bit 0
IDAC1_1
IDAC1_0
The DAC code bits set the output of DAC2 from 0 to fullscale. The value of the full-scale current is set by this Byte,
VREF, RDAC, and the DAC2 range bits in the ACR register.
17
ODAC (Address 05H) Offset DAC Setting
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SIGN
OSET6
OSET5
OSET4
OSET3
OSET2
OSET1
OSET0
bit 7
Offset Sign
0 = Positive
1 = Negative
bit 6-0 Offset =
VREF
Code 
•
2 • PGA  127 
NOTE: Calibration will cancel the value in the ODAC register. Therefore, writing
to the ODAC register should be done after calibration.
DIO (Address 06H) Digital I/O
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIO7
DIO6
DIO5
DIO4
DIO3
DIO2
DIO1
DIO0
A value written to this register will appear on the digital
I/O pins if the pin is configured as an output in the DIR
register. Reading this register will return the value of the
digital I/O pins.
DIR (Address 07H) Direction control for digital I/O
Reset Value = FFH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
Each bit controls whether the Digital I/O pin is an output
(= 0) or input (= 1). The default power-up state is as inputs.
DEC0 (Address 08H) Decimation Register
(Least Significant 8 bits)
Reset Value = 80H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DEC07
DEC06
DEC05
DEC04
DEC03
DEC02
DEC01
DEC00
The decimation value is defined with 11 bits for a range of
20 to 2047. This register is the least significant 8 bits. The
3 most significant bits are contained in the M/DEC1 register.
The default data rate is 10Hz with a 2.4576MHz crystal.
M/DEC1 (Address 09H) Mode and Decimation Register
Reset Value = 07H
bit 7
bit 6
DRDY
U/B
bit 5
bit 4
SMODE1 SMODE0
bit 3
bit 2
bit 1
bit 0
WREN
DEC10
DEC09
DEC08
bit 7
DRDY: Data Ready (Read Only)
This bit duplicates the state of the DRDY pin.
bit 6
U/B: Data Format
0 = Bipolar (default)
1 = Unipolar
U/B
0
1
18
ANALOG INPUT
DIGITAL OUTPUT
+FSR
Zero
–FSR
+FSR
Zero
–FSR
0x7FFFFF
0x000000
0x800000
0xFFFFFF
0x000000
0x000000
bit 5-4 SMODE1: SMODE0: Settling Mode
00 = Auto (default)
01 = Fast Settling filter
10 = Sinc2 filter
11 = Sinc3 Flash filter
bit 3
WREN: Write Enable
0 = Flash Writing Disabled (default)
1 = Flash Writing Enabled
This bit is AND’d with the WREN pin to enable or
disable Flash Writing and Erasing
bit 2-0 DEC10: DEC09: DEC08: Most Significant Bits of
the Decimation Value
OCR0 (Address 0AH) Offset Calibration Coefficient
(Least Significant Byte)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
OCR1 (Address 0BH) Offset Calibration Coefficient
(Middle Byte)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR15
OCR14
OCR13
OCR12
OCR11
OCR10
OCR09
OCR08
OCR2 (Address 0CH) Offset Calibration Coefficient
(Most Significant Byte)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR23
OCR22
OCR21
OCR20
OCR19
OCR18
OCR17
OCR16
FSR0 (Address 0DH) Full-Scale Register
(Least Significant Byte)
Reset Value = 24H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR07
FSR06
FSR05
FSR04
FSR03
FSR02
FSR01
FSR00
FSR1 (Address 0EH) Full-Scale Register
(Middle Byte)
Reset Value = 90H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR15
FSR14
FSR13
FSR12
FSR011
FSR10
FSR09
FSR08
FSR2 (Address 0FH) Full-Scale Register
(Most Significant Byte)
Reset Value = 67H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR23
FSR22
FSR21
FSR20
FSR019
FSR18
FSR17
FSR16
ADS1218
SBAS187
COMMAND DEFINITIONS
Operands:
The commands listed below control the operation of the
ADS1218. Some of the commands are stand-alone commands (e.g., RESET) while others require additional bytes
(e.g., WREG requires command, count, and the data bytes).
Commands that output data require a minimum of four fOSC
cycles before the data is ready (e.g., RDATA).
COMMANDS
DESCRIPTION
RDATA
RDATAC
STOPC
RREG
RRAM
CREG
CREGA
WREG
WRAM
RF2R
WR2F
CRAM
CSRAMX
CSARAMX
CSREG
CSRAM
CSARAM
CSFL
SELFCAL
SELFOCAL
SELFGCAL
SYSOCAL
SYSGCAL
DSYNC
SLEEP
RESET
Read Data
Read Data Continuously
Stop Read Data Continuously
Read from REG Bank “rrrr”
Read from RAM Bank “aaa”
Copy REGs to RAM Bank “aaa”
Copy REGS to all RAM Banks
Write to REG “rrrr”
Write to RAM Bank “aaa”
Read FLASH page to RAM
Write RAM to FLASH page
Copy RAM Bank “aaa” to REG
Calc RAM Bank “aaa” Checksum
Calc all RAM Bank Checksum
Calc REG Checksum
Calc RAM Bank “aaa” Checksum
Calc all RAM Banks Checksum
Calc FLASH Checksum
Self Cal Offset and Gain
Self Cal Offset
Self Cal Gain
Sys Cal Offset
Sys Cal Gain
Sync DRDY
Put in SLEEP Mode
Reset to Power-Up Values
n = count (0 to 127)
r = register (0 to 15)
x = don’t care
a = RAM bank address (0 to 7)
f = FLASH page address (0 to 31)
COMMAND BYTE
0000
0000
0000
0001
0010
0100
0100
0101
0110
100f
101f
1100
1101
1101
1101
1110
1110
1110
1111
1111
1111
1111
1111
1111
1111
1111
2ND COMMAND BYTE
0001 (01H)
0011 (03H)
1111 (0FH)
r r r r (1x H)
0aaa (2x H)
0aaa (4x H)
1000 (48H)
r r r r (5x H)
0aaa (6x H)
f f f f (8, 9xH)
f f f f (A, BxH)
0aaa (CxH)
0aaa (DxH)
1000 (D8 H)
1111 (DFH)
0aaa (ExH)
1000 (E8H)
1100 (ECH)
0000 (F0H)
0001 (F1H)
0010 (F2H)
0011 (F3H)
0100 (F4H)
1100 (FCH)
1101 (FDH)
1110 (FE H)
—
—
—
xxxx_nnnn (# of reg-1)
xnnn_nnnn (# of bytes-1)
—
—
xxxx_nnnn (# of reg-1)
xnnn_nnnn (# of bytes-1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NOTE: (1) The data received by the A/D is always MSB First, the data out format is set by the BIT ORDER bit in ACR reg.
TABLE III. Command Summary.
RDATA
Read Data
RDATAC
Description: Read a single data value from the Data Output
Register (DOR) which is the most recent conversion result.
This is a 24-bit value.
Operands: None
Bytes:
1
Encoding: 0000 0001
Data Transfer Sequence:
DIN
0000 0001
• • •(1)
xxxx xxxx
xxxx xxxx
xxxx xxxx
DOUT
xxxx xxxx
• • •(1)
MSB
Mid-Byte
LSB
Read Data Continuous
Description: Read Data Continuous mode enables the continuous output of new data on each DRDY. This command
eliminates the need to send the Read Data Command on each
DRDY. This mode may be terminated by either the STOP
Read Continuous command or the RESET command.
Operands: None
Bytes:
1
Encoding: 0000 0011
Data Transfer Sequence:
Command terminated when “uuuu uuuu” equals STOPC
or RESET.
DIN
0000 0011
• • •(1)
uuuu uuuu
uuuu uuuu
uuuu uuuu
DOUT
xxxx xxxx
• • •(1)
MSB
Mid-Byte
LSB
NOTE: (1) For wait time, refer to timing specification.
•••
DRDY
•••
DIN
xxxx
xxxx
xxxx
MSB
Mid-Byte
LSB
•••
DOUT
NOTE: (1) For wait time, refer to timing specification.
ADS1218
SBAS187
19
STOPC
Stop Continuous
CREG
Description: Ends the continuous data output mode.
Operands: None
Bytes:
1
Encoding: 0000 1111
Data Transfer Sequence:
RREG
DIN
0000 1111
DOUT
xxxx xxxx
Copy Registers to RAM Bank
Description: Copy the 16 control registers to the RAM bank
specified in the op code. Refer to timing specifications for
command execution time.
Operands: a
Bytes:
1
Encoding: 0100 0aaa
Data Transfer Sequence:
Copy Register Values to RAM Bank 3
Read from Registers
Description: Output the data from up to 16 registers starting
with the register address specified as part of the instruction.
The number of registers read will be one plus the second byte.
If the count exceeds the remaining registers, the addresses will
wrap back to the beginning.
Operands: r, n
Bytes:
2
Encoding: 0001 rrrr xxxx nnnn
Data Transfer Sequence:
Read Two Registers Starting from Register 01H (MUX)
DIN
0001 0001
0000 0001
• • •(1)
xxxx xxxx
xxxx xxxx
DOUT
xxxx xxxx
xxxx xxxx
• • •(1)
MUX
ACR
CREGA
DIN
0100 0011
DOUT
xxxx xxxx
Copy Registers to All RAM Banks
Description: Duplicate the 16 control registers to all the
RAM banks. Refer to timing specifications for command
execution time.
Operands: None
Bytes:
1
Encoding: 0100 1000
Data Transfer Sequence:
DIN
0100 1000
DOUT
xxxx xxxx
NOTE: (1) For wait time, refer to timing specification.
WREG
RRAM
Read from RAM
Description: Up to 128 bytes can be read from RAM starting
at the bank specified in the op code. All reads start at the
address for the beginning of the RAM bank. The number of
bytes to read will be one plus the value of the second byte.
Operands: a, n
Bytes:
2
Encoding: 0010 0aaa xnnn nnnn
Data Transfer Sequence:
Read Two RAM Locations Starting from 20H
DIN
0010 0010
x000 0001
• • •(1)
xxxx xxxx
xxxx xxxx
DOUT
xxxx xxxx
xxxx xxxx
• • •(1)
RAM Data
20H
RAM Data
21H
Write to Register
Description: Write to the registers starting with the register
specified as part of the instruction. The number of registers
that will be written is one plus the value of the second byte.
Operands: r, n
Bytes:
2
Encoding: 0101 rrrr xxxx nnnn
Data Transfer Sequence:
Write Two Registers Starting from 06H (DIO)
DIN
0101 0110
xxxx 0001
Data for DIO
Data for DIR
DOUT
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
NOTE: (1) For wait time, refer to timing specification.
20
ADS1218
SBAS187
WRAM
Write to RAM
CRAM
Description: Write up to 128 RAM locations starting at the
beginning of the RAM bank specified as part of the instruction. The number of bytes written is RAM is one plus the value
of the second byte.
Operands: a, n
Bytes:
2
Encoding: 0110 0aaa xnnn nnnn
Data Transfer Sequence:
Write to Two RAM Locations starting from 10H
DIN
0110 0001
x000 0001
Data for
10H
Data for
11H
DOUT
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
Description: Copy the selected RAM Bank to the Configuration Registers. This will overwrite all of the registers with the
data from the RAM bank.
Operands: a
Bytes:
1
Encoding: 1100 0aaa
Data Transfer Sequence:
Copy RAM Bank 0 to the Registers
CSRAMX
RF2R Read FLASH Page to RAM
Description: Read the selected FLASH page to the RAM.
Operands: f
Bytes:
1
Encoding: 100f ffff
Data Transfer Sequence:
Read FLASH Page 2 to RAM
DIN
1000 0010
DOUT
xxxx xxxx
Copy RAM Bank to Registers
DIN
1100 0000
DOUT
xxxx xxxx
Calculate RAM Bank Checksum
Description: Calculate the checksum of the selected RAM
Bank. The checksum is calculated as a sum of all the bytes
with the carry ignored. The ID, DRDY and DIO bits are
masked so they are not included in the checksum.
Operands: a
Bytes:
1
Encoding: 1101 0aaa
Data Transfer Sequence:
Calculate Checksum for RAM Bank 3
DIN
1101 0011
DOUT
xxxx xxxx
WR2F Write RAM to FLASH
Description: Write the contents of RAM to the selected
FLASH page.
Operands: f
Bytes:
1
Encoding: 101f ffff
Data Transfer Sequence:
Write RAM to FLASH page 31
ADS1218
SBAS187
DIN
1011 1111
DOUT
xxxx xxxx
CSARAMX Calculate the Checksum
for all RAM Banks
Description: Calculate the checksum of all RAM Banks. The
checksum is calculated as a sum of all the bytes with the carry
ignored. The ID, DRDY and DIO bits are masked so they are
not included in the checksum.
Operands: None
Bytes:
1
Encoding: 1101 1000
Data Transfer Sequence:
DIN
1101 1000
DOUT
xxxx xxxx
21
CSREG
Calculate the Checksum of
Registers
Description: Calculate the checksum of all the registers. The
checksum is calculated as a sum of all the bytes with the carry
ignored. The ID, DRDY and DIO bits are masked so they are
not included in the checksum.
Operands: None
Bytes:
1
Encoding: 1101 1111
Data Transfer Sequence:
DIN
DOUT
CSFL Calculate Checksum for all FLASH Pages
Description: Calculate the checksum for all FLASH pages.
The checksum is calculated as a sum of all the bytes with the
carry ignored. All bits are included in the checksum calculation, there is no masking of bits.
Operands: None
Bytes:
1
Encoding: 1110 1100
Data Transfer Sequence:
Calculate RAM Bank Checksum
Description: Calculate the checksum of the selected RAM
Bank. The checksum is calculated as a sum of all the bytes
with the carry ignored. All bits are included in the checksum
calculation, there is no masking of bits.
Operands: a
Bytes:
1
Encoding: 1110 0aaa
Data Transfer Sequence:
Calculate Checksum for RAM Bank 2
CSARAM
DIN
1110 0010
DOUT
xxxx xxxx
Calculate Checksum for all
RAM Banks
Description: Calculate the checksum of all RAM Banks. The
checksum is calculated as a sum of all the bytes with the carry
ignored. All bits are included in the checksum calculation,
there is no masking of bits.
Operands: None
Bytes:
1
Encoding: 1110 1000
Data Transfer Sequence:
22
1110 1100
DOUT
xxxx xxxx
xxxx xxxx
SELFCAL
CSRAM
DIN
1101 1111
DIN
1110 1000
DOUT
xxxx xxxx
Offset and Gain Self Calibration
Description: Starts the process of self calibration. The Offset
Control Register (OCR) and the Full-Scale Register (FSR) are
updated with new values after this operation.
Operands: None
Bytes:
1
Encoding: 1111 0000
Data Transfer Sequence:
DIN
1111 0000
DOUT
xxxx xxxx
SELFOCAL Offset Self Calibration
Description: Starts the process of self-calibration for offset.
The Offset Control Register (OCR) is updated after this
operation.
Operands: None
Bytes:
1
Encoding: 1111 0001
Data Transfer Sequence:
DIN
1111 0001
DOUT
xxxx xxxx
ADS1218
SBAS187
SELFGCAL Gain Self Calibration
DSYNC
Description: Starts the process of self-calibration for gain.
The Full-Scale Register (FSR) is updated with new values
after this operation.
Description: Synchronizes the ADS1218 to the serial clock
edge.
Operands: None
Bytes:
1
Encoding: 1111 0010
Data Transfer Sequence:
DIN
1111 0010
DOUT
xxxx xxxx
Operands: None
Bytes:
1
Encoding: 1111 1100
Data Transfer Sequence:
SLEEP
SYSOCAL
System Offset Calibration
Description: Starts the system offset calibration process. For
a system offset calibration the input should be set to 0V
differential, and the ADS1218 computes the OCR register
value that will compensate for offset errors. The Offset
Control Register (OCR) is updated after this operation.
SYSGCAL
1111 0011
DOUT
xxxx xxxx
Description: Starts the system gain calibration process. For a
system gain calibration, the differential input should be set to
the reference voltage and the ADS1218 computes the FSR
register value that will compensate for gain errors. The FSR is
updated after this operation.
Operands: None
Bytes:
1
Encoding: 1111 0100
Data Transfer Sequence:
ADS1218
SBAS187
DIN
1111 0100
DOUT
xxxx xxxx
1111 1100
DOUT
xxxx xxxx
Sleep Mode
Operands: None
Bytes:
1
Encoding: 1111 1101
Data Transfer Sequence:
RESET
System Gain Calibration
DIN
Description: Puts the ADS1218 into a low power sleep mode.
To exit sleep mode strobe SCLK.
Operands: None
Bytes:
1
Encoding: 1111 0011
Data Transfer Sequence:
DIN
Sync DRDY
DIN
1111 1101
DOUT
xxxx xxxx
Reset to Powerup Values
Description: Restore the registers to their power-up values.
This command will also stop the Read Continuous mode. It
does not affect the contents of RAM.
Operands: None
Bytes:
1
Encoding: 1111 1110
Data Transfer Sequence:
DIN
1111 1110
DOUT
xxxx xxxx
23
LSB
MSB
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
x
rdata
x
rdatac
x
x
x
x
x
x
x
x
x
x
x
stopc
0001
rreg
0
rreg
1
rreg
2
rreg
3
rreg
4
rreg
5
rreg
6
rreg
7
rreg
8
rreg
9
rreg
A
rreg
B
rreg
C
rreg
D
rreg
E
rreg
F
0010
rram
0
rram
1
rram
2
rram
3
rram
4
rram
5
rram
6
rram
7
x
x
x
x
x
x
x
x
0011
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0100
creg
0
creg
1
creg
2
creg
3
creg
4
creg
5
creg
6
creg
7
crega
x
x
x
x
x
x
x
0101
wreg
0
wreg
1
wreg
2
wreg
3
wreg
4
wreg
5
wreg
6
wreg
7
wreg
8
wreg
9
wreg
A
wreg
B
wreg
C
wreg
D
wreg
E
wreg
F
0110
wram
0
wram
1
wram
2
wram
3
wram
4
wram
5
wram
6
wram
7
x
x
x
x
x
x
x
x
0111
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1000
rf2r
0
r f2r
1
r f2r
2
r f2r
3
r f2r
4
rf2r
5
r f2r
6
rf2r
7
rf2r
8
r f2r
9
rf2r
A
rf2r
B
rf2r
C
r f2r
D
rf2r
E
r f2r
F
1001
r f2r
10
r f2r
11
r f2r
12
r f2r
13
r f2r
14
rf2r
15
r f2r
16
rf2r
17
rf2r
18
r f2r
19
rf2r
1A
rf2r
1B
rf2r
1C
r f2r
1D
rf2r
1E
r f2r
1F
1010
w r2f
0
w r2f
1
w r2f
2
w r2f
3
w r2f
4
wr 2f
5
w r 2f
6
wr 2f
7
wr 2f
8
w r 2f
9
wr 2f
A
wr 2f
B
wr 2f
C
w r 2f
D
wr 2f
E
w r 2f
F
1011
w r2f
10
w r2f
11
w r2f
12
w r2f
13
w r2f
14
wr 2f
15
w r 2f
16
wr 2f
17
wr 2f
18
w r 2f
19
wr 2f
1A
wr 2f
1B
wr 2f
1C
w r 2f
1D
wr 2f
1E
w r 2f
1F
cram 7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
csreg
x
x
x
csfl
x
x
x
x
x
x
dsync
sleep
reset
x
1100
cram 0 cram 1
cram 2
cram 3 cram 4
cram 5 cram 6
1101
csramx csramx
0
1
csramx csramx csramx csramx csramx
2
3
4
5
6
csramx csramx
7
1110
csram 0 csram 1 csram2 csram 3 csram 4 csram 5 csram 6 csram 7
1111
self
cal
self
ocal
self
gcal
sys
ocal
sys
gcal
x
x
x
csram
x
x = Reserved
TABLE IV. ADS1218 Command Map.
24
ADS1218
SBAS187
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI), allows a controller to
communicate synchronously with the ADS1218. The
ADS1218 operates in slave only mode.
SPI Transfer Formats
During an SPI transfer, data is simultaneously transmitted
and received. The SCLK signal synchronizes shifting and
sampling of the information on the two serial data lines: DIN
and DOUT. The CS signal allows individual selection of an
ADS1218 device; an ADS1218 with CS HIGH is not active
on the bus.
Clock Phase and Polarity Controls (POL)
The clock polarity is specified by the POL pin, which selects
an active HIGH or active LOW clock, and has no effect on
the transfer format.
Serial Clock (SCLK)
SCLK, a Schmitt Trigger input to the ADS1218, is generated by the master device and synchronizes data transfer on
the DIN and DOUT lines. When transferring data to or from
the ADS1218, burst mode may be used i.e., multiple bits of
data may be transferred back-to-back with no delay in
SCLKs or toggling of CS.
Chip Select (CS)
The chip select (CS) input of the ADS1218 must be externally asserted before a master device can exchange data with
the ADS1218. CS must be LOW before data transactions
and must stay LOW for the duration of the transaction.
DIGITAL INTERFACE
The ADS1218’s programmable functions are controlled
using a set of on-chip registers, as outlined previously. Data
is written to these registers via the part’s serial interface and
read access to the on-chip registers is also provided by this
interface.
The ADS1218’s serial interface consists of four signals: CS,
SCLK, DIN, and DOUT. The DIN line is used for transferring
data into the on-chip registers while the DOUT line is used for
accessing data from the on-chip registers. SCLK is the serial
clock input for the device and all data transfers (either on
DIN or DOUT) take place with respect to this SCLK signal.
The DRDY line is used as a status signal to indicate when
data is ready to be read from the ADS1218’s data register.
DRDY goes LOW when a new data word is available in the
DOR register. It is reset HIGH when a read operation from
the data register is complete. It also goes HIGH prior to the
updating of the output register to indicate when not to read
from the device to ensure that a data read is not attempted
while the register is being updated.
ADS1218
SBAS187
CS is used to select the device. It can be used to decode the
ADS1218 in systems where a number of parts are connected
to the serial bus.
The timing specification shows the timing diagram for
interfacing to the ADS1218 with CS used to decode the part.
The ADS1218 serial interface can operate in three-wire
mode by tying the CS input LOW. In this case, the SCLK,
DIN, and DOUT lines are used to communicate with the
ADS1218 and the status of DRDY can be obtained by
interrogating bit 7 of the M/DEC1 register. This scheme is
suitable for interfacing to microcontrollers. If CS is required
as a decoding signal, it can be generated from a port pin.
DEFINITION OF TERMS
Analog Input Voltage—the voltage at any one analog input
relative to AGND.
Analog Input Differential Voltage—given by the following
equation: (IN+ – IN–). Thus, a positive digital output is produced whenever the analog input differential voltage is positive, while a negative digital output is produced whenever the
differential is negative.
For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 1, the positive
full-scale output is produced when the analog input differential is 2.5V. The negative full-scale output is produced when
the differential is –2.5V. In each case, the actual input
voltages must remain within the AGND to AVDD range.
Conversion Cycle—the term “conversion cycle” usually
refers to a discrete A/D conversion operation, such as that
performed by a successive approximation converter. As
used here, a conversion cycle refers to the tDATA time period.
However, each digital output is actually based on the modulator results from several tDATA time periods.
FILTER SETTING
MODULATOR RESULTS
fast settling
1 tDATA time period
sinc2
2 tDATA time period
sinc3
3 tDATA time period
Data Rate—The rate at which conversions are completed.
See definition for fDATA.
Decimation Ratio—defines the ratio between the output of
the modulator and the output Data Rate. Valid values for the
Decimation Ratio are from 20 to 2047. Larger Decimation
Ratios will have lower noise and vice-versa.
25
Effective Resolution—the effective resolution of the
ADS1218 in a particular configuration can be expressed in
two different units: bits rms (referenced to output) and Vrms
(referenced to input). Computed directly from the converter’s
output data, each is a statistical calculation. The conversion
from one to the other is shown below.
BITS rms
PGA SETTING
SAMPLING FREQUENCY
1, 2, 4, 8
f SAMP =
fOSC
mfactor
BIPOLAR Vrms
UNIPOLAR Vrms
16
f SAMP =
fOSC • 2
mfactor
 2 • VREF 
 PGA 
 VREF 
 PGA 
32
f SAMP =
fOSC • 4
mfactor
64, 128
f SAMP =
fOSC • 8
mfactor
10
 6.02 • ER 
 20 
10
 6.02 • ER 
 20 
24
298nV
22
1.19µV
597nV
20
4.77µV
2.39µV
18
19.1µV
9.55µV
16
76.4µV
38.2µV
14
505µV
152.7µV
12
1.22mV
610µV
149nV
Filter Selection—the ADS1218 uses a (sinx /x) filter or sinc
filter. Actually there are three different sinc filters that can
be selected. A fast settling filter will settle in one tDATA
cycle. The sinc2 filter will settle in two cycles and have
lower noise. The sinc3 will achieve the lowest noise and
highest number of effective bits, but requires three cycles to
settle. The ADS1218 will operate with any one of these
filters, or it can operate in an auto mode, where it will select
the fast settling filter after a new channel is selected and will
then switch to sinc2 followed by sinc3. This allows fast
settling response and still achieves low noise after the
necessary number of tDATA cycles.
fOSC—the frequency of the crystal oscillator or CMOS
compatible input signal at the XIN input of the ADS1218.
fMOD—the frequency or speed at which the modulator of the
ADS1218 is running. This depends on the SPEED bit as
given by the following equation:
SPEED = 0
SPEED = 1
128
256
mfactor
fMOD =
fSAMP—the frequency, or switching speed, of the input
sampling capacitor. The value is given by one of the following equations:
fDATA—the frequency of the digital output data produced by
the ADS1218, fDATA is also referred to as the Data Rate.

 

fMOD
fOSC
fDATA = 
 =

 Decimation Ratio   mfactor • Decimation Ratio 
Full-Scale Range (FSR)—as with most A/D converters, the
full-scale range of the ADS1218 is defined as the “input”,
which produces the positive full-scale digital output minus
the “input”, which produces the negative full-scale digital
output. The full-scale range changes with gain setting as
shown in Table V.
For example, when the converter is configured with a 2.5V
reference and is placed in a gain setting of 2, the full-scale
range is: [1.25V (positive full-scale) minus –1.25V (negative full-scale)] = 2.5V.
Least Significant Bit (LSB) Weight—this is the theoretical
amount of voltage that the differential voltage at the analog
input would have to change in order to observe a change in
the output data of one least significant bit. It is computed as
follows:
Full − Scale Range
LSB Weight =
2N
where N is the number of bits in the digital output.
tDATA—the inverse of fDATA, or the period between each
data output.
fOSC
mfactor
5V SUPPLY ANALOG INPUT(1)
GAIN SETTING
FULL-SCALE RANGE
DIFFERENTIAL
INPUT VOLTAGES(2)
GENERAL EQUATIONS
PGA OFFSET
RANGE
FULL-SCALE
RANGE
DIFFERENTIAL
INPUT VOLTAGES(2)
2 • VREF
PGA
±VREF
PGA
1
5V
±2.5V
±1.25V
2
2.5V
±1.25V
±0.625V
4
1.25V
±0.625V
±312.5mV
8
0.625V
±312.5mV
±156.25mV
16
312.5mV
±156.25mV
±78.125mV
32
156.25mV
±78.125mV
±39.0625mV
64
78.125mV
±39.0625mV
±19.531mV
128
39.0625mV
±19.531mV
±9.766mV
PGA SHIFT
RANGE
± VREF
2 • PGA
NOTES: (1) With a 2.5V reference. (2) The ADS1218 allows common-mode voltage as long as the absolute input voltage on AINP or AINN does not go below
AGND or above AVDD.
TABLE V. Full-Scale Range versus PGA Setting.
26
ADS1218
SBAS187
TOPIC INDEX
TOPIC
PAGE
ABSOLUTE MAXIMUM RATINGS .......................................................................................................................... 2
PACKAGE AND ORDERING INFORMATION ........................................................................................................ 2
ELECTRICAL CHARACTERISTICS (AVDD = 5V) .................................................................................................. 2
ELECTRICAL CHARACTERISTICS (AVDD = 3V) .................................................................................................. 4
PIN CONFIGURATION ............................................................................................................................................ 6
TIMING SPECIFICATIONS ...................................................................................................................................... 7
TYPICAL CHARACTERISTICS ............................................................................................................................... 8
OVERVIEW .............................................................................................................................................................12
MEMORY ................................................................................................................................................................15
REGISTER BANK TOPOLOGY ............................................................................................................................15
DETAILED REGISTER DEFINITIONS ..................................................................................................................17
COMMAND DEFINITIONS .....................................................................................................................................19
ADS1218 COMMAND MAP ...................................................................................................................................24
SERIAL PERIPHERAL INTERFACE .....................................................................................................................25
DIGITAL INTERFACE ............................................................................................................................................25
DEFINITION OF TERMS ........................................................................................................................................25
ADS1218
SBAS187
27
PACKAGE DRAWING
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
0°– 7°
1,05
0,95
Seating Plane
1,20 MAX
0,75
0,45
0,08
4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
28
ADS1218
SBAS187
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
ADS1218Y/250
ACTIVE
TQFP
PFB
48
250
ADS1218Y/2K
ACTIVE
TQFP
PFB
48
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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