TI DRV8332 Three phase pwm motor driver Datasheet

DRV8312
DRV8332
www.ti.com
SLES256 – MAY 2010
Three Phase PWM Motor Driver
Check for Samples: DRV8312, DRV8332
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
High-Efficiency Power Stage (up to 97%) with
Low RDS(on) MOSFETs (80 mΩ at TJ = 25°C)
Operating Supply Voltage up to 50 V
(70 V Absolute Maximum)
DRV8312 (power pad down): up to 3.5 A
Continuous Phase Current (6.5 A Peak)
DRV8332 (power pad up): up to 8 A
Continuous Phase Current ( 13 A Peak)
Independent Control of Three Phases
PWM Operating Frequency up to 500 kHz
Integrated Self-Protection Circuits Including
Undervoltage, Overtemperature, Overload, and
Short Circuit
Programmable Cycle-by-Cycle Current Limit
Protection
Independent Supply and Ground Pins for Each
Half Bridge
Intelligent Gate Drive and Cross Conduction
Prevention
No External Snubber or Schottky Diode is
Required
Because of the low RDS(on) of the power MOSFETs
and intelligent gate drive design, the efficiency of
these motor drivers can be up to 97%, which enables
the use of smaller power supplies and heatsinks, and
are good candidates for energy efficient applications.
The DRV8312/32 require two power supplies, one at
12 V for GVDD and VDD, and another up to 50 V for
PVDD. The DRV8312/32 can operate at up to
500-kHz switching frequency while still maintain
precise control and high efficiency. They also have an
innovative protection system safeguarding the device
against a wide range of fault conditions that could
damage the system. These safeguards are
short-circuit protection, overcurrent protection,
undervoltage protection, and two-stage thermal
protection. The DRV8312/32 have a current-limiting
circuit that prevents device shutdown during load
transients such as motor start-up. A programmable
overcurrent detector allows adjustable current limit
and protection level to meet different motor
requirements.
The DRV8312/32 have unique independent supply
and ground pins for each half bridge, which makes it
possible to provide current measurement through
external shunt resistor and support half bridge drivers
with different power supply voltage requirements.
APPLICATIONS
•
•
•
•
•
Simplified Application Diagram
BLDC Motors
Three Phase Permanent Magnet Synchronous
Motors
Inverters
Half Bridge Drivers
Robotic Control Systems
PVDD
GVDD
GVDD_B
OTW
FAULT
GVDD_A
BST_A
PVDD_A
PWM_A
OUT_A
RESET_A
GND_A
PWM_B
GND_B
OC_ADJ
OUT_B
M
Controller
DESCRIPTION
GND
AGND
The DRV8312/32 are high performance, integrated
three phase motor drivers with an advanced
protection system.
BST_B
VREG
NC
M3
NC
M2
GND
M1
PWM_C
GVDD
PVDD_B
GND
GND_C
RESET_C
OUT_C
RESET_B
PVDD_C
VDD
GVDD_C
BST_C
GVDD_C
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
DRV8312
DRV8332
SLES256 – MAY 2010
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range unless otherwise noted
(1)
VALUE
VDD to GND
–0.3 V to 13.2 V
GVDD_X to GND
–0.3 V to 13.2 V
PVDD_X to GND_X
(2)
–0.3 V to 70 V
OUT_X to GND_X
(2)
–0.3 V to 70 V
BST_X to GND_X
(2)
–0.3 V to 80 V
Transient peak output current (per pin), pulse width limited by internal over-current protection circuit.
16 A
Transient peak output current for latch shut down (per pin)
20 A
VREG to AGND
–0.3 V to 4.2 V
GND_X to GND
–0.3 V to 0.3 V
GND to AGND
–0.3 V to 0.3 V
PWM_X, RESET_X to GND
–0.3 V to 4.2 V
OC_ADJ, M1, M2, M3 to AGND
–0.3 V to 4.2 V
FAULT, OTW to GND
–0.3 V to 7 V
Maximum continuous sink current (FAULT, OTW)
9 mA
Maximum operating junction temperature range, TJ
-40°C to 150°C
Storage temperature, TSTG
–55°C to 150°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
0
50
52.5
V
Supply for logic regulators and gate-drive circuitry
10.8
12
13.2
V
VDD
Digital regulator supply voltage
10.8
12
13.2
V
IO_PULSE
Pulsed peak current per output pin (could be limited by thermal)
15
A
IO
Continuous current per output pin (DRV8332)
8
A
FSW
PWM switching frequency
500
kHz
ROCP_CBC
OC programming resistor range in cycle-by-cycle current limit modes
22
200
kΩ
ROCP_OCL
OC programming resistor range in OC latching shutdown modes
19
200
kΩ
CBST
Bootstrap capacitor range
33
220
nF
TON_MIN
Minimum PWM pulse duration, low side
TA
Operating ambient temperature
PVDD_X
Half bridge X (A, B, or C) DC supply voltage
GVDD_X
(1)
2
50
-40
nS
85 (1)
°C
Depending on power dissipation and heat-sinking, the DRV8312/32 can support ambient temperature in excess of 85°C. Refer to the
package heat dissipation ratings table and package power deratings table.
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SLES256 – MAY 2010
PACKAGE HEAT DISSIPATION RATINGS
DRV8312
DRV8332
RqJC, junction-to-case (power pad / heat slug)
thermal resistance
PARAMETER
1.1 °C/W
0.9 °C/W
RqJA, junction-to-ambient thermal resistance
25 °C/W
This device is not intended to be used
without a heatsink. Therefore, RqJA is not
specified. See the Thermal Information
section.
Exposed power pad / heat slug area
34 mm2
80 mm2
PACKAGE POWER DERATINGS (DRV8312) (1)
PACKAGE
TA = 25°C
POWER
RATING
DERATING
FACTOR
ABOVE TA =
25°C
TA = 70°C POWER
RATING
TA = 85°C POWER
RATING
TA = 125°C POWER
RATING
44-PIN TSSOP (DDW)
5.0 W
40.0 mW/°C
3.2 W
2.6 W
1.0 W
(1)
Based on EVM board layout
MODE SELECTION PINS
MODE PINS
M3
M2
M1
OUTPUT
CONFIGURATION
1
0
0
1 3PH or 3 HB
Three-phase or three half bridges with cycle-by-cycle current limit
1
0
1
1 3PH or 3 HB
Three-phase or three half bridges with OC latching shutdown (no
cycle-by-cycle current limit)
0
x
x
Reserved
1
1
x
Reserved
DESCRIPTION
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DEVICE INFORMATION
Pin Assignment
Here are the pinouts for the DRV8312/32:
• DRV8312: 44-pin TSSOP power pad down DDW package. This package contains a thermal pad that is
located on the bottom side of the device for dissipating heat through PCB.
• DRV8332: 36-pin PSOP3 DKD package. This package contains a thick heat slug that is located on the top
side of the device for dissipating heat through heatsink.
DRV8332
DKD Package
(Top View)
DRV8312
DDW Package
(Top View)
GVDD_C
1
44
VDD
NC
NC
PWM_C
2
43
3
42
4
41
5
40
RESET_C
RESET_B
M1
M2
M3
VREG
AGND
GND
OC_ADJ
PWM_B
RESET_A
PWM_A
6
39
7
38
8
37
9
36
FAULT
NC
NC
OTW
GVDD_B
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
GVDD_C
BST_C
NC
PVDD_C
PVDD_C
OUT_C
GND_C
GND
GND
NC
NC
BST_B
PVDD_B
OUT_B
GND_B
GND_A
OUT_A
PVDD_A
PVDD_A
NC
BST_A
GVDD_A
GVDD_B
1
36
GVDD_A
OTW
2
35
BST_A
FAULT
3
34
PVDD_A
PWM_A
4
33
OUT_A
RESET_A
5
32
GND_A
PWM_B
6
31
GND_B
OC_ADJ
7
30
OUT_B
GND
8
29
PVDD_B
AGND
9
28
BST_B
VREG
10
27
NC
M3
11
26
NC
M2
12
25
GND
M1
13
24
GND
RESET_B
14
23
GND_C
RESET_C
15
22
OUT_C
PWM_C
16
21
PVDD_C
VDD
17
20
BST_C
GVDD_C
18
19
GVDD_C
Pin Functions
PIN
(1)
4
NAME
DRV8312
FUNCTION
DRV8332
(1)
DESCRIPTION
AGND
12
9
P
Analog ground
BST_A
24
35
P
High side bootstrap supply (BST), external capacitor to OUT_A required
BST_B
33
28
P
High side bootstrap supply (BST), external capacitor to OUT_B required
BST_C
43
20
P
High side bootstrap supply (BST), external capacitor to OUT_C required
GND
13, 36, 37
8
P
Ground
GND_A
29
32
P
Power ground for half-bridge A requires close decoupling capacitor to ground
GND_B
30
31
P
Power ground for half-bridge B requires close decoupling capacitor to ground
GND_C
38
23
P
Power ground for half-bridge C requires close decoupling capacitor to ground
GVDD_A
23
36
P
Gate-drive voltage supply
GVDD_B
22
1
P
Gate-drive voltage supply
GVDD_C
1, 44
18, 19
P
Gate-drive voltage supply
M1
8
13
I
Mode selection pin
M2
9
12
I
Mode selection pin
M3
10
11
I
Reserved mode selection pin, AGND connection is recommended
NC
3,4,19,20,25,34,35
,42
26,27
-
No connection pin. Ground connection is recommended
OC_ADJ
14
7
O
Analog overcurrent programming pin, requires resistor to AGND
I = input, O = output, P = power, T = thermal
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PIN
FUNCTION
(1)
DESCRIPTION
NAME
DRV8312
DRV8332
OTW
21
2
O
Overtemperature warning signal, open-drain, active-low. An internal pull-up resistor
to VREG (3.3 V) is provided on output. Level compliance for 5-V logic can be
obtained by adding external pull-up resistor to 5 V
OUT_A
28
33
O
Output, half-bridge A
OUT_B
31
30
O
Output, half-bridge B
OUT_C
39
22
O
Output, half-bridge C
PVDD_A
26,27
34
P
Power supply input for half-bridge A requires close decoupling capacitor to ground.
PVDD_B
32
29
P
Power supply input for half-bridge B requires close decoupling capacitor to gound.
PVDD_C
40,41
21
P
Power supply input for half-bridge C requires close decoupling capacitor to ground.
PWM_A
17
4
I
Input signal for half-bridge A
PWM_B
15
6
I
Input signal for half-bridge B
PWM_C
5
16
I
Input signal for half-bridge C
RESET_A
16
5
I
Reset signal for half-bridge A, active-low
RESET_B
7
15
I
Reset signal for half-bridge B, active-low
RESET_C
6
15
I
Reset signal for half-bridge C, active-low
FAULT
18
3
O
Fault signal, open-drain, active-low. An internal pull-up resistor to VREG (3.3 V) is
provided on output. Level compliance for 5-V logic can be obtained by adding
external pull-up resistor to 5 V
VDD
2
17
P
Power supply for digital voltage regulator requires capacitor to ground for
decoupling.
VREG
11
10
P
Digital regulator supply filter pin requires 0.1-mF capacitor to AGND.
THERMAL PAD
--
N/A
T
Solder the exposed thermal pad at the bottom of the DRV8312DDW package to the
landing pad on the PCB. Connect the landing pad through vias to large ground
plate for better thermal dissipation.
HEAT SLUG
N/A
--
T
Mount heatsink with thermal interface to the heat slug on the top of the
DRV8332DKD package to improve thermal dissipation.
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SYSTEM BLOCK DIAGRAM
VDD
4
Undervoltage
Protection
OTW
Internal Pullup
Resistors to VREG
FAULT
M1
Protection
and
I/O Logic
M2
M3
4
VREG
VREG
Power
On
Reset
AGND
Temp.
Sense
GND
RESET_A
Overload
Protection
RESET_B
Isense
OC_ADJ
RESET_C
GVDD_C
BST_C
PVDD_C
PWM_C
PWM
Rcv.
Ctrl.
Timing
Gate
Drive
OUT_C
GND_C
GVDD_B
BST_B
PVDD_B
PWM_B
PWM
Rcv.
Ctrl.
Timing
Gate
Drive
OUT_B
GND_B
GVDD_A
BST_A
PVDD_A
PWM_A
PWM
Rcv.
Ctrl.
Timing
Gate
Drive
OUT_A
GND_A
6
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ELECTRICAL CHARACTERISTICS
TA = 25 °C, PVDD = 50 V, GVDD = VDD = 12 V, fSw = 400 kHz, unless otherwise noted. All performance is in accordance
with recommended operating conditions unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.95
3.3
3.65
9
12
mA
2.5
mA
1
mA
Internal Voltage Regulator and Current Consumption
VREG
Voltage regulator, only used as a reference node
IVDD
VDD = 12 V
Idle, reset mode
VDD supply current
Operating, 50% duty cycle
V
10.5
Reset mode
1.7
IGVDD_X
Gate supply current per half-bridge
IPVDD_X
Half-bridge X (A, B, or C) idle current
Reset mode
0.7
MOSFET drain-to-source resistance, low side (LS)
TJ = 25°C, GVDD = 12 V
80
mΩ
80
mΩ
Operating, 50% duty cycle
8
Output Stage
RDS(on)
MOSFET drain-to-source resistance, high side (HS)
TJ = 25°C, GVDD = 12 V
VF
Diode forward voltage drop
TJ = 25°C - 125°C, IO = 5 A
tR
Output rise time
tF
tPD_ON
1
V
Resistive load, IO = 5 A
14
nS
Output fall time
Resistive load, IO = 5 A
14
nS
Propagation delay when FET is on
Resistive load, IO = 5 A
38
nS
tPD_OFF
Propagation delay when FET is off
Resistive load, IO = 5 A
38
nS
tDT
Dead time between HS and LS FETs
Resistive load, IO = 5 A
5.5
nS
8.5
V
I/O Protection
Gate supply voltage GVDD_X undervoltage
protection threshold
Vuvp,G
Vuvp,hyst
(1)
Hysteresis for gate supply undervoltage event
OTW (1)
Overtemperature warning
OTWhyst (1)
Hysteresis temperature to reset OTW event
OTSD (1)
Overtemperature shut down
OTEOTWdifferential (1)
0.8
115
125
V
135
°C
25
°C
150
°C
OTE-OTW overtemperature detect temperature
difference
25
°C
OTSDHYST (1)
Hysteresis temperature for FAULT to be released
following an OTSD event
25
°C
IOC
Overcurrent limit protection
Resistor—programmable, nominal, ROCP = 27 kΩ
9.7
A
Overcurrent response time
Time from application of short condition to Hi-Z of
affected FET(s)
250
ns
IOCT
Static Digital Specifications
VIH
High-level input voltage
PWM_A, PWM_B, PWM_C, M1, M2, M3
2
3.6
V
VIH
High-level input voltage
RESET_A, RESET_B, RESET_C
2
3.6
V
VIL
Low-level input voltage
PWM_A, PWM_B, PWM_C, M1, M2, M3,
RESET_A, RESET_B, RESET_C
0.8
V
llkg
Input leakage current
100
mA
kΩ
-100
OTW / FAULT
RINT_PU
Internal pullup resistance, OTW to VREG, FAULT to
VREG
VOH
High-level output voltage
VOL
Low-level output voltage
(1)
Internal pullup resistor only
External pullup of 4.7 kΩ to 5 V
IO = 4 mA
20
26
35
2.95
3.3
3.65
4.5
5
0.2
0.4
V
V
Specified by design
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TYPICAL CHARACTERISTICS
EFFICIENCY
vs
SWITCHING FREQUENCY (DRV8332)
NORMALIZED RDS(on)
vs
GATE DRIVE
1.10
100
TJ = 25°C
Normalized RDS(on) / (RDS(on) at 12 V)
90
80
Efficiency – %
70
60
50
40
30
Full Bridge
20
Load = 5 A
PVDD = 50 V
TC = 75°C
10
0
0
50
1.08
1.06
1.04
1.02
1.00
0.98
0.96
8.0
100 150 200 250 300 350 400 450 500
8.5
9.0
10.5
11.0
11.5
Figure 2.
NORMALIZED RDS(on)
vs
JUNCTION TEMPERATURE
DRAIN TO SOURCE DIODE FORWARD
ON CHARACTERISTICS
12
6
TJ = 25°C
GVDD = 12 V
5
1.4
4
1.2
I – Current – A
Normalized RDS(on) / (RDS(on) at 25oC)
10.0
Figure 1.
1.6
1.0
3
2
0.8
1
0.6
0.4
–40 –20
0
0
20
40
60
80
100 120 140
–1
0
0.2
o
TJ – Junction Temperature – C
Figure 3.
8
9.5
GVDD – Gate Drive – V
f – Switching Frequency – kHz
0.4
0.6
0.8
1
1.2
V – Voltage – V
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
OUTPUT DUTY CYCLE
vs
INPUT DUTY CYCLE
100
fS = 500 kHz
TC = 25°C
90
Output Duty Cycle – %
80
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
70
80
90
100
Input Duty Cycle – %
Figure 5.
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THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the DRV8312/32 need
only a 12-V supply in addition to H-Bridge power
supply (PVDD). An internal voltage regulator provides
suitable voltage levels for the digital and low-voltage
analog circuitry. Additionally, the high-side gate drive
requiring a floating voltage supply, which is
accommodated by built-in bootstrap circuitry requiring
external bootstrap capacitor.
To provide symmetrical electrical characteristics, the
PWM signal path, including gate drive and output
stage, is designed as identical, independent
half-bridges. For this reason, each half-bridge has a
separate gate drive supply (GVDD_X), a bootstrap
pin (BST_X), and a power-stage supply pin
(PVDD_X). Furthermore, an additional pin (VDD) is
provided as supply for all common circuits. Special
attention should be paid to place all decoupling
capacitors as close to their associated pins as
possible. In general, inductance between the power
supply pins and decoupling capacitors must be
avoided. Furthermore, decoupling capacitors need a
short ground path back to the device.
For a properly functioning bootstrap circuit, a small
ceramic capacitor (an X5R or better) must be
connected from each bootstrap pin (BST_X) to the
power-stage output pin (OUT_X). When the
power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected
between the gate-drive power-supply pin (GVDD_X)
and the bootstrap pin. When the power-stage output
is high, the bootstrap capacitor potential is shifted
above the output potential and thus provides a
suitable voltage supply for the high-side gate driver.
In an application with PWM switching frequencies in
the range from 10 kHz to 500 kHz, the use of 100-nF
ceramic capacitors (X5R or better), size 0603 or
0805, is recommended for the bootstrap supply.
These 100-nF capacitors ensure sufficient energy
storage, even during minimal PWM duty cycles, to
keep the high-side power stage FET fully turned on
during the remaining part of the PWM cycle. In an
application running at a switching frequency lower
than 10 kHz, the bootstrap capacitor might need to be
increased in value.
10
Special attention should be paid to the power-stage
power supply; this includes component selection,
PCB placement, and routing. As indicated, each
half-bridge has independent power-stage supply pin
(PVDD_X). For optimal electrical performance, EMI
compliance, and system reliability, it is important that
each PVDD_X pin is decoupled with a ceramic
capacitor (X5R or better) placed as close as possible
to each supply pin. It is recommended to follow the
PCB layout of the DRV8312/32 EVM board.
The 12-V supply should be from a low-noise,
low-output-impedance voltage regulator. Likewise, the
50-V power-stage supply is assumed to have low
output impedance and low noise. The power-supply
sequence is not critical as facilitated by the internal
power-on-reset circuit. Moreover, the DRV8312/32
are fully protected against erroneous power-stage
turn-on due to parasitic gate charging. Thus,
voltage-supply ramp rates (dv/dt) are non-critical
within the specified voltage range (see the
Recommended Operating Conditions section of this
data sheet).
SYSTEM POWER-UP/POWER-DOWN
SEQUENCE
Powering Up
The DRV8312/32 do not require a power-up
sequence. The outputs of the H-bridges remain in a
high impedance state until the gate-drive supply
voltage GVDD_X and VDD voltage are above the
undervoltage protection (UVP) voltage threshold (see
the Electrical Characteristics section of this data
sheet). Although not specifically required, holding
RESET_A, RESET_B, and RESET_C in a low state
while powering up the device is recommended. This
allows an internal circuit to charge the external
bootstrap capacitors by enabling a weak pulldown of
the half-bridge output.
Powering Down
The DRV8312/32 do not require a power-down
sequence. The device remains fully operational as
long as the gate-drive supply (GVDD_X) voltage and
VDD voltage are above the UVP voltage threshold
(see the Electrical Characteristics section of this data
sheet). Although not specifically required, it is a good
practice to hold RESET_A, RESET_B and RESET_C
low during power down to prevent any unknown state
during this transition.
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ERROR REPORTING
Bootstrap Capacitor Under Voltage Protection
The FAULT and OTW pins are both active-low,
open-drain
outputs.
Their
function
is
for
protection-mode signaling to a PWM controller or
other system-control device.
When the device runs at a low switching frequency
(e.g. less than 10 kHz with a 100-nF bootstrap
capacitor), the bootstrap capacitor voltage might not
be able to maintain a proper voltage level for the
high-side gate driver. A bootstrap capacitor
undervoltage protection circuit (BST_UVP) will
prevent potential failure of the high-side MOSFET.
When the voltage on the bootstrap capacitors is less
than the required value for safe operation, the
DRV8312/32 will initiate bootstrap capacitor recharge
sequences (turn off high side FET for a short period)
until the bootstrap capacitors are properly charged for
safe operation. This function may also be activated
when PWM duty cycle is too high (e.g. less than 20
ns off time at 10 kHz). Note that bootstrap capacitor
might not be able to be charged if no load or
extremely light load is presented at output during
BST_UVP operation, so it is recommended to turn on
the low side FET for at least 50 ns for each PWM
cycle to avoid BST_UVP operation if possible.
Any fault resulting in device shutdown, such as
overtemperatue shut down, overcurrent shut-down, or
undervoltage protection, is signaled by the FAULT pin
going low. Likewise, OTW goes low when the device
junction temperature exceeds 125°C (see Table 1).
Table 1. Protection Mode Signal Descriptions
FAULT
OTW
DESCRIPTION
0
0
Overtemperature warning and
(overtemperature shut down or overcurrent
shut down or undervoltage protection) occurred
0
1
Overcurrent shut-down or GVDD undervoltage
protection occurred
1
0
Overtemperature warning
1
1
Device under normal operation
TI recommends monitoring the OTW signal using the
system microcontroller and responding to an OTW
signal by reducing the load current to prevent further
heating of the device resulting in device
overtemperature shutdown (OTSD).
To reduce external component count, an internal
pullup resistor to internal VREG (3.3 V) is provided on
both FAULT and OTW outputs. Level compliance for
5-V logic can be obtained by adding external pull-up
resistors to 5 V (see the Electrical Characteristics
section of this data sheet for further specifications).
DEVICE PROTECTION SYSTEM
The DRV8312/32 contain advanced protection
circuitry carefully designed to facilitate system
integration and ease of use, as well as to safeguard
the device from permanent failure due to a wide
range of fault conditions such as short circuits,
overcurrent, overtemperature, and undervoltage. The
DRV8312/32 respond to a fault by immediately
setting the half bridge outputs in a high-impedance
(Hi-Z) state and asserting the FAULT pin low. In
situations other than overcurrent or overtemperature,
the device automatically recovers when the fault
condition has been removed or the gate supply
voltage has increased. For highest possible reliability,
reset the device externally no sooner than 1 second
after the shutdown when recovering from an
overcurrent shut down (OCSD) or OTSD fault.
For applications with lower than 10 kHz switching
frequency and not to trigger BST_UVP protection, a
larger bootstrap capacitor can be used (e.g., 1 uF cap
for 800 Hz operation). When using a bootstrap cap
larger than 220 nF, it is recommended to add 5 ohm
resistors between 12V GVDD power supply and
GVDD_X pins to limit the inrush current on the
internal bootstrap diodes.
Overcurrent (OC) Protection
The DRV8312/32 have independent, fast-reacting
current detectors with programmable trip threshold
(OC threshold) on all high-side and low-side
power-stage FETs. There are two settings for OC
protection
through
mode
selection
pins:
cycle-by-cycle (CBC) current limiting mode and OC
latching (OCL) shut down mode.
In CBC current limiting mode, the detector outputs
are monitored by two protection systems. The first
protection system controls the power stage in order to
prevent the output current from further increasing,
i.e., it performs a CBC current-limiting function rather
than prematurely shutting down the device. This
feature could effectively limit the inrush current during
motor start-up or transient without damaging the
device. During short to power and short to ground
conditions, the current limit circuitry might not be able
to control the current to a proper level, a second
protection system triggers a latching shutdown,
resulting in the related half bridge being set in the
high-impedance (Hi-Z) state. Current limiting and
overcurrent
protection
are
independent
for
half-bridges A, B, and C, respectively.
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Figure 6 illustrates cycle-by-cycle operation with high
side OC event and Figure 7 shows cycle-by-cycle
operation with low side OC. Dashed lines are the
operation waveforms when no CBC event is triggered
and solide lines show the waveforms when CBC
event is triggered. In CBC current limiting mode,
when low side FET OC is detected, devcie will turn
off the affected low side FET and keep the high side
FET at the same half brdige off until next PWM cycle;
when high side FET OC is detected, devcie will turn
off the affected high side FET and turn on the low
side FET at the half brdige until next PWM cycle.
In OC latching shut down mode, the CBC current limit
and error recovery circuitries are disabled and an
overcurrent condition will cause the device to
shutdown immediately. After shutdown, RESET_A,
RESET_B, and / or RESET_C must be asserted to
restore normal operation after the overcurrent
condition is removed.
For added flexibility, the OC threshold is
programmable using a single external resistor
connected between the OC_ADJ pin and AGND pin.
See Table 2 for information on the correlation
between programming-resistor value and the OC
threshold.
Table 2. Programming-Resistor Values and OC
Threshold
OC-ADJUST RESISTOR
VALUES (kΩ)
19
(1)
12
MAXIMUM CURRENT BEFORE
OC OCCURS (A)
(1)
13.2
22
11.6
24
10.7
27
9.7
30
8.8
36
7.4
39
6.9
43
6.3
47
5.8
56
4.9
68
4.1
82
3.4
100
2.8
120
2.4
150
1.9
200
1.4
Recommended to use in OC Latching Mode Only
It should be noted that a properly functioning
overcurrent detector assumes the presence of a
proper inductor or power ferrite bead at the
power-stage output. Short-circuit protection is not
guaranteed with direct short at the output pins of the
power stage.
Overtemperature Protection
The
DRV8312/32
have
a
two-level
temperature-protection system that asserts an
active-low warning signal (OTW) when the device
junction temperature exceeds 125°C (nominal) and, if
the device junction temperature exceeds 150°C
(nominal), the device is put into thermal shutdown,
resulting in all half-bridge outputs being set in the
high-impedance (Hi-Z) state and FAULT being
asserted low. OTSD is latched in this case and
RESET_A, RESET_B, and RESET_C must be
asserted low to clear the latch.
Undervoltage Protection (UVP) and Power-On
Reset (POR)
The UVP and POR circuits of the DRV8312/32 fully
protect the device in any power-up / down and
brownout situation. While powering up, the POR
circuit resets the overcurrent circuit and ensures that
all circuits are fully operational when the GVDD_X
and VDD supply voltages reach 9.8 V (typical).
Although GVDD_X and VDD are independently
monitored, a supply voltage drop below the UVP
threshold on any VDD or GVDD_X pin results in all
half-bridge outputs immediately being set in the
high-impedance (Hi-Z) state and FAULT being
asserted low. The device automatically resumes
operation when all supply voltage on the bootstrap
capacitors have increased above the UVP threshold.
DEVICE RESET
Three reset pins are provided for independent control
of half-bridges A, B, and C. When RESET_X is
asserted low, two power-stage FETs in half-bridges X
are forced into a high-impedance (Hi-Z) state.
A rising-edge transition on reset input allows the
device to resume operation after a shut-down fault.
E.g., when half-bridge X has OC shutdown, a low to
high transition of RESET_X pin will clear the fault and
FAULT pin. When an OTSD occurs, all three
RESET_A, RESET_B, and RESET_C need to have a
low to high transition to clear the fault and reset
FAULT signal.
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DIFFERENT OPERATIONAL MODES
The DRV8312/32 support two different modes of
operation:
1. Three-phase (3PH) or three half bridges (HB)
with CBC current limit
2. Three-phase or three half bridges with OC
latching shutdown (no CBC current limit)
Because each half bridge has independent supply
and ground pins, a shunt sensing resistor can be
inserted between PVDD to PVDD_X or GND_X to
GND (ground plane). A high side shunt resistor
between PVDD and PVDD_X is recommended for
differential current sensing because a high bias
voltage on the low side sensing could affect device
operation. If low side sensing has to be used, a shunt
resistor value of 10 mΩ or less or sense voltage 100
mV or less is recommended.
Figure 8 and Figure 9 show the three-phase
application examples, and Figure 10 shows how to
connect to DRV8312/32 with some simple logic to
accommodate conventional 6 PWM inputs control.
We recommend using complementary control
scheme for switching phases to prevent circulated
energy flowing inside the phases and to make current
limiting feature active all the time. Complementary
control scheme also forces the current flowing
through sense resistors all the time to have a better
current sensing and control of the system.
Figure 11 shows six steps trapezoidal scheme with
hall sensor control and Figure 12 shows six steps
trapezoidal scheme with sensorless control. The hall
sensor sequence in real application might be different
than the one we showed in Figure 11 depending on
the motor used. Please check motor manufacture
datasheet for the right sequence in applications. In
six step trapezoidal complementary control scheme, a
half bridge with larger than 50% duty cycle will have a
positive current and a half bridge with less than 50%
duty cycle will have a negative current. For normal
operation, changing PWM duty cycle from 50% to
100% will adjust the current from 0 to maximum value
with six steps control. It is recommanded to apply a
minimum 50ns to 100 nS PWM pulse at each
switching cycle at lower side to properly charge the
bootstrap cap. The impact of minimum pulse at low
side FET is pretty small, e.g., the maximum duty
cycle is 99.9% with 100ns minimum pulse on low
side. RESET_Xpin can be used to get channel X into
high impedance mode. If you prefer PWM switching
one channel but hold low side FET of the other
channel on (and third channel in Hi-Z) for 2-quadrant
mode, OT latching shutdown mode is recommended
to prevent the channel with low side FET on stuck in
Hi-Z during OC event in CBC mode.
The DRV8312/32 can also be used for sinusoidal
waveform control and field oriented control. Please
check TI website MCU motor control library for
control algorithms.
CBC with High Side OC
During T_OC Period
PVDD
Current Limit
Load
Current
PWM_HS
Load
PWM_LS
PWM_HS
PWM_LS
GND_X
T_HS T_OC T_LS
Figure 6. Cycle-by-Cycle Operation with High Side OC (dashed line: normal operation; solid line: CBC
event)
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During T_OC Period
CBC with Low Side OC
PVDD
Current Limit
Load
Current
PWM_HS
PWM_HS
Load
PWM_LS
PWM_LS
T_LS T_OC T_HS
GND_X
Figure 7. Cycle-by-Cycle Operation with Low Side OC (dashed line: normal operation; solid line: CBC
event)
GVDD
PVDD
1 mF
DRV8332
330 mF
3.3
1000 mF
GVDD_B
1mF
OTW
GVDD_A
10 nF
BST_A
100 nF
FAULT
PVDD_A
PWM_A
OUT_A
RESET_A
GND_A
Loc
Rsense_A
100nF
M
Rsense_B
Controller
(MSP430
C2000 or
Stellaris MCU)
PWM_B
GND_B
Loc
Roc_adj
OC_ADJ
1
GND
OUT_B
PVDD_B
AGND
BST_B
100 nF
100nF
100 nF
VREG
NC
M3
NC
M2
GND
M1
Rsense_x £ 10 mW
or
Vsense < 100 mV
GND
Rsense_C
RESET_B
GND_C
RESET_C
OUT_C
PWM_C
GVDD
VDD
47 mF
Loc
PVDD_C
BST_C
100 nF
1 mF
GVDD_C
GVDD_C
100nF
PVDD
1mF
Figure 8. DRV8332 Application Diagram for Three-Phase Operation
14
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1mF
DRV8312
GVDD
GVDD_B
GVDD_A
PVDD
100 nF
1mF
330 mF
OTW
BST_A
3.3
NC
10 nF
1000 mF
NC
Controller
(MSP430
C2000 or
Stellaris MCU)
NC
PVDD_A
FAULT
PVDD_A
PWM_A
OUT_A
RESET_A
GND_A
PWM_B
GND_B
Loc
Rsense_A
100nF
M
Rsense_B
Loc
Roc_adj
OC_ADJ
OUT_B
1
GND
PVDD_B
AGND
BST_B
VREG
NC
M3
NC
M2
GND
100 nF
100nF
100 nF
M1
Rsense_x £ 10 mW
or
Vsense < 100 mV
GND
Rsense_C
GVDD
1mF
47 mF
RESET_B
GND_C
RESET_C
OUT_C
PWM_C
PVDD_C
NC
PVDD_C
NC
NC
VDD
GVDD_C
Loc
100nF
PVDD
BST_C
GVDD_C
100 nF
1mF
Figure 9. DRV8312 Application Diagram for Three-Phase Operation
PVDD
Controller
PWM_AH
PWM_BH
PWM_CH
PWM_A
PWM_B
PWM_C
MOTOR
OUT_A
OUT_B
RESET_A
OUT_C
PWM_AL
RESET_B
PWM_BL
RESET_C
PWM_CL
GND_A
GND_B
GND_C
Figure 10. Control Signal Logic with Conventional 6 PWM Input Scheme
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S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
Hall Sensor H1
Hall Sensor H2
Hall Sensor H3
Phase Current A
Phase Current B
Phase Current C
PWM_A
PWM_B
PWM_C
RESET_A
RESET_B
RESET_C
360
o
PWM= 100%
360
o
PWM=75%
Figure 11. Hall Sensor Control with 6 Steps Trapezoidal Scheme
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S1
Back EMF (Vab)
Back EMF (Vbc)
Back EMF (Vca)
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
0V
0V
0V
Phase A
Current and Voltage
Va
Ia
0A
0V
Phase B
Current and Voltage
Vb
Ib
0A
0V
Vc
Phase C
Current and Voltage
Ic
0A
0V
PWM_A
PWM_B
PWM_C
RESET_A
RESET_B
RESET_C
360
o
PWM= 100%
360
o
PWM= 75%
Figure 12. Sensorless Control with 6 Steps Trapezoidal Scheme
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APPLICATION INFORMATION
SYSTEM DESIGN RECOMMENDATIONS
Voltage of Decoupling Capacitor
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. The high frequency decoupling capacitor
should use ceramic capacitor with X5R or better rating. For a 50-V application, a minimum voltage rating of 63 V
is recommended.
Current Requirement of 12V Power Supply
The DRV8312/32 require a 12V power supply for GVDD and VDD pins. The total supply current is pretty low at
room temp (less than 50mA), but the current could increase significantly when the device temperature goes too
high (e.g. above 125°C), especially at heave load conditions due to substrate current collection by 12V guard
rings. So it is recommended to design the 12V power supply with current capability at least 5-10% of your load
current and no less than 100mA to assure the device performance across all temperature range.
VREG Pin
The VREG pin is used for internal logic and should not be used as a voltage source for external circuitries. The
capacitor on VREG pin should be connected to AGND.
VDD Pin
The transient current in VDD pin could be significantly higher than average current through VDD pin. A low
resistive path to GVDD should be used. A 22-µF to 47-µF capacitor should be placed on VDD pin beside the
100-nF to 1-µF decoupling capacitor to provide a constant voltage during transient.
OTW Pin
OTW reporting indicates the device approaching high junction temperature. This signal can be used with MCU to
decrease system power when OTW is low in order to prevent OT shut down at a higher temperature.
No external pull up resistor or 3.3V power supply is needed for 3.3V logic. The OTW pin has an internal pullup
resistor connecting to an internal 3.3V to reduce external component count. For 5V logic, an external pull up
resistor to 5V is needed.
FAULT Pin
The FAULT pin reports any fault condition resulting in device shut down. No external pull up resistor or 3.3V
power supply is needed for 3.3V logic. The FAULT pin has an internal pullup resistor connecting to an internal
3.3V to reduce external component count. For 5V logic, an external pull upresistor to 5V is needed.
OC_ADJ Pin
For accurate control of the oevercurrent protection, the OC_ADJ pin has to be connected to AGND through an
OC adjust resistor.
PWM_X and RESET_X Pins
It is recommanded to connect these pins to either AGND or GND when they are not used, and these pins only
support 3.3V logic.
Mode Select Pins
Mode select pins (M1, M2, and M3) should be connected to either VREG (for logic high) or AGND for logic low. It
is not recommended to connect mode pins to board ground if 1-Ω resistor is used between AGND and GND.
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Output Inductor Selection
For normal operation, inductance in motor (assume larger than 10 µH) is sufficient to provide low di/dt output
(e.g. for EMI) and proper protection during overload condition (CBC current limiting feature). So no additional
output inductors are needed during normal operation.
However during a short condition, the motor (or other load) could be shorted, so the load inductance might not
present in the system anymore; the current in short condition can reach such a high level that may exceed the
abs max current rating due to extremely low impendence in the short circuit path and high di/dt before oc
detection circuit kicks in. So a ferrite bead or inductor is recommended to utilize the short circuit protection
feature in DRV8312/32. With an external inductor or ferrite bead, the current will rise at a much slower rate and
reach a lower current level before oc protection starts. The device will then either operate CBC current limit or
OC shut down automatically (when current is well above the current limit threshold) to protect the system.
For a system that has limited space, a power ferrite bead can be used instead of an inductor. The current rating
of ferrite bead has to be higher than the RMS current of the system at normal operation. A ferrite bead designed
for very high frequency is NOT recommended. A minimum impedance of 10 Ω or higher is recommended at 10
MHz or lower frequency to effectively limit the current rising rate during short circuit condition.
The TDK MPZ2012S300A and MPZ2012S101A (with size of 0805 inch type) have been tested in our system to
meet short circuit conditions in the DRV8312. But other ferrite beads that have similar frequency characteristics
can be used as well.
For higher power applications, such as in the DRV8332, there might be limited options to select suitable ferrite
bead with high current rating. If an adequate ferrite bead cannot be found, an inductor can be used.
The inductance can be calculated as:
PVDD × Toc _ delay
Loc _ min =
Ipeak - Iave
(1)
Where Toc_delay = 250 nS, Ipeak = 15 A (below abs max rating).
Because an inductor usually saturates pretty quickly after reaching its current rating, it is recommended to use an
inductor with a doubled value or an inductor with a current rating well above the operating condition.
PCB LAYOUT RECOMMENDATION
PCB Material Recommendation
FR-4 Glass Epoxy material with 2 oz. copper on both top and bottom layer is recommended for improved thermal
performance (better heat sinking) and less noise susceptibility (lower PCB trace inductance).
Ground Plane
Because of the power level of these devices, it is recommended to use a big unbroken single ground plane for
the whole system / board. The ground plane can be easily made at bottom PCB layer. In order to minimize the
impedance and inductance of ground traces, the traces from ground pins should keep as short and wide as
possible before connected to bottom ground plane through vias. Multiple vias are suggested to reduce the
impedance of vias. Try to clear the space around the device as much as possible especially at bottom PCB side
to improve the heat spreading.
Decoupling Capacitor
High frequency decoupling capacitors (100 nF) should be placed close to PVDD_X pins and with a short ground
return path to minimize the inductance on the PCB trace.
AGND
AGND is a localized internal ground for logic signals. A 1-Ω resistor is recommended to be connected between
GND and AGND to isolate the noise from board ground to AGND. There are other two components are
connected to this local ground: 0.1-µF capacitor between VREG to AGND and Roc_adj resistor between
OC_ADJ and AGND. Capacitor for VREG should be placed close to VREG and AGND pins and connected
without vias.
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Current Shunt Resistor
If current shunt resistor is connected between GND_X to GND or PVDD_X to PVDD, make sure there is only one
single path to connect each GND_X or PVDD_X pin to shunt resistor, and the path is short and symmetrical on
each sense path to minimize the measurement error due to additional resistance on the trace.
PCB LAYOUT EXAMPLE
An example of the schematic and PCB layout of DRV8312 are shown in Figure 13, Figure 14, and Figure 15.
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U1
1
3
1
3
2
1
3
2
RSTB
2
1
3
GVDD
RSTC
M1
GND
HTSSOP44-DDW
PowerPad
S1
2
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GVDD
GVDD
GND
Orange
Orange
Orange
Orange
0603
1.0ufd/16V
0603
C34
GND
1.0ufd/16V
0603
C35
GND
47K
R37
1.0 1/4W
0805
R36
0.1ufd/16V
0603
C33
Orange
1.0ufd/16V
0603
47ufd/16V
M
GND
C32
GND
C31
GND
+
1.0ufd/16V
0603
C30
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HTSSOP44-DDW
DRV8312DDW
U1
44
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
GND
0.1ufd/100V
0805
C45
0.1ufd/100V
0805
C42
0.1ufd/100V
0805
C36
PVDD
PVDD
GND
0.1ufd/100V
0805
C46
GND
0.1ufd/100V
0805
C43
GND
0.1ufd/100V
0805
C37
PVDD
OUT_C
Orange
OUT_A
Orange
OUT_B
Orange
L2
30ohms/6A
0805
L4
30ohms/6A
0805
L3
30ohms/6A
0805
0.0
0603
R21
0.0
0603
R20
0.0
0603
R23
0.0
0603
R22
+3.3V
+3.3V
R18
R19
5
V-
5
1
2
V+
V+
GND
499
0603
R39
+3.3V
+3.3V
GND
R63
R64
GND
OA4
+IN
-IN
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10.2K
0603
R27
10.2K
0603
R26
SOT23-DBV
OPA365AIDBV
V+
VOUT
V-
0.1ufd/16V
0603
C39
5
1
2
SOT23-DBV
+IN
-IN
OPA365AIDBV
V+
VOUT
OA3
C19
+2.5V
IS-IhbC
30.1K
0603
R41
220pfd/50V
0603
C20
3
4
3
619
0603
R31
15.4K
0603
R55
619
0603
R30
15.4K
0603
R54
0.01 1W
1206
0.01 1W
1206
IS
30.1K
0603
R62
220pfd/50V
0603
C22
+2.5V
30.1K
0603
R16
220pfd/50V
0603
C21
+2.5V
GND
GND
GND
0.005 1W
1206
R51
OUTC
220pfd/50V
0603
C28
931
0603
R34
220pfd/50V
0603
C27
931
0603
R35
1000pfd/50V
0603
C60
IS-IhbB
1000pfd/50V
0603
C59
IS-IhbA
OUTA
OUTB
ROUTED GROUND
(SHIELDED FROM GND PLANE)
IS-TOTAL
1000pfd/50V
0603
C58
IS-IhbC
1000pfd/50V
0603
C57
IS-TOTAL
STUFF OPTION
R53
R52
4
220pfd/50V
0603
C26
931
0603
R33
220pfd/50V
0603
C25
931
0603
R32
STUFF OPTION
IS-IhbA -IhbB
0.01 1W
1206
GND
GND
+2.5V
30.1K
0603
R40
220pfd/50V
0603
R50
619
0603
R29
15.4K
0603
R49
619
0603
R28
15.4K
0603
R48
www.ti.com
33 1/8W
0805
5
1
V-
0.1ufd/16V
0603
C29
GND
GND
33 1/8W
0805
GND
2
GND
1000pfd/100V
0603
C56
ADC-Vhb2
GND
1000pfd/100V
0603
GND
10.2K
0603
R25
3
4
3
4
1000pfd/100V
0603
C50
10.2K
0603
R24
SOT23-DBV
C55
GND
499
0603
499
0603
+IN
-IN
OPA365AIDBV
R43
R45
OA2
SOT23-DBV
VOUT
V-
10.0K
0603
10.0K
0603
+IN
-IN
OPA365AIDBV
R42
R44
OA1
VOUT
0.1ufd/16V
0603
C24
10.0K
0603
R38
GND
33 1/8W
0805
2
1
0.1ufd/16V
0603
C23
GND
GND
33 1/8W
0805
GND
DRV8312
DRV8332
SLES256 – MAY 2010
Figure 13. DRV8312 Schematic Example
21
DRV8312
DRV8332
SLES256 – MAY 2010
www.ti.com
C37
T3
T4
T2
C33
T1
C43
C46
T1: PVDD decoupling capacitors C37, C43, and C46 should be placed very close to PVDD_X pins and ground return
path.
T2: VREG decoupling capacitor C33 should be placed very close to VREG abd AGND pins.
T3: Clear the space above and below the device as much as possible to improve the thermal spreading.
T4: Add many vias to reduce the impedance of ground path through top to bottom side. Make traces as wide as
possible for ground path such as GND_X path.
Figure 14. Printed Circuit Board – Top Layer
B1
B1: Do not block the heat transfer path at bottom side. Clear as much space as possible for better heat spreading.
Figure 15. Printed Circuit Board – Bottom Layer
22
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): DRV8312 DRV8332
DRV8312
DRV8332
www.ti.com
SLES256 – MAY 2010
THERMAL INFORMATION
The thermally enhanced package provided with the DRV8332 is designed to interface directly to heat sink using
a thermal interface compound in between, (e.g., Ceramique from Arctic Silver, TIMTronics 413, etc.). The heat
sink then absorbs heat from the ICs and couples it to the local air. It is also a good practice to connect the
heatsink to system ground on the PCB board to reduce the ground noise.
RqJA is a system thermal resistance from junction to ambient air. As such, it is a system parameter with the
following components:
• RqJC (the thermal resistance from junction to case, or in this example the power pad or heat slug)
• Thermal grease thermal resistance
• Heat sink thermal resistance
The thermal grease thermal resistance can be calculated from the exposed power pad or heat slug area and the
thermal grease manufacturer's area thermal resistance (expressed in °C-in 2/W or °C-mm2/W). The approximate
exposed heat slug size is as follows:
• DRV8332, 36-pin PSOP3 …… 0.124 in2 (80 mm 2)
The thermal resistance of a thermal pad is considered higher than a thin thermal grease layer and is not
recommended. Thermal tape has an even higher thermal resistance and should not be used at all. Heat sink
thermal resistance is predicted by the heat sink vendor, modeled using a continuous flow dynamics (CFD) model,
or measured.
Thus the system RqJA = RqJC + thermal grease resistance + heat sink resistance.
See the TI application report, IC Package Thermal Metrics (SPRA953A), for more thermal information.
DRV8312 Thermal Via Design Recommendation
Thermal pad of the DRV8312 is attached at bottom of device to improve the thermal capability of the device. The
thermal pad has to be soldered with a very good coverage on PCB in order to deliver the power specified in the
datasheet. The figure below shows the recommended thermal via and land pattern design for the DRV8312. For
additional information, see TI application report, PowerPad Made Easy (SLMA004B) and PowerPad Layout
Guidelines (SOLA120).
Figure 16. DRV8312 Thermal Via Footprint
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): DRV8312 DRV8332
23
PACKAGE OPTION ADDENDUM
www.ti.com
5-Mar-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
DRV8312DDW
ACTIVE
HTSSOP
DDW
44
35
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
DRV8312DDWR
ACTIVE
HTSSOP
DDW
44
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
DRV8332DKD
ACTIVE
HSSOP
DKD
36
29
Green (RoHS
& no Sb/Br)
NIPDAU
Level-4-260C-72 HR
DRV8332DKDR
ACTIVE
HSSOP
DKD
36
500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-4-260C-72 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
DRV8312DDWR
HTSSOP
DDW
44
2000
330.0
24.4
DRV8332DKDR
HSSOP
DKD
36
500
330.0
24.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.6
15.6
1.8
12.0
24.0
Q1
14.7
16.4
4.0
20.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8312DDWR
HTSSOP
DDW
44
2000
346.0
346.0
41.0
DRV8332DKDR
HSSOP
DKD
36
500
346.0
346.0
41.0
Pack Materials-Page 2
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