AD ADUM1400 Quad-channel digital isolator Datasheet

Quad-Channel Digital Isolators
ADuM1400/ADuM1401/ADuM1402
Data Sheet
FEATURES
GENERAL DESCRIPTION
Qualified for automotive applications
Low power operation
5 V operation
1.0 mA per channel maximum at 0 Mbps to 2 Mbps
3.5 mA per channel maximum at 10 Mbps
31 mA per channel maximum at 90 Mbps
3 V operation
0.7 mA per channel maximum at 0 Mbps to 2 Mbps
2.1 mA per channel maximum at 10 Mbps
20 mA per channel maximum at 90 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 125°C
High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics
2 ns maximum pulse width distortion
2 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body package
RoHS-compliant models available
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak
TÜV approval: IEC/EN/UL/CSA 61010-1
The ADuM140x1 are quad-channel digital isolators based on
Analog Devices, Inc., iCoupler® technology. Combining high
speed CMOS and monolithic air core transformer technology,
these isolation components provide outstanding performance
characteristics superior to alternatives, such as optocoupler
devices.
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain
current transfer ratios, nonlinear transfer functions, and
temperature and lifetime effects are eliminated with the simple
iCoupler digital interfaces and stable performance characteristics.
The need for external drivers and other discrete components
is eliminated with these iCoupler products. Furthermore,
iCoupler devices consume one-tenth to one-sixth of the power
of optocouplers at comparable signal data rates.
The ADuM140x isolators provide four independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). All models operate with the supply
voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. In
addition, the ADuM140x provides low pulse width distortion
(<2 ns for CRW grade) and tight channel-to-channel matching
(<2 ns for CRW grade). Unlike other optocoupler alternatives,
the ADuM140x isolators have a patented refresh feature that
ensures dc correctness in the absence of input logic transitions
and when power is not applied to one of the supplies.
APPLICATIONS
General-purpose multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
Automotive systems
1
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
VDD1 1
16 VDD2
VDD1 1
16
VDD2
VDD1 1
16
VDD2
GND1 2
15 GND2
GND1 2
15
GND2
GND1 2
15
GND2
VOA
VIA 3
ENCODE
DECODE
14
VOA
VOB
VIA 3
ENCODE
DECODE
14 VOA
VIA 3
ENCODE
DECODE
14
VIB 4
DECODE
ENCODE
DECODE
13
VOB
VIB 4
ENCODE
DECODE
13
VIC 5
ENCODE
DECODE
12 VOC
VIC 5
ENCODE
DECODE
12
VOC
VOC 5
DECODE
ENCODE
12
VIC
VID 6
ENCODE
DECODE
11 VOD
VOD 6
DECODE
ENCODE
11
VID
VOD 6
DECODE
ENCODE
11
VID
10 VE2
VE1 7
10
VE2
VE1 7
10
VE2
GND1 8
9
GND1 8
9
NC 7
9 GND2
GND1 8
Figure 1. ADuM1400
Rev. I
Figure 2. ADuM1401
GND2
03786-002
ENCODE
13 VOB
03786-001
VIB 4
GND2
03786-003
FUNCTIONAL BLOCK DIAGRAMS
Figure 3. ADuM1402
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Technical Support
www.analog.com
ADuM1400/ADuM1401/ADuM1402
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 20
General Description ......................................................................... 1
Recommended Operating Conditions .................................... 20
Functional Block Diagrams ............................................................. 1
Absolute Maximum Ratings ......................................................... 21
Revision History ............................................................................... 3
ESD Caution................................................................................ 21
Specifications..................................................................................... 4
Pin Configurations and Function Descriptions ......................... 22
Electrical Characteristics—5 V, 105°C Operation ................... 4
Typical Performance Characteristics ........................................... 25
Electrical Characteristics—3 V, 105°C Operation ................... 6
Applications Information .............................................................. 27
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V,
105°C Operation ........................................................................... 8
PC Board Layout ........................................................................ 27
Electrical Characteristics—5 V, 125°C Operation ................. 11
DC Correctness and Magnetic Field Immunity ..................... 27
Electrical Characteristics—3 V, 125°C Operation ................. 13
Power Consumption .................................................................. 28
Electrical Characteristics—Mixed 5 V/3 V, 125°C Operation 15
Insulation Lifetime ..................................................................... 29
Electrical Characteristics—Mixed 3 V/5 V, 125°C Operation 17
Outline Dimensions ....................................................................... 30
Package Characteristics ............................................................. 19
Ordering Guide .......................................................................... 30
Regulatory Information ............................................................. 19
Automotive Products ................................................................. 31
Propagation Delay-Related Parameters ................................... 27
Insulation and Safety-Related Specifications .......................... 19
Rev. I | Page 2 of 32
Data Sheet
ADuM1400/ADuM1401/ADuM1402
REVISION HISTORY
4/14—Rev. H to Rev. I
Change to Table 9 ............................................................................19
3/12—Rev. G to Rev. H
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section ................................................................. 1
Change to PC Board Layout Section ............................................27
Updated Outline Dimensions ........................................................30
Moved Automotive Products Section ...........................................31
5/08—Rev. F to Rev. G
Added ADuM1400W, ADuM1401W, and ADuM1402W
Parts ..................................................................................... Universal
Added Table 4 ..................................................................................11
Added Table 5 ..................................................................................13
Added Table 6 ..................................................................................15
Added Table 7 ..................................................................................17
Changes to Table 12 ........................................................................20
Changes to Table 13 ........................................................................21
Added Automotive Products Section ...........................................29
Changes to Ordering Guide ...........................................................30
11/07—Rev. E to Rev. F
Changes to Note 1 ............................................................................. 1
Added ADuM140xARW Change vs. Temperature Parameter ... 4
Added ADuM140xARW Change vs. Temperature Parameter ... 5
Added ADuM140xARW Change vs. Temperature Parameter ... 8
Changes to Figure 17 ......................................................................18
6/07—Rev. D to Rev. E
Updated VDE Certification Throughout ....................................... 1
Changes to Features and Note 1 ...................................................... 1
Changes to Figure 1, Figure 2, and Figure 3 .................................. 1
Changes to Regulatory Information Section ...............................10
Changes to Table 7 ..........................................................................11
Added Table 10 ................................................................................12
Added Insulation Lifetime Section ...............................................20
Updated Outline Dimensions ........................................................21
Changes to Ordering Guide ...........................................................21
2/06—Rev. C to Rev. D
Updated Format ................................................................. Universal
Added TÜV Approval ....................................................... Universal
5/05—Rev. B to Rev. C
Changes to Format ............................................................. Universal
Changes to Figure 2 .......................................................................... 1
Changes to Table 3 ............................................................................ 8
Changes to Table 6 .......................................................................... 12
Changes to Ordering Guide ........................................................... 21
6/04—Rev. A to Rev. B
Changes to Format ............................................................. Universal
Changes to Features .......................................................................... 1
Changes to Electrical Characteristics—5 V Operation................ 3
Changes to Electrical Characteristics—3 V Operation................ 5
Changes to Electrical Characteristics—Mixed 5 V/3 V or
3 V/5 V Operation ............................................................................ 7
Changes to DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation
Characteristics Title ........................................................................ 11
Changes to the Ordering Guide .................................................... 19
5/04—Rev. 0 to Rev. A
Updated Format ................................................................. Universal
Changes to the Features.................................................................... 1
Changes to Table 7 and Table 8 ..................................................... 14
Changes to Table 9 .......................................................................... 15
Changes to the DC Correctness and Magnetic Field Immunity
Section .............................................................................................. 20
Changes to the Power Consumption Section .............................. 21
Changes to the Ordering Guide .................................................... 22
9/03—Revision 0: Initial Version
Rev. I | Page 3 of 32
ADuM1400/ADuM1401/ADuM1402
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION 1
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. These specifications do not apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 1.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM1400 Total Supply Current, Four Channels 2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1401 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 or VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 or VDD2 Supply Current
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM140xARW
Minimum Pulse Width 3
Maximum Data Rate 4
Propagation Delay 5
Symbol
Typ
Max Unit
IDDI (Q)
IDDO (Q)
0.50
0.19
0.53 mA
0.21 mA
IDD1 (Q)
IDD2 (Q)
2.2
0.9
2.8
1.4
IDD1 (10)
IDD2 (10)
8.6
2.6
10.6 mA
3.5 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (90)
IDD2 (90)
70
18
100
25
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
IDD1 (Q)
IDD2 (Q)
1.8
1.2
2.4
1.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
7.1
4.1
9.0
5.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (90)
IDD2 (90)
57
31
82
43
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
IDD1 (Q), IDD2 (Q)
1.5
2.1
mA
DC to 1 MHz logic signal freq.
IDD1 (10), IDD2 (10)
5.6
7.0
mA
5 MHz logic signal freq.
IDD1 (90), IDD2 (90)
44
62
mA
45 MHz logic signal freq.
µA
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH,
VOCH, VODH
VOAL, VOBL,
VOCL, VODL
Min
−10
+0.01 +10
2.0
0.8
V
V
V
V
V
V
V
(VDD1 or VDD2) − 0.1 5.0
(VDD1 or VDD2) − 0.4 4.8
0.0
0.04
0.2
0.1
0.1
0.4
1
50
1000 ns
Mbps
100 ns
PW
tPHL, tPLH
mA
mA
Rev. I | Page 4 of 32
65
Test Conditions
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Data Sheet
Parameter
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew 6
Channel-to-Channel Matching 7
ADuM140xBRW
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
Channel-to-Channel Matching, OpposingDirectional Channels7
ADuM140xCRW
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
Channel-to-Channel Matching, OpposingDirectional Channels7
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
Output Enable Propagation Delay (High
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at Logic
High Output 8
Common-Mode Transient Immunity at Logic
Low Output8
Refresh Rate
Input Dynamic Supply Current per Channel 9
Output Dynamic Supply Current per Channel9
ADuM1400/ADuM1401/ADuM1402
Symbol
PWD
Min
Typ
11
tPSK
tPSKCD/tPSKOD
PW
Max Unit
40
ns
ps/°C
50
ns
50
ns
Test Conditions
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
100
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSK
tPSKCD
15
3
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
6
ns
tPHL, tPLH
PWD
10
20
32
50
3
5
PW
tPSK
tPSKCD
11.1 ns
Mbps
32
ns
2
ns
ps/°C
10
ns
2
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
tPHL, tPLH
PWD
90
18
8.3
120
27
0.5
3
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
tR/tF
|CMH|
25
2.5
35
ns
kV/µs
|CML|
25
35
kV/µs
1.2
0.19
0.05
Mbps
mA/Mbps
mA/Mbps
fr
IDDI (D)
IDDO (D)
All voltages are relative to their respective ground.
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
1
2
Rev. I | Page 5 of 32
ADuM1400/ADuM1401/ADuM1402
Data Sheet
ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION 1
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. These specifications do not apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 2.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM1400 Total Supply Current, Four Channels 2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1401 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 or VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 or VDD2 Supply Current
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM140xARW
Minimum Pulse Width 3
Maximum Data Rate 4
Propagation Delay 5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew 6
Channel-to-Channel Matching 7
Symbol
Min
Typ
Max Unit
IDDI (Q)
IDDO (Q)
0.26
0.11
0.31
0.14
mA
mA
IDD1 (Q)
IDD2 (Q)
1.2
0.5
1.9
0.9
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
4.5
1.4
6.5
2.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (90)
IDD2 (90)
37
11
65
15
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
IDD1 (Q)
IDD2 (Q)
1.0
0.7
1.6
1.2
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
3.7
2.2
5.4
3.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (90)
IDD2 (90)
30
18
52
27
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
IDD1 (Q), IDD2 (Q)
0.9
1.5
mA
DC to 1 MHz logic signal freq.
IDD1 (10), IDD2 (10)
3.0
4.2
mA
5 MHz logic signal freq.
IDD1 (90), IDD2 (90)
24
39
mA
45 MHz logic signal freq.
µA
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH,
VOCH, VODH
−10
+0.01 +10
1.6
0.4
(VDD1 or VDD2) − 0.1
(VDD1 or VDD2) − 0.4
VOAL, VOBL,
VOCL, VODL
3.0
2.8
0.0
0.04
0.2
PW
1
50
tPHL, tPLH
PWD
75
11
tPSK
tPSKCD/tPSKOD
Rev. I | Page 6 of 32
0.1
0.1
0.4
V
V
V
V
V
V
V
1000 ns
Mbps
100 ns
40
ns
ps/°C
50
ns
50
ns
Test Conditions
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Data Sheet
Parameter
ADuM140xBRW
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
Channel-to-Channel Matching, OpposingDirectional Channels7
ADuM140xCRW
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
Channel-to-Channel Matching, OpposingDirectional Channels7
For All Models
Output Disable Propagation Delay (High/Low to
High Impedance)
Output Enable Propagation Delay (High
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at Logic
High Output 8
Common-Mode Transient Immunity at Logic
Low Output8
Refresh Rate
Input Dynamic Supply Current per Channel 9
Output Dynamic Supply Current per Channel9
ADuM1400/ADuM1401/ADuM1402
Symbol
Min
Typ
PW
Max Unit
Test Conditions
100
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSK
tPSKCD
22
3
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
11.1
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPHL, tPLH
PWD
10
20
38
50
3
5
PW
tPSK
tPSKCD
16
2
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
tPHL, tPLH
PWD
90
20
8.3
120
34
0.5
3
45
2
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
tR/tF
|CMH|
25
3
35
|CML|
25
35
fr
IDDI (D)
1.1
0.10
IDDO (D)
0.03
ns
CL = 15 pF, CMOS signal levels
kV/µs VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Mbps
mA/
Mbps
mA/
Mbps
All voltages are relative to their respective ground.
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
1
2
Rev. I | Page 7 of 32
ADuM1400/ADuM1401/ADuM1402
Data Sheet
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION 1
5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all
minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications
are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.0 V. These specifications do not apply to ADuM1400W, ADuM1401W,
and ADuM1402W automotive grade versions.
Table 3.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
5 V/3 V Operation
3 V/5 V Operation
Output Supply Current per Channel, Quiescent
5 V/3 V Operation
3 V/5 V Operation
ADuM1400 Total Supply Current, Four Channels 2
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
90 Mbps (CRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
ADuM1401 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
Symbol
Min
Typ
Max
Unit
Test Conditions
0.50
0.26
0.53
0.31
mA
mA
0.11
0.19
0.14
0.21
mA
mA
2.2
1.2
2.8
1.9
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
0.5
0.9
0.9
1.4
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
8.6
4.5
10.6
6.5
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
1.4
2.6
2.0
3.5
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
70
37
100
65
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
11
18
15
25
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
1.8
1.0
2.4
1.6
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
0.7
1.2
1.2
1.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
7.1
3.7
9.0
5.4
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
2.2
4.1
3.0
5.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDDI (Q)
IDDO (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (10)
IDD2 (10)
IDD1 (90)
IDD2 (90)
IDD1 (Q)
IDD2 (Q)
IDD1 (10)
IDD2 (10)
Rev. I | Page 8 of 32
Data Sheet
Parameter
90 Mbps (CRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
ADuM1402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
90 Mbps (CRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
For All Models
Input Currents
Logic High Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM140xARW
Minimum Pulse Width 3
Maximum Data Rate 4
Propagation Delay 5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew 6
Channel-to-Channel Matching 7
ADuM140xBRW
Minimum Pulse Width3
ADuM1400/ADuM1401/ADuM1402
Symbol
Typ
Max
Unit
Test Conditions
57
30
82
52
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
18
31
27
43
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
1.5
0.9
2.1
1.5
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
0.9
1.5
1.5
2.1
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
5.6
3.0
7.0
4.2
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
3.0
5.6
4.2
7.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
44
24
62
39
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
24
44
39
62
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
+0.01
+10
µA
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
IDD1 (90)
IDD2 (90)
IDD1 (Q)
IDD2 (Q)
IDD1 (10)
IDD2 (10)
IDD1 (90)
IDD2 (90)
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
−10
2.0
1.6
V
V
VIL, VEL
0.8
0.4
VOAH, VOBH,
VOCH, VODH
VOAL, VOBL,
VOCL, VODL
(VDD1 or VDD2) − 0.1 (VDD1 or VDD2)
(VDD1 or VDD2) − 0.4 (VDD1 or VDD2) − 0.2
0.0
0.04
0.2
PW
tPHL, tPLH
PWD
1
50
70
0.1
0.1
0.4
PW
15
35
Rev. I | Page 9 of 32
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
50
50
ps/°C
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
100
ns
CL = 15 pF, CMOS signal levels
Mbps
CL = 15 pF, CMOS signal levels
ns
CL = 15 pF, CMOS signal levels
10
tPHL, tPLH
V
V
V
V
V
V
V
1000 ns
Mbps
100 ns
40
ns
11
tPSK
tPSKCD/tPSKOD
Maximum Data Rate4
Propagation Delay5
Min
50
ADuM1400/ADuM1401/ADuM1402
Parameter
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
Channel-to-Channel Matching, OpposingDirectional Channels7
ADuM140xCRW
Minimum Pulse Width3
Symbol
PWD
Max
3
Unit
ns
Test Conditions
CL = 15 pF, CMOS signal levels
tPSK
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
Channel-to-Channel Matching, OpposingDirectional Channels7
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
Output Enable Propagation Delay (High
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
3 V/5 V Operation
Common-Mode Transient Immunity at Logic
High Output 8
Common-Mode Transient Immunity at Logic
Low Output8
Refresh Rate
5 V/3 V Operation
3 V/5 V Operation
Input Dynamic Supply Current per Channel 9
5 V/3 V Operation
3 V/5 V Operation
Output Dynamic Supply Current per Channel9
5 V/3 V Operation
3 V/5 V Operation
Min
Typ
22
ps/°C
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
11.1
ns
CL = 15 pF, CMOS signal levels
Mbps
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
5
PW
Maximum Data Rate4
Propagation Delay5
Data Sheet
8.3
90
120
20
30
40
ns
0.5
2
ns
CL = 15 pF, CMOS signal levels
tPSK
14
ps/°C
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSKCD
2
ns
CL = 15 pF, CMOS signal levels
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
tPHL, tPLH
PWD
3
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
tR/tF
CL = 15 pF, CMOS signal levels
|CMH|
25
3.0
2.5
35
ns
ns
kV/µs
|CML|
25
35
kV/µs
1.2
1.1
Mbps
Mbps
0.19
0.10
mA/Mbps
mA/Mbps
0.03
0.05
mA/Mbps
mA/Mbps
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
fr
IDDI (D)
IDDO (D)
All voltages are relative to their respective ground.
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
1
2
Rev. I | Page 10 of 32
Data Sheet
ADuM1400/ADuM1401/ADuM1402
ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION 1
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. These specifications apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 4.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM1400W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1401W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1402W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current
10 Mbps (TRWZ Grade Only)
VDD1 or VDD2 Supply Current
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM140xWSRWZ
Minimum Pulse Width 3
Maximum Data Rate 4
Propagation Delay 5
Pulse Width Distortion, |tPLH − tPHL|5
Propagation Delay Skew 6
Channel-to-Channel Matching 7
Symbol
Typ
Max
Unit
IDDI (Q)
IDDO (Q)
0.50
0.19
0.53
0.21
mA
mA
IDD1 (Q)
IDD2 (Q)
2.2
0.9
2.8
1.4
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
8.6
2.6
10.6
3.5
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (Q)
IDD2 (Q)
1.8
1.2
2.4
1.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
7.1
4.1
9.0
5.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (Q), IDD2 (Q)
1.5
2.1
mA
DC to 1 MHz logic signal freq.
IDD1 (10), IDD2 (10)
5.6
7.0
mA
5 MHz logic signal freq.
µA
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH,
VOCH, VODH
Min
−10
+0.01 +10
2.0
0.8
(VDD1 or VDD2) − 0.1
(VDD1 or VDD2) − 0.4
VOAL, VOBL,
VOCL, VODL
5.0
4.8
0.0
0.04
0.2
PW
tPHL, tPLH
PWD
tPSK
tPSKCD/tPSKOD
1
50
Rev. I | Page 11 of 32
65
0.1
0.1
0.4
V
V
V
V
V
V
V
1000 ns
Mbps
100 ns
40
ns
50
ns
50
ns
Test Conditions
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
ADuM1400/ADuM1401/ADuM1402
Parameter
ADuM140xWTRWZ
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
Channel-to-Channel Matching, OpposingDirectional Channels7
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
Output Enable Propagation Delay (High
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at Logic
High Output 8
Common-Mode Transient Immunity at Logic
Low Output8
Refresh Rate
Input Dynamic Supply Current per Channel 9
Output Dynamic Supply Current per Channel9
Symbol
Data Sheet
Min
Typ
PW
Max
Unit
Test Conditions
100
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSK
tPSKCD
15
3
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
tPHL, tPLH
PWD
10
18
27
32
3
5
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
tR/tF
|CMH|
25
2.5
35
ns
kV/µs
|CML|
25
35
kV/µs
1.2
0.19
0.05
Mbps
mA/Mbps
mA/Mbps
fr
IDDI (D)
IDDO (D)
All voltages are relative to their respective ground.
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
1
2
Rev. I | Page 12 of 32
Data Sheet
ADuM1400/ADuM1401/ADuM1402
ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION 1
3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. These specifications apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 5.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM1400W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1401W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1402W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current
10 Mbps (TRWZ Grade Only)
VDD1 or VDD2 Supply Current
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM140xWSRWZ
Minimum Pulse Width 3
Maximum Data Rate 4
Propagation Delay 5
Pulse Width Distortion, |tPLH − tPHL|5
Propagation Delay Skew 6
Channel-to-Channel Matching 7
Symbol
Typ
Max
Unit
IDDI (Q)
IDDO (Q)
0.26
0.11
0.31
0.14
mA
mA
IDD1 (Q)
IDD2 (Q)
1.2
0.5
1.9
0.9
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
4.5
1.4
6.5
2.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (Q)
IDD2 (Q)
1.0
0.7
1.6
1.2
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
3.7
2.2
5.4
3.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (Q), IDD2 (Q)
0.9
1.5
mA
DC to 1 MHz logic signal freq.
IDD1 (10), IDD2 (10)
3.0
4.2
mA
5 MHz logic signal freq.
µA
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH,
VOCH, VODH
Min
−10
+0.01 +10
1.6
0.4
(VDD1 or VDD2) − 0.1
(VDD1 or VDD2) − 0.4
VOAL, VOBL,
VOCL, VODL
3.0
2.8
0.0
0.04
0.2
PW
tPHL, tPLH
PWD
tPSK
tPSKCD/tPSKOD
1
50
Rev. I | Page 13 of 32
75
0.1
0.1
0.4
V
V
V
V
V
V
V
1000 ns
Mbps
100 ns
40
ns
50
ns
50
ns
Test Conditions
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
ADuM1400/ADuM1401/ADuM1402
Parameter
ADuM140xWTRWZ
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
Channel-to-Channel Matching, OpposingDirectional Channels7
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
Output Enable Propagation Delay (High
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at Logic
High Output 8
Common-Mode Transient Immunity at Logic
Low Output8
Refresh Rate
Input Dynamic Supply Current per Channel 9
Output Dynamic Supply Current per Channel9
Symbol
Data Sheet
Min
Typ
PW
Max
Unit
Test Conditions
100
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSK
tPSKCD
22
3
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
tPHL, tPLH
PWD
10
20
34
45
3
5
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
tR/tF
|CMH|
25
3
35
ns
kV/µs
|CML|
25
35
kV/µs
1.1
0.10
0.03
Mbps
mA/Mbps
mA/Mbps
fr
IDDI (D)
IDDO (D)
All voltages are relative to their respective ground.
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
1
2
Rev. I | Page 14 of 32
Data Sheet
ADuM1400/ADuM1401/ADuM1402
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V, 125°C OPERATION 1
4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 5 V, VDD2 = 3.0 V. These specifications apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 6.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM1400W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1401W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1402W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
For All Models
Input Currents
Logic High Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM140xWSRWZ
Minimum Pulse Width 3
Maximum Data Rate 4
Propagation Delay 5
Pulse Width Distortion, |tPLH − tPHL|5
Propagation Delay Skew 6
Channel-to-Channel Matching 7
Symbol
Typ
Max Unit
IDDI (Q)
IDDO (Q)
0.50
0.11
0.53 mA
0.14 mA
IDD1 (Q)
IDD2 (Q)
2.2
0.5
2.8
0.9
IDD1 (10)
IDD2 (10)
8.6
1.4
10.6 mA
2.0
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (Q)
IDD2 (Q)
1.8
0.7
2.4
1.2
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
7.1
2.2
9.0
3.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (Q)
IDD2 (Q)
1.5
0.9
2.1
1.5
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
5.6
3.0
7.0
4.2
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
+0.01
+10
µA
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1
or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1
or VDD2
IIA, IIB, IIC,
IID, IE1, IE2
Min
−10
mA
mA
Test Conditions
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VIH, VEH
2.0
1.6
V
V
VIL, VEL
0.8
0.4
VOAH, VOBH,
VOCH, VODH
(VDD1 or VDD2) − 0.1
(VDD1 or VDD2) − 0.4
VOAL, VOBL,
VOCL, VODL
VDD1 or VDD2
VDD1, VDD2 − 0.2
0.0
0.1
0.04
0.1
0.2
0.4
PW
tPHL, tPLH
PWD
tPSK
tPSKCD/tPSKOD
1
50
Rev. I | Page 15 of 32
70
V
V
V
V
V
V
V
1000 ns
Mbps
100 ns
40
ns
50
ns
50
ns
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
ADuM1400/ADuM1401/ADuM1402
Parameter
ADuM140xWTRWZ
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
Channel-to-Channel Matching, OpposingDirectional Channels7
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
Output Enable Propagation Delay (High
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at Logic
High Output 8
Common-Mode Transient Immunity at Logic
Low Output8
Refresh Rate
Input Dynamic Supply Current per Channel9
Output Dynamic Supply Current per Channel9
Symbol
Data Sheet
Min
Typ
PW
Max Unit
Test Conditions
100
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSK
tPSKCD
22
3
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
tPHL, tPLH
PWD
10
20
30
40
3
5
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
tR/tF
|CMH|
25
3.0
35
ns
kV/µs
|CML|
25
35
kV/µs
1.2
0.19
0.03
Mbps
mA/Mbps
mA/Mbps
fr
IDDI (D)
IDDO (D)
All voltages are relative to their respective ground.
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
1
2
Rev. I | Page 16 of 32
Data Sheet
ADuM1400/ADuM1401/ADuM1402
ELECTRICAL CHARACTERISTICS—MIXED 3 V/5 V, 125°C OPERATION 1
3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V. These specifications apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 7.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM1400W, Total Supply Current, Four Channels 2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1401W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1402W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM140xWSRWZ
Minimum Pulse Width 3
Maximum Data Rate 4
Propagation Delay 5
Pulse Width Distortion, |tPLH − tPHL|5
Propagation Delay Skew 6
Channel-to-Channel Matching 7
Symbol
Typ
Max
Unit
IDDI (Q)
IDDO (Q)
0.26
0.19
0.31
0.21
mA
mA
IDD1 (Q)
IDD2 (Q)
1.2
0.9
1.9
1.4
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
4.5
2.6
6.5
3.5
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (Q)
IDD2 (Q)
1.0
1.2
1.6
1.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
3.7
4.1
5.4
5.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (Q)
IDD2 (Q)
0.9
1.5
1.5
2.1
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
3.0
5.6
4.2
7.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
+0.01
+10
µA
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH,
VOCH, VODH
VOAL, VOBL,
VOCL, VODL
Min
−10
1.6
PW
tPHL, tPLH
PWD
V
V
V
V
V
V
V
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
100
40
ns
Mbps
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
50
50
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
0.4
(VDD1 or VDD2) − 0.1 VDD1, VDD2
(VDD1 or VDD2) − 0.4 VDD1, VDD2 − 0.2
0.0
0.04
0.2
0.1
0.1
0.4
1000
1
50
70
tPSK
tPSKCD/tPSKOD
Rev. I | Page 17 of 32
Test Conditions
ADuM1400/ADuM1401/ADuM1402
Parameter
ADuM140xWTRWZ
Minimum Pulse Width3
Symbol
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
Channel-to-Channel Matching, OpposingDirectional Channels7
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
Output Enable Propagation Delay (High
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at Logic
High Output 8
Common-Mode Transient Immunity at Logic
Low Output8
Refresh Rate
Input Dynamic Supply Current per Channel9
Output Dynamic Supply Current per Channel9
Min
Typ
PW
Maximum Data Rate4
Propagation Delay5
Data Sheet
Max
Unit
Test Conditions
100
ns
CL = 15 pF, CMOS signal levels
10
tPHL, tPLH
20
30
PWD
40
Mbps
CL = 15 pF, CMOS signal levels
ns
CL = 15 pF, CMOS signal levels
3
ns
CL = 15 pF, CMOS signal levels
tPSK
22
ps/°C
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
5
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V, transient
magnitude = 800 V
tR/tF
|CMH|
25
2.5
35
ns
kV/µs
|CML|
25
35
kV/µs
1.1
0.10
0.05
Mbps
mA/Mbps
mA/Mbps
fr
IDDI (D)
IDDO (D)
All voltages are relative to their respective ground.
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
1
2
Rev. I | Page 18 of 32
Data Sheet
ADuM1400/ADuM1401/ADuM1402
PACKAGE CHARACTERISTICS
Table 8.
Parameter
Resistance (Input-to-Output) 1
Capacitance (Input-to-Output)1
Input Capacitance 2
IC Junction-to-Case Thermal Resistance, Side 1
IC Junction-to-Case Thermal Resistance, Side 2
Symbol
RI-O
CI-O
CI
θJCI
θJCO
Min
Typ
1012
2.2
4.0
33
28
Max
Unit
Ω
pF
pF
°C/W
°C/W
Test Conditions
f = 1 MHz
Thermocouple located at
center of package underside
Device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14,
Pin 15, and Pin 16 are shorted together.
2
Input capacitance is from any input data pin to ground.
1
REGULATORY INFORMATION
The ADuM140x are approved by the organizations listed in Table 9. Refer to Table 14 and the Insulation Lifetime section for details
regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 9.
UL
Recognized under
1577 Component
Recognition
Program 1
CSA
Approved under CSA Component
Acceptance Notice #5A
VDE
Certified according to DIN V VDE V
0884-10 (VDE V 0884-10):2006-12 2
Single protection,
2500 V rms
isolation voltage
Basic insulation per CSA 60950-1-03 and
IEC 60950-1, 800 V rms (1131 V peak)
maximum working voltage
Reinforced insulation per CSA 60950-1-03
and IEC 60950-1, 400 V rms (566 V peak)
maximum working voltage
File 205078
Reinforced insulation, 560 V peak
File E214100
1
2
File 2471900-4880-0001
TÜV
Approved according to:
IEC 61010-1:2001 (2nd Edition),
EN 61010-1:2001 (2nd Edition)
UL 61010-1:2004
CSA C22.2.61010.1:2005
Reinforced insulation,
400 V rms maximum working
voltage
Certificate U8V 05 06 56232 002
In accordance with UL 1577, each ADuM140x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA).
In accordance with DIN V VDE V 0884-10, each ADuM140x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection
limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 10.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol Value
2500
L(I01)
7.7 min
Unit Conditions
V rms 1-minute duration
mm
Measured from input terminals to output terminals,
shortest distance through air
8.1 min
mm
Measured from input terminals to output terminals,
shortest distance path along body
0.017 min mm
Insulation distance through insulation
>175
V
DIN IEC 112/VDE 0303 Part 1
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Minimum External Tracking (Creepage)
L(I02)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
Rev. I | Page 19 of 32
ADuM1400/ADuM1401/ADuM1402
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval.
Table 11.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
Input-to-Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Safety-Limiting Values
SAFETY-LIMITING CURRENT (mA)
Case Temperature
Side 1 Current
Side 2 Current
Insulation Resistance at TS
Conditions
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
Symbol
Characteristic
Unit
VIORM
VPR
I to IV
I to III
I to II
40/105/21
2
560
1050
V peak
V peak
896
672
V peak
V peak
VTR
4000
V peak
TS
IS1
IS2
RS
150
265
335
>109
°C
mA
mA
Ω
VPR
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
Transient overvoltage, tTR = 10 seconds
Maximum value allowed in the event of a failure
(see Figure 4)
VIO = 500 V
350
RECOMMENDED OPERATING CONDITIONS
300
Table 12.
Parameter
Operating Temperature (TA) 1
Operating Temperature (TA) 2
Supply Voltages (VDD1, VDD2)1, 3
Supply Voltages (VDD1, VDD2)2, 3
Input Signal Rise and Fall Times
250
SIDE #2
200
150
SIDE #1
100
Does not apply to ADuM1400W, ADuM1401W, and ADuM1402W automotive
grade versions.
Applies to ADuM1400W, ADuM1401W, and ADuM1402W automotive grade
versions.
3
All voltages are relative to their respective ground. See the DC Correctness
and Magnetic Field Immunity section for information on immunity to
external magnetic fields.
1
50
0
50
100
150
CASE TEMPERATURE (°C)
200
03786-004
2
0
Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
Rating
−40°C to +105°C
−40°C to +125°C
2.7 V to 5.5 V
3.0 V to 5.5 V
1.0 ms
Rev. I | Page 20 of 32
Data Sheet
ADuM1400/ADuM1401/ADuM1402
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 13.
Parameter
Storage Temperature (TST)
Ambient Operating Temperature (TA)1
Ambient Operating Temperature (TA)2
Supply Voltages (VDD1, VDD2)3
Input Voltage (VIA, VIB, VIC, VID, VE1, VE2)3, 4
Output Voltage (VOA, VOB, VOC, VOD)3, 4
Average Output Current per Pin5
Side 1 (IO1)
Side 2 (IO2)
Common-Mode Transients6
Rating
−65°C to +150°C
−40°C to +105°C
−40°C to +125°C
−0.5 V to +7.0 V
−0.5 V to VDDI + 0.5 V
−0.5 V to VDDO + 0.5 V
ESD CAUTION
−18 mA to +18 mA
−22 mA to +22 mA
−100 kV/µs to +100 kV/µs
Does not apply to ADuM1400W, ADuM1401W, and ADuM1402W
automotive grade versions.
Applies to ADuM1400W, ADuM1401W, and ADuM1402W automotive grade
versions.
3
All voltages are relative to their respective ground.
4
VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PC Board Layout section.
5
See Figure 4 for maximum rated current values for various temperatures.
6
This refers to common-mode transients across the insulation barrier.
Common-mode transients exceeding the Absolute Maximum Ratings
may cause latch-up or permanent damage.
1
2
Table 14. Maximum Continuous Working Voltage 1
Parameter
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
Basic Insulation
Reinforced Insulation
1
Max
565
Unit
V peak
Constraint
50-year minimum lifetime
1131
560
V peak
V peak
Maximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1131
560
V peak
V peak
Maximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Table 15. Truth Table (Positive Logic)
VIx Input 1
H
L
X
X
X
X
VEx Input1, 2
H or NC
H or NC
L
H or NC
L
X
VDDI State1
Powered
Powered
Powered
Unpowered
Unpowered
Powered
VDDO State1
Powered
Powered
Powered
Powered
Powered
Unpowered
VOx Output1
Notes
H
L
Z
H
Outputs return to the input state within 1 µs of VDDI power restoration.
Z
Indeterminate Outputs return to the input state within 1 µs of VDDO power restoration
if the VEx state is H or NC. Outputs return to a high impedance state
within 8 ns of VDDO power restoration if the VEx state is L.
VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VEx refers to the output enable signal on the same side as the VOx outputs. VDDI and
VDDO refer to the supply voltages on the input and output sides of the given channel, respectively.
2
In noisy environments, connecting VEx to an external logic high or low is recommended.
1
Rev. I | Page 21 of 32
ADuM1400/ADuM1401/ADuM1402
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1
16 VDD2
15 GND2*
VIA 3
ADuM1400
VIB 4
TOP VIEW
(Not to Scale)
VIC 5
14 VOA
13 VOB
12 VOC
VID 6
11 VOD
NC 7
10 VE2
*GND1 8
9
GND2*
NC = NO CONNECT
03786-005
*GND1 2
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 5. ADuM1400 Pin Configuration
Table 16. ADuM1400 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
VDD1
GND1
VIA
VIB
VIC
VID
NC
GND1
GND2
VE2
11
12
13
14
15
16
VOD
VOC
VOB
VOA
GND2
VDD2
Description
Supply Voltage for Isolator Side 1.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
No Connect.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected.
VOA, VOB, VOC, and VOD outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic
high or low is recommended.
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2.
Supply Voltage for Isolator Side 2.
Rev. I | Page 22 of 32
Data Sheet
ADuM1400/ADuM1401/ADuM1402
VDD1 1
16 VDD2
15 GND2*
VIA 3
ADuM1401
VIB 4
TOP VIEW
(Not to Scale)
VIC 5
14 VOA
13 VOB
12 VOC
VOD 6
11 VID
VE1 7
10 VE2
*GND1 8
9
GND2*
03786-006
*GND1 2
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 6. ADuM1401 Pin Configuration
Table 17. ADuM1401 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
Mnemonic
VDD1
GND1
VIA
VIB
VIC
VOD
VE1
8
9
10
GND1
GND2
VE2
11
12
13
14
15
16
VID
VOC
VOB
VOA
GND2
VDD2
Description
Supply Voltage for Isolator Side 1.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Output D.
Output Enable 1. Active high logic input. VOD output is enabled when VE1 is high or disconnected. VOD is disabled
when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is recommended.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 is high or disconnected. VOA,
VOB, and VOC outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or
low is recommended.
Logic Input D.
Logic Output C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2.
Supply Voltage for Isolator Side 2.
Rev. I | Page 23 of 32
ADuM1400/ADuM1401/ADuM1402
Data Sheet
VDD1 1
16 VDD2
15 GND2*
VIA 3
ADuM1402
VIB 4
TOP VIEW
(Not to Scale)
VOC 5
14 VOA
13 VOB
12 VIC
VOD 6
11 VID
VE1 7
10 VE2
*GND1 8
9
GND2*
03786-007
*GND1 2
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 7. ADuM1402 Pin Configuration
Table 18. ADuM1402 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
Mnemonic
VDD1
GND1
VIA
VIB
VOC
VOD
VE1
8
9
10
GND1
GND2
VE2
11
12
13
14
15
16
VID
VIC
VOB
VOA
GND2
VDD2
Description
Supply Voltage for Isolator Side 1.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Output C.
Logic Output D.
Output Enable 1. Active high logic input. VOC and VOD outputs are enabled when VE1 is high or disconnected. VOC and
VOD outputs are disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is
recommended.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA and VOB outputs are enabled when VE2 is high or disconnected. VOA and
VOB outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is
recommended.
Logic Input D.
Logic Input C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2.
Supply Voltage for Isolator Side 2.
Rev. I | Page 24 of 32
Data Sheet
ADuM1400/ADuM1401/ADuM1402
TYPICAL PERFORMANCE CHARACTERISTICS
20
80
15
60
CURRENT (mA)
CURRENT/CHANNEL (mA)
70
10
5V
50
40
5V
30
3V
3V
20
5
0
20
40
60
DATA RATE (Mbps)
80
100
0
03786-008
0
0
Figure 8. Typical Input Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation
40
60
DATA RATE (Mbps)
80
100
Figure 11. Typical ADuM1400 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
25
6
5
20
4
CURRENT (mA)
3
5V
2
15
10
5V
3V
3V
5
1
0
20
40
60
DATA RATE (Mbps)
80
100
0
03786-009
0
0
Figure 9. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
20
40
60
DATA RATE (Mbps)
80
100
03786-012
CURRENT/CHANNEL (mA)
20
03786-011
10
Figure 12. Typical ADuM1400 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
10
35
30
25
CURRENT (mA)
CURRENT/CHANNEL (mA)
8
6
4
5V
20
15
5V
10
3V
2
3V
0
20
40
60
DATA RATE (Mbps)
80
100
Figure 10. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (15 pF Output Load)
0
0
20
40
60
DATA RATE (Mbps)
80
100
Figure 13. Typical ADuM1401 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Rev. I | Page 25 of 32
03786-013
0
03786-010
5
ADuM1400/ADuM1401/ADuM1402
Data Sheet
40
40
35
PROPAGATION DELAY (ns)
25
20
5V
15
3V
10
3V
35
30
5V
0
0
20
40
60
DATA RATE (Mbps)
80
100
03786-014
5
Figure 14. Typical ADuM1401 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
45
40
CURRENT (mA)
35
30
25
20
5V
15
3V
10
20
60
40
DATA RATE (Mbps)
80
100
03786-015
5
0
–25
0
50
25
TEMPERATURE (°C)
75
Figure 16. Propagation Delay vs. Temperature, C Grade
50
0
25
–50
Figure 15. Typical ADuM1402 VDD1 or VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Rev. I | Page 26 of 32
100
03786-016
CURRENT (mA)
30
Data Sheet
ADuM1400/ADuM1401/ADuM1402
APPLICATIONS INFORMATION
PC BOARD LAYOUT
VDD1
GND1
VIA
VIB
VIC/VOC
VID/VOD
NC/VE1
GND1
VDD2
GND2
VOA
VOB
VOC/VIC
VOD/VID
VE2
GND2
03786-017
The ADuM140x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 17). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16
for VDD2. The capacitor value should be between 0.01 μF and
0.1 μF. The total lead length between both ends of the capacitor
and the input power supply pin should not exceed 20 mm.
Bypassing between Pin 1 and Pin 8 and between Pin 9 and
Pin 16 should also be considered, unless the ground pair on
each package side is connected close to the package.
Figure 17. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isolation
barrier is minimized. Furthermore, the board layout should be
designed such that any coupling that does occur equally affects
all pins on a given component side. Failure to ensure this could
cause voltage differentials between pins exceeding the Absolute
Maximum Ratings of the device, thereby leading to latch-up or
permanent damage.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a Logic 0 output may differ from the propagation delay
to a Logic 1 output.
The limitation on the magnetic field immunity of the ADuM140x
is set by the condition in which induced voltage in the receiving
coil of the transformer is sufficiently large enough to either
falsely set or reset the decoder. The following analysis defines
the conditions under which this may occur. The 3 V operating
condition of the ADuM140x is examined because it represents
the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt)∑∏rn2; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM140x and
an imposed requirement that the induced voltage be 50% at
most of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 19.
100
03786-018
tPHL
50%
Figure 18. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM140x component.
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
50%
tPLH
OUTPUT (VOx)
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1 μs, a
periodic set of refresh pulses indicative of the correct input state
are sent to ensure dc correctness at the output. If the decoder
receives no internal pulses of more than about 5 μs, the input
side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a default state (see Table 15)
by the watchdog timer circuit.
10
1
0.1
0.01
0.001
1k
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM140x
components operating under the same conditions.
10k
1M
10M
100k
MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 19. Maximum Allowable External Magnetic Flux Density
Rev. I | Page 27 of 32
03786-019
INPUT (VIx)
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
ADuM1400/ADuM1401/ADuM1402
Data Sheet
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse
(and has the worst-case polarity), it reduces the received pulse
from >1.0 V to 0.75 V—still well above the 0.5 V sensing
threshold of the decoder.
POWER CONSUMPTION
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM140x transformers. Figure 20 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown, the ADuM140x is extremely immune
and can be affected only by extremely large currents operated
at high frequency very close to the component. For the 1 MHz
example noted, one would have to place a 0.5 kA current 5 mm
away from the ADuM140x to affect the operation of the
component.
For each output channel, the supply current is given by
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
0.01
1k
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
03786-020
MAXIMUM ALLOWABLE CURRENT (kA)
1000
Figure 20. Maximum Allowable Current
for Various Current-to-ADuM140x Spacings
The supply current at a given channel of the ADuM140x isolator
is a function of the supply voltage, the data rate of the channel,
and the output load of the channel.
For each input channel, the supply current is given by
IDDI = IDDI (Q)
f ≤ 0.5 fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q)
f > 0.5 fr
IDDO = IDDO (Q)
f ≤ 0.5 fr
IDDO = (IDDO (D) + (0.5 × 10 ) × CL × VDDO) × (2f − fr) + IDDO (Q)
f > 0.5 fr
−3
where:
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz); it is half of the input
data rate expressed in units of Mbps.
fr is the input stage refresh rate (Mbps).
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
To calculate the total VDD1 and VDD2 supply current, the supply
currents for each input and output channel corresponding to
VDD1 and VDD2 are calculated and totaled. Figure 8 and Figure 9
provide per-channel supply currents as a function of data rate
for an unloaded output condition. Figure 10 provides perchannel supply current as a function of data rate for a 15 pF
output condition. Figure 11 through Figure 15 provide total
VDD1 and VDD2 supply current as a function of data rate for
ADuM1400/ADuM1401/ADuM1402 channel configurations.
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces
could induce error voltages sufficiently large enough to trigger
the thresholds of succeeding circuitry. Care should be taken in
the layout of such traces to avoid this possibility.
Rev. I | Page 28 of 32
Data Sheet
ADuM1400/ADuM1401/ADuM1402
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of
the voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM140x.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage. The values shown in Table 14 summarize the
peak voltage for 50 years of service life for a bipolar ac operating
condition and the maximum CSA/VDE approved working
voltages. In many cases, the approved working voltage is higher
than a 50-year service life voltage. Operation at these high working
voltages can lead to shortened insulation life in some cases.
In the case of unipolar ac or dc voltage, the stress on the
insulation is significantly lower, which allows operation at
higher working voltages while still achieving a 50-year service
life. The working voltages listed in Table 14 can be applied while
maintaining the 50-year minimum lifetime, provided the voltage
conforms to either the unipolar ac or dc voltage cases. Any crossinsulation voltage waveform that does not conform to Figure 22
or Figure 23 should be treated as a bipolar ac waveform, and its
peak voltage should be limited to the 50-year lifetime voltage
value listed in Table 14.
Note that the voltage presented in Figure 22 is shown as sinusoidal
for illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage cannot
cross 0 V.
RATED PEAK VOLTAGE
03786-021
INSULATION LIFETIME
0V
Figure 21. Bipolar AC Waveform
The insulation lifetime of the ADuM140x depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar
ac, or dc. Figure 21, Figure 22, and Figure 23 illustrate these
different isolation voltage waveforms, respectively.
03786-022
RATED PEAK VOLTAGE
0V
Figure 22. Unipolar AC Waveform
RATED PEAK VOLTAGE
03786-023
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the Analog Devices recommended maximum
working voltage.
0V
Figure 23. DC Waveform
Rev. I | Page 29 of 32
ADuM1400/ADuM1401/ADuM1402
Data Sheet
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
1
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
45°
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
8°
0°
0.33 (0.0130)
0.20 (0.0079)
1.27 (0.0500)
0.40 (0.0157)
03-27-2007-B
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 24. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model 1, 2, 3, 4
ADuM1400ARW
ADuM1400BRW
ADuM1400CRW
ADuM1400ARWZ
ADuM1400BRWZ
ADuM1400CRWZ
ADuM1400WSRWZ
ADuM1400WTRWZ
ADuM1401ARW
ADuM1401BRW
ADuM1401CRW
ADuM1401ARWZ
ADuM1401BRWZ
ADuM1401CRWZ
ADuM1401WSRWZ
ADuM1401WTRWZ
ADuM1402ARW
ADuM1402BRW
ADuM1402CRW
ADuM1402ARWZ
ADuM1402BRWZ
ADuM1402CRWZ
ADuM1402WSRWZ
ADuM1402WTRWZ
EVAL-ADuMQSEBZ
Number
of Inputs,
VDD1 Side
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
Number
of Inputs,
VDD2 Side
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
Maximum
Data Rate
(Mbps)
1
10
90
1
10
90
1
10
1
10
90
1
10
90
1
10
1
10
90
1
10
90
1
10
Maximum
Propagation
Delay, 5 V (ns)
100
50
32
100
50
32
100
32
100
50
32
100
50
32
100
32
100
50
32
100
50
32
100
32
Maximum
Pulse Width
Distortion (ns)
40
3
2
40
3
2
40
3
40
3
2
40
3
2
40
3
40
3
2
40
3
2
40
3
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
3
Tape and reel are available. The addition of an -RL suffix designates a 13” (1,000 units) tape and reel option.
4
No tape and reel option is available for the ADuM1402BRW model.
1
2
Rev. I | Page 30 of 32
Temperature
Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +125°C
−40°C to +125°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +125°C
−40°C to +125°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +125°C
−40°C to +125°C
Package
Description
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
Evaluation Board
Package
Option
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
Data Sheet
ADuM1400/ADuM1401/ADuM1402
AUTOMOTIVE PRODUCTS
The ADuM1400W/ADuM1401W/ADuM1402W models are available with controlled manufacturing to support the quality and reliability
requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial
models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products
shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product
ordering information and to obtain the specific Automotive Reliability reports for these models.
Rev. I | Page 31 of 32
ADuM1400/ADuM1401/ADuM1402
Data Sheet
NOTES
©2003–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03786-0-4/14(I)
Rev. I | Page 32 of 32