RF PLL Frequency Synthesizers ADF4116/ADF4117/ADF4118 FEATURES GENERAL DESCRIPTION ADF4116: 550 MHz ADF4117: 1.2 GHz ADF4118: 3.0 GHz 2.7 V to 5.5 V power supply Separate VP allows extended tuning voltage in 3 V systems Y Grade: −40°C to +125°C Dual-modulus prescaler ADF4116: 8/9 ADF4117/ADF4118: 32/33 3-wire serial interface Digital lock detect Power-down mode Fastlock mode The ADF411x family of frequency synthesizers can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. They consist of a low noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (5-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). APPLICATIONS All of the on-chip registers are controlled via a simple 3-wire interface. The devices operate with a power supply ranging from 2.7 V to 5.5 V and can be powered down when not in use. Base stations for wireless radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs Communications test equipment CATV equipment FUNCTIONAL BLOCK DIAGRAM AVDD DVDD VP CPGND REFERENCE ADF4116/ADF4117/ADF4118 14-BIT R COUNTER REFIN PHASE FREQUENCY DETECTOR 14 CHARGE PUMP CP R COUNTER LATCH 21-BIT INPUT REGISTER FUNCTION LATCH 19 A, B COUNTER LATCH SDOUT FROM FUNCTION LATCH LOCK DETECT 18 HIGH Z AVDD 13 MUX N = BP + A RFINA PRESCALER P/P + 1 RFINB 13-BIT B COUNTER SDOUT LOAD LOAD 5-BIT A COUNTER M3 M2 M1 FLO SWITCH 5 CE MUXOUT AGND DGND FLO 00392-001 CLK DATA LE Figure 1. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2000–2007 Analog Devices, Inc. All rights reserved. ADF4116/ADF4117/ADF4118 TABLE OF CONTENTS Features .............................................................................................. 1 Latch Summaries ........................................................................ 14 Applications....................................................................................... 1 Latch Maps .................................................................................. 15 General Description ......................................................................... 1 Function Latch................................................................................ 19 Functional Block Diagram .............................................................. 1 Counter Reset ............................................................................. 19 Revision History ............................................................................... 2 Power-Down ............................................................................... 19 Specifications..................................................................................... 3 MUXOUT Control..................................................................... 19 Timing Characteristics ................................................................ 5 Phase Detector Polarity ............................................................. 19 Absolute Maximum Ratings............................................................ 6 Charge Pump Three-State......................................................... 19 ESD Caution.................................................................................. 6 Fastlock Enable Bit ..................................................................... 19 Pin Configuration and Function Descriptions............................. 7 Fastlock Mode Bit....................................................................... 19 Typical Performance Characteristics ............................................. 8 Timer Counter Control ............................................................. 19 Circuit Description......................................................................... 12 Initialization Latch ..................................................................... 20 Reference Input Section............................................................. 12 Device Programming After Initial Power-Up ........................ 20 RF Input Stage............................................................................. 12 Applications Information .............................................................. 21 Prescaler (P/P + 1)...................................................................... 12 Local Oscillator for the GSM Base Station Transmitter........ 21 A Counter and B Counter ......................................................... 12 Shutdown Circuit ....................................................................... 21 R Counter .................................................................................... 12 Direct Conversion Modulator .................................................. 21 Phase Frequency Detector (PFD) and Charge Pump............ 13 Interfacing ................................................................................... 24 MUXOUT and Lock Detect...................................................... 13 Outline Dimensions ....................................................................... 25 Input Shift Register..................................................................... 13 Ordering Guide .......................................................................... 25 REVISION HISTORY 4/07—Rev. C to Rev. D Changes to REFIN Characteristics Section..................................... 3 Changes to Table 4............................................................................ 7 Changes to Figure 35...................................................................... 22 Changes to Ordering Guide .......................................................... 25 9/04—Rev. A to Rev. B Changes to Specifications.................................................................3 Changes to Ordering Guide .......................................................... 25 3/01—Rev. 0 to Rev. A 4/00—Rev. 0: Initial Version 11/05—Rev. B to Rev. C Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 5 Changes to Table 3............................................................................ 6 Changes to Table 4............................................................................ 7 Changed OSC 3B1-13M0 to FOX801BH-130 ............................ 21 Changes to Ordering Guide .......................................................... 25 Rev. D | Page 2 of 28 ADF4116/ADF4117/ADF4118 SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 1. Parameter RF CHARACTERISTICS RF Input Sensitivity RF Input Frequency ADF4116 ADF4117 ADF4118 Maximum Allowable Prescaler Output Frequency 3 REFIN CHARACTERISTICS Reference Input Frequency Reference Input Sensitivity 4,5 REFIN Input Capacitance REFIN Input Current PHASE DETECTOR FREQUENCY5 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance Reference Input Current LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage B Version 1 Y Version 2 Unit Test Conditions/Comments −15 to 0 −10 to 0 −10 to 0 −10 to 0 dBm min to max dBm min to max AVDD = 3 V AVDD = 5 V See Figure 26 for input circuit 80 to 550 45 to 550 0.1 to 1.2 0.1 to 3.0 0.2 to 3.0 165 200 MHz min to max MHz min to max 165 200 GHz min to max GHz min to max GHz min to max MHz max MHz max 5 to 100 0.4 to AVDD 0.7 to AVDD 10 ±100 55 5 to 100 0.4 to AVDD 0.7 to AVDD 10 ±100 55 MHz min to max V p-p min to max V p-p min to max pF max μA max MHz max 1 250 2.5 3 1 3 2 2 1 250 2.5 25 16 3 2 2 mA typ μA typ % typ nA max nA typ % typ % typ % typ 0.8 × DVDD 0.2 × DVDD ±1 10 ±100 0.8 × DVDD 0.2 × DVDD ±1 10 ± 100 V min V max μA max pF max μA max DVDD − 0.4 0.4 DVDD − 0.4 0.4 V min V max 0.1 to 3.0 Rev. D | Page 3 of 28 Input level = −8 dBm; for lower frequencies, ensure slew rate (SR) > 36 V/μs Input level = −10 dBm Input level = −15 dBm AVDD, DVDD = 3 V AVDD, DVDD = 5 V For f < 5 MHz, ensure SR > 100 V/μs AVDD = 3.3 V, biased at AVDD/2 For f ≥ 10 MHz, AVDD = 5 V, biased at AVDD/2 0.5 V ≤ VCP ≤ VP − 0.5 0.5 V ≤ VCP ≤ VP − 0.5 VCP = VP/2 IOH = 500 μA IOL = 500 μA ADF4116/ADF4117/ADF4118 Parameter POWER SUPPLIES AVDD DVDD VP IDD (AIDD + DIDD) 6 ADF4116 ADF4117 ADF4118 IP Low-Power Sleep Mode NOISE CHARACTERISTICS ADF4118 Normalized Phase Noise Floor 7 Phase Noise Performance 8 ADF4116 540 MHz Output 9 ADF4117 900 MHz Output 10 ADF4118 900 MHz Output10 ADF4117 836 MHz Output 11 ADF4118 1750 MHz Output 12 ADF4118 1750 MHz Output 13 ADF4118 1960 MHz Output 14 Spurious Signals ADF4116 540 MHz Output10 ADF4117 900 MHz Output10 ADF4118 900 MHz Output 10 ADF4117 836 MHz Output11 ADF4118 1750 MHz Output12 ADF4118 1750 MHz Output13 ADF4118 1960 MHz Output14 B Version 1 Y Version 2 Unit 2.7 to 5.5 AVDD AVDD to 6.0 2.7 to 5.5 AVDD AVDD to 6.0 V min to V max V min to V max AVDD ≤ VP ≤ 6.0 V 5.5 5.5 7.5 0.4 1 7.5 0.4 1 mA max mA max mA max mA max μA typ 4.5 mA typical 4.5 mA typical 6.5 mA typical TA = 25°C −213 −213 dBc/Hz typ −89 −87 −90 −78 −85 −65 −84 −89 −87 −90 −78 −85 −65 −84 dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ @ VCO output @ 1 kHz offset and 200 kHz PFD frequency @ 1 kHz offset and 200 kHz PFD frequency @ 1 kHz offset and 200 kHz PFD frequency @ 300 Hz offset and 30 kHz PFD frequency @ 1 kHz offset and 200 kHz PFD frequency @ 200 Hz offset and 10 kHz PFD frequency @ 1 kHz offset and 200 kHz PFD frequency −88/−99 −90/−104 −91/−100 −80/−84 −88/−90 −65/−73 −80/−86 −88/−99 −90/−104 −91/−100 −80/−84 −88/−90 −65/−73 −80/−86 dBc typ dBc typ dBc typ dBc typ dBc typ dBc typ dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency @ 200 kHz/400 kHz and 200 kHz PFD frequency @ 200 kHz/400 kHz and 200 kHz PFD frequency @ 30 kHz/60 kHz and 30 kHz PFD frequency @ 200 kHz/400 kHz and 200 kHz PFD frequency @ 10 kHz/20 kHz and 10 kHz PFD frequency @ 200 kHz/400 kHz and 200 kHz PFD frequency 1 Test Conditions/Comments Operating temperature range for the B version is −40°C to +85°C. Operating temperature range for the Y version is −40°C to +125°C. 3 This is the maximum operating frequency of the CMOS counters. 4 AC coupling ensures AVDD/2 bias. See Figure 35 for typical circuit. 5 Guaranteed by design. 6 TA = 25°C; AVDD = DVDD = 3 V; RFIN for ADF4116 = 540 MHz; RFIN for ADF4117, ADF4118 = 900 MHz. 7 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PN TOT, and subtracting 20logN (where N is the N divider value) and 10logFPFD: PNSYNTH = PNTOT – 10logFPFD – 20logN. 8 The phase noise is measured with the EVAL-ADF411xEB and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). 9 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; loop bandwidth = 20 kHz. 10 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop bandwidth = 20 kHz. 11 fREFIN = 10 MHz; fPFD = 30 kHz; offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; loop bandwidth = 3 kHz. 12 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; loop bandwidth = 20 kHz. 13 fREFIN = 10 MHz; fPFD = 10 kHz; offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; loop bandwidth = 1 kHz. 14 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; loop bandwidth = 20 kHz. 2 Rev. D | Page 4 of 28 ADF4116/ADF4117/ADF4118 TIMING CHARACTERISTICS AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤ VP < 6.0 V; AGND = DGND = CPGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Guaranteed by design, but not production tested. Table 2. Parameter t1 t2 t3 t4 t5 t6 Limit at TMIN to TMAX (B, Y Version) 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min t3 Test Conditions/Comments DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width t4 CLK t1 DATA DB20 (MSB) t2 DB19 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 LE 00392-002 t5 LE Figure 2. Timing Diagram Rev. D | Page 5 of 28 ADF4116/ADF4117/ADF4118 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND1 AVDD to DVDD VP to GND1 VP to AVDD Digital I/O Voltage to GND1 Analog I/O Voltage to GND1 REFIN, RFINA, RFINB to GND1 RFINA to RFINB Operating Temperature Range Industrial (B Version) Extended (Y Version) Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature Transistor Count CMOS Bipolar 1 Rating −0.3 V to +7 V −0.3 V to +0.3 V −0.3 V to +7 V −0.3 V to +5.5 V −0.3 V to VDD + 0.3 V −0.3 V to VP + 0.3 V −0.3 V to VDD + 0.3 V ±320 mV −40°C to +85°C −40°C to +125°C −65°C to +150°C 150°C 112°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. ESD CAUTION 260°C 40 sec 6425 303 GND = AGND = DGND = 0 V. Rev. D | Page 6 of 28 ADF4116/ADF4117/ADF4118 FLO 1 16 VP CP 2 15 DVDD CPGND 3 14 MUXOUT AGND 4 13 LE RFINB 5 12 DATA RFINA 6 11 CLK AVDD 7 10 CE REFIN 8 9 ADF4116/ ADF4117/ ADF4118 TOP VIEW (Not to Scale) DGND 00392-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic FLO 2 CP 3 4 5 CPGND AGND RFINB 6 7 RFINA AVDD 8 REFIN 9 10 DGND CE 11 CLK 12 DATA 13 LE 14 MUXOUT 15 DVDD 16 VP Description Fast Lock Switch Output. This can be used to switch an external resistor to change the loop filter bandwidth and speed up locking the PLL. Charge Pump Output. When enabled, this provides the ± ICP to the external loop filter, which in turn drives the external VCO. Charge Pump Ground. This is the ground return path for the charge pump. Analog Ground. This is the ground return path for the prescaler. Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. See Figure 26. Input to the RF Prescaler. This small signal input is ac-coupled from the VCO. Analog Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AVDD must have the same value as DVDD. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 kΩ. See Figure 25. The oscillator input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. Digital Ground. Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode. Taking the pin high powers up the device depending on the status of the power-down bit F2. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 21-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. Digital Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground plane (1 μF, 1 nF) should be placed as close as possible to this pin. For best performance, the 1 μF capacitor should be placed within 2 mm of the pin. The placing of the 1 nF capacitor is less critical, but should still be within 5 mm of the pin. DVDD must have the same value as AVDD. Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, this supply can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V. Rev. D | Page 7 of 28 ADF4116/ADF4117/ADF4118 TYPICAL PERFORMANCE CHARACTERISTICS 10dB/DIVISION –40 FREQ- PARAM-TYPE DATA-FORMAT KEYWORD IMPEDANCEUNIT OHMS GHz S MA R 50 FREQ MagS11 AngS11 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.89207 0.8886 0.89022 0.96323 0.90566 0.90307 0.89318 0.89806 0.89565 0.88538 0.89699 0.89927 0.87797 0.90765 0.88526 0.81267 0.90357 0.92954 –2.0571 –4.4427 –6.3212 –2.1393 –12.13 –13.52 –15.746 –18.056 –19.693 –22.246 –24.336 –25.948 –28.457 –29.735 –31.879 –32.681 –31.522 –34.222 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 0.92087 0.93788 0.9512 0.93458 0.94782 0.96875 0.92216 0.93755 0.96178 0.94354 0.95189 0.97647 0.98619 0.95459 0.97945 0.98864 0.97399 0.97216 –36.961 –39.343 –40.134 –43.747 –44.393 –46.937 –49.6 –51.884 –51.21 –53.55 –56.786 –58.781 –60.545 –61.43 –61.241 –64.051 –66.19 –63.775 –50 0.64° rms –60 –70 –80 –90 –100 –110 –120 –130 –140 100Hz 0 10dB/DIVISION –40 VDD = 3V VP = 3V –15 –20 –25 TA = –40°C –35 0.575° rms 0.5 1.5 2.0 2.5 3.0 1.0 RF INPUT FREQUENCY (GHz) 3.5 –80 –90 –100 –110 –120 00392-008 TA = +25°C 0 RMS NOISE = 0.575° –70 00392-005 TA = +85°C –40 –130 4.0 –140 100Hz FREQUENCY OFFSET FROM 900MHz CARRIER 1MHz Figure 8. ADF4118 Integrated Phase Noise (900 MHz, 200 kHz, 20 kHz, Typical Lock Time: 400 μs) Figure 5. Input Sensitivity (ADF4118) 0 0 REFERENCE LEVEL = –4.2dBm –10 VDD = 3V, VP = 5V –10 ICP = 1mA REFERENCE LEVEL = –3.8dBm VDD = 3V, VP = 5V ICP = 1mA –20 PFD FREQUENCY = 200kHz –20 PFD FREQUENCY = 200kHz –30 LOOP BANDWIDTH = 20kHz –30 LOOP BANDWIDTH = 20kHz OUTPUT POWER (dB) RES. BANDWIDTH = 10Hz –40 VIDEO BANDWIDTH = 10Hz –50 SWEEP = 1.9 SECONDS AVERAGES = 22 –60 –90.2dBc/Hz –70 VIDEO BANDWIDTH = 1kHz –50 SWEEP = 2.5 SECONDS AVERAGES = 4 –60 –70 –91.5dBc –80 00392-006 –80 –90 –100 RES. BANDWIDTH = 1kHz –40 –2kHz –1kHz 900MHz 1kHz 00392-009 OUTPUT POWER (dB) RL = –40dBc/Hz –60 –30 1MHz –50 PHASE NOISE (dBc/Hz) RF INPUT POWER (dBm) –10 –45 FREQUENCY OFFSET FROM 900MHz CARRIER Figure 7. ADF4118 Integrated Phase Noise (900 MHz, 200 kHz, 35 kHz, Typical Lock Time: 200 μs) Figure 4. S-Parameter Data for the ADF4118 RF Input (Up to 1.8 GHz) –5 RMS NOISE = 0.64° 00392-007 AngS11 PHASE NOISE (dBc/Hz) MagS11 00392-004 FREQ RL = –40dBc/Hz –90 –100 2kHz –400kHz –200kHz 900MHz 200kHz Figure 9. ADF4118 Reference Spurs (900 MHz, 200 kHz, 20 kHz) Figure 6. ADF4118 Phase Noise (900 MHz, 200 kHz, 20 kHz) Rev. D | Page 8 of 28 400kHz ADF4116/ADF4117/ADF4118 0 REFERENCE LEVEL = –4.2dBm –10 –20 0 VDD = 3V, VP = 5V ICP = 1mA –10 PFD FREQUENCY = 200kHz –20 REFERENCE LEVEL = –7.0dBm PFD FREQUENCY = 30kHz LOOP BANDWIDTH = 5kHz RES. BANDWIDTH = 1kHz –40 VIDEO BANDWIDTH = 1kHz OUTPUT POWER (dB) SWEEP = 2.5 SECONDS –50 AVERAGES = 10 –60 –70 –90.67dBc –80 RES. BANDWIDTH = 300Hz –40 VIDEO BANDWIDTH = 300Hz SWEEP = 4.2ms –50 AVERAGES = 20 –60 –72.3dBc –70 00392-010 –80 –90 –100 –30 –400kHz –200kHz 900MHz 200kHz 00392-013 OUTPUT POWER (dB) LOOP BANDWIDTH = 35kHz –30 –90 –100 400kHz –60kHz Figure 10. ADF4118 Reference Spurs (900 MHz, 200 kHz, 35 kHz) 0 REFERENCE LEVEL = –7.0dBm –10 ICP = 1mA RES. BANDWIDTH = 10kHz –40 VIDEO BANDWIDTH = 10kHz SWEEP = 477ms AVERAGES = 25 –60 –70 –71.5dBc/Hz 60kHz VDD = 3V, VP = 5V ICP = 1mA LOOP BANDWIDTH = 100kHz –30 RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz –40 SWEEP = 1.9 SECONDS –50 AVERAGES = 26 –60 –85.2dBc/Hz –70 –400kHz –200kHz 1750MHz 200kHz 00392-014 00392-011 –80 –90 –90 –100 400kHz –2kHz 10dB/DIVISION –40 RL = –40dBc/Hz RMS NOISE = 2.0° 10dB/DIVISION –40 1kHz 2kHz RL = –40dBc/Hz RMS NOISE = 1.552° 1.55° rms 2.0° rms PHASE NOISE (dBc/Hz) –60 –70 –80 –90 –100 –110 –70 –80 –90 –100 –110 00392-012 –130 FREQUENCY OFFSET FROM 1.75GHz CARRIER 00392-015 –120 –120 –140 100Hz 2800MHz –50 –50 –60 –1kHz Figure 14. ADF4118 Phase Noise (2800 MHz, 1 MHz, 100 kHz) Figure 11. ADF4118 Phase Noise (1750 MHz, 30 kHz, 3 kHz) PHASE NOISE (dBc/Hz) 30kHz PFD FREQUENCY = 1MHz –20 OUTPUT POWER (dB) OUTPUT POWER (dB) REFERENCE LEVEL = –10.3dBm –10 LOOP BANDWIDTH = 5kHz –80 1750MHz 0 VDD = 3V, VP = 5V –30 –50 –30kHz Figure 13. ADF4118 Reference Spurs (1750 MHz, 30 kHz, 3 kHz) PFD FREQUENCY = 30kHz –20 –100 VDD = 3V, VP = 5V ICP = 5mA –130 –140 100Hz 1MHz FREQUENCY OFFSET FROM 2.8GHz CARRIER Figure 15. ADF4118 Integrated Phase Noise (2800 MHz, 1 MHz, 100 kHz) Figure 12. ADF4118 Integrated Phase Noise (1750 MHz, 30 kHz, 3 kHz) Rev. D | Page 9 of 28 1MHz ADF4116/ADF4117/ADF4118 REFERENCE LEVEL = –9.3dBm –10 ICP = 1mA LOOP BANDWIDTH = 100kHz –30 RES. BANDWIDTH = 3kHz VIDEO BANDWIDTH = 3kHz –40 SWEEP = 1.4 SECONDS –50 AVERAGES = 4 –60 –77.3dBc –70 00392-016 –80 –90 –100 –2MHz –1MHz 2800MHz 1MHz VDD = 3V VP = 5V FIRST REFERENCE SPUR (dBc) PFD FREQUENCY = 1MHz –20 OUTPUT POWER (dB) –60 VDD = 3V, VP = 5V –70 –80 –90 –100 –40 2MHz 00392-019 0 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 16. ADF4118 Reference Spurs (2800 MHz, 1 MHz, 100 kHz) Figure 19. ADF4118 Reference Spurs vs. Temperature (900 MHz, 200 kHz, 20 kHz) –130 5 PHASE NOISE (dBc/Hz) –140 –145 –150 –155 –160 –165 –175 00392-017 –170 1 100 1000 10 PHASE DETECTOR FREQUENCY (kHz) –15 –25 –35 –45 –55 –65 –75 –85 00392-020 FIRST REFERENCE SPUR (dBc) –135 VDD = 3V VP = 5V –5 VDD = 3V VP = 5V –95 –105 10000 0 1 2 3 Figure 17. ADF4118 Phase Noise (Referred to CP Output) vs. PFD Frequency Figure 20. ADF4118 Reference Spurs (200 kHz) vs. VTUNE (900 MHz, 200 kHz, 20 kHz) –60 –60 VDD = 3V VP = 5V –80 –90 –20 0 20 40 60 80 –70 –80 –90 100 TEMPERATURE (°C) 00392-021 PHASE NOISE (dBc/Hz) –70 00392-018 PHASE NOISE (dBc/Hz) VDD = 3V VP = 5V –100 –40 5 4 TUNING VOLTAGE 0 20 40 60 80 TEMPERATURE (°C) Figure 18. ADF4118 Phase Noise vs. Temperature (900 MHz, 200 kHz, 20 kHz) Figure 21. ADF4118 Phase Noise vs. Temperature (836 MHz, 30 kHz, 3 kHz) Rev. D | Page 10 of 28 100 ADF4116/ADF4117/ADF4118 1.2 –60 1.0 0.6 ICP (mA) 0.4 –80 0.2 0 –0.2 –0.4 –90 –0.6 0 20 40 60 80 –1.0 –1.2 100 0 TEMPERATURE (°C) Figure 22. ADF4118 Reference Spurs vs. Temperature (836 MHz, 30 kHz, 3 kHz) 2.5 2.0 1.5 1.0 00392-023 0.5 0 50 100 150 0.5 1.0 1.5 2.0 2.5 3.0 VCP (V) 3.5 4.0 Figure 24. Charge Pump Output Characteristics 3.0 0 00392-024 –0.8 –100 DIDD (mA) VP = 5V ICP SETTING: 1mA 0.8 –70 00392-022 FIRST REFERENCE SPUR (dBc) VDD = 3V VP = 5V 200 PRESCALER OUTPUT FREQUENCY (MHz) Figure 23. DIDD vs. Prescaler Output Frequency Rev. D | Page 11 of 28 4.5 5.0 ADF4116/ADF4117/ADF4118 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION A COUNTER AND B COUNTER The reference input stage is shown in Figure 25. SW1 and SW2 are normally closed switches; SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. The A CMOS counter and B CMOS counter combine with the dual-modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the prescaler output is 200 MHz or less. POWER-DOWN CONTROL NC REFIN NC The A counter and B counter, in conjunction with the dualmodulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by R. The equation for the VCO frequency is as follows: 100kΩ SW2 Pulse Swallow Function TO R COUNTER fVCO = [(P × B ) + A]× f REFIN / R BUFFER SW1 00392-025 SW3 NO where: Figure 25. Reference Input Stage fVCO is the output frequency of external voltage controlled oscillator (VCO). P is the preset modulus of dual-modulus prescaler. B is the preset divide ratio of binary 13-bit counter (3 to 8191). A is the preset divide ratio of binary 5-bit swallow counter (0 to 31). fREFIN is the output frequency of the external reference frequency oscillator. R is the preset divide ratio of binary 14-bit programmable reference counter (1 to 16,383). RF INPUT STAGE The RF input stage is shown in Figure 26. It is followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the prescaler. BIAS GENERATOR 500Ω 1.6V AVDD 500Ω R COUNTER RFINA The 14-bit R counter allows the input reference frequency to be divided down to produce the input clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed. N = BP + A Figure 26. RF Input Stage FROM RF INPUT STAGE PRESCALER (P/P + 1) The dual-modulus prescaler (P/P + 1), along with the A counter and B counter, enables the large division ratio, N, to be realized (N = PB + A). The dual-modulus prescaler takes the CML clock from the RF input stage and divides it down to a manageable frequency for the CMOS A counter and CMOS B counter. The prescaler is programmable. It can be set in software to 8/9 for the ADF4116 and to 32/33 for the ADF4117 and ADF4118. It is based on a synchronous 4/5 core. Rev. D | Page 12 of 28 13-BIT B COUNTER PRESCALER P/P + 1 MODULUS CONTROL TO PFD LOAD LOAD 5-BIT A COUNTER Figure 27. A Counter and B Counter 00392-027 AGND 00392-026 RFINB ADF4116/ADF4117/ADF4118 MUXOUT AND LOCK DETECT The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 28 is a simplified schematic of the PFD. The PFD includes a fixed delay element that sets the width of the antibacklash pulse. This is typically 3 ns. This pulse ensures that there is no dead zone in the PFD transfer function and gives a consistent reference spur level. VP HI D1 Q1 The output multiplexer on the ADF411x family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. Figure 33 shows the full truth table. Figure 29 shows the MUXOUT section in block diagram form. DVDD ANALOG LOCK DETECT DIGITAL LOCK DETECT R COUNTER OUTPUT N COUNTER OUTPUT SDOUT CHARGE PUMP UP U1 MUX MUXOUT CONTROL R DIVIDER CLR1 DGND Figure 29. MUXOUT Circuit CP DELAY 00392-029 PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP U3 Lock Detect MUXOUT can be programmed for both digital lock detect and analog lock detect. CLR2 HI D2 Q2 DOWN Digital lock detect is active high. It is set high when the phase error on three consecutive phase detector cycles is less than 15 ns. It stays set high until a phase error greater than 25 ns is detected on any subsequent PD cycle. U2 N DIVIDER CPGND The N channel, open-drain, analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When lock is detected, it is high with narrow low going pulses. R DIVIDER CP OUTPUT Figure 28. PFD Simplified Schematic and Timing (In Lock) 00392-028 N DIVIDER INPUT SHIFT REGISTER The ADF411x family digital section includes a 21-bit input shift register, a 14-bit R counter, and an 18-bit N counter, comprising a 5-bit A counter and a 13-bit B counter. Data is clocked into the 21-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs, DB1 and DB0, as shown in the timing diagram in Figure 2. The truth table for these bits is shown in Figure 34. Table 5 summarizes how the latches are programmed. Table 5. Programming Data Latches C2 0 0 1 1 Rev. D | Page 13 of 28 Control Bits C1 0 1 0 1 Data Latch R Counter N Counter (A and B) Function Latch Initialization Latch ADF4116/ADF4117/ADF4118 LATCH SUMMARIES LOCK DETECT PRECISION REFERENCE COUNTER LATCH TEST MODE BITS CONTROL BITS 14-BIT REFERENCE COUNTER, R DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LDP T4 T3 T2 T1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) CP GAIN AB COUNTER LATCH 13-BIT B COUNTER CONTROL BITS 5-BIT A COUNTER DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A5 A4 A3 A2 A1 C2 (0) C1 (1) RESERVED POWERDOWN 2 FASTLOCK MODE RESERVED FASTLOCK ENABLE CP THREESTATE PHASE DETECTOR POLARITY POWERDOWN 1 COUNTER RESET FUNCTION LATCH DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X PD2 X X X TC4 TC3 TC2 TC1 F6 X F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0) TIMER COUNTER CONTROL RESERVED MUXOUT CONTROL CONTROL BITS RESERVED POWERDOWN 2 FASTLOCK MODE RESERVED FASTLOCK ENABLE CP THREESTATE PHASE DETECTOR POLARITY POWERDOWN 1 COUNTER RESET INITIALIZATION LATCH DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X PD2 X X X TC4 TC3 TC2 TC1 F6 X F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (1) Figure 30. ADF411x family Latch Summary Rev. D | Page 14 of 28 MUXOUT CONTROL CONTROL BITS 00392-030 TIMER COUNTER CONTROL RESERVED ADF4116/ADF4117/ADF4118 LOCK DETECT PRECISION LATCH MAPS TEST MODE BITS CONTROL BITS 14-BIT REFERENCE COUNTER, R DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LDP T4 T3 T2 T1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) R14 R13 R12 •• • •• • • • • • R3 R2 R1 DIVIDE RATIO 0 0 0 •• • • • • •• • • 0 0 1 1 0 0 0 •• • • • • •• • • 0 1 0 2 0 0 0 •• • • • • •• • • 0 1 1 3 0 0 0 •• • • • • •• • • 1 0 0 4 • • • •• • • • • •• • • • • • • • • • •• • • • • •• • • • • • • • • • •• • • • • •• • • • • • • 1 1 1 •• • • • • •• • • 1 0 0 163 80 1 1 1 •• • • • • •• • • 1 0 1 163 81 1 1 1 •• • • • • •• • • 1 1 0 163 82 1 1 1 • •• • • • • •• • 1 1 1 163 83 TEST MODE BITS SHOULD BE SET TO 0000 FOR NORMAL OPERATION 0 1 OPERATION 3 CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. 5 CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. 00392-031 LDP Figure 31. Reference Counter Latch Map Rev. D | Page 15 of 28 CP GAIN ADF4116/ADF4117/ADF4118 13-BIT B COUNTER CONTROL BITS 5-BIT A COUNTER DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A5 A4 A3 A2 A1 C2 (0) C1 (1) ADF4116 ADF4117/ADF4118 A4 A3 A2 A1 A COUNTER DIVIDE RATIO X X 0 0 0 0 X X 0 0 1 1 • • • • • • • • • • • • X X 1 1 0 6 X X 1 1 1 7 A5 A4 A3 A2 A1 A COUNTER DIVIDE RATIO 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 • • • • • • • • • • • • 1 1 1 0 1 29 1 1 1 1 0 30 1 1 1 1 1 31 B13 B12 B11 • • • •• • • • • • B3 B2 B1 B COUNTER DIVIDE RATIO 0 0 0 • • •• • • • • •• 0 0 1 NOT ALLOWED 0 0 0 • • •• • • • • •• 0 1 0 NOT ALLOWED 0 0 0 • • •• • • • • •• 0 1 1 3 0 0 0 • • •• • • • • •• 1 0 0 4 • • • • • •• • • • • •• • • • • • • • • • •• • • • • •• • • • • • • • • • •• • • • • •• • • • • 1 1 1 • • •• • • • • •• 1 0 0 8188 1 1 1 • • •• • • • • •• 1 0 1 8189 1 1 1 • • •• • • • • •• 1 1 0 8190 1 1 1 • • • •• • • • • • 1 1 1 8191 CURRENT SETTINGS 0 250µA 1 1mA N = BP + A, P IS PRESCALER VALUE. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES OF NX FREF , NMIN IS (P2 – P). Figure 32. A Counter/B Counter Latch Map Rev. D | Page 16 of 28 00392-032 LDP A5 RESERVED POWERDOWN 2 FASTLOCK MODE RESERVED FASTLOCK ENABLE CP THREESTATE PHASE DETECTOR POLARITY POWERDOWN 1 COUNTER RESET ADF4116/ADF4117/ADF4118 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X PD2 X X X TC4 TC3 TC2 TC1 F6 X F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0) TIMER COUNTER CONTROL RESERVED MUXOUT CONTROL COUNTER OPERATION F1 CE PIN PD2 PD1 0 X X CONTROL BITS 0 NORMAL 1 R, A, B COUNTERS HELD IN RESET MODE ASYNCHRONOUS POWER-DOWN M3 M2 M1 0 0 0 THREE-STATE OUTPUT OUTPUT 1 X 0 NORMAL OPERATION 1 0 1 ASYNCHRONOUS POWER-DOWN 0 0 1 DIGITAL LOCK DETECT (ACTIVE HIGH) 1 1 1 SYNCHRONOUS POWER-DOWN 0 1 0 N DIVIDER OUTPUT 0 1 1 AVDD 1 0 0 R DIVIDER OUTPUT 1 0 1 ANALOG LOCK DETECT (N CHANNEL OPEN DRAIN) 1 1 0 SERIAL DATA OUTPUT (INVERSE POLARITY OF SERIAL DATA INPUT) 1 1 1 DGND PHASE DETECTOR POLARITY 0 NEGATIVE 1 POSITIVE F3 CHARGE PUMP OUTPUT 0 NORMAL 1 THREE-STATE F4 F6 0 X FASTLOCK DISABLED 1 0 FASTLOCK MODE 1 1 1 FASTLOCK MODE FASTLOCK MODE 2 TIMEOUT (PFD CYCLES) TC4 TC3 TC2 0 0 0 0 0 0 0 1 7 0 0 1 0 11 0 0 1 1 15 0 1 0 0 19 0 1 0 1 23 0 1 1 0 27 0 1 1 1 31 1 0 0 0 35 1 0 0 1 39 1 0 1 0 43 1 0 1 1 47 1 1 0 0 51 1 1 0 1 55 1 1 1 0 59 1 1 1 1 63 3 Figure 33. Function Latch Map Rev. D | Page 17 of 28 00392-033 TC1 F2 RESERVED POWERDOWN 2 FASTLOCK MODE RESERVED FASTLOCK ENABLE CP THREESTATE PHASE DETECTOR POLARITY POWERDOWN 1 COUNTER RESET ADF4116/ADF4117/ADF4118 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X PD2 X X X TC4 TC3 TC2 TC1 F6 X F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (1) TIMER COUNTER CONTROL MUXOUT CONTROL COUNTER OPERATION F1 CE PIN PD2 PD1 CONTROL BITS 0 NORMAL 1 R, A, B COUNTERS HELD IN RESET M3 M2 M1 0 0 0 THREE-STATE OUTPUT 0 0 1 DIGITAL LOCK DETECT (ACTIVE HIGH) MODE OUTPUT 0 X X ASYNCHRONOUS POWER-DOWN 1 X 0 NORMAL OPERATION 1 0 1 ASYNCHRONOUS POWER-DOWN 0 1 0 N DIVIDER OUTPUT 1 1 1 SYNCHRONOUS POWER-DOWN 0 1 1 AV DD 1 0 0 R DIVIDER OUTPUT 1 0 1 ANALOG LOCK DETECT (N CHANNEL OPEN DRAIN) 1 1 0 SERIAL DATA OUTPUT (INVERSE POLARITY OF SERIAL DATA INPUT) 1 1 1 DGND F3 PHASE DETECTOR POLARITY 0 NEGATIVE 1 POSITIVE CHARGE PUMP OUTPUT 0 NORMAL 1 THREE-STATE F4 F6 FASTLOCK MODE 0 X FASTLOCK DISABLED 1 0 FASTLOCK MODE 1 1 1 FASTLOCK MODE 2 TC1 F2 TIMEOUT (PFD CYCLES) TC4 TC3 TC2 0 0 0 0 0 0 0 1 7 0 0 1 0 11 0 0 1 1 15 0 1 0 0 19 0 1 0 1 23 0 1 1 0 27 0 1 1 1 31 1 0 0 0 35 1 0 0 1 39 1 0 1 0 43 1 0 1 1 47 1 1 0 0 51 1 1 0 1 55 1 1 1 0 59 1 1 1 1 63 3 Figure 34. Initialization Latch Map Rev. D | Page 18 of 28 00392-034 RESERVED ADF4116/ADF4117/ADF4118 FUNCTION LATCH With C2 and C1 set to 1 and 0, respectively, the on-chip function latch is programmed. Figure 33 shows the input data format for programming the function latch. CHARGE PUMP THREE-STATE COUNTER RESET FASTLOCK ENABLE BIT DB2 (F1) is the counter reset bit. When this bit is set to 1, the R counter, A counter, and B counter are reset. For normal operation, this bit should be set to 0. On power-up, the F1 bit needs to be disabled, for the N counter to resume counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle.) DB9 (F4) of the function latch is the fastlock enable bit. Fastlock is enabled only when DB9 is set to 1. POWER-DOWN DB3 (PD1) and DB19 (PD2) on the ADF411x family provide programmable power-down modes. They are enabled by the CE pin. When the CE pin is low, the device is immediately disabled regardless of the states of PD2 and PD1. The DB8 (F3) bit puts the charge pump into three-state mode when programmed to 1. It should be set to 0 for normal operation. FASTLOCK MODE BIT DB11 (F6) of the function latch is the fastlock mode bit. When fastlock is enabled, this bit determines which fastlock mode is used. If the fastlock mode bit is 0, Fastlock Mode 1 is selected; if the fastlock mode bit is 1, Fastlock Mode 2 is selected. If fastlock is not enabled (DB9 = 0), DB11 (ADF4116) determines the state of the FLO output. FLO state is the same as that programmed to DB11. Fastlock Mode 1 In programmed asynchronous power-down, the device powers down immediately after latching a 1 into the PD1 bit, with the condition that PD2 is loaded with a 0. In programmed synchronous power-down, the device powerdown is gated by the charge pump to prevent unwanted frequency jumps. Once power-down is enabled by writing a 1 into the PD1 bit (on condition that a 1 is also loaded to PD2), the device goes into power-down after the first successive charge pump event. When a power-down is activated (either synchronous or asynchronous mode including CE pin-activated power-down), the following events occur: In the ADF411x family, the output level of FLO is programmed to a low state, and the charge pump current is switched to the high value (1 mA). FLO is used to switch a resistor in the loop filter and to ensure stability while in fastlock by altering the loop bandwidth. The device enters fastlock by having a 1 written to the CP Gain bit in the N register. The device exits fastlock by having a 0 written to the CP Gain bit in the N register. Fastlock Mode 2 In the ADF411x family, the output level of FLO is programmed to a low state, and the charge pump current is switched to the high value (1 mA). FLO is used to switch a resistor in the loop filter and to ensure stability while in fastlock by altering the loop bandwidth. • All active dc current paths are removed. • The R counter, N counter, and timeout counter are forced to their load state conditions. • The charge pump is forced into three-state mode. • The digital clock detect circuitry is reset. • The RFIN input is debiased. The device enters fastlock by having a 1 written to the CP gain bit in the N register. The device exits fastlock under the control of the timer counter. After the timeout period determined by the value in TC4 to TC1, the CP Gain bit in the N register is automatically reset to 0, and the device reverts to normal mode instead of fastlock. • The oscillator input buffer circuitry is disabled. TIMER COUNTER CONTROL • The input register remains active and capable of loading and latching data. In the ADF411x family, the user has the option of switching between two charge pump current values to speed up locking to a new frequency. MUXOUT CONTROL The on-chip multiplexer is controlled by DB6 (M3), DB5 (M2), and DB4 (M1) on the ADF411x family. Figure 33 shows the truth table. When using the fastlock feature with the ADF411x family, the following should be noted: • PHASE DETECTOR POLARITY DB7 (F2) of the function latch sets the phase detector polarity. When the VCO characteristics are positive, DB7 should be set to 1. When they are negative, it should be set to 0. Rev. D | Page 19 of 28 The user must make sure that fastlock is enabled. Set DB9 to 1. The user must also choose which fastlock mode to use. ADF4116/ADF4117/ADF4118 • Fastlock Mode 2 uses the values in the timer counter to determine the timeout period before reverting to normal mode operation after fastlock. Fastlock Mode 2 is chosen by setting DB11 to 1. • The user must also decide how long to keep the high current (1 mA) active before reverting to low current (250 μA). This is controlled by the timer counter control bits, DB14 to DB11 (TC4 to TC1), in the function latch. The truth table is given in Figure 33. • To program a new output frequency, program the A counter and B counter latch with new values for A and B. At the same time, set the CP Gain bit to a 1, which sets the charge pump to 1 mA for a period of time determined by TC4 to TC1. When this time is up, the charge pump current reverts to 250 μA. At the same time, the CP Gain bit in the A counter and B counter latch is reset to 0 and is ready for the next time that the user wants to change the frequency. INITIALIZATION LATCH When C2 and C1 are both set to 1, the initialization latch is programmed. This is essentially the same as the function latch that is programmed when C2, C1 = 1, 0. However, when the initialization latch is programmed, an additional internal reset pulse is applied to the R counter and N counter. This pulse ensures that the N counter is at a load point when the N counter data is latched and that the device begins counting in close phase alignment. 4. Do an N load (01 in 2 LSBs). When the initialization latch is loaded, the following occurs: • The function latch contents are loaded. • An internal pulse resets the R, N, and timeout counters to load state conditions and also three-states the charge pump. Note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes. • Latching the first N counter data after the initialization word activates the same internal reset pulse. Successive N loads do not trigger the internal reset pulse unless there is another initialization. CE Pin Method 1. Apply VDD. 2. Bring CE low to put the device into power-down. This is an asynchronous power-down in that it happens immediately. 3. Program the function latch (10). 4. Program the R counter latch (00). 5. Program the N counter latch (01). 6. Bring CE high to take the device out of power-down. The R counter and N counter resume counting in close alignment. Note that after CE goes high, a duration of 1 μs may be required for the prescaler band gap voltage and oscillator input buffer bias to reach a steady state. If the latch is programmed for synchronous power-down (CE pin is high; PD1 bit is high; PD2 bit is low), the internal pulse also triggers this power-down. The prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse, so close phase alignment is maintained when counting resumes. CE can be used to power up and power down the device to check for channel activity. The input register does not need to be reprogrammed each time the device is disabled and enabled, as long as it is programmed at least once after VCC is initially applied. Counter Reset Method When the first N counter data is latched after initialization, the internal reset pulse is again activated. However, successive N counter loads do not trigger the internal reset pulse. 1. Apply VDD. 2. DEVICE PROGRAMMING AFTER INITIAL POWER-UP Do a function latch load (10 in 2 LSBs). As part of this, load 1 to the F1 bit. This enables the counter reset. 3. Do an R counter load (00 in 2 LSBs). 4. Do an N counter load (01 in 2 LSBs). 5. Do a function latch load (10 in 2 LSBs). As part of this, load 0 to the F1 bit. This disables the counter reset. After initial power-up, the device can be programmed by the initialization latch method, the CE pin method, or the counter reset method. Initialization Latch Method 1. Apply VDD. 2. Program the initialization latch (11 in 2 LSBs of input word). Make sure that F1 bit is programmed to 0. 3. Do an R load (00 in 2 LSBs). This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three-states the charge pump, but it does not trigger synchronous power-down. The counter reset method requires an extra function latch load compared to the initialization latch method. Rev. D | Page 20 of 28 ADF4116/ADF4117/ADF4118 APPLICATIONS INFORMATION LOCAL OSCILLATOR FOR THE GSM BASE STATION TRANSMITTER SHUTDOWN CIRCUIT Figure 35 shows the ADF4117/ADF4118 being used with a VCO to produce the LO for a GSM base station transmitter. The reference input signal is applied to the circuit at FREFIN and, in this case, is terminated in 50 Ω. A typical GSM system has a 13 MHz TCXO driving the reference input without a 50 Ω termination. To have a channel spacing of 200 kHz (the GSM standard), the reference input must be divided by 65, using the on-chip reference divider of the ADF4117/ADF1118. The charge pump output of the ADF4117/ADF1118 (Pin 2) drives the loop filter. In calculating the loop filter component values, a number of items need to be considered. In this example, the loop filter was designed so that the overall phase margin for the system is 45°. Other PLL system specifications include: KD = 1 mA KV = 12 MHz/V Loop bandwidth = 20 kHz FREF = 200 kHz N = 4500 Extra reference spur attenuation = 10 dB All of these specifications are needed and are used to produce the loop filter component values shown in Figure 36. The loop filter output drives the VCO, which, in turn, is fed back to the RF input of the PLL synthesizer; it also drives the RF output terminal. A T-circuit configuration provides 50 Ω matching between the VCO output, the RF output, and the RFIN terminal of the synthesizer. In a PLL system, it is important to know when the system is in locked mode. In Figure 35, this is accomplished by using the MUXOUT signal from the synthesizer. The MUXOUT pin can be programmed to monitor various internal signals in the synthesizer. One of these is the LD or lock-detect signal. The attached circuit in Figure 36 shows how to shut down both the ADF411x family and the accompanying VCO. The ADG702 switch goes open-circuit when a Logic 1 is applied to the IN input. The low cost switch is available in both SOT-23 and MSOP packages. DIRECT CONVERSION MODULATOR In some applications, a direct conversion architecture can be used in base station transmitters. Figure 37 shows the combination available from Analog Devices, Inc. to implement this solution. The circuit diagram shows the AD9761 being used with the AD8346. The use of dual integrated DACs, such as the AD9761 with specified ±0.02 dB and ±0.004 dB gain and offset matching characteristics, ensures minimum error contribution (over temperature) from this portion of the signal chain. The local oscillator is implemented by using the ADF4117/ ADF4118. In this case, the FOX801BH-130 provides the stable 13 MHz reference frequency. The system is designed for 200 kHz channel spacing and an output center frequency of 1960 MHz. The target application is a WCDMA base station transmitter. Typical phase noise performance from this LO is −85 dBc/Hz at a 1 kHz offset. The LO port of the AD8346 is driven in single-ended fashion. LOIN is ac-coupled to ground with the 100 pF capacitor, and LOIP is driven through the accoupling capacitor from a 50 Ω source. An LO drive level between −6 dBm and −12 dBm is required. The circuit in Figure 37 gives a typical level of −8 dBm. The RF output is designed to drive a 50 Ω load, but it must be ac-coupled as shown in Figure 37. If the I and Q inputs are driven in quadrature by 2 V p-p signals, the resulting output power is approximately −10 dBm. Rev. D | Page 21 of 28 ADF4116/ADF4117/ADF4118 VDD RFOUT VP 100pF 7 1000pF 1000pF FREFIN 8 51Ω* 15 16 AVDD DVDD VP CP REFIN 27kΩ 0.15nF FLO VCC 3.3kΩ 2 620pF 18Ω 100pF 18Ω VCO190-902T 18Ω 1 ADF4117/ ADF4118 10kΩ 1.5nF SPI-COMPATIBLE SERIAL BUS 14 CE LOCK MUXOUT CLK DETECT DATA 100pF LE 6 RFINA 3 DGND AGND CPGND RFINB 5 4 51Ω** 100pF 9 *TO BE USED WHEN GENERATOR SOURCE IMPEDANCE IS 50Ω. **OPTIONAL MATCHING RESISTOR DEPENDING ON RFOUT FREQUENCY. 00392-035 DECOUPLING CAPACITORS ON AVDD, DVDD, AND VP OF THE ADF4117/ADF4118 AND ON VCC OF THE VCO190-920T HAVE BEEN OMITTED FROM THE DIAGRAM FOR CLARITY. Figure 35. Local Oscillator for GSM Base Station VP POWER-DOWN CONTROL S D 7 15 16 AVDD DVDD VP CE CP FLO 2 AGND DGND 9 RFINB GND VCC 100pF 100pF 18Ω VCO 18Ω 18Ω GND 10kΩ RFINA 6 4 LOOP FILTER 1 ADF4116/ ADF4117/ ADF4118 3 RFOUT 100pF 5 51Ω 100pF DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE BEEN OMITTED FROM THE DIAGRAM FOR CLARITY. Figure 36. Local Oscillator Shutdown Circuit Rev. D | Page 22 of 28 00392-036 REFIN CPGND FREFIN 8 VDD IN ADG702 VDD ADF4116/ADF4117/ADF4118 0.1µF REFIO MODULATED DIGITAL DATA AD9761 TxDAC IOUTA IOUTB 100pF VOUT IBBP QBBP LOW-PASS FILTER QOUTB QBBP 2kΩ LOIN LOIP 100pF FOX801BH-130 100pF 18Ω REFIN SERIAL DIGITAL INTERFACE CP ADF4118 680pF 1kΩ 18pF VCO190-1960T 6.8nF RFINB 100pF 10kΩ 100pF 18Ω 18Ω RFINA 100pF 51Ω POWER SUPPLY CONNECTIONS AND DECOUPLING CAPACITORS ARE OMITTED FROM DIAGRAM FOR CLARITY. Figure 37. Direct Conversion Transmitter Solution Rev. D | Page 23 of 28 00392-037 TCXO RFOUT AD8346 QOUTA FS ADJ IBBP LOW-PASS FILTER ADF4116/ADF4117/ADF4118 The ADF411x family has a simple SPI®-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE (latch enable) goes high, the 24 bits that are clocked into the input register on each rising edge of CLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the latch truth table. The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 833 kHz or one update every 1.2 μs. This is more than adequate for systems that have typical lock times in hundreds of microseconds. ADuC812 Interface Figure 38 shows the interface between the ADF411x family and the ADuC812 MicroConverter®. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF411x family needs a 24-bit word. This is accomplished by writing three 8-bit bytes from the MicroConverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer. On first applying power to the ADF411x family, it requires three writes (one each to the R counter latch, the N counter latch, and the initialization latch) for the output to become active. I/O port lines on the ADuC812 are also used to control powerdown (CE input) and to detect lock (MUXOUT configured as lock detect and polled by the port input). When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 166 kHz. ADSP-21xx Interface Figure 39 shows the interface between the ADF411x family and the ADSP-21xx digital signal processor. The ADF411x family needs a 21-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. SCLK ADSP-21xx DT TFS I/O FLAGS ADuC812 MOSI CLK DATA LE CE ADF4116/ ADF4117/ ADF4118 MUXOUT (LOCK DETECT) DATA LE I/O PORTS CE ADF4116/ ADF4117/ ADF4118 MUXOUT (LOCK DETECT) Figure 38. ADuC812 to ADF411x family Interface Figure 39. ADSP-21xx to ADF411x family Interface 00392-038 SCLOCK CLK 00392-039 INTERFACING Set up the word length for 8 bits and use three memory locations for each 24-bit word. To program each 21-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. Rev. D | Page 24 of 28 ADF4116/ADF4117/ADF4118 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.20 0.09 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AB Figure 40. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model ADF4116BRU Temperature Range −40°C to +85°C Package Description 16-Lead Thin Shrink Small Outline Package (TSSOP) Package Option RU-16 ADF4116BRU-REEL ADF4116BRU-REEL7 ADF4116BRUZ 1 ADF4116BRUZ-REEL1 ADF4116BRUZ-REEL71 −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 RU-16 RU-16 RU-16 RU-16 ADF4117BRU ADF4117BRU-REEL ADF4117BRU-REEL7 ADF4117BRUZ1 ADF4117BRUZ-RL1 ADF4117BRUZ-RL71 −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 ADF4118BRU ADF4118BRU-REEL ADF4118BRU-REEL7 ADF4118BRUZ1 −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +125°C −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) Evaluation Board Evaluation Board RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 ADF4118BRUZ-RL1 ADF4118BRUZ-RL71 ADF4118YRUZ1 ADF4118YRUZ-RL1 ADF4118YRUZ-RL71 EVAL-ADF4118EBZ11 EVAL-ADF411XEBZ11 1 Z = RoHS Compliant Part. Rev. D | Page 25 of 28 ADF4116/ADF4117/ADF4118 NOTES Rev. D | Page 26 of 28 ADF4116/ADF4117/ADF4118 NOTES Rev. D | Page 27 of 28 ADF4116/ADF4117/ADF4118 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2000–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00392-0-4/07(D) Rev. D | Page 28 of 28